1/*
  2 * Core pinctrl/GPIO driver for Intel GPIO controllers
  3 *
  4 * Copyright (C) 2015, Intel Corporation
  5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
  6 *          Mika Westerberg <mika.westerberg@linux.intel.com>
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License version 2 as
 10 * published by the Free Software Foundation.
 11 */
 12
 13#ifndef PINCTRL_INTEL_H
 14#define PINCTRL_INTEL_H
 15
 16struct pinctrl_pin_desc;
 17struct platform_device;
 18struct device;
 19
 20/**
 21 * struct intel_pingroup - Description about group of pins
 22 * @name: Name of the groups
 23 * @pins: All pins in this group
 24 * @npins: Number of pins in this groups
 25 * @mode: Native mode in which the group is muxed out @pins. Used if @modes
 26 *        is %NULL.
 27 * @modes: If not %NULL this will hold mode for each pin in @pins
 28 */
 29struct intel_pingroup {
 30	const char *name;
 31	const unsigned *pins;
 32	size_t npins;
 33	unsigned short mode;
 34	const unsigned *modes;
 35};
 36
 37/**
 38 * struct intel_function - Description about a function
 39 * @name: Name of the function
 40 * @groups: An array of groups for this function
 41 * @ngroups: Number of groups in @groups
 42 */
 43struct intel_function {
 44	const char *name;
 45	const char * const *groups;
 46	size_t ngroups;
 47};
 48
 49/**
 50 * struct intel_padgroup - Hardware pad group information
 51 * @reg_num: GPI_IS register number
 52 * @base: Starting pin of this group
 53 * @size: Size of this group (maximum is 32).
 54 * @gpio_base: Starting GPIO base of this group (%0 if matches with @base,
 55 *	       and %-1 if no GPIO mapping should be created)
 56 * @padown_num: PAD_OWN register number (assigned by the core driver)
 57 *
 58 * If pad groups of a community are not the same size, use this structure
 59 * to specify them.
 60 */
 61struct intel_padgroup {
 62	unsigned reg_num;
 63	unsigned base;
 64	unsigned size;
 65	int gpio_base;
 66	unsigned padown_num;
 67};
 68
 69/**
 70 * struct intel_community - Intel pin community description
 71 * @barno: MMIO BAR number where registers for this community reside
 72 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
 73 *                 then there is no support for owner.
 74 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
 75 *                     locking is not supported.
 76 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
 77 *                  is assumed that the host owns the pin (rather than
 78 *                  ACPI).
 79 * @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the
 80 *             default (%0x100).
 81 * @ie_offset: Register offset of GPI_IE from @regs.
 82 * @pin_base: Starting pin of pins in this community
 83 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
 84 *            HOSTSW_OWN,  GPI_IS, GPI_IE, etc. Used when @gpps is %NULL.
 85 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
 86 *			 minimum. Use %0 if the number of registers can be
 87 *			 determined by the size of the group.
 88 * @npins: Number of pins in this community
 89 * @features: Additional features supported by the hardware
 90 * @gpps: Pad groups if the controller has variable size pad groups
 91 * @ngpps: Number of pad groups in this community
 92 * @regs: Community specific common registers (reserved for core driver)
 93 * @pad_regs: Community specific pad registers (reserved for core driver)
 94 *
 95 * Most Intel GPIO host controllers this driver supports each pad group is
 96 * of equal size (except the last one). In that case the driver can just
 97 * fill in @gpp_size field and let the core driver to handle the rest. If
 98 * the controller has pad groups of variable size the client driver can
 99 * pass custom @gpps and @ngpps instead.
100 */
101struct intel_community {
102	unsigned barno;
103	unsigned padown_offset;
104	unsigned padcfglock_offset;
105	unsigned hostown_offset;
106	unsigned is_offset;
107	unsigned ie_offset;
108	unsigned pin_base;
109	unsigned gpp_size;
110	unsigned gpp_num_padown_regs;
111	size_t npins;
112	unsigned features;
113	const struct intel_padgroup *gpps;
114	size_t ngpps;
115	/* Reserved for the core driver */
116	void __iomem *regs;
117	void __iomem *pad_regs;
118};
119
120/* Additional features supported by the hardware */
121#define PINCTRL_FEATURE_DEBOUNCE	BIT(0)
122#define PINCTRL_FEATURE_1K_PD		BIT(1)
123
124/**
125 * PIN_GROUP - Declare a pin group
126 * @n: Name of the group
127 * @p: An array of pins this group consists
128 * @m: Mode which the pins are put when this group is active. Can be either
129 *     a single integer or an array of integers in which case mode is per
130 *     pin.
131 */
132#define PIN_GROUP(n, p, m)					\
133	{							\
134		.name = (n),					\
135		.pins = (p),					\
136		.npins = ARRAY_SIZE((p)),			\
137		.mode = __builtin_choose_expr(			\
138			__builtin_constant_p((m)), (m), 0),	\
139		.modes = __builtin_choose_expr(			\
140			__builtin_constant_p((m)), NULL, (m)),	\
141	}
142
143#define FUNCTION(n, g)				\
144	{					\
145		.name = (n),			\
146		.groups = (g),			\
147		.ngroups = ARRAY_SIZE((g)),	\
148	}
149
150/**
151 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
152 * @uid: ACPI _UID for the probe driver use if needed
153 * @pins: Array if pins this pinctrl controls
154 * @npins: Number of pins in the array
155 * @groups: Array of pin groups
156 * @ngroups: Number of groups in the array
157 * @functions: Array of functions
158 * @nfunctions: Number of functions in the array
159 * @communities: Array of communities this pinctrl handles
160 * @ncommunities: Number of communities in the array
161 *
162 * The @communities is used as a template by the core driver. It will make
163 * copy of all communities and fill in rest of the information.
164 */
165struct intel_pinctrl_soc_data {
166	const char *uid;
167	const struct pinctrl_pin_desc *pins;
168	size_t npins;
169	const struct intel_pingroup *groups;
170	size_t ngroups;
171	const struct intel_function *functions;
172	size_t nfunctions;
173	const struct intel_community *communities;
174	size_t ncommunities;
175};
176
177int intel_pinctrl_probe(struct platform_device *pdev,
178			const struct intel_pinctrl_soc_data *soc_data);
179#ifdef CONFIG_PM_SLEEP
180int intel_pinctrl_suspend(struct device *dev);
181int intel_pinctrl_resume(struct device *dev);
182#endif
183
184#endif /* PINCTRL_INTEL_H */