Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/kernel.h>
11#include <linux/mfd/syscon.h>
12#include <linux/module.h>
13#include <linux/nvmem-consumer.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/phy/phy.h>
17#include <linux/platform_device.h>
18#include <linux/regmap.h>
19#include <linux/regulator/consumer.h>
20#include <linux/reset.h>
21#include <linux/slab.h>
22
23#define QUSB2PHY_PLL_TEST 0x04
24#define CLK_REF_SEL BIT(7)
25
26#define QUSB2PHY_PLL_TUNE 0x08
27#define QUSB2PHY_PLL_USER_CTL1 0x0c
28#define QUSB2PHY_PLL_USER_CTL2 0x10
29#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
30#define QUSB2PHY_PLL_PWR_CTRL 0x18
31
32/* QUSB2PHY_PLL_STATUS register bits */
33#define PLL_LOCKED BIT(5)
34
35/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
36#define CORE_READY_STATUS BIT(0)
37
38/* QUSB2PHY_PORT_POWERDOWN register bits */
39#define CLAMP_N_EN BIT(5)
40#define FREEZIO_N BIT(1)
41#define POWER_DOWN BIT(0)
42
43/* QUSB2PHY_PWR_CTRL1 register bits */
44#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
45#define PWR_CTRL1_CLAMP_N_EN BIT(1)
46
47#define QUSB2PHY_REFCLK_ENABLE BIT(0)
48
49#define PHY_CLK_SCHEME_SEL BIT(0)
50
51/* QUSB2PHY_INTR_CTRL register bits */
52#define DMSE_INTR_HIGH_SEL BIT(4)
53#define DPSE_INTR_HIGH_SEL BIT(3)
54#define CHG_DET_INTR_EN BIT(2)
55#define DMSE_INTR_EN BIT(1)
56#define DPSE_INTR_EN BIT(0)
57
58/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
59#define CORE_PLL_EN_FROM_RESET BIT(4)
60#define CORE_RESET BIT(5)
61#define CORE_RESET_MUX BIT(6)
62
63#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
64#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
65#define QUSB2PHY_PLL_CMODE 0x2c
66#define QUSB2PHY_PLL_LOCK_DELAY 0x184
67#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
68#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
69#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
70#define QUSB2PHY_PWR_CTRL2 0x214
71#define QUSB2PHY_IMP_CTRL1 0x220
72#define QUSB2PHY_IMP_CTRL2 0x224
73#define QUSB2PHY_CHG_CTRL2 0x23c
74
75struct qusb2_phy_init_tbl {
76 unsigned int offset;
77 unsigned int val;
78 /*
79 * register part of layout ?
80 * if yes, then offset gives index in the reg-layout
81 */
82 int in_layout;
83};
84
85#define QUSB2_PHY_INIT_CFG(o, v) \
86 { \
87 .offset = o, \
88 .val = v, \
89 }
90
91#define QUSB2_PHY_INIT_CFG_L(o, v) \
92 { \
93 .offset = o, \
94 .val = v, \
95 .in_layout = 1, \
96 }
97
98/* set of registers with offsets different per-PHY */
99enum qusb2phy_reg_layout {
100 QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
101 QUSB2PHY_PLL_STATUS,
102 QUSB2PHY_PORT_TUNE1,
103 QUSB2PHY_PORT_TUNE2,
104 QUSB2PHY_PORT_TUNE3,
105 QUSB2PHY_PORT_TUNE4,
106 QUSB2PHY_PORT_TUNE5,
107 QUSB2PHY_PORT_TEST1,
108 QUSB2PHY_PORT_TEST2,
109 QUSB2PHY_PORT_POWERDOWN,
110 QUSB2PHY_INTR_CTRL,
111};
112
113static const unsigned int msm8996_regs_layout[] = {
114 [QUSB2PHY_PLL_STATUS] = 0x38,
115 [QUSB2PHY_PORT_TUNE1] = 0x80,
116 [QUSB2PHY_PORT_TUNE2] = 0x84,
117 [QUSB2PHY_PORT_TUNE3] = 0x88,
118 [QUSB2PHY_PORT_TUNE4] = 0x8c,
119 [QUSB2PHY_PORT_TUNE5] = 0x90,
120 [QUSB2PHY_PORT_TEST1] = 0xb8,
121 [QUSB2PHY_PORT_TEST2] = 0x9c,
122 [QUSB2PHY_PORT_POWERDOWN] = 0xb4,
123 [QUSB2PHY_INTR_CTRL] = 0xbc,
124};
125
126static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
127 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
128 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
129 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
130 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
131
132 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
133 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
134 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
135
136 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
137
138 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
139 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
140};
141
142static const unsigned int qusb2_v2_regs_layout[] = {
143 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
144 [QUSB2PHY_PLL_STATUS] = 0x1a0,
145 [QUSB2PHY_PORT_TUNE1] = 0x240,
146 [QUSB2PHY_PORT_TUNE2] = 0x244,
147 [QUSB2PHY_PORT_TUNE3] = 0x248,
148 [QUSB2PHY_PORT_TUNE4] = 0x24c,
149 [QUSB2PHY_PORT_TUNE5] = 0x250,
150 [QUSB2PHY_PORT_TEST1] = 0x254,
151 [QUSB2PHY_PORT_TEST2] = 0x258,
152 [QUSB2PHY_PORT_POWERDOWN] = 0x210,
153 [QUSB2PHY_INTR_CTRL] = 0x230,
154};
155
156static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
157 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
158 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
159 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
160 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
161 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
162 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
163 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
164 QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
165 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
166 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
167
168 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
169 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
170 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
171 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
172 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
173
174 QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
175};
176
177struct qusb2_phy_cfg {
178 const struct qusb2_phy_init_tbl *tbl;
179 /* number of entries in the table */
180 unsigned int tbl_num;
181 /* offset to PHY_CLK_SCHEME register in TCSR map */
182 unsigned int clk_scheme_offset;
183
184 /* array of registers with different offsets */
185 const unsigned int *regs;
186 unsigned int mask_core_ready;
187 unsigned int disable_ctrl;
188 unsigned int autoresume_en;
189
190 /* true if PHY has PLL_TEST register to select clk_scheme */
191 bool has_pll_test;
192
193 /* true if TUNE1 register must be updated by fused value, else TUNE2 */
194 bool update_tune1_with_efuse;
195
196 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
197 bool has_pll_override;
198};
199
200static const struct qusb2_phy_cfg msm8996_phy_cfg = {
201 .tbl = msm8996_init_tbl,
202 .tbl_num = ARRAY_SIZE(msm8996_init_tbl),
203 .regs = msm8996_regs_layout,
204
205 .has_pll_test = true,
206 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
207 .mask_core_ready = PLL_LOCKED,
208 .autoresume_en = BIT(3),
209};
210
211static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
212 .tbl = qusb2_v2_init_tbl,
213 .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
214 .regs = qusb2_v2_regs_layout,
215
216 .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
217 POWER_DOWN),
218 .mask_core_ready = CORE_READY_STATUS,
219 .has_pll_override = true,
220 .autoresume_en = BIT(0),
221};
222
223static const char * const qusb2_phy_vreg_names[] = {
224 "vdda-pll", "vdda-phy-dpdm",
225};
226
227#define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names)
228
229/**
230 * struct qusb2_phy - structure holding qusb2 phy attributes
231 *
232 * @phy: generic phy
233 * @base: iomapped memory space for qubs2 phy
234 *
235 * @cfg_ahb_clk: AHB2PHY interface clock
236 * @ref_clk: phy reference clock
237 * @iface_clk: phy interface clock
238 * @phy_reset: phy reset control
239 * @vregs: regulator supplies bulk data
240 *
241 * @tcsr: TCSR syscon register map
242 * @cell: nvmem cell containing phy tuning value
243 *
244 * @cfg: phy config data
245 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
246 * @phy_initialized: indicate if PHY has been initialized
247 * @mode: current PHY mode
248 */
249struct qusb2_phy {
250 struct phy *phy;
251 void __iomem *base;
252
253 struct clk *cfg_ahb_clk;
254 struct clk *ref_clk;
255 struct clk *iface_clk;
256 struct reset_control *phy_reset;
257 struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
258
259 struct regmap *tcsr;
260 struct nvmem_cell *cell;
261
262 const struct qusb2_phy_cfg *cfg;
263 bool has_se_clk_scheme;
264 bool phy_initialized;
265 enum phy_mode mode;
266};
267
268static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
269{
270 u32 reg;
271
272 reg = readl(base + offset);
273 reg |= val;
274 writel(reg, base + offset);
275
276 /* Ensure above write is completed */
277 readl(base + offset);
278}
279
280static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
281{
282 u32 reg;
283
284 reg = readl(base + offset);
285 reg &= ~val;
286 writel(reg, base + offset);
287
288 /* Ensure above write is completed */
289 readl(base + offset);
290}
291
292static inline
293void qcom_qusb2_phy_configure(void __iomem *base,
294 const unsigned int *regs,
295 const struct qusb2_phy_init_tbl tbl[], int num)
296{
297 int i;
298
299 for (i = 0; i < num; i++) {
300 if (tbl[i].in_layout)
301 writel(tbl[i].val, base + regs[tbl[i].offset]);
302 else
303 writel(tbl[i].val, base + tbl[i].offset);
304 }
305}
306
307/*
308 * Fetches HS Tx tuning value from nvmem and sets the
309 * QUSB2PHY_PORT_TUNE1/2 register.
310 * For error case, skip setting the value and use the default value.
311 */
312static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
313{
314 struct device *dev = &qphy->phy->dev;
315 const struct qusb2_phy_cfg *cfg = qphy->cfg;
316 u8 *val;
317
318 /*
319 * Read efuse register having TUNE2/1 parameter's high nibble.
320 * If efuse register shows value as 0x0, or if we fail to find
321 * a valid efuse register settings, then use default value
322 * as 0xB for high nibble that we have already set while
323 * configuring phy.
324 */
325 val = nvmem_cell_read(qphy->cell, NULL);
326 if (IS_ERR(val) || !val[0]) {
327 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
328 return;
329 }
330
331 /* Fused TUNE1/2 value is the higher nibble only */
332 if (cfg->update_tune1_with_efuse)
333 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
334 val[0] << 0x4);
335 else
336 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
337 val[0] << 0x4);
338
339}
340
341static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)
342{
343 struct qusb2_phy *qphy = phy_get_drvdata(phy);
344
345 qphy->mode = mode;
346
347 return 0;
348}
349
350static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
351{
352 struct qusb2_phy *qphy = dev_get_drvdata(dev);
353 const struct qusb2_phy_cfg *cfg = qphy->cfg;
354 u32 intr_mask;
355
356 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
357
358 if (!qphy->phy_initialized) {
359 dev_vdbg(dev, "PHY not initialized, bailing out\n");
360 return 0;
361 }
362
363 /*
364 * Enable DP/DM interrupts to detect line state changes based on current
365 * speed. In other words, enable the triggers _opposite_ of what the
366 * current D+/D- levels are e.g. if currently D+ high, D- low
367 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
368 */
369 intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
370 switch (qphy->mode) {
371 case PHY_MODE_USB_HOST_HS:
372 case PHY_MODE_USB_HOST_FS:
373 case PHY_MODE_USB_DEVICE_HS:
374 case PHY_MODE_USB_DEVICE_FS:
375 intr_mask |= DMSE_INTR_HIGH_SEL;
376 break;
377 case PHY_MODE_USB_HOST_LS:
378 case PHY_MODE_USB_DEVICE_LS:
379 intr_mask |= DPSE_INTR_HIGH_SEL;
380 break;
381 default:
382 /* No device connected, enable both DP/DM high interrupt */
383 intr_mask |= DMSE_INTR_HIGH_SEL;
384 intr_mask |= DPSE_INTR_HIGH_SEL;
385 break;
386 }
387
388 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
389
390 /* hold core PLL into reset */
391 if (cfg->has_pll_override) {
392 qusb2_setbits(qphy->base,
393 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
394 CORE_PLL_EN_FROM_RESET | CORE_RESET |
395 CORE_RESET_MUX);
396 }
397
398 /* enable phy auto-resume only if device is connected on bus */
399 if (qphy->mode != PHY_MODE_INVALID) {
400 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
401 cfg->autoresume_en);
402 /* Autoresume bit has to be toggled in order to enable it */
403 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
404 cfg->autoresume_en);
405 }
406
407 if (!qphy->has_se_clk_scheme)
408 clk_disable_unprepare(qphy->ref_clk);
409
410 clk_disable_unprepare(qphy->cfg_ahb_clk);
411 clk_disable_unprepare(qphy->iface_clk);
412
413 return 0;
414}
415
416static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
417{
418 struct qusb2_phy *qphy = dev_get_drvdata(dev);
419 const struct qusb2_phy_cfg *cfg = qphy->cfg;
420 int ret;
421
422 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
423
424 if (!qphy->phy_initialized) {
425 dev_vdbg(dev, "PHY not initialized, bailing out\n");
426 return 0;
427 }
428
429 ret = clk_prepare_enable(qphy->iface_clk);
430 if (ret) {
431 dev_err(dev, "failed to enable iface_clk, %d\n", ret);
432 return ret;
433 }
434
435 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
436 if (ret) {
437 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
438 goto disable_iface_clk;
439 }
440
441 if (!qphy->has_se_clk_scheme) {
442 clk_prepare_enable(qphy->ref_clk);
443 if (ret) {
444 dev_err(dev, "failed to enable ref clk, %d\n", ret);
445 goto disable_ahb_clk;
446 }
447 }
448
449 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
450
451 /* bring core PLL out of reset */
452 if (cfg->has_pll_override) {
453 qusb2_clrbits(qphy->base,
454 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
455 CORE_RESET | CORE_RESET_MUX);
456 }
457
458 return 0;
459
460disable_ahb_clk:
461 clk_disable_unprepare(qphy->cfg_ahb_clk);
462disable_iface_clk:
463 clk_disable_unprepare(qphy->iface_clk);
464
465 return ret;
466}
467
468static int qusb2_phy_init(struct phy *phy)
469{
470 struct qusb2_phy *qphy = phy_get_drvdata(phy);
471 const struct qusb2_phy_cfg *cfg = qphy->cfg;
472 unsigned int val = 0;
473 unsigned int clk_scheme;
474 int ret;
475
476 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
477
478 /* turn on regulator supplies */
479 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
480 if (ret)
481 return ret;
482
483 ret = clk_prepare_enable(qphy->iface_clk);
484 if (ret) {
485 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
486 goto poweroff_phy;
487 }
488
489 /* enable ahb interface clock to program phy */
490 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
491 if (ret) {
492 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
493 goto disable_iface_clk;
494 }
495
496 /* Perform phy reset */
497 ret = reset_control_assert(qphy->phy_reset);
498 if (ret) {
499 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
500 goto disable_ahb_clk;
501 }
502
503 /* 100 us delay to keep PHY in reset mode */
504 usleep_range(100, 150);
505
506 ret = reset_control_deassert(qphy->phy_reset);
507 if (ret) {
508 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
509 goto disable_ahb_clk;
510 }
511
512 /* Disable the PHY */
513 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
514 qphy->cfg->disable_ctrl);
515
516 if (cfg->has_pll_test) {
517 /* save reset value to override reference clock scheme later */
518 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
519 }
520
521 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
522 cfg->tbl_num);
523
524 /* Set efuse value for tuning the PHY */
525 qusb2_phy_set_tune2_param(qphy);
526
527 /* Enable the PHY */
528 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
529 POWER_DOWN);
530
531 /* Required to get phy pll lock successfully */
532 usleep_range(150, 160);
533
534 /* Default is single-ended clock on msm8996 */
535 qphy->has_se_clk_scheme = true;
536 /*
537 * read TCSR_PHY_CLK_SCHEME register to check if single-ended
538 * clock scheme is selected. If yes, then disable differential
539 * ref_clk and use single-ended clock, otherwise use differential
540 * ref_clk only.
541 */
542 if (qphy->tcsr) {
543 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
544 &clk_scheme);
545 if (ret) {
546 dev_err(&phy->dev, "failed to read clk scheme reg\n");
547 goto assert_phy_reset;
548 }
549
550 /* is it a differential clock scheme ? */
551 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
552 dev_vdbg(&phy->dev, "%s(): select differential clk\n",
553 __func__);
554 qphy->has_se_clk_scheme = false;
555 } else {
556 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
557 __func__);
558 }
559 }
560
561 if (!qphy->has_se_clk_scheme) {
562 ret = clk_prepare_enable(qphy->ref_clk);
563 if (ret) {
564 dev_err(&phy->dev, "failed to enable ref clk, %d\n",
565 ret);
566 goto assert_phy_reset;
567 }
568 }
569
570 if (cfg->has_pll_test) {
571 if (!qphy->has_se_clk_scheme)
572 val &= ~CLK_REF_SEL;
573 else
574 val |= CLK_REF_SEL;
575
576 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
577
578 /* ensure above write is through */
579 readl(qphy->base + QUSB2PHY_PLL_TEST);
580 }
581
582 /* Required to get phy pll lock successfully */
583 usleep_range(100, 110);
584
585 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
586 if (!(val & cfg->mask_core_ready)) {
587 dev_err(&phy->dev,
588 "QUSB2PHY pll lock failed: status reg = %x\n", val);
589 ret = -EBUSY;
590 goto disable_ref_clk;
591 }
592 qphy->phy_initialized = true;
593
594 return 0;
595
596disable_ref_clk:
597 if (!qphy->has_se_clk_scheme)
598 clk_disable_unprepare(qphy->ref_clk);
599assert_phy_reset:
600 reset_control_assert(qphy->phy_reset);
601disable_ahb_clk:
602 clk_disable_unprepare(qphy->cfg_ahb_clk);
603disable_iface_clk:
604 clk_disable_unprepare(qphy->iface_clk);
605poweroff_phy:
606 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
607
608 return ret;
609}
610
611static int qusb2_phy_exit(struct phy *phy)
612{
613 struct qusb2_phy *qphy = phy_get_drvdata(phy);
614
615 /* Disable the PHY */
616 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
617 qphy->cfg->disable_ctrl);
618
619 if (!qphy->has_se_clk_scheme)
620 clk_disable_unprepare(qphy->ref_clk);
621
622 reset_control_assert(qphy->phy_reset);
623
624 clk_disable_unprepare(qphy->cfg_ahb_clk);
625 clk_disable_unprepare(qphy->iface_clk);
626
627 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
628
629 qphy->phy_initialized = false;
630
631 return 0;
632}
633
634static const struct phy_ops qusb2_phy_gen_ops = {
635 .init = qusb2_phy_init,
636 .exit = qusb2_phy_exit,
637 .set_mode = qusb2_phy_set_mode,
638 .owner = THIS_MODULE,
639};
640
641static const struct of_device_id qusb2_phy_of_match_table[] = {
642 {
643 .compatible = "qcom,msm8996-qusb2-phy",
644 .data = &msm8996_phy_cfg,
645 }, {
646 .compatible = "qcom,qusb2-v2-phy",
647 .data = &qusb2_v2_phy_cfg,
648 },
649 { },
650};
651MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
652
653static const struct dev_pm_ops qusb2_phy_pm_ops = {
654 SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
655 qusb2_phy_runtime_resume, NULL)
656};
657
658static int qusb2_phy_probe(struct platform_device *pdev)
659{
660 struct device *dev = &pdev->dev;
661 struct qusb2_phy *qphy;
662 struct phy_provider *phy_provider;
663 struct phy *generic_phy;
664 struct resource *res;
665 int ret, i;
666 int num;
667
668 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
669 if (!qphy)
670 return -ENOMEM;
671
672 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
673 qphy->base = devm_ioremap_resource(dev, res);
674 if (IS_ERR(qphy->base))
675 return PTR_ERR(qphy->base);
676
677 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
678 if (IS_ERR(qphy->cfg_ahb_clk)) {
679 ret = PTR_ERR(qphy->cfg_ahb_clk);
680 if (ret != -EPROBE_DEFER)
681 dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
682 return ret;
683 }
684
685 qphy->ref_clk = devm_clk_get(dev, "ref");
686 if (IS_ERR(qphy->ref_clk)) {
687 ret = PTR_ERR(qphy->ref_clk);
688 if (ret != -EPROBE_DEFER)
689 dev_err(dev, "failed to get ref clk, %d\n", ret);
690 return ret;
691 }
692
693 qphy->iface_clk = devm_clk_get(dev, "iface");
694 if (IS_ERR(qphy->iface_clk)) {
695 ret = PTR_ERR(qphy->iface_clk);
696 if (ret == -EPROBE_DEFER)
697 return ret;
698 qphy->iface_clk = NULL;
699 dev_dbg(dev, "failed to get iface clk, %d\n", ret);
700 }
701
702 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
703 if (IS_ERR(qphy->phy_reset)) {
704 dev_err(dev, "failed to get phy core reset\n");
705 return PTR_ERR(qphy->phy_reset);
706 }
707
708 num = ARRAY_SIZE(qphy->vregs);
709 for (i = 0; i < num; i++)
710 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
711
712 ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
713 if (ret) {
714 dev_err(dev, "failed to get regulator supplies\n");
715 return ret;
716 }
717
718 /* Get the specific init parameters of QMP phy */
719 qphy->cfg = of_device_get_match_data(dev);
720
721 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
722 "qcom,tcsr-syscon");
723 if (IS_ERR(qphy->tcsr)) {
724 dev_dbg(dev, "failed to lookup TCSR regmap\n");
725 qphy->tcsr = NULL;
726 }
727
728 qphy->cell = devm_nvmem_cell_get(dev, NULL);
729 if (IS_ERR(qphy->cell)) {
730 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
731 return -EPROBE_DEFER;
732 qphy->cell = NULL;
733 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
734 }
735 pm_runtime_set_active(dev);
736 pm_runtime_enable(dev);
737 /*
738 * Prevent runtime pm from being ON by default. Users can enable
739 * it using power/control in sysfs.
740 */
741 pm_runtime_forbid(dev);
742
743 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
744 if (IS_ERR(generic_phy)) {
745 ret = PTR_ERR(generic_phy);
746 dev_err(dev, "failed to create phy, %d\n", ret);
747 pm_runtime_disable(dev);
748 return ret;
749 }
750 qphy->phy = generic_phy;
751
752 dev_set_drvdata(dev, qphy);
753 phy_set_drvdata(generic_phy, qphy);
754
755 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
756 if (!IS_ERR(phy_provider))
757 dev_info(dev, "Registered Qcom-QUSB2 phy\n");
758 else
759 pm_runtime_disable(dev);
760
761 return PTR_ERR_OR_ZERO(phy_provider);
762}
763
764static struct platform_driver qusb2_phy_driver = {
765 .probe = qusb2_phy_probe,
766 .driver = {
767 .name = "qcom-qusb2-phy",
768 .pm = &qusb2_phy_pm_ops,
769 .of_match_table = qusb2_phy_of_match_table,
770 },
771};
772
773module_platform_driver(qusb2_phy_driver);
774
775MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
776MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
777MODULE_LICENSE("GPL v2");