1/*
 2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
 3 *
 4 * Permission to use, copy, modify, and/or distribute this software for any
 5 * purpose with or without fee is hereby granted, provided that the above
 6 * copyright notice and this permission notice appear in all copies.
 7 *
 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef __MT76x2_DMA_H
18#define __MT76x2_DMA_H
19
20#include "dma.h"
21
22#define MT_TXD_INFO_LEN			GENMASK(13, 0)
23#define MT_TXD_INFO_NEXT_VLD		BIT(16)
24#define MT_TXD_INFO_TX_BURST		BIT(17)
25#define MT_TXD_INFO_80211		BIT(19)
26#define MT_TXD_INFO_TSO			BIT(20)
27#define MT_TXD_INFO_CSO			BIT(21)
28#define MT_TXD_INFO_WIV			BIT(24)
29#define MT_TXD_INFO_QSEL		GENMASK(26, 25)
30#define MT_TXD_INFO_TCO			BIT(29)
31#define MT_TXD_INFO_UCO			BIT(30)
32#define MT_TXD_INFO_ICO			BIT(31)
33
34#define MT_RX_FCE_INFO_LEN		GENMASK(13, 0)
35#define MT_RX_FCE_INFO_SELF_GEN		BIT(15)
36#define MT_RX_FCE_INFO_CMD_SEQ		GENMASK(19, 16)
37#define MT_RX_FCE_INFO_EVT_TYPE		GENMASK(23, 20)
38#define MT_RX_FCE_INFO_PCIE_INTR	BIT(24)
39#define MT_RX_FCE_INFO_QSEL		GENMASK(26, 25)
40#define MT_RX_FCE_INFO_D_PORT		GENMASK(29, 27)
41#define MT_RX_FCE_INFO_TYPE		GENMASK(31, 30)
42
43/* MCU request message header  */
44#define MT_MCU_MSG_LEN			GENMASK(15, 0)
45#define MT_MCU_MSG_CMD_SEQ		GENMASK(19, 16)
46#define MT_MCU_MSG_CMD_TYPE		GENMASK(26, 20)
47#define MT_MCU_MSG_PORT			GENMASK(29, 27)
48#define MT_MCU_MSG_TYPE			GENMASK(31, 30)
49#define MT_MCU_MSG_TYPE_CMD		BIT(30)
50
51enum mt76x2_qsel {
52	MT_QSEL_MGMT,
53	MT_QSEL_HCCA,
54	MT_QSEL_EDCA,
55	MT_QSEL_EDCA_2,
56};
57
58enum dma_msg_port {
59	WLAN_PORT,
60	CPU_RX_PORT,
61	CPU_TX_PORT,
62	HOST_PORT,
63	VIRTUAL_CPU_RX_PORT,
64	VIRTUAL_CPU_TX_PORT,
65	DISCARD,
66};
67
68#endif