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1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <linux/pci.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/bitops.h>
23
24#include "core.h"
25#include "debug.h"
26#include "coredump.h"
27
28#include "targaddrs.h"
29#include "bmi.h"
30
31#include "hif.h"
32#include "htc.h"
33
34#include "ce.h"
35#include "pci.h"
36
37enum ath10k_pci_reset_mode {
38 ATH10K_PCI_RESET_AUTO = 0,
39 ATH10K_PCI_RESET_WARM_ONLY = 1,
40};
41
42static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
43static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
44
45module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
46MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
47
48module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
49MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
50
51/* how long wait to wait for target to initialise, in ms */
52#define ATH10K_PCI_TARGET_WAIT 3000
53#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
54
55/* Maximum number of bytes that can be handled atomically by
56 * diag read and write.
57 */
58#define ATH10K_DIAG_TRANSFER_LIMIT 0x5000
59
60#define QCA99X0_PCIE_BAR0_START_REG 0x81030
61#define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c
62#define QCA99X0_CPU_MEM_DATA_REG 0x4d010
63
64static const struct pci_device_id ath10k_pci_id_table[] = {
65 /* PCI-E QCA988X V2 (Ubiquiti branded) */
66 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) },
67
68 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
69 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
70 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
71 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
72 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
73 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
74 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
75 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
76 {0}
77};
78
79static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
80 /* QCA988X pre 2.0 chips are not supported because they need some nasty
81 * hacks. ath10k doesn't have them and these devices crash horribly
82 * because of that.
83 */
84 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV },
85 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
86
87 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
88 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
89 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
90 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
91 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
92
93 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
94 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
95 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
96 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
97 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
98
99 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
100
101 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },
102
103 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV },
104
105 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
106 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
107
108 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV },
109};
110
111static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
112static int ath10k_pci_cold_reset(struct ath10k *ar);
113static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
114static int ath10k_pci_init_irq(struct ath10k *ar);
115static int ath10k_pci_deinit_irq(struct ath10k *ar);
116static int ath10k_pci_request_irq(struct ath10k *ar);
117static void ath10k_pci_free_irq(struct ath10k *ar);
118static int ath10k_pci_bmi_wait(struct ath10k *ar,
119 struct ath10k_ce_pipe *tx_pipe,
120 struct ath10k_ce_pipe *rx_pipe,
121 struct bmi_xfer *xfer);
122static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
123static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
124static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
125static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
126static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
127static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
128static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
129
130static struct ce_attr host_ce_config_wlan[] = {
131 /* CE0: host->target HTC control and raw streams */
132 {
133 .flags = CE_ATTR_FLAGS,
134 .src_nentries = 16,
135 .src_sz_max = 256,
136 .dest_nentries = 0,
137 .send_cb = ath10k_pci_htc_tx_cb,
138 },
139
140 /* CE1: target->host HTT + HTC control */
141 {
142 .flags = CE_ATTR_FLAGS,
143 .src_nentries = 0,
144 .src_sz_max = 2048,
145 .dest_nentries = 512,
146 .recv_cb = ath10k_pci_htt_htc_rx_cb,
147 },
148
149 /* CE2: target->host WMI */
150 {
151 .flags = CE_ATTR_FLAGS,
152 .src_nentries = 0,
153 .src_sz_max = 2048,
154 .dest_nentries = 128,
155 .recv_cb = ath10k_pci_htc_rx_cb,
156 },
157
158 /* CE3: host->target WMI */
159 {
160 .flags = CE_ATTR_FLAGS,
161 .src_nentries = 32,
162 .src_sz_max = 2048,
163 .dest_nentries = 0,
164 .send_cb = ath10k_pci_htc_tx_cb,
165 },
166
167 /* CE4: host->target HTT */
168 {
169 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
170 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
171 .src_sz_max = 256,
172 .dest_nentries = 0,
173 .send_cb = ath10k_pci_htt_tx_cb,
174 },
175
176 /* CE5: target->host HTT (HIF->HTT) */
177 {
178 .flags = CE_ATTR_FLAGS,
179 .src_nentries = 0,
180 .src_sz_max = 512,
181 .dest_nentries = 512,
182 .recv_cb = ath10k_pci_htt_rx_cb,
183 },
184
185 /* CE6: target autonomous hif_memcpy */
186 {
187 .flags = CE_ATTR_FLAGS,
188 .src_nentries = 0,
189 .src_sz_max = 0,
190 .dest_nentries = 0,
191 },
192
193 /* CE7: ce_diag, the Diagnostic Window */
194 {
195 .flags = CE_ATTR_FLAGS,
196 .src_nentries = 2,
197 .src_sz_max = DIAG_TRANSFER_LIMIT,
198 .dest_nentries = 2,
199 },
200
201 /* CE8: target->host pktlog */
202 {
203 .flags = CE_ATTR_FLAGS,
204 .src_nentries = 0,
205 .src_sz_max = 2048,
206 .dest_nentries = 128,
207 .recv_cb = ath10k_pci_pktlog_rx_cb,
208 },
209
210 /* CE9 target autonomous qcache memcpy */
211 {
212 .flags = CE_ATTR_FLAGS,
213 .src_nentries = 0,
214 .src_sz_max = 0,
215 .dest_nentries = 0,
216 },
217
218 /* CE10: target autonomous hif memcpy */
219 {
220 .flags = CE_ATTR_FLAGS,
221 .src_nentries = 0,
222 .src_sz_max = 0,
223 .dest_nentries = 0,
224 },
225
226 /* CE11: target autonomous hif memcpy */
227 {
228 .flags = CE_ATTR_FLAGS,
229 .src_nentries = 0,
230 .src_sz_max = 0,
231 .dest_nentries = 0,
232 },
233};
234
235/* Target firmware's Copy Engine configuration. */
236static struct ce_pipe_config target_ce_config_wlan[] = {
237 /* CE0: host->target HTC control and raw streams */
238 {
239 .pipenum = __cpu_to_le32(0),
240 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
241 .nentries = __cpu_to_le32(32),
242 .nbytes_max = __cpu_to_le32(256),
243 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
244 .reserved = __cpu_to_le32(0),
245 },
246
247 /* CE1: target->host HTT + HTC control */
248 {
249 .pipenum = __cpu_to_le32(1),
250 .pipedir = __cpu_to_le32(PIPEDIR_IN),
251 .nentries = __cpu_to_le32(32),
252 .nbytes_max = __cpu_to_le32(2048),
253 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
254 .reserved = __cpu_to_le32(0),
255 },
256
257 /* CE2: target->host WMI */
258 {
259 .pipenum = __cpu_to_le32(2),
260 .pipedir = __cpu_to_le32(PIPEDIR_IN),
261 .nentries = __cpu_to_le32(64),
262 .nbytes_max = __cpu_to_le32(2048),
263 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
264 .reserved = __cpu_to_le32(0),
265 },
266
267 /* CE3: host->target WMI */
268 {
269 .pipenum = __cpu_to_le32(3),
270 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
271 .nentries = __cpu_to_le32(32),
272 .nbytes_max = __cpu_to_le32(2048),
273 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
274 .reserved = __cpu_to_le32(0),
275 },
276
277 /* CE4: host->target HTT */
278 {
279 .pipenum = __cpu_to_le32(4),
280 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
281 .nentries = __cpu_to_le32(256),
282 .nbytes_max = __cpu_to_le32(256),
283 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
284 .reserved = __cpu_to_le32(0),
285 },
286
287 /* NB: 50% of src nentries, since tx has 2 frags */
288
289 /* CE5: target->host HTT (HIF->HTT) */
290 {
291 .pipenum = __cpu_to_le32(5),
292 .pipedir = __cpu_to_le32(PIPEDIR_IN),
293 .nentries = __cpu_to_le32(32),
294 .nbytes_max = __cpu_to_le32(512),
295 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
296 .reserved = __cpu_to_le32(0),
297 },
298
299 /* CE6: Reserved for target autonomous hif_memcpy */
300 {
301 .pipenum = __cpu_to_le32(6),
302 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
303 .nentries = __cpu_to_le32(32),
304 .nbytes_max = __cpu_to_le32(4096),
305 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
306 .reserved = __cpu_to_le32(0),
307 },
308
309 /* CE7 used only by Host */
310 {
311 .pipenum = __cpu_to_le32(7),
312 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
313 .nentries = __cpu_to_le32(0),
314 .nbytes_max = __cpu_to_le32(0),
315 .flags = __cpu_to_le32(0),
316 .reserved = __cpu_to_le32(0),
317 },
318
319 /* CE8 target->host packtlog */
320 {
321 .pipenum = __cpu_to_le32(8),
322 .pipedir = __cpu_to_le32(PIPEDIR_IN),
323 .nentries = __cpu_to_le32(64),
324 .nbytes_max = __cpu_to_le32(2048),
325 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
326 .reserved = __cpu_to_le32(0),
327 },
328
329 /* CE9 target autonomous qcache memcpy */
330 {
331 .pipenum = __cpu_to_le32(9),
332 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
333 .nentries = __cpu_to_le32(32),
334 .nbytes_max = __cpu_to_le32(2048),
335 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
336 .reserved = __cpu_to_le32(0),
337 },
338
339 /* It not necessary to send target wlan configuration for CE10 & CE11
340 * as these CEs are not actively used in target.
341 */
342};
343
344/*
345 * Map from service/endpoint to Copy Engine.
346 * This table is derived from the CE_PCI TABLE, above.
347 * It is passed to the Target at startup for use by firmware.
348 */
349static struct service_to_pipe target_service_to_ce_map_wlan[] = {
350 {
351 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
352 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
353 __cpu_to_le32(3),
354 },
355 {
356 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
357 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
358 __cpu_to_le32(2),
359 },
360 {
361 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
362 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
363 __cpu_to_le32(3),
364 },
365 {
366 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
367 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
368 __cpu_to_le32(2),
369 },
370 {
371 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
372 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
373 __cpu_to_le32(3),
374 },
375 {
376 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
377 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
378 __cpu_to_le32(2),
379 },
380 {
381 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
382 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
383 __cpu_to_le32(3),
384 },
385 {
386 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
387 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
388 __cpu_to_le32(2),
389 },
390 {
391 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
392 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
393 __cpu_to_le32(3),
394 },
395 {
396 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
397 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
398 __cpu_to_le32(2),
399 },
400 {
401 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
402 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
403 __cpu_to_le32(0),
404 },
405 {
406 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
407 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
408 __cpu_to_le32(1),
409 },
410 { /* not used */
411 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
412 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
413 __cpu_to_le32(0),
414 },
415 { /* not used */
416 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
417 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
418 __cpu_to_le32(1),
419 },
420 {
421 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
422 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
423 __cpu_to_le32(4),
424 },
425 {
426 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
427 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
428 __cpu_to_le32(5),
429 },
430
431 /* (Additions here) */
432
433 { /* must be last */
434 __cpu_to_le32(0),
435 __cpu_to_le32(0),
436 __cpu_to_le32(0),
437 },
438};
439
440static bool ath10k_pci_is_awake(struct ath10k *ar)
441{
442 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
443 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
444 RTC_STATE_ADDRESS);
445
446 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
447}
448
449static void __ath10k_pci_wake(struct ath10k *ar)
450{
451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
452
453 lockdep_assert_held(&ar_pci->ps_lock);
454
455 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
456 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
457
458 iowrite32(PCIE_SOC_WAKE_V_MASK,
459 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
460 PCIE_SOC_WAKE_ADDRESS);
461}
462
463static void __ath10k_pci_sleep(struct ath10k *ar)
464{
465 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
466
467 lockdep_assert_held(&ar_pci->ps_lock);
468
469 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
470 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
471
472 iowrite32(PCIE_SOC_WAKE_RESET,
473 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
474 PCIE_SOC_WAKE_ADDRESS);
475 ar_pci->ps_awake = false;
476}
477
478static int ath10k_pci_wake_wait(struct ath10k *ar)
479{
480 int tot_delay = 0;
481 int curr_delay = 5;
482
483 while (tot_delay < PCIE_WAKE_TIMEOUT) {
484 if (ath10k_pci_is_awake(ar)) {
485 if (tot_delay > PCIE_WAKE_LATE_US)
486 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n",
487 tot_delay / 1000);
488 return 0;
489 }
490
491 udelay(curr_delay);
492 tot_delay += curr_delay;
493
494 if (curr_delay < 50)
495 curr_delay += 5;
496 }
497
498 return -ETIMEDOUT;
499}
500
501static int ath10k_pci_force_wake(struct ath10k *ar)
502{
503 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
504 unsigned long flags;
505 int ret = 0;
506
507 if (ar_pci->pci_ps)
508 return ret;
509
510 spin_lock_irqsave(&ar_pci->ps_lock, flags);
511
512 if (!ar_pci->ps_awake) {
513 iowrite32(PCIE_SOC_WAKE_V_MASK,
514 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
515 PCIE_SOC_WAKE_ADDRESS);
516
517 ret = ath10k_pci_wake_wait(ar);
518 if (ret == 0)
519 ar_pci->ps_awake = true;
520 }
521
522 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
523
524 return ret;
525}
526
527static void ath10k_pci_force_sleep(struct ath10k *ar)
528{
529 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
530 unsigned long flags;
531
532 spin_lock_irqsave(&ar_pci->ps_lock, flags);
533
534 iowrite32(PCIE_SOC_WAKE_RESET,
535 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
536 PCIE_SOC_WAKE_ADDRESS);
537 ar_pci->ps_awake = false;
538
539 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
540}
541
542static int ath10k_pci_wake(struct ath10k *ar)
543{
544 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
545 unsigned long flags;
546 int ret = 0;
547
548 if (ar_pci->pci_ps == 0)
549 return ret;
550
551 spin_lock_irqsave(&ar_pci->ps_lock, flags);
552
553 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
554 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
555
556 /* This function can be called very frequently. To avoid excessive
557 * CPU stalls for MMIO reads use a cache var to hold the device state.
558 */
559 if (!ar_pci->ps_awake) {
560 __ath10k_pci_wake(ar);
561
562 ret = ath10k_pci_wake_wait(ar);
563 if (ret == 0)
564 ar_pci->ps_awake = true;
565 }
566
567 if (ret == 0) {
568 ar_pci->ps_wake_refcount++;
569 WARN_ON(ar_pci->ps_wake_refcount == 0);
570 }
571
572 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
573
574 return ret;
575}
576
577static void ath10k_pci_sleep(struct ath10k *ar)
578{
579 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
580 unsigned long flags;
581
582 if (ar_pci->pci_ps == 0)
583 return;
584
585 spin_lock_irqsave(&ar_pci->ps_lock, flags);
586
587 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
588 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
589
590 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
591 goto skip;
592
593 ar_pci->ps_wake_refcount--;
594
595 mod_timer(&ar_pci->ps_timer, jiffies +
596 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
597
598skip:
599 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
600}
601
602static void ath10k_pci_ps_timer(struct timer_list *t)
603{
604 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, ps_timer);
605 struct ath10k *ar = ar_pci->ar;
606 unsigned long flags;
607
608 spin_lock_irqsave(&ar_pci->ps_lock, flags);
609
610 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
611 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
612
613 if (ar_pci->ps_wake_refcount > 0)
614 goto skip;
615
616 __ath10k_pci_sleep(ar);
617
618skip:
619 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
620}
621
622static void ath10k_pci_sleep_sync(struct ath10k *ar)
623{
624 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
625 unsigned long flags;
626
627 if (ar_pci->pci_ps == 0) {
628 ath10k_pci_force_sleep(ar);
629 return;
630 }
631
632 del_timer_sync(&ar_pci->ps_timer);
633
634 spin_lock_irqsave(&ar_pci->ps_lock, flags);
635 WARN_ON(ar_pci->ps_wake_refcount > 0);
636 __ath10k_pci_sleep(ar);
637 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
638}
639
640static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
641{
642 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
643 int ret;
644
645 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
646 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
647 offset, offset + sizeof(value), ar_pci->mem_len);
648 return;
649 }
650
651 ret = ath10k_pci_wake(ar);
652 if (ret) {
653 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
654 value, offset, ret);
655 return;
656 }
657
658 iowrite32(value, ar_pci->mem + offset);
659 ath10k_pci_sleep(ar);
660}
661
662static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
663{
664 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
665 u32 val;
666 int ret;
667
668 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
669 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
670 offset, offset + sizeof(val), ar_pci->mem_len);
671 return 0;
672 }
673
674 ret = ath10k_pci_wake(ar);
675 if (ret) {
676 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
677 offset, ret);
678 return 0xffffffff;
679 }
680
681 val = ioread32(ar_pci->mem + offset);
682 ath10k_pci_sleep(ar);
683
684 return val;
685}
686
687inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
688{
689 struct ath10k_ce *ce = ath10k_ce_priv(ar);
690
691 ce->bus_ops->write32(ar, offset, value);
692}
693
694inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
695{
696 struct ath10k_ce *ce = ath10k_ce_priv(ar);
697
698 return ce->bus_ops->read32(ar, offset);
699}
700
701u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
702{
703 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
704}
705
706void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
707{
708 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
709}
710
711u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
712{
713 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
714}
715
716void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
717{
718 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
719}
720
721bool ath10k_pci_irq_pending(struct ath10k *ar)
722{
723 u32 cause;
724
725 /* Check if the shared legacy irq is for us */
726 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
727 PCIE_INTR_CAUSE_ADDRESS);
728 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
729 return true;
730
731 return false;
732}
733
734void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
735{
736 /* IMPORTANT: INTR_CLR register has to be set after
737 * INTR_ENABLE is set to 0, otherwise interrupt can not be
738 * really cleared.
739 */
740 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
741 0);
742 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
743 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
744
745 /* IMPORTANT: this extra read transaction is required to
746 * flush the posted write buffer.
747 */
748 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
749 PCIE_INTR_ENABLE_ADDRESS);
750}
751
752void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
753{
754 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
755 PCIE_INTR_ENABLE_ADDRESS,
756 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
757
758 /* IMPORTANT: this extra read transaction is required to
759 * flush the posted write buffer.
760 */
761 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
762 PCIE_INTR_ENABLE_ADDRESS);
763}
764
765static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
766{
767 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
768
769 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI)
770 return "msi";
771
772 return "legacy";
773}
774
775static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
776{
777 struct ath10k *ar = pipe->hif_ce_state;
778 struct ath10k_ce *ce = ath10k_ce_priv(ar);
779 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
780 struct sk_buff *skb;
781 dma_addr_t paddr;
782 int ret;
783
784 skb = dev_alloc_skb(pipe->buf_sz);
785 if (!skb)
786 return -ENOMEM;
787
788 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
789
790 paddr = dma_map_single(ar->dev, skb->data,
791 skb->len + skb_tailroom(skb),
792 DMA_FROM_DEVICE);
793 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
794 ath10k_warn(ar, "failed to dma map pci rx buf\n");
795 dev_kfree_skb_any(skb);
796 return -EIO;
797 }
798
799 ATH10K_SKB_RXCB(skb)->paddr = paddr;
800
801 spin_lock_bh(&ce->ce_lock);
802 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
803 spin_unlock_bh(&ce->ce_lock);
804 if (ret) {
805 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
806 DMA_FROM_DEVICE);
807 dev_kfree_skb_any(skb);
808 return ret;
809 }
810
811 return 0;
812}
813
814static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
815{
816 struct ath10k *ar = pipe->hif_ce_state;
817 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
818 struct ath10k_ce *ce = ath10k_ce_priv(ar);
819 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
820 int ret, num;
821
822 if (pipe->buf_sz == 0)
823 return;
824
825 if (!ce_pipe->dest_ring)
826 return;
827
828 spin_lock_bh(&ce->ce_lock);
829 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
830 spin_unlock_bh(&ce->ce_lock);
831
832 while (num >= 0) {
833 ret = __ath10k_pci_rx_post_buf(pipe);
834 if (ret) {
835 if (ret == -ENOSPC)
836 break;
837 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
838 mod_timer(&ar_pci->rx_post_retry, jiffies +
839 ATH10K_PCI_RX_POST_RETRY_MS);
840 break;
841 }
842 num--;
843 }
844}
845
846void ath10k_pci_rx_post(struct ath10k *ar)
847{
848 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
849 int i;
850
851 for (i = 0; i < CE_COUNT; i++)
852 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
853}
854
855void ath10k_pci_rx_replenish_retry(struct timer_list *t)
856{
857 struct ath10k_pci *ar_pci = from_timer(ar_pci, t, rx_post_retry);
858 struct ath10k *ar = ar_pci->ar;
859
860 ath10k_pci_rx_post(ar);
861}
862
863static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
864{
865 u32 val = 0, region = addr & 0xfffff;
866
867 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
868 & 0x7ff) << 21;
869 val |= 0x100000 | region;
870 return val;
871}
872
873static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
874{
875 u32 val = 0, region = addr & 0xfffff;
876
877 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
878 val |= 0x100000 | region;
879 return val;
880}
881
882static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
883{
884 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
885
886 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr))
887 return -ENOTSUPP;
888
889 return ar_pci->targ_cpu_to_ce_addr(ar, addr);
890}
891
892/*
893 * Diagnostic read/write access is provided for startup/config/debug usage.
894 * Caller must guarantee proper alignment, when applicable, and single user
895 * at any moment.
896 */
897static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
898 int nbytes)
899{
900 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
901 struct ath10k_ce *ce = ath10k_ce_priv(ar);
902 int ret = 0;
903 u32 *buf;
904 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
905 struct ath10k_ce_pipe *ce_diag;
906 /* Host buffer address in CE space */
907 u32 ce_data;
908 dma_addr_t ce_data_base = 0;
909 void *data_buf = NULL;
910 int i;
911
912 spin_lock_bh(&ce->ce_lock);
913
914 ce_diag = ar_pci->ce_diag;
915
916 /*
917 * Allocate a temporary bounce buffer to hold caller's data
918 * to be DMA'ed from Target. This guarantees
919 * 1) 4-byte alignment
920 * 2) Buffer in DMA-able space
921 */
922 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
923
924 data_buf = (unsigned char *)dma_zalloc_coherent(ar->dev,
925 alloc_nbytes,
926 &ce_data_base,
927 GFP_ATOMIC);
928
929 if (!data_buf) {
930 ret = -ENOMEM;
931 goto done;
932 }
933
934 remaining_bytes = nbytes;
935 ce_data = ce_data_base;
936 while (remaining_bytes) {
937 nbytes = min_t(unsigned int, remaining_bytes,
938 DIAG_TRANSFER_LIMIT);
939
940 ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &ce_data, ce_data);
941 if (ret != 0)
942 goto done;
943
944 /* Request CE to send from Target(!) address to Host buffer */
945 /*
946 * The address supplied by the caller is in the
947 * Target CPU virtual address space.
948 *
949 * In order to use this address with the diagnostic CE,
950 * convert it from Target CPU virtual address space
951 * to CE address space
952 */
953 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
954
955 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
956 0);
957 if (ret)
958 goto done;
959
960 i = 0;
961 while (ath10k_ce_completed_send_next_nolock(ce_diag,
962 NULL) != 0) {
963 mdelay(1);
964 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
965 ret = -EBUSY;
966 goto done;
967 }
968 }
969
970 i = 0;
971 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
972 (void **)&buf,
973 &completed_nbytes)
974 != 0) {
975 mdelay(1);
976
977 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
978 ret = -EBUSY;
979 goto done;
980 }
981 }
982
983 if (nbytes != completed_nbytes) {
984 ret = -EIO;
985 goto done;
986 }
987
988 if (*buf != ce_data) {
989 ret = -EIO;
990 goto done;
991 }
992
993 remaining_bytes -= nbytes;
994 memcpy(data, data_buf, nbytes);
995
996 address += nbytes;
997 data += nbytes;
998 }
999
1000done:
1001
1002 if (data_buf)
1003 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1004 ce_data_base);
1005
1006 spin_unlock_bh(&ce->ce_lock);
1007
1008 return ret;
1009}
1010
1011static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
1012{
1013 __le32 val = 0;
1014 int ret;
1015
1016 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
1017 *value = __le32_to_cpu(val);
1018
1019 return ret;
1020}
1021
1022static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
1023 u32 src, u32 len)
1024{
1025 u32 host_addr, addr;
1026 int ret;
1027
1028 host_addr = host_interest_item_address(src);
1029
1030 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1031 if (ret != 0) {
1032 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1033 src, ret);
1034 return ret;
1035 }
1036
1037 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1038 if (ret != 0) {
1039 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1040 addr, len, ret);
1041 return ret;
1042 }
1043
1044 return 0;
1045}
1046
1047#define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1048 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1049
1050int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1051 const void *data, int nbytes)
1052{
1053 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1054 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1055 int ret = 0;
1056 u32 *buf;
1057 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
1058 struct ath10k_ce_pipe *ce_diag;
1059 void *data_buf = NULL;
1060 u32 ce_data; /* Host buffer address in CE space */
1061 dma_addr_t ce_data_base = 0;
1062 int i;
1063
1064 spin_lock_bh(&ce->ce_lock);
1065
1066 ce_diag = ar_pci->ce_diag;
1067
1068 /*
1069 * Allocate a temporary bounce buffer to hold caller's data
1070 * to be DMA'ed to Target. This guarantees
1071 * 1) 4-byte alignment
1072 * 2) Buffer in DMA-able space
1073 */
1074 orig_nbytes = nbytes;
1075 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
1076 orig_nbytes,
1077 &ce_data_base,
1078 GFP_ATOMIC);
1079 if (!data_buf) {
1080 ret = -ENOMEM;
1081 goto done;
1082 }
1083
1084 /* Copy caller's data to allocated DMA buf */
1085 memcpy(data_buf, data, orig_nbytes);
1086
1087 /*
1088 * The address supplied by the caller is in the
1089 * Target CPU virtual address space.
1090 *
1091 * In order to use this address with the diagnostic CE,
1092 * convert it from
1093 * Target CPU virtual address space
1094 * to
1095 * CE address space
1096 */
1097 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1098
1099 remaining_bytes = orig_nbytes;
1100 ce_data = ce_data_base;
1101 while (remaining_bytes) {
1102 /* FIXME: check cast */
1103 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1104
1105 /* Set up to receive directly into Target(!) address */
1106 ret = ce_diag->ops->ce_rx_post_buf(ce_diag, &address, address);
1107 if (ret != 0)
1108 goto done;
1109
1110 /*
1111 * Request CE to send caller-supplied data that
1112 * was copied to bounce buffer to Target(!) address.
1113 */
1114 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
1115 nbytes, 0, 0);
1116 if (ret != 0)
1117 goto done;
1118
1119 i = 0;
1120 while (ath10k_ce_completed_send_next_nolock(ce_diag,
1121 NULL) != 0) {
1122 mdelay(1);
1123
1124 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1125 ret = -EBUSY;
1126 goto done;
1127 }
1128 }
1129
1130 i = 0;
1131 while (ath10k_ce_completed_recv_next_nolock(ce_diag,
1132 (void **)&buf,
1133 &completed_nbytes)
1134 != 0) {
1135 mdelay(1);
1136
1137 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
1138 ret = -EBUSY;
1139 goto done;
1140 }
1141 }
1142
1143 if (nbytes != completed_nbytes) {
1144 ret = -EIO;
1145 goto done;
1146 }
1147
1148 if (*buf != address) {
1149 ret = -EIO;
1150 goto done;
1151 }
1152
1153 remaining_bytes -= nbytes;
1154 address += nbytes;
1155 ce_data += nbytes;
1156 }
1157
1158done:
1159 if (data_buf) {
1160 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
1161 ce_data_base);
1162 }
1163
1164 if (ret != 0)
1165 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1166 address, ret);
1167
1168 spin_unlock_bh(&ce->ce_lock);
1169
1170 return ret;
1171}
1172
1173static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1174{
1175 __le32 val = __cpu_to_le32(value);
1176
1177 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1178}
1179
1180/* Called by lower (CE) layer when a send to Target completes. */
1181static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1182{
1183 struct ath10k *ar = ce_state->ar;
1184 struct sk_buff_head list;
1185 struct sk_buff *skb;
1186
1187 __skb_queue_head_init(&list);
1188 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1189 /* no need to call tx completion for NULL pointers */
1190 if (skb == NULL)
1191 continue;
1192
1193 __skb_queue_tail(&list, skb);
1194 }
1195
1196 while ((skb = __skb_dequeue(&list)))
1197 ath10k_htc_tx_completion_handler(ar, skb);
1198}
1199
1200static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1201 void (*callback)(struct ath10k *ar,
1202 struct sk_buff *skb))
1203{
1204 struct ath10k *ar = ce_state->ar;
1205 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1206 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1207 struct sk_buff *skb;
1208 struct sk_buff_head list;
1209 void *transfer_context;
1210 unsigned int nbytes, max_nbytes;
1211
1212 __skb_queue_head_init(&list);
1213 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1214 &nbytes) == 0) {
1215 skb = transfer_context;
1216 max_nbytes = skb->len + skb_tailroom(skb);
1217 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1218 max_nbytes, DMA_FROM_DEVICE);
1219
1220 if (unlikely(max_nbytes < nbytes)) {
1221 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1222 nbytes, max_nbytes);
1223 dev_kfree_skb_any(skb);
1224 continue;
1225 }
1226
1227 skb_put(skb, nbytes);
1228 __skb_queue_tail(&list, skb);
1229 }
1230
1231 while ((skb = __skb_dequeue(&list))) {
1232 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1233 ce_state->id, skb->len);
1234 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1235 skb->data, skb->len);
1236
1237 callback(ar, skb);
1238 }
1239
1240 ath10k_pci_rx_post_pipe(pipe_info);
1241}
1242
1243static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state,
1244 void (*callback)(struct ath10k *ar,
1245 struct sk_buff *skb))
1246{
1247 struct ath10k *ar = ce_state->ar;
1248 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1249 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1250 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl;
1251 struct sk_buff *skb;
1252 struct sk_buff_head list;
1253 void *transfer_context;
1254 unsigned int nbytes, max_nbytes, nentries;
1255 int orig_len;
1256
1257 /* No need to aquire ce_lock for CE5, since this is the only place CE5
1258 * is processed other than init and deinit. Before releasing CE5
1259 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1260 */
1261 __skb_queue_head_init(&list);
1262 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context,
1263 &nbytes) == 0) {
1264 skb = transfer_context;
1265 max_nbytes = skb->len + skb_tailroom(skb);
1266
1267 if (unlikely(max_nbytes < nbytes)) {
1268 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1269 nbytes, max_nbytes);
1270 continue;
1271 }
1272
1273 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1274 max_nbytes, DMA_FROM_DEVICE);
1275 skb_put(skb, nbytes);
1276 __skb_queue_tail(&list, skb);
1277 }
1278
1279 nentries = skb_queue_len(&list);
1280 while ((skb = __skb_dequeue(&list))) {
1281 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1282 ce_state->id, skb->len);
1283 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1284 skb->data, skb->len);
1285
1286 orig_len = skb->len;
1287 callback(ar, skb);
1288 skb_push(skb, orig_len - skb->len);
1289 skb_reset_tail_pointer(skb);
1290 skb_trim(skb, 0);
1291
1292 /*let device gain the buffer again*/
1293 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1294 skb->len + skb_tailroom(skb),
1295 DMA_FROM_DEVICE);
1296 }
1297 ath10k_ce_rx_update_write_idx(ce_pipe, nentries);
1298}
1299
1300/* Called by lower (CE) layer when data is received from the Target. */
1301static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1302{
1303 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1304}
1305
1306static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1307{
1308 /* CE4 polling needs to be done whenever CE pipe which transports
1309 * HTT Rx (target->host) is processed.
1310 */
1311 ath10k_ce_per_engine_service(ce_state->ar, 4);
1312
1313 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1314}
1315
1316/* Called by lower (CE) layer when data is received from the Target.
1317 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1318 */
1319static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1320{
1321 ath10k_pci_process_rx_cb(ce_state,
1322 ath10k_htt_rx_pktlog_completion_handler);
1323}
1324
1325/* Called by lower (CE) layer when a send to HTT Target completes. */
1326static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1327{
1328 struct ath10k *ar = ce_state->ar;
1329 struct sk_buff *skb;
1330
1331 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1332 /* no need to call tx completion for NULL pointers */
1333 if (!skb)
1334 continue;
1335
1336 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1337 skb->len, DMA_TO_DEVICE);
1338 ath10k_htt_hif_tx_complete(ar, skb);
1339 }
1340}
1341
1342static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1343{
1344 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1345 ath10k_htt_t2h_msg_handler(ar, skb);
1346}
1347
1348/* Called by lower (CE) layer when HTT data is received from the Target. */
1349static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1350{
1351 /* CE4 polling needs to be done whenever CE pipe which transports
1352 * HTT Rx (target->host) is processed.
1353 */
1354 ath10k_ce_per_engine_service(ce_state->ar, 4);
1355
1356 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1357}
1358
1359int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1360 struct ath10k_hif_sg_item *items, int n_items)
1361{
1362 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1363 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1364 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1365 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1366 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1367 unsigned int nentries_mask;
1368 unsigned int sw_index;
1369 unsigned int write_index;
1370 int err, i = 0;
1371
1372 spin_lock_bh(&ce->ce_lock);
1373
1374 nentries_mask = src_ring->nentries_mask;
1375 sw_index = src_ring->sw_index;
1376 write_index = src_ring->write_index;
1377
1378 if (unlikely(CE_RING_DELTA(nentries_mask,
1379 write_index, sw_index - 1) < n_items)) {
1380 err = -ENOBUFS;
1381 goto err;
1382 }
1383
1384 for (i = 0; i < n_items - 1; i++) {
1385 ath10k_dbg(ar, ATH10K_DBG_PCI,
1386 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1387 i, items[i].paddr, items[i].len, n_items);
1388 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1389 items[i].vaddr, items[i].len);
1390
1391 err = ath10k_ce_send_nolock(ce_pipe,
1392 items[i].transfer_context,
1393 items[i].paddr,
1394 items[i].len,
1395 items[i].transfer_id,
1396 CE_SEND_FLAG_GATHER);
1397 if (err)
1398 goto err;
1399 }
1400
1401 /* `i` is equal to `n_items -1` after for() */
1402
1403 ath10k_dbg(ar, ATH10K_DBG_PCI,
1404 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
1405 i, items[i].paddr, items[i].len, n_items);
1406 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1407 items[i].vaddr, items[i].len);
1408
1409 err = ath10k_ce_send_nolock(ce_pipe,
1410 items[i].transfer_context,
1411 items[i].paddr,
1412 items[i].len,
1413 items[i].transfer_id,
1414 0);
1415 if (err)
1416 goto err;
1417
1418 spin_unlock_bh(&ce->ce_lock);
1419 return 0;
1420
1421err:
1422 for (; i > 0; i--)
1423 __ath10k_ce_send_revert(ce_pipe);
1424
1425 spin_unlock_bh(&ce->ce_lock);
1426 return err;
1427}
1428
1429int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1430 size_t buf_len)
1431{
1432 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1433}
1434
1435u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1436{
1437 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1438
1439 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1440
1441 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1442}
1443
1444static void ath10k_pci_dump_registers(struct ath10k *ar,
1445 struct ath10k_fw_crash_data *crash_data)
1446{
1447 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1448 int i, ret;
1449
1450 lockdep_assert_held(&ar->data_lock);
1451
1452 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1453 hi_failure_state,
1454 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1455 if (ret) {
1456 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1457 return;
1458 }
1459
1460 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1461
1462 ath10k_err(ar, "firmware register dump:\n");
1463 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1464 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1465 i,
1466 __le32_to_cpu(reg_dump_values[i]),
1467 __le32_to_cpu(reg_dump_values[i + 1]),
1468 __le32_to_cpu(reg_dump_values[i + 2]),
1469 __le32_to_cpu(reg_dump_values[i + 3]));
1470
1471 if (!crash_data)
1472 return;
1473
1474 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1475 crash_data->registers[i] = reg_dump_values[i];
1476}
1477
1478static int ath10k_pci_dump_memory_section(struct ath10k *ar,
1479 const struct ath10k_mem_region *mem_region,
1480 u8 *buf, size_t buf_len)
1481{
1482 const struct ath10k_mem_section *cur_section, *next_section;
1483 unsigned int count, section_size, skip_size;
1484 int ret, i, j;
1485
1486 if (!mem_region || !buf)
1487 return 0;
1488
1489 cur_section = &mem_region->section_table.sections[0];
1490
1491 if (mem_region->start > cur_section->start) {
1492 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n",
1493 mem_region->start, cur_section->start);
1494 return 0;
1495 }
1496
1497 skip_size = cur_section->start - mem_region->start;
1498
1499 /* fill the gap between the first register section and register
1500 * start address
1501 */
1502 for (i = 0; i < skip_size; i++) {
1503 *buf = ATH10K_MAGIC_NOT_COPIED;
1504 buf++;
1505 }
1506
1507 count = 0;
1508
1509 for (i = 0; cur_section != NULL; i++) {
1510 section_size = cur_section->end - cur_section->start;
1511
1512 if (section_size <= 0) {
1513 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n",
1514 cur_section->start,
1515 cur_section->end);
1516 break;
1517 }
1518
1519 if ((i + 1) == mem_region->section_table.size) {
1520 /* last section */
1521 next_section = NULL;
1522 skip_size = 0;
1523 } else {
1524 next_section = cur_section + 1;
1525
1526 if (cur_section->end > next_section->start) {
1527 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n",
1528 next_section->start,
1529 cur_section->end);
1530 break;
1531 }
1532
1533 skip_size = next_section->start - cur_section->end;
1534 }
1535
1536 if (buf_len < (skip_size + section_size)) {
1537 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len);
1538 break;
1539 }
1540
1541 buf_len -= skip_size + section_size;
1542
1543 /* read section to dest memory */
1544 ret = ath10k_pci_diag_read_mem(ar, cur_section->start,
1545 buf, section_size);
1546 if (ret) {
1547 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n",
1548 cur_section->start, ret);
1549 break;
1550 }
1551
1552 buf += section_size;
1553 count += section_size;
1554
1555 /* fill in the gap between this section and the next */
1556 for (j = 0; j < skip_size; j++) {
1557 *buf = ATH10K_MAGIC_NOT_COPIED;
1558 buf++;
1559 }
1560
1561 count += skip_size;
1562
1563 if (!next_section)
1564 /* this was the last section */
1565 break;
1566
1567 cur_section = next_section;
1568 }
1569
1570 return count;
1571}
1572
1573static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config)
1574{
1575 u32 val;
1576
1577 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1578 FW_RAM_CONFIG_ADDRESS, config);
1579
1580 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1581 FW_RAM_CONFIG_ADDRESS);
1582 if (val != config) {
1583 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n",
1584 val, config);
1585 return -EIO;
1586 }
1587
1588 return 0;
1589}
1590
1591/* if an error happened returns < 0, otherwise the length */
1592static int ath10k_pci_dump_memory_sram(struct ath10k *ar,
1593 const struct ath10k_mem_region *region,
1594 u8 *buf)
1595{
1596 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1597 u32 base_addr, i;
1598
1599 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG);
1600 base_addr += region->start;
1601
1602 for (i = 0; i < region->len; i += 4) {
1603 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG);
1604 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG);
1605 }
1606
1607 return region->len;
1608}
1609
1610/* if an error happened returns < 0, otherwise the length */
1611static int ath10k_pci_dump_memory_reg(struct ath10k *ar,
1612 const struct ath10k_mem_region *region,
1613 u8 *buf)
1614{
1615 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1616 u32 i;
1617
1618 for (i = 0; i < region->len; i += 4)
1619 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i);
1620
1621 return region->len;
1622}
1623
1624/* if an error happened returns < 0, otherwise the length */
1625static int ath10k_pci_dump_memory_generic(struct ath10k *ar,
1626 const struct ath10k_mem_region *current_region,
1627 u8 *buf)
1628{
1629 int ret;
1630
1631 if (current_region->section_table.size > 0)
1632 /* Copy each section individually. */
1633 return ath10k_pci_dump_memory_section(ar,
1634 current_region,
1635 buf,
1636 current_region->len);
1637
1638 /* No individiual memory sections defined so we can
1639 * copy the entire memory region.
1640 */
1641 ret = ath10k_pci_diag_read_mem(ar,
1642 current_region->start,
1643 buf,
1644 current_region->len);
1645 if (ret) {
1646 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n",
1647 current_region->name, ret);
1648 return ret;
1649 }
1650
1651 return current_region->len;
1652}
1653
1654static void ath10k_pci_dump_memory(struct ath10k *ar,
1655 struct ath10k_fw_crash_data *crash_data)
1656{
1657 const struct ath10k_hw_mem_layout *mem_layout;
1658 const struct ath10k_mem_region *current_region;
1659 struct ath10k_dump_ram_data_hdr *hdr;
1660 u32 count, shift;
1661 size_t buf_len;
1662 int ret, i;
1663 u8 *buf;
1664
1665 lockdep_assert_held(&ar->data_lock);
1666
1667 if (!crash_data)
1668 return;
1669
1670 mem_layout = ath10k_coredump_get_mem_layout(ar);
1671 if (!mem_layout)
1672 return;
1673
1674 current_region = &mem_layout->region_table.regions[0];
1675
1676 buf = crash_data->ramdump_buf;
1677 buf_len = crash_data->ramdump_buf_len;
1678
1679 memset(buf, 0, buf_len);
1680
1681 for (i = 0; i < mem_layout->region_table.size; i++) {
1682 count = 0;
1683
1684 if (current_region->len > buf_len) {
1685 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n",
1686 current_region->name,
1687 current_region->len,
1688 buf_len);
1689 break;
1690 }
1691
1692 /* To get IRAM dump, the host driver needs to switch target
1693 * ram config from DRAM to IRAM.
1694 */
1695 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 ||
1696 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) {
1697 shift = current_region->start >> 20;
1698
1699 ret = ath10k_pci_set_ram_config(ar, shift);
1700 if (ret) {
1701 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n",
1702 current_region->name, ret);
1703 break;
1704 }
1705 }
1706
1707 /* Reserve space for the header. */
1708 hdr = (void *)buf;
1709 buf += sizeof(*hdr);
1710 buf_len -= sizeof(*hdr);
1711
1712 switch (current_region->type) {
1713 case ATH10K_MEM_REGION_TYPE_IOSRAM:
1714 count = ath10k_pci_dump_memory_sram(ar, current_region, buf);
1715 break;
1716 case ATH10K_MEM_REGION_TYPE_IOREG:
1717 count = ath10k_pci_dump_memory_reg(ar, current_region, buf);
1718 break;
1719 default:
1720 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf);
1721 if (ret < 0)
1722 break;
1723
1724 count = ret;
1725 break;
1726 }
1727
1728 hdr->region_type = cpu_to_le32(current_region->type);
1729 hdr->start = cpu_to_le32(current_region->start);
1730 hdr->length = cpu_to_le32(count);
1731
1732 if (count == 0)
1733 /* Note: the header remains, just with zero length. */
1734 break;
1735
1736 buf += count;
1737 buf_len -= count;
1738
1739 current_region++;
1740 }
1741}
1742
1743static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1744{
1745 struct ath10k_fw_crash_data *crash_data;
1746 char guid[UUID_STRING_LEN + 1];
1747
1748 spin_lock_bh(&ar->data_lock);
1749
1750 ar->stats.fw_crash_counter++;
1751
1752 crash_data = ath10k_coredump_new(ar);
1753
1754 if (crash_data)
1755 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1756 else
1757 scnprintf(guid, sizeof(guid), "n/a");
1758
1759 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1760 ath10k_print_driver_info(ar);
1761 ath10k_pci_dump_registers(ar, crash_data);
1762 ath10k_ce_dump_registers(ar, crash_data);
1763 ath10k_pci_dump_memory(ar, crash_data);
1764
1765 spin_unlock_bh(&ar->data_lock);
1766
1767 queue_work(ar->workqueue, &ar->restart_work);
1768}
1769
1770void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1771 int force)
1772{
1773 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1774
1775 if (!force) {
1776 int resources;
1777 /*
1778 * Decide whether to actually poll for completions, or just
1779 * wait for a later chance.
1780 * If there seem to be plenty of resources left, then just wait
1781 * since checking involves reading a CE register, which is a
1782 * relatively expensive operation.
1783 */
1784 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1785
1786 /*
1787 * If at least 50% of the total resources are still available,
1788 * don't bother checking again yet.
1789 */
1790 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1791 return;
1792 }
1793 ath10k_ce_per_engine_service(ar, pipe);
1794}
1795
1796static void ath10k_pci_rx_retry_sync(struct ath10k *ar)
1797{
1798 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1799
1800 del_timer_sync(&ar_pci->rx_post_retry);
1801}
1802
1803int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1804 u8 *ul_pipe, u8 *dl_pipe)
1805{
1806 const struct service_to_pipe *entry;
1807 bool ul_set = false, dl_set = false;
1808 int i;
1809
1810 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1811
1812 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1813 entry = &target_service_to_ce_map_wlan[i];
1814
1815 if (__le32_to_cpu(entry->service_id) != service_id)
1816 continue;
1817
1818 switch (__le32_to_cpu(entry->pipedir)) {
1819 case PIPEDIR_NONE:
1820 break;
1821 case PIPEDIR_IN:
1822 WARN_ON(dl_set);
1823 *dl_pipe = __le32_to_cpu(entry->pipenum);
1824 dl_set = true;
1825 break;
1826 case PIPEDIR_OUT:
1827 WARN_ON(ul_set);
1828 *ul_pipe = __le32_to_cpu(entry->pipenum);
1829 ul_set = true;
1830 break;
1831 case PIPEDIR_INOUT:
1832 WARN_ON(dl_set);
1833 WARN_ON(ul_set);
1834 *dl_pipe = __le32_to_cpu(entry->pipenum);
1835 *ul_pipe = __le32_to_cpu(entry->pipenum);
1836 dl_set = true;
1837 ul_set = true;
1838 break;
1839 }
1840 }
1841
1842 if (WARN_ON(!ul_set || !dl_set))
1843 return -ENOENT;
1844
1845 return 0;
1846}
1847
1848void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1849 u8 *ul_pipe, u8 *dl_pipe)
1850{
1851 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1852
1853 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1854 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1855 ul_pipe, dl_pipe);
1856}
1857
1858void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1859{
1860 u32 val;
1861
1862 switch (ar->hw_rev) {
1863 case ATH10K_HW_QCA988X:
1864 case ATH10K_HW_QCA9887:
1865 case ATH10K_HW_QCA6174:
1866 case ATH10K_HW_QCA9377:
1867 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1868 CORE_CTRL_ADDRESS);
1869 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1870 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1871 CORE_CTRL_ADDRESS, val);
1872 break;
1873 case ATH10K_HW_QCA99X0:
1874 case ATH10K_HW_QCA9984:
1875 case ATH10K_HW_QCA9888:
1876 case ATH10K_HW_QCA4019:
1877 /* TODO: Find appropriate register configuration for QCA99X0
1878 * to mask irq/MSI.
1879 */
1880 break;
1881 case ATH10K_HW_WCN3990:
1882 break;
1883 }
1884}
1885
1886static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1887{
1888 u32 val;
1889
1890 switch (ar->hw_rev) {
1891 case ATH10K_HW_QCA988X:
1892 case ATH10K_HW_QCA9887:
1893 case ATH10K_HW_QCA6174:
1894 case ATH10K_HW_QCA9377:
1895 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1896 CORE_CTRL_ADDRESS);
1897 val |= CORE_CTRL_PCIE_REG_31_MASK;
1898 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1899 CORE_CTRL_ADDRESS, val);
1900 break;
1901 case ATH10K_HW_QCA99X0:
1902 case ATH10K_HW_QCA9984:
1903 case ATH10K_HW_QCA9888:
1904 case ATH10K_HW_QCA4019:
1905 /* TODO: Find appropriate register configuration for QCA99X0
1906 * to unmask irq/MSI.
1907 */
1908 break;
1909 case ATH10K_HW_WCN3990:
1910 break;
1911 }
1912}
1913
1914static void ath10k_pci_irq_disable(struct ath10k *ar)
1915{
1916 ath10k_ce_disable_interrupts(ar);
1917 ath10k_pci_disable_and_clear_legacy_irq(ar);
1918 ath10k_pci_irq_msi_fw_mask(ar);
1919}
1920
1921static void ath10k_pci_irq_sync(struct ath10k *ar)
1922{
1923 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1924
1925 synchronize_irq(ar_pci->pdev->irq);
1926}
1927
1928static void ath10k_pci_irq_enable(struct ath10k *ar)
1929{
1930 ath10k_ce_enable_interrupts(ar);
1931 ath10k_pci_enable_legacy_irq(ar);
1932 ath10k_pci_irq_msi_fw_unmask(ar);
1933}
1934
1935static int ath10k_pci_hif_start(struct ath10k *ar)
1936{
1937 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1938
1939 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
1940
1941 napi_enable(&ar->napi);
1942
1943 ath10k_pci_irq_enable(ar);
1944 ath10k_pci_rx_post(ar);
1945
1946 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
1947 ar_pci->link_ctl);
1948
1949 return 0;
1950}
1951
1952static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1953{
1954 struct ath10k *ar;
1955 struct ath10k_ce_pipe *ce_pipe;
1956 struct ath10k_ce_ring *ce_ring;
1957 struct sk_buff *skb;
1958 int i;
1959
1960 ar = pci_pipe->hif_ce_state;
1961 ce_pipe = pci_pipe->ce_hdl;
1962 ce_ring = ce_pipe->dest_ring;
1963
1964 if (!ce_ring)
1965 return;
1966
1967 if (!pci_pipe->buf_sz)
1968 return;
1969
1970 for (i = 0; i < ce_ring->nentries; i++) {
1971 skb = ce_ring->per_transfer_context[i];
1972 if (!skb)
1973 continue;
1974
1975 ce_ring->per_transfer_context[i] = NULL;
1976
1977 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1978 skb->len + skb_tailroom(skb),
1979 DMA_FROM_DEVICE);
1980 dev_kfree_skb_any(skb);
1981 }
1982}
1983
1984static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
1985{
1986 struct ath10k *ar;
1987 struct ath10k_ce_pipe *ce_pipe;
1988 struct ath10k_ce_ring *ce_ring;
1989 struct sk_buff *skb;
1990 int i;
1991
1992 ar = pci_pipe->hif_ce_state;
1993 ce_pipe = pci_pipe->ce_hdl;
1994 ce_ring = ce_pipe->src_ring;
1995
1996 if (!ce_ring)
1997 return;
1998
1999 if (!pci_pipe->buf_sz)
2000 return;
2001
2002 for (i = 0; i < ce_ring->nentries; i++) {
2003 skb = ce_ring->per_transfer_context[i];
2004 if (!skb)
2005 continue;
2006
2007 ce_ring->per_transfer_context[i] = NULL;
2008
2009 ath10k_htc_tx_completion_handler(ar, skb);
2010 }
2011}
2012
2013/*
2014 * Cleanup residual buffers for device shutdown:
2015 * buffers that were enqueued for receive
2016 * buffers that were to be sent
2017 * Note: Buffers that had completed but which were
2018 * not yet processed are on a completion queue. They
2019 * are handled when the completion thread shuts down.
2020 */
2021static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
2022{
2023 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2024 int pipe_num;
2025
2026 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
2027 struct ath10k_pci_pipe *pipe_info;
2028
2029 pipe_info = &ar_pci->pipe_info[pipe_num];
2030 ath10k_pci_rx_pipe_cleanup(pipe_info);
2031 ath10k_pci_tx_pipe_cleanup(pipe_info);
2032 }
2033}
2034
2035void ath10k_pci_ce_deinit(struct ath10k *ar)
2036{
2037 int i;
2038
2039 for (i = 0; i < CE_COUNT; i++)
2040 ath10k_ce_deinit_pipe(ar, i);
2041}
2042
2043void ath10k_pci_flush(struct ath10k *ar)
2044{
2045 ath10k_pci_rx_retry_sync(ar);
2046 ath10k_pci_buffer_cleanup(ar);
2047}
2048
2049static void ath10k_pci_hif_stop(struct ath10k *ar)
2050{
2051 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2052 unsigned long flags;
2053
2054 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
2055
2056 /* Most likely the device has HTT Rx ring configured. The only way to
2057 * prevent the device from accessing (and possible corrupting) host
2058 * memory is to reset the chip now.
2059 *
2060 * There's also no known way of masking MSI interrupts on the device.
2061 * For ranged MSI the CE-related interrupts can be masked. However
2062 * regardless how many MSI interrupts are assigned the first one
2063 * is always used for firmware indications (crashes) and cannot be
2064 * masked. To prevent the device from asserting the interrupt reset it
2065 * before proceeding with cleanup.
2066 */
2067 ath10k_pci_safe_chip_reset(ar);
2068
2069 ath10k_pci_irq_disable(ar);
2070 ath10k_pci_irq_sync(ar);
2071 ath10k_pci_flush(ar);
2072 napi_synchronize(&ar->napi);
2073 napi_disable(&ar->napi);
2074
2075 spin_lock_irqsave(&ar_pci->ps_lock, flags);
2076 WARN_ON(ar_pci->ps_wake_refcount > 0);
2077 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
2078}
2079
2080int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
2081 void *req, u32 req_len,
2082 void *resp, u32 *resp_len)
2083{
2084 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2085 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
2086 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
2087 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
2088 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
2089 dma_addr_t req_paddr = 0;
2090 dma_addr_t resp_paddr = 0;
2091 struct bmi_xfer xfer = {};
2092 void *treq, *tresp = NULL;
2093 int ret = 0;
2094
2095 might_sleep();
2096
2097 if (resp && !resp_len)
2098 return -EINVAL;
2099
2100 if (resp && resp_len && *resp_len == 0)
2101 return -EINVAL;
2102
2103 treq = kmemdup(req, req_len, GFP_KERNEL);
2104 if (!treq)
2105 return -ENOMEM;
2106
2107 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
2108 ret = dma_mapping_error(ar->dev, req_paddr);
2109 if (ret) {
2110 ret = -EIO;
2111 goto err_dma;
2112 }
2113
2114 if (resp && resp_len) {
2115 tresp = kzalloc(*resp_len, GFP_KERNEL);
2116 if (!tresp) {
2117 ret = -ENOMEM;
2118 goto err_req;
2119 }
2120
2121 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
2122 DMA_FROM_DEVICE);
2123 ret = dma_mapping_error(ar->dev, resp_paddr);
2124 if (ret) {
2125 ret = -EIO;
2126 goto err_req;
2127 }
2128
2129 xfer.wait_for_resp = true;
2130 xfer.resp_len = 0;
2131
2132 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
2133 }
2134
2135 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
2136 if (ret)
2137 goto err_resp;
2138
2139 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer);
2140 if (ret) {
2141 dma_addr_t unused_buffer;
2142 unsigned int unused_nbytes;
2143 unsigned int unused_id;
2144
2145 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
2146 &unused_nbytes, &unused_id);
2147 } else {
2148 /* non-zero means we did not time out */
2149 ret = 0;
2150 }
2151
2152err_resp:
2153 if (resp) {
2154 dma_addr_t unused_buffer;
2155
2156 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
2157 dma_unmap_single(ar->dev, resp_paddr,
2158 *resp_len, DMA_FROM_DEVICE);
2159 }
2160err_req:
2161 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
2162
2163 if (ret == 0 && resp_len) {
2164 *resp_len = min(*resp_len, xfer.resp_len);
2165 memcpy(resp, tresp, xfer.resp_len);
2166 }
2167err_dma:
2168 kfree(treq);
2169 kfree(tresp);
2170
2171 return ret;
2172}
2173
2174static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
2175{
2176 struct bmi_xfer *xfer;
2177
2178 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
2179 return;
2180
2181 xfer->tx_done = true;
2182}
2183
2184static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
2185{
2186 struct ath10k *ar = ce_state->ar;
2187 struct bmi_xfer *xfer;
2188 unsigned int nbytes;
2189
2190 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer,
2191 &nbytes))
2192 return;
2193
2194 if (WARN_ON_ONCE(!xfer))
2195 return;
2196
2197 if (!xfer->wait_for_resp) {
2198 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
2199 return;
2200 }
2201
2202 xfer->resp_len = nbytes;
2203 xfer->rx_done = true;
2204}
2205
2206static int ath10k_pci_bmi_wait(struct ath10k *ar,
2207 struct ath10k_ce_pipe *tx_pipe,
2208 struct ath10k_ce_pipe *rx_pipe,
2209 struct bmi_xfer *xfer)
2210{
2211 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
2212 unsigned long started = jiffies;
2213 unsigned long dur;
2214 int ret;
2215
2216 while (time_before_eq(jiffies, timeout)) {
2217 ath10k_pci_bmi_send_done(tx_pipe);
2218 ath10k_pci_bmi_recv_data(rx_pipe);
2219
2220 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) {
2221 ret = 0;
2222 goto out;
2223 }
2224
2225 schedule();
2226 }
2227
2228 ret = -ETIMEDOUT;
2229
2230out:
2231 dur = jiffies - started;
2232 if (dur > HZ)
2233 ath10k_dbg(ar, ATH10K_DBG_BMI,
2234 "bmi cmd took %lu jiffies hz %d ret %d\n",
2235 dur, HZ, ret);
2236 return ret;
2237}
2238
2239/*
2240 * Send an interrupt to the device to wake up the Target CPU
2241 * so it has an opportunity to notice any changed state.
2242 */
2243static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
2244{
2245 u32 addr, val;
2246
2247 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS;
2248 val = ath10k_pci_read32(ar, addr);
2249 val |= CORE_CTRL_CPU_INTR_MASK;
2250 ath10k_pci_write32(ar, addr, val);
2251
2252 return 0;
2253}
2254
2255static int ath10k_pci_get_num_banks(struct ath10k *ar)
2256{
2257 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2258
2259 switch (ar_pci->pdev->device) {
2260 case QCA988X_2_0_DEVICE_ID_UBNT:
2261 case QCA988X_2_0_DEVICE_ID:
2262 case QCA99X0_2_0_DEVICE_ID:
2263 case QCA9888_2_0_DEVICE_ID:
2264 case QCA9984_1_0_DEVICE_ID:
2265 case QCA9887_1_0_DEVICE_ID:
2266 return 1;
2267 case QCA6164_2_1_DEVICE_ID:
2268 case QCA6174_2_1_DEVICE_ID:
2269 switch (MS(ar->chip_id, SOC_CHIP_ID_REV)) {
2270 case QCA6174_HW_1_0_CHIP_ID_REV:
2271 case QCA6174_HW_1_1_CHIP_ID_REV:
2272 case QCA6174_HW_2_1_CHIP_ID_REV:
2273 case QCA6174_HW_2_2_CHIP_ID_REV:
2274 return 3;
2275 case QCA6174_HW_1_3_CHIP_ID_REV:
2276 return 2;
2277 case QCA6174_HW_3_0_CHIP_ID_REV:
2278 case QCA6174_HW_3_1_CHIP_ID_REV:
2279 case QCA6174_HW_3_2_CHIP_ID_REV:
2280 return 9;
2281 }
2282 break;
2283 case QCA9377_1_0_DEVICE_ID:
2284 return 9;
2285 }
2286
2287 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
2288 return 1;
2289}
2290
2291static int ath10k_bus_get_num_banks(struct ath10k *ar)
2292{
2293 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2294
2295 return ce->bus_ops->get_num_banks(ar);
2296}
2297
2298int ath10k_pci_init_config(struct ath10k *ar)
2299{
2300 u32 interconnect_targ_addr;
2301 u32 pcie_state_targ_addr = 0;
2302 u32 pipe_cfg_targ_addr = 0;
2303 u32 svc_to_pipe_map = 0;
2304 u32 pcie_config_flags = 0;
2305 u32 ealloc_value;
2306 u32 ealloc_targ_addr;
2307 u32 flag2_value;
2308 u32 flag2_targ_addr;
2309 int ret = 0;
2310
2311 /* Download to Target the CE Config and the service-to-CE map */
2312 interconnect_targ_addr =
2313 host_interest_item_address(HI_ITEM(hi_interconnect_state));
2314
2315 /* Supply Target-side CE configuration */
2316 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
2317 &pcie_state_targ_addr);
2318 if (ret != 0) {
2319 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
2320 return ret;
2321 }
2322
2323 if (pcie_state_targ_addr == 0) {
2324 ret = -EIO;
2325 ath10k_err(ar, "Invalid pcie state addr\n");
2326 return ret;
2327 }
2328
2329 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2330 offsetof(struct pcie_state,
2331 pipe_cfg_addr)),
2332 &pipe_cfg_targ_addr);
2333 if (ret != 0) {
2334 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2335 return ret;
2336 }
2337
2338 if (pipe_cfg_targ_addr == 0) {
2339 ret = -EIO;
2340 ath10k_err(ar, "Invalid pipe cfg addr\n");
2341 return ret;
2342 }
2343
2344 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2345 target_ce_config_wlan,
2346 sizeof(struct ce_pipe_config) *
2347 NUM_TARGET_CE_CONFIG_WLAN);
2348
2349 if (ret != 0) {
2350 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2351 return ret;
2352 }
2353
2354 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2355 offsetof(struct pcie_state,
2356 svc_to_pipe_map)),
2357 &svc_to_pipe_map);
2358 if (ret != 0) {
2359 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2360 return ret;
2361 }
2362
2363 if (svc_to_pipe_map == 0) {
2364 ret = -EIO;
2365 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2366 return ret;
2367 }
2368
2369 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2370 target_service_to_ce_map_wlan,
2371 sizeof(target_service_to_ce_map_wlan));
2372 if (ret != 0) {
2373 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2374 return ret;
2375 }
2376
2377 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2378 offsetof(struct pcie_state,
2379 config_flags)),
2380 &pcie_config_flags);
2381 if (ret != 0) {
2382 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2383 return ret;
2384 }
2385
2386 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2387
2388 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2389 offsetof(struct pcie_state,
2390 config_flags)),
2391 pcie_config_flags);
2392 if (ret != 0) {
2393 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2394 return ret;
2395 }
2396
2397 /* configure early allocation */
2398 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2399
2400 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2401 if (ret != 0) {
2402 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret);
2403 return ret;
2404 }
2405
2406 /* first bank is switched to IRAM */
2407 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2408 HI_EARLY_ALLOC_MAGIC_MASK);
2409 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2410 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2411 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2412
2413 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2414 if (ret != 0) {
2415 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2416 return ret;
2417 }
2418
2419 /* Tell Target to proceed with initialization */
2420 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2421
2422 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2423 if (ret != 0) {
2424 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2425 return ret;
2426 }
2427
2428 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2429
2430 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2431 if (ret != 0) {
2432 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2433 return ret;
2434 }
2435
2436 return 0;
2437}
2438
2439static void ath10k_pci_override_ce_config(struct ath10k *ar)
2440{
2441 struct ce_attr *attr;
2442 struct ce_pipe_config *config;
2443
2444 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2445 * since it is currently used for other feature.
2446 */
2447
2448 /* Override Host's Copy Engine 5 configuration */
2449 attr = &host_ce_config_wlan[5];
2450 attr->src_sz_max = 0;
2451 attr->dest_nentries = 0;
2452
2453 /* Override Target firmware's Copy Engine configuration */
2454 config = &target_ce_config_wlan[5];
2455 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2456 config->nbytes_max = __cpu_to_le32(2048);
2457
2458 /* Map from service/endpoint to Copy Engine */
2459 target_service_to_ce_map_wlan[15].pipenum = __cpu_to_le32(1);
2460}
2461
2462int ath10k_pci_alloc_pipes(struct ath10k *ar)
2463{
2464 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2465 struct ath10k_pci_pipe *pipe;
2466 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2467 int i, ret;
2468
2469 for (i = 0; i < CE_COUNT; i++) {
2470 pipe = &ar_pci->pipe_info[i];
2471 pipe->ce_hdl = &ce->ce_states[i];
2472 pipe->pipe_num = i;
2473 pipe->hif_ce_state = ar;
2474
2475 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
2476 if (ret) {
2477 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2478 i, ret);
2479 return ret;
2480 }
2481
2482 /* Last CE is Diagnostic Window */
2483 if (i == CE_DIAG_PIPE) {
2484 ar_pci->ce_diag = pipe->ce_hdl;
2485 continue;
2486 }
2487
2488 pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max);
2489 }
2490
2491 return 0;
2492}
2493
2494void ath10k_pci_free_pipes(struct ath10k *ar)
2495{
2496 int i;
2497
2498 for (i = 0; i < CE_COUNT; i++)
2499 ath10k_ce_free_pipe(ar, i);
2500}
2501
2502int ath10k_pci_init_pipes(struct ath10k *ar)
2503{
2504 int i, ret;
2505
2506 for (i = 0; i < CE_COUNT; i++) {
2507 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
2508 if (ret) {
2509 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2510 i, ret);
2511 return ret;
2512 }
2513 }
2514
2515 return 0;
2516}
2517
2518static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2519{
2520 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2521 FW_IND_EVENT_PENDING;
2522}
2523
2524static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2525{
2526 u32 val;
2527
2528 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2529 val &= ~FW_IND_EVENT_PENDING;
2530 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2531}
2532
2533static bool ath10k_pci_has_device_gone(struct ath10k *ar)
2534{
2535 u32 val;
2536
2537 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2538 return (val == 0xffffffff);
2539}
2540
2541/* this function effectively clears target memory controller assert line */
2542static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2543{
2544 u32 val;
2545
2546 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2547 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2548 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2549 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2550
2551 msleep(10);
2552
2553 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2554 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2555 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2556 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2557
2558 msleep(10);
2559}
2560
2561static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2562{
2563 u32 val;
2564
2565 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2566
2567 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2568 SOC_RESET_CONTROL_ADDRESS);
2569 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2570 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2571}
2572
2573static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2574{
2575 u32 val;
2576
2577 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2578 SOC_RESET_CONTROL_ADDRESS);
2579
2580 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2581 val | SOC_RESET_CONTROL_CE_RST_MASK);
2582 msleep(10);
2583 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
2584 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2585}
2586
2587static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2588{
2589 u32 val;
2590
2591 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
2592 SOC_LF_TIMER_CONTROL0_ADDRESS);
2593 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
2594 SOC_LF_TIMER_CONTROL0_ADDRESS,
2595 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2596}
2597
2598static int ath10k_pci_warm_reset(struct ath10k *ar)
2599{
2600 int ret;
2601
2602 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2603
2604 spin_lock_bh(&ar->data_lock);
2605 ar->stats.fw_warm_reset_counter++;
2606 spin_unlock_bh(&ar->data_lock);
2607
2608 ath10k_pci_irq_disable(ar);
2609
2610 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2611 * were to access copy engine while host performs copy engine reset
2612 * then it is possible for the device to confuse pci-e controller to
2613 * the point of bringing host system to a complete stop (i.e. hang).
2614 */
2615 ath10k_pci_warm_reset_si0(ar);
2616 ath10k_pci_warm_reset_cpu(ar);
2617 ath10k_pci_init_pipes(ar);
2618 ath10k_pci_wait_for_target_init(ar);
2619
2620 ath10k_pci_warm_reset_clear_lf(ar);
2621 ath10k_pci_warm_reset_ce(ar);
2622 ath10k_pci_warm_reset_cpu(ar);
2623 ath10k_pci_init_pipes(ar);
2624
2625 ret = ath10k_pci_wait_for_target_init(ar);
2626 if (ret) {
2627 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2628 return ret;
2629 }
2630
2631 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2632
2633 return 0;
2634}
2635
2636static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
2637{
2638 ath10k_pci_irq_disable(ar);
2639 return ath10k_pci_qca99x0_chip_reset(ar);
2640}
2641
2642static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2643{
2644 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2645
2646 if (!ar_pci->pci_soft_reset)
2647 return -ENOTSUPP;
2648
2649 return ar_pci->pci_soft_reset(ar);
2650}
2651
2652static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2653{
2654 int i, ret;
2655 u32 val;
2656
2657 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2658
2659 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2660 * It is thus preferred to use warm reset which is safer but may not be
2661 * able to recover the device from all possible fail scenarios.
2662 *
2663 * Warm reset doesn't always work on first try so attempt it a few
2664 * times before giving up.
2665 */
2666 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2667 ret = ath10k_pci_warm_reset(ar);
2668 if (ret) {
2669 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2670 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2671 ret);
2672 continue;
2673 }
2674
2675 /* FIXME: Sometimes copy engine doesn't recover after warm
2676 * reset. In most cases this needs cold reset. In some of these
2677 * cases the device is in such a state that a cold reset may
2678 * lock up the host.
2679 *
2680 * Reading any host interest register via copy engine is
2681 * sufficient to verify if device is capable of booting
2682 * firmware blob.
2683 */
2684 ret = ath10k_pci_init_pipes(ar);
2685 if (ret) {
2686 ath10k_warn(ar, "failed to init copy engine: %d\n",
2687 ret);
2688 continue;
2689 }
2690
2691 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2692 &val);
2693 if (ret) {
2694 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2695 ret);
2696 continue;
2697 }
2698
2699 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2700 return 0;
2701 }
2702
2703 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2704 ath10k_warn(ar, "refusing cold reset as requested\n");
2705 return -EPERM;
2706 }
2707
2708 ret = ath10k_pci_cold_reset(ar);
2709 if (ret) {
2710 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2711 return ret;
2712 }
2713
2714 ret = ath10k_pci_wait_for_target_init(ar);
2715 if (ret) {
2716 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2717 ret);
2718 return ret;
2719 }
2720
2721 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2722
2723 return 0;
2724}
2725
2726static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2727{
2728 int ret;
2729
2730 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2731
2732 /* FIXME: QCA6174 requires cold + warm reset to work. */
2733
2734 ret = ath10k_pci_cold_reset(ar);
2735 if (ret) {
2736 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2737 return ret;
2738 }
2739
2740 ret = ath10k_pci_wait_for_target_init(ar);
2741 if (ret) {
2742 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2743 ret);
2744 return ret;
2745 }
2746
2747 ret = ath10k_pci_warm_reset(ar);
2748 if (ret) {
2749 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2750 return ret;
2751 }
2752
2753 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2754
2755 return 0;
2756}
2757
2758static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2759{
2760 int ret;
2761
2762 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2763
2764 ret = ath10k_pci_cold_reset(ar);
2765 if (ret) {
2766 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2767 return ret;
2768 }
2769
2770 ret = ath10k_pci_wait_for_target_init(ar);
2771 if (ret) {
2772 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2773 ret);
2774 return ret;
2775 }
2776
2777 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2778
2779 return 0;
2780}
2781
2782static int ath10k_pci_chip_reset(struct ath10k *ar)
2783{
2784 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2785
2786 if (WARN_ON(!ar_pci->pci_hard_reset))
2787 return -ENOTSUPP;
2788
2789 return ar_pci->pci_hard_reset(ar);
2790}
2791
2792static int ath10k_pci_hif_power_up(struct ath10k *ar)
2793{
2794 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2795 int ret;
2796
2797 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2798
2799 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2800 &ar_pci->link_ctl);
2801 pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2802 ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
2803
2804 /*
2805 * Bring the target up cleanly.
2806 *
2807 * The target may be in an undefined state with an AUX-powered Target
2808 * and a Host in WoW mode. If the Host crashes, loses power, or is
2809 * restarted (without unloading the driver) then the Target is left
2810 * (aux) powered and running. On a subsequent driver load, the Target
2811 * is in an unexpected state. We try to catch that here in order to
2812 * reset the Target and retry the probe.
2813 */
2814 ret = ath10k_pci_chip_reset(ar);
2815 if (ret) {
2816 if (ath10k_pci_has_fw_crashed(ar)) {
2817 ath10k_warn(ar, "firmware crashed during chip reset\n");
2818 ath10k_pci_fw_crashed_clear(ar);
2819 ath10k_pci_fw_crashed_dump(ar);
2820 }
2821
2822 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2823 goto err_sleep;
2824 }
2825
2826 ret = ath10k_pci_init_pipes(ar);
2827 if (ret) {
2828 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2829 goto err_sleep;
2830 }
2831
2832 ret = ath10k_pci_init_config(ar);
2833 if (ret) {
2834 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2835 goto err_ce;
2836 }
2837
2838 ret = ath10k_pci_wake_target_cpu(ar);
2839 if (ret) {
2840 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2841 goto err_ce;
2842 }
2843
2844 return 0;
2845
2846err_ce:
2847 ath10k_pci_ce_deinit(ar);
2848
2849err_sleep:
2850 return ret;
2851}
2852
2853void ath10k_pci_hif_power_down(struct ath10k *ar)
2854{
2855 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2856
2857 /* Currently hif_power_up performs effectively a reset and hif_stop
2858 * resets the chip as well so there's no point in resetting here.
2859 */
2860}
2861
2862static int ath10k_pci_hif_suspend(struct ath10k *ar)
2863{
2864 /* Nothing to do; the important stuff is in the driver suspend. */
2865 return 0;
2866}
2867
2868static int ath10k_pci_suspend(struct ath10k *ar)
2869{
2870 /* The grace timer can still be counting down and ar->ps_awake be true.
2871 * It is known that the device may be asleep after resuming regardless
2872 * of the SoC powersave state before suspending. Hence make sure the
2873 * device is asleep before proceeding.
2874 */
2875 ath10k_pci_sleep_sync(ar);
2876
2877 return 0;
2878}
2879
2880static int ath10k_pci_hif_resume(struct ath10k *ar)
2881{
2882 /* Nothing to do; the important stuff is in the driver resume. */
2883 return 0;
2884}
2885
2886static int ath10k_pci_resume(struct ath10k *ar)
2887{
2888 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2889 struct pci_dev *pdev = ar_pci->pdev;
2890 u32 val;
2891 int ret = 0;
2892
2893 ret = ath10k_pci_force_wake(ar);
2894 if (ret) {
2895 ath10k_err(ar, "failed to wake up target: %d\n", ret);
2896 return ret;
2897 }
2898
2899 /* Suspend/Resume resets the PCI configuration space, so we have to
2900 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
2901 * from interfering with C3 CPU state. pci_restore_state won't help
2902 * here since it only restores the first 64 bytes pci config header.
2903 */
2904 pci_read_config_dword(pdev, 0x40, &val);
2905 if ((val & 0x0000ff00) != 0)
2906 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2907
2908 return ret;
2909}
2910
2911static bool ath10k_pci_validate_cal(void *data, size_t size)
2912{
2913 __le16 *cal_words = data;
2914 u16 checksum = 0;
2915 size_t i;
2916
2917 if (size % 2 != 0)
2918 return false;
2919
2920 for (i = 0; i < size / 2; i++)
2921 checksum ^= le16_to_cpu(cal_words[i]);
2922
2923 return checksum == 0xffff;
2924}
2925
2926static void ath10k_pci_enable_eeprom(struct ath10k *ar)
2927{
2928 /* Enable SI clock */
2929 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0);
2930
2931 /* Configure GPIOs for I2C operation */
2932 ath10k_pci_write32(ar,
2933 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2934 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN,
2935 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG,
2936 GPIO_PIN0_CONFIG) |
2937 SM(1, GPIO_PIN0_PAD_PULL));
2938
2939 ath10k_pci_write32(ar,
2940 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
2941 4 * QCA9887_1_0_SI_CLK_GPIO_PIN,
2942 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) |
2943 SM(1, GPIO_PIN0_PAD_PULL));
2944
2945 ath10k_pci_write32(ar,
2946 GPIO_BASE_ADDRESS +
2947 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,
2948 1u << QCA9887_1_0_SI_CLK_GPIO_PIN);
2949
2950 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
2951 ath10k_pci_write32(ar,
2952 SI_BASE_ADDRESS + SI_CONFIG_OFFSET,
2953 SM(1, SI_CONFIG_ERR_INT) |
2954 SM(1, SI_CONFIG_BIDIR_OD_DATA) |
2955 SM(1, SI_CONFIG_I2C) |
2956 SM(1, SI_CONFIG_POS_SAMPLE) |
2957 SM(1, SI_CONFIG_INACTIVE_DATA) |
2958 SM(1, SI_CONFIG_INACTIVE_CLK) |
2959 SM(8, SI_CONFIG_DIVIDER));
2960}
2961
2962static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out)
2963{
2964 u32 reg;
2965 int wait_limit;
2966
2967 /* set device select byte and for the read operation */
2968 reg = QCA9887_EEPROM_SELECT_READ |
2969 SM(addr, QCA9887_EEPROM_ADDR_LO) |
2970 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI);
2971 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);
2972
2973 /* write transmit data, transfer length, and START bit */
2974 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
2975 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) |
2976 SM(4, SI_CS_TX_CNT));
2977
2978 /* wait max 1 sec */
2979 wait_limit = 100000;
2980
2981 /* wait for SI_CS_DONE_INT */
2982 do {
2983 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
2984 if (MS(reg, SI_CS_DONE_INT))
2985 break;
2986
2987 wait_limit--;
2988 udelay(10);
2989 } while (wait_limit > 0);
2990
2991 if (!MS(reg, SI_CS_DONE_INT)) {
2992 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n",
2993 addr);
2994 return -ETIMEDOUT;
2995 }
2996
2997 /* clear SI_CS_DONE_INT */
2998 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);
2999
3000 if (MS(reg, SI_CS_DONE_ERR)) {
3001 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr);
3002 return -EIO;
3003 }
3004
3005 /* extract receive data */
3006 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
3007 *out = reg;
3008
3009 return 0;
3010}
3011
3012static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data,
3013 size_t *data_len)
3014{
3015 u8 *caldata = NULL;
3016 size_t calsize, i;
3017 int ret;
3018
3019 if (!QCA_REV_9887(ar))
3020 return -EOPNOTSUPP;
3021
3022 calsize = ar->hw_params.cal_data_len;
3023 caldata = kmalloc(calsize, GFP_KERNEL);
3024 if (!caldata)
3025 return -ENOMEM;
3026
3027 ath10k_pci_enable_eeprom(ar);
3028
3029 for (i = 0; i < calsize; i++) {
3030 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]);
3031 if (ret)
3032 goto err_free;
3033 }
3034
3035 if (!ath10k_pci_validate_cal(caldata, calsize))
3036 goto err_free;
3037
3038 *data = caldata;
3039 *data_len = calsize;
3040
3041 return 0;
3042
3043err_free:
3044 kfree(caldata);
3045
3046 return -EINVAL;
3047}
3048
3049static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
3050 .tx_sg = ath10k_pci_hif_tx_sg,
3051 .diag_read = ath10k_pci_hif_diag_read,
3052 .diag_write = ath10k_pci_diag_write_mem,
3053 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
3054 .start = ath10k_pci_hif_start,
3055 .stop = ath10k_pci_hif_stop,
3056 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
3057 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
3058 .send_complete_check = ath10k_pci_hif_send_complete_check,
3059 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
3060 .power_up = ath10k_pci_hif_power_up,
3061 .power_down = ath10k_pci_hif_power_down,
3062 .read32 = ath10k_pci_read32,
3063 .write32 = ath10k_pci_write32,
3064 .suspend = ath10k_pci_hif_suspend,
3065 .resume = ath10k_pci_hif_resume,
3066 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom,
3067};
3068
3069/*
3070 * Top-level interrupt handler for all PCI interrupts from a Target.
3071 * When a block of MSI interrupts is allocated, this top-level handler
3072 * is not used; instead, we directly call the correct sub-handler.
3073 */
3074static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
3075{
3076 struct ath10k *ar = arg;
3077 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3078 int ret;
3079
3080 if (ath10k_pci_has_device_gone(ar))
3081 return IRQ_NONE;
3082
3083 ret = ath10k_pci_force_wake(ar);
3084 if (ret) {
3085 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
3086 return IRQ_NONE;
3087 }
3088
3089 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY) &&
3090 !ath10k_pci_irq_pending(ar))
3091 return IRQ_NONE;
3092
3093 ath10k_pci_disable_and_clear_legacy_irq(ar);
3094 ath10k_pci_irq_msi_fw_mask(ar);
3095 napi_schedule(&ar->napi);
3096
3097 return IRQ_HANDLED;
3098}
3099
3100static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
3101{
3102 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
3103 int done = 0;
3104
3105 if (ath10k_pci_has_fw_crashed(ar)) {
3106 ath10k_pci_fw_crashed_clear(ar);
3107 ath10k_pci_fw_crashed_dump(ar);
3108 napi_complete(ctx);
3109 return done;
3110 }
3111
3112 ath10k_ce_per_engine_service_any(ar);
3113
3114 done = ath10k_htt_txrx_compl_task(ar, budget);
3115
3116 if (done < budget) {
3117 napi_complete_done(ctx, done);
3118 /* In case of MSI, it is possible that interrupts are received
3119 * while NAPI poll is inprogress. So pending interrupts that are
3120 * received after processing all copy engine pipes by NAPI poll
3121 * will not be handled again. This is causing failure to
3122 * complete boot sequence in x86 platform. So before enabling
3123 * interrupts safer to check for pending interrupts for
3124 * immediate servicing.
3125 */
3126 if (ath10k_ce_interrupt_summary(ar)) {
3127 napi_reschedule(ctx);
3128 goto out;
3129 }
3130 ath10k_pci_enable_legacy_irq(ar);
3131 ath10k_pci_irq_msi_fw_unmask(ar);
3132 }
3133
3134out:
3135 return done;
3136}
3137
3138static int ath10k_pci_request_irq_msi(struct ath10k *ar)
3139{
3140 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3141 int ret;
3142
3143 ret = request_irq(ar_pci->pdev->irq,
3144 ath10k_pci_interrupt_handler,
3145 IRQF_SHARED, "ath10k_pci", ar);
3146 if (ret) {
3147 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
3148 ar_pci->pdev->irq, ret);
3149 return ret;
3150 }
3151
3152 return 0;
3153}
3154
3155static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
3156{
3157 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3158 int ret;
3159
3160 ret = request_irq(ar_pci->pdev->irq,
3161 ath10k_pci_interrupt_handler,
3162 IRQF_SHARED, "ath10k_pci", ar);
3163 if (ret) {
3164 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
3165 ar_pci->pdev->irq, ret);
3166 return ret;
3167 }
3168
3169 return 0;
3170}
3171
3172static int ath10k_pci_request_irq(struct ath10k *ar)
3173{
3174 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3175
3176 switch (ar_pci->oper_irq_mode) {
3177 case ATH10K_PCI_IRQ_LEGACY:
3178 return ath10k_pci_request_irq_legacy(ar);
3179 case ATH10K_PCI_IRQ_MSI:
3180 return ath10k_pci_request_irq_msi(ar);
3181 default:
3182 return -EINVAL;
3183 }
3184}
3185
3186static void ath10k_pci_free_irq(struct ath10k *ar)
3187{
3188 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3189
3190 free_irq(ar_pci->pdev->irq, ar);
3191}
3192
3193void ath10k_pci_init_napi(struct ath10k *ar)
3194{
3195 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_pci_napi_poll,
3196 ATH10K_NAPI_BUDGET);
3197}
3198
3199static int ath10k_pci_init_irq(struct ath10k *ar)
3200{
3201 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3202 int ret;
3203
3204 ath10k_pci_init_napi(ar);
3205
3206 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
3207 ath10k_info(ar, "limiting irq mode to: %d\n",
3208 ath10k_pci_irq_mode);
3209
3210 /* Try MSI */
3211 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
3212 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI;
3213 ret = pci_enable_msi(ar_pci->pdev);
3214 if (ret == 0)
3215 return 0;
3216
3217 /* fall-through */
3218 }
3219
3220 /* Try legacy irq
3221 *
3222 * A potential race occurs here: The CORE_BASE write
3223 * depends on target correctly decoding AXI address but
3224 * host won't know when target writes BAR to CORE_CTRL.
3225 * This write might get lost if target has NOT written BAR.
3226 * For now, fix the race by repeating the write in below
3227 * synchronization checking.
3228 */
3229 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
3230
3231 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3232 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
3233
3234 return 0;
3235}
3236
3237static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
3238{
3239 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3240 0);
3241}
3242
3243static int ath10k_pci_deinit_irq(struct ath10k *ar)
3244{
3245 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3246
3247 switch (ar_pci->oper_irq_mode) {
3248 case ATH10K_PCI_IRQ_LEGACY:
3249 ath10k_pci_deinit_irq_legacy(ar);
3250 break;
3251 default:
3252 pci_disable_msi(ar_pci->pdev);
3253 break;
3254 }
3255
3256 return 0;
3257}
3258
3259int ath10k_pci_wait_for_target_init(struct ath10k *ar)
3260{
3261 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3262 unsigned long timeout;
3263 u32 val;
3264
3265 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
3266
3267 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
3268
3269 do {
3270 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
3271
3272 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
3273 val);
3274
3275 /* target should never return this */
3276 if (val == 0xffffffff)
3277 continue;
3278
3279 /* the device has crashed so don't bother trying anymore */
3280 if (val & FW_IND_EVENT_PENDING)
3281 break;
3282
3283 if (val & FW_IND_INITIALIZED)
3284 break;
3285
3286 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_LEGACY)
3287 /* Fix potential race by repeating CORE_BASE writes */
3288 ath10k_pci_enable_legacy_irq(ar);
3289
3290 mdelay(10);
3291 } while (time_before(jiffies, timeout));
3292
3293 ath10k_pci_disable_and_clear_legacy_irq(ar);
3294 ath10k_pci_irq_msi_fw_mask(ar);
3295
3296 if (val == 0xffffffff) {
3297 ath10k_err(ar, "failed to read device register, device is gone\n");
3298 return -EIO;
3299 }
3300
3301 if (val & FW_IND_EVENT_PENDING) {
3302 ath10k_warn(ar, "device has crashed during init\n");
3303 return -ECOMM;
3304 }
3305
3306 if (!(val & FW_IND_INITIALIZED)) {
3307 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
3308 val);
3309 return -ETIMEDOUT;
3310 }
3311
3312 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
3313 return 0;
3314}
3315
3316static int ath10k_pci_cold_reset(struct ath10k *ar)
3317{
3318 u32 val;
3319
3320 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
3321
3322 spin_lock_bh(&ar->data_lock);
3323
3324 ar->stats.fw_cold_reset_counter++;
3325
3326 spin_unlock_bh(&ar->data_lock);
3327
3328 /* Put Target, including PCIe, into RESET. */
3329 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
3330 val |= 1;
3331 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3332
3333 /* After writing into SOC_GLOBAL_RESET to put device into
3334 * reset and pulling out of reset pcie may not be stable
3335 * for any immediate pcie register access and cause bus error,
3336 * add delay before any pcie access request to fix this issue.
3337 */
3338 msleep(20);
3339
3340 /* Pull Target, including PCIe, out of RESET. */
3341 val &= ~1;
3342 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3343
3344 msleep(20);
3345
3346 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
3347
3348 return 0;
3349}
3350
3351static int ath10k_pci_claim(struct ath10k *ar)
3352{
3353 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3354 struct pci_dev *pdev = ar_pci->pdev;
3355 int ret;
3356
3357 pci_set_drvdata(pdev, ar);
3358
3359 ret = pci_enable_device(pdev);
3360 if (ret) {
3361 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
3362 return ret;
3363 }
3364
3365 ret = pci_request_region(pdev, BAR_NUM, "ath");
3366 if (ret) {
3367 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
3368 ret);
3369 goto err_device;
3370 }
3371
3372 /* Target expects 32 bit DMA. Enforce it. */
3373 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3374 if (ret) {
3375 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
3376 goto err_region;
3377 }
3378
3379 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3380 if (ret) {
3381 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
3382 ret);
3383 goto err_region;
3384 }
3385
3386 pci_set_master(pdev);
3387
3388 /* Arrange for access to Target SoC registers. */
3389 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
3390 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
3391 if (!ar_pci->mem) {
3392 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
3393 ret = -EIO;
3394 goto err_master;
3395 }
3396
3397 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%pK\n", ar_pci->mem);
3398 return 0;
3399
3400err_master:
3401 pci_clear_master(pdev);
3402
3403err_region:
3404 pci_release_region(pdev, BAR_NUM);
3405
3406err_device:
3407 pci_disable_device(pdev);
3408
3409 return ret;
3410}
3411
3412static void ath10k_pci_release(struct ath10k *ar)
3413{
3414 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3415 struct pci_dev *pdev = ar_pci->pdev;
3416
3417 pci_iounmap(pdev, ar_pci->mem);
3418 pci_release_region(pdev, BAR_NUM);
3419 pci_clear_master(pdev);
3420 pci_disable_device(pdev);
3421}
3422
3423static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
3424{
3425 const struct ath10k_pci_supp_chip *supp_chip;
3426 int i;
3427 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3428
3429 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3430 supp_chip = &ath10k_pci_supp_chips[i];
3431
3432 if (supp_chip->dev_id == dev_id &&
3433 supp_chip->rev_id == rev_id)
3434 return true;
3435 }
3436
3437 return false;
3438}
3439
3440int ath10k_pci_setup_resource(struct ath10k *ar)
3441{
3442 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3443 struct ath10k_ce *ce = ath10k_ce_priv(ar);
3444 int ret;
3445
3446 spin_lock_init(&ce->ce_lock);
3447 spin_lock_init(&ar_pci->ps_lock);
3448
3449 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0);
3450
3451 if (QCA_REV_6174(ar) || QCA_REV_9377(ar))
3452 ath10k_pci_override_ce_config(ar);
3453
3454 ret = ath10k_pci_alloc_pipes(ar);
3455 if (ret) {
3456 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3457 ret);
3458 return ret;
3459 }
3460
3461 return 0;
3462}
3463
3464void ath10k_pci_release_resource(struct ath10k *ar)
3465{
3466 ath10k_pci_rx_retry_sync(ar);
3467 netif_napi_del(&ar->napi);
3468 ath10k_pci_ce_deinit(ar);
3469 ath10k_pci_free_pipes(ar);
3470}
3471
3472static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3473 .read32 = ath10k_bus_pci_read32,
3474 .write32 = ath10k_bus_pci_write32,
3475 .get_num_banks = ath10k_pci_get_num_banks,
3476};
3477
3478static int ath10k_pci_probe(struct pci_dev *pdev,
3479 const struct pci_device_id *pci_dev)
3480{
3481 int ret = 0;
3482 struct ath10k *ar;
3483 struct ath10k_pci *ar_pci;
3484 enum ath10k_hw_rev hw_rev;
3485 u32 chip_id;
3486 bool pci_ps;
3487 int (*pci_soft_reset)(struct ath10k *ar);
3488 int (*pci_hard_reset)(struct ath10k *ar);
3489 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
3490
3491 switch (pci_dev->device) {
3492 case QCA988X_2_0_DEVICE_ID_UBNT:
3493 case QCA988X_2_0_DEVICE_ID:
3494 hw_rev = ATH10K_HW_QCA988X;
3495 pci_ps = false;
3496 pci_soft_reset = ath10k_pci_warm_reset;
3497 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3498 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3499 break;
3500 case QCA9887_1_0_DEVICE_ID:
3501 hw_rev = ATH10K_HW_QCA9887;
3502 pci_ps = false;
3503 pci_soft_reset = ath10k_pci_warm_reset;
3504 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3505 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3506 break;
3507 case QCA6164_2_1_DEVICE_ID:
3508 case QCA6174_2_1_DEVICE_ID:
3509 hw_rev = ATH10K_HW_QCA6174;
3510 pci_ps = true;
3511 pci_soft_reset = ath10k_pci_warm_reset;
3512 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3513 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3514 break;
3515 case QCA99X0_2_0_DEVICE_ID:
3516 hw_rev = ATH10K_HW_QCA99X0;
3517 pci_ps = false;
3518 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3519 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3520 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3521 break;
3522 case QCA9984_1_0_DEVICE_ID:
3523 hw_rev = ATH10K_HW_QCA9984;
3524 pci_ps = false;
3525 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3526 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3527 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3528 break;
3529 case QCA9888_2_0_DEVICE_ID:
3530 hw_rev = ATH10K_HW_QCA9888;
3531 pci_ps = false;
3532 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3533 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3534 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3535 break;
3536 case QCA9377_1_0_DEVICE_ID:
3537 hw_rev = ATH10K_HW_QCA9377;
3538 pci_ps = true;
3539 pci_soft_reset = NULL;
3540 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3541 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3542 break;
3543 default:
3544 WARN_ON(1);
3545 return -ENOTSUPP;
3546 }
3547
3548 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3549 hw_rev, &ath10k_pci_hif_ops);
3550 if (!ar) {
3551 dev_err(&pdev->dev, "failed to allocate core\n");
3552 return -ENOMEM;
3553 }
3554
3555 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3556 pdev->vendor, pdev->device,
3557 pdev->subsystem_vendor, pdev->subsystem_device);
3558
3559 ar_pci = ath10k_pci_priv(ar);
3560 ar_pci->pdev = pdev;
3561 ar_pci->dev = &pdev->dev;
3562 ar_pci->ar = ar;
3563 ar->dev_id = pci_dev->device;
3564 ar_pci->pci_ps = pci_ps;
3565 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops;
3566 ar_pci->pci_soft_reset = pci_soft_reset;
3567 ar_pci->pci_hard_reset = pci_hard_reset;
3568 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr;
3569 ar->ce_priv = &ar_pci->ce;
3570
3571 ar->id.vendor = pdev->vendor;
3572 ar->id.device = pdev->device;
3573 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3574 ar->id.subsystem_device = pdev->subsystem_device;
3575
3576 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0);
3577
3578 ret = ath10k_pci_setup_resource(ar);
3579 if (ret) {
3580 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3581 goto err_core_destroy;
3582 }
3583
3584 ret = ath10k_pci_claim(ar);
3585 if (ret) {
3586 ath10k_err(ar, "failed to claim device: %d\n", ret);
3587 goto err_free_pipes;
3588 }
3589
3590 ret = ath10k_pci_force_wake(ar);
3591 if (ret) {
3592 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3593 goto err_sleep;
3594 }
3595
3596 ath10k_pci_ce_deinit(ar);
3597 ath10k_pci_irq_disable(ar);
3598
3599 ret = ath10k_pci_init_irq(ar);
3600 if (ret) {
3601 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3602 goto err_sleep;
3603 }
3604
3605 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3606 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode,
3607 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3608
3609 ret = ath10k_pci_request_irq(ar);
3610 if (ret) {
3611 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3612 goto err_deinit_irq;
3613 }
3614
3615 ret = ath10k_pci_chip_reset(ar);
3616 if (ret) {
3617 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3618 goto err_free_irq;
3619 }
3620
3621 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3622 if (chip_id == 0xffffffff) {
3623 ath10k_err(ar, "failed to get chip id\n");
3624 goto err_free_irq;
3625 }
3626
3627 if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
3628 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3629 pdev->device, chip_id);
3630 goto err_free_irq;
3631 }
3632
3633 ret = ath10k_core_register(ar, chip_id);
3634 if (ret) {
3635 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3636 goto err_free_irq;
3637 }
3638
3639 return 0;
3640
3641err_free_irq:
3642 ath10k_pci_free_irq(ar);
3643 ath10k_pci_rx_retry_sync(ar);
3644
3645err_deinit_irq:
3646 ath10k_pci_deinit_irq(ar);
3647
3648err_sleep:
3649 ath10k_pci_sleep_sync(ar);
3650 ath10k_pci_release(ar);
3651
3652err_free_pipes:
3653 ath10k_pci_free_pipes(ar);
3654
3655err_core_destroy:
3656 ath10k_core_destroy(ar);
3657
3658 return ret;
3659}
3660
3661static void ath10k_pci_remove(struct pci_dev *pdev)
3662{
3663 struct ath10k *ar = pci_get_drvdata(pdev);
3664 struct ath10k_pci *ar_pci;
3665
3666 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3667
3668 if (!ar)
3669 return;
3670
3671 ar_pci = ath10k_pci_priv(ar);
3672
3673 if (!ar_pci)
3674 return;
3675
3676 ath10k_core_unregister(ar);
3677 ath10k_pci_free_irq(ar);
3678 ath10k_pci_deinit_irq(ar);
3679 ath10k_pci_release_resource(ar);
3680 ath10k_pci_sleep_sync(ar);
3681 ath10k_pci_release(ar);
3682 ath10k_core_destroy(ar);
3683}
3684
3685MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3686
3687static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev)
3688{
3689 struct ath10k *ar = dev_get_drvdata(dev);
3690 int ret;
3691
3692 ret = ath10k_pci_suspend(ar);
3693 if (ret)
3694 ath10k_warn(ar, "failed to suspend hif: %d\n", ret);
3695
3696 return ret;
3697}
3698
3699static __maybe_unused int ath10k_pci_pm_resume(struct device *dev)
3700{
3701 struct ath10k *ar = dev_get_drvdata(dev);
3702 int ret;
3703
3704 ret = ath10k_pci_resume(ar);
3705 if (ret)
3706 ath10k_warn(ar, "failed to resume hif: %d\n", ret);
3707
3708 return ret;
3709}
3710
3711static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops,
3712 ath10k_pci_pm_suspend,
3713 ath10k_pci_pm_resume);
3714
3715static struct pci_driver ath10k_pci_driver = {
3716 .name = "ath10k_pci",
3717 .id_table = ath10k_pci_id_table,
3718 .probe = ath10k_pci_probe,
3719 .remove = ath10k_pci_remove,
3720#ifdef CONFIG_PM
3721 .driver.pm = &ath10k_pci_pm_ops,
3722#endif
3723};
3724
3725static int __init ath10k_pci_init(void)
3726{
3727 int ret;
3728
3729 ret = pci_register_driver(&ath10k_pci_driver);
3730 if (ret)
3731 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3732 ret);
3733
3734 ret = ath10k_ahb_init();
3735 if (ret)
3736 printk(KERN_ERR "ahb init failed: %d\n", ret);
3737
3738 return ret;
3739}
3740module_init(ath10k_pci_init);
3741
3742static void __exit ath10k_pci_exit(void)
3743{
3744 pci_unregister_driver(&ath10k_pci_driver);
3745 ath10k_ahb_exit();
3746}
3747
3748module_exit(ath10k_pci_exit);
3749
3750MODULE_AUTHOR("Qualcomm Atheros");
3751MODULE_DESCRIPTION("Driver support for Qualcomm Atheros 802.11ac WLAN PCIe/AHB devices");
3752MODULE_LICENSE("Dual BSD/GPL");
3753
3754/* QCA988x 2.0 firmware files */
3755MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3756MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3757MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3758MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3759MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);
3760MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3761
3762/* QCA9887 1.0 firmware files */
3763MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3764MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" QCA9887_HW_1_0_BOARD_DATA_FILE);
3765MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3766
3767/* QCA6174 2.1 firmware files */
3768MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3769MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3770MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" QCA6174_HW_2_1_BOARD_DATA_FILE);
3771MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3772
3773/* QCA6174 3.1 firmware files */
3774MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3775MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3776MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3777MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
3778MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3779
3780/* QCA9377 1.0 firmware files */
3781MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3782MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3783MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);