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1/*
2 * Intel IXP4xx Ethernet driver for Linux
3 *
4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 * Ethernet port config (0x00 is not present on IXP42X):
11 *
12 * logical port 0x00 0x10 0x20
13 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
14 * physical PortId 2 0 1
15 * TX queue 23 24 25
16 * RX-free queue 26 27 28
17 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
18 *
19 *
20 * Queue entries:
21 * bits 0 -> 1 - NPE ID (RX and TX-done)
22 * bits 0 -> 2 - priority (TX, per 802.1D)
23 * bits 3 -> 4 - port ID (user-set?)
24 * bits 5 -> 31 - physical descriptor address
25 */
26
27#include <linux/delay.h>
28#include <linux/dma-mapping.h>
29#include <linux/dmapool.h>
30#include <linux/etherdevice.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
33#include <linux/net_tstamp.h>
34#include <linux/phy.h>
35#include <linux/platform_device.h>
36#include <linux/ptp_classify.h>
37#include <linux/slab.h>
38#include <linux/module.h>
39#include <mach/ixp46x_ts.h>
40#include <mach/npe.h>
41#include <mach/qmgr.h>
42
43#define DEBUG_DESC 0
44#define DEBUG_RX 0
45#define DEBUG_TX 0
46#define DEBUG_PKT_BYTES 0
47#define DEBUG_MDIO 0
48#define DEBUG_CLOSE 0
49
50#define DRV_NAME "ixp4xx_eth"
51
52#define MAX_NPES 3
53
54#define RX_DESCS 64 /* also length of all RX queues */
55#define TX_DESCS 16 /* also length of all TX queues */
56#define TXDONE_QUEUE_LEN 64 /* dwords */
57
58#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
59#define REGS_SIZE 0x1000
60#define MAX_MRU 1536 /* 0x600 */
61#define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
62
63#define NAPI_WEIGHT 16
64#define MDIO_INTERVAL (3 * HZ)
65#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
66#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
67
68#define NPE_ID(port_id) ((port_id) >> 4)
69#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
70#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
71#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
72#define TXDONE_QUEUE 31
73
74#define PTP_SLAVE_MODE 1
75#define PTP_MASTER_MODE 2
76#define PORT2CHANNEL(p) NPE_ID(p->id)
77
78/* TX Control Registers */
79#define TX_CNTRL0_TX_EN 0x01
80#define TX_CNTRL0_HALFDUPLEX 0x02
81#define TX_CNTRL0_RETRY 0x04
82#define TX_CNTRL0_PAD_EN 0x08
83#define TX_CNTRL0_APPEND_FCS 0x10
84#define TX_CNTRL0_2DEFER 0x20
85#define TX_CNTRL0_RMII 0x40 /* reduced MII */
86#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
87
88/* RX Control Registers */
89#define RX_CNTRL0_RX_EN 0x01
90#define RX_CNTRL0_PADSTRIP_EN 0x02
91#define RX_CNTRL0_SEND_FCS 0x04
92#define RX_CNTRL0_PAUSE_EN 0x08
93#define RX_CNTRL0_LOOP_EN 0x10
94#define RX_CNTRL0_ADDR_FLTR_EN 0x20
95#define RX_CNTRL0_RX_RUNT_EN 0x40
96#define RX_CNTRL0_BCAST_DIS 0x80
97#define RX_CNTRL1_DEFER_EN 0x01
98
99/* Core Control Register */
100#define CORE_RESET 0x01
101#define CORE_RX_FIFO_FLUSH 0x02
102#define CORE_TX_FIFO_FLUSH 0x04
103#define CORE_SEND_JAM 0x08
104#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
105
106#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
107 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
108 TX_CNTRL0_2DEFER)
109#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
110#define DEFAULT_CORE_CNTRL CORE_MDC_EN
111
112
113/* NPE message codes */
114#define NPE_GETSTATUS 0x00
115#define NPE_EDB_SETPORTADDRESS 0x01
116#define NPE_EDB_GETMACADDRESSDATABASE 0x02
117#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
118#define NPE_GETSTATS 0x04
119#define NPE_RESETSTATS 0x05
120#define NPE_SETMAXFRAMELENGTHS 0x06
121#define NPE_VLAN_SETRXTAGMODE 0x07
122#define NPE_VLAN_SETDEFAULTRXVID 0x08
123#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
124#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
125#define NPE_VLAN_SETRXQOSENTRY 0x0B
126#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
127#define NPE_STP_SETBLOCKINGSTATE 0x0D
128#define NPE_FW_SETFIREWALLMODE 0x0E
129#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
130#define NPE_PC_SETAPMACTABLE 0x11
131#define NPE_SETLOOPBACK_MODE 0x12
132#define NPE_PC_SETBSSIDTABLE 0x13
133#define NPE_ADDRESS_FILTER_CONFIG 0x14
134#define NPE_APPENDFCSCONFIG 0x15
135#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
136#define NPE_MAC_RECOVERY_START 0x17
137
138
139#ifdef __ARMEB__
140typedef struct sk_buff buffer_t;
141#define free_buffer dev_kfree_skb
142#define free_buffer_irq dev_kfree_skb_irq
143#else
144typedef void buffer_t;
145#define free_buffer kfree
146#define free_buffer_irq kfree
147#endif
148
149struct eth_regs {
150 u32 tx_control[2], __res1[2]; /* 000 */
151 u32 rx_control[2], __res2[2]; /* 010 */
152 u32 random_seed, __res3[3]; /* 020 */
153 u32 partial_empty_threshold, __res4; /* 030 */
154 u32 partial_full_threshold, __res5; /* 038 */
155 u32 tx_start_bytes, __res6[3]; /* 040 */
156 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
157 u32 tx_2part_deferral[2], __res8[2]; /* 060 */
158 u32 slot_time, __res9[3]; /* 070 */
159 u32 mdio_command[4]; /* 080 */
160 u32 mdio_status[4]; /* 090 */
161 u32 mcast_mask[6], __res10[2]; /* 0A0 */
162 u32 mcast_addr[6], __res11[2]; /* 0C0 */
163 u32 int_clock_threshold, __res12[3]; /* 0E0 */
164 u32 hw_addr[6], __res13[61]; /* 0F0 */
165 u32 core_control; /* 1FC */
166};
167
168struct port {
169 struct resource *mem_res;
170 struct eth_regs __iomem *regs;
171 struct npe *npe;
172 struct net_device *netdev;
173 struct napi_struct napi;
174 struct eth_plat_info *plat;
175 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
176 struct desc *desc_tab; /* coherent */
177 u32 desc_tab_phys;
178 int id; /* logical port ID */
179 int speed, duplex;
180 u8 firmware[4];
181 int hwts_tx_en;
182 int hwts_rx_en;
183};
184
185/* NPE message structure */
186struct msg {
187#ifdef __ARMEB__
188 u8 cmd, eth_id, byte2, byte3;
189 u8 byte4, byte5, byte6, byte7;
190#else
191 u8 byte3, byte2, eth_id, cmd;
192 u8 byte7, byte6, byte5, byte4;
193#endif
194};
195
196/* Ethernet packet descriptor */
197struct desc {
198 u32 next; /* pointer to next buffer, unused */
199
200#ifdef __ARMEB__
201 u16 buf_len; /* buffer length */
202 u16 pkt_len; /* packet length */
203 u32 data; /* pointer to data buffer in RAM */
204 u8 dest_id;
205 u8 src_id;
206 u16 flags;
207 u8 qos;
208 u8 padlen;
209 u16 vlan_tci;
210#else
211 u16 pkt_len; /* packet length */
212 u16 buf_len; /* buffer length */
213 u32 data; /* pointer to data buffer in RAM */
214 u16 flags;
215 u8 src_id;
216 u8 dest_id;
217 u16 vlan_tci;
218 u8 padlen;
219 u8 qos;
220#endif
221
222#ifdef __ARMEB__
223 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
224 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
225 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
226#else
227 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
228 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
229 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
230#endif
231};
232
233
234#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
235 (n) * sizeof(struct desc))
236#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
237
238#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
239 ((n) + RX_DESCS) * sizeof(struct desc))
240#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
241
242#ifndef __ARMEB__
243static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
244{
245 int i;
246 for (i = 0; i < cnt; i++)
247 dest[i] = swab32(src[i]);
248}
249#endif
250
251static spinlock_t mdio_lock;
252static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
253static struct mii_bus *mdio_bus;
254static int ports_open;
255static struct port *npe_port_tab[MAX_NPES];
256static struct dma_pool *dma_pool;
257
258static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
259{
260 u8 *data = skb->data;
261 unsigned int offset;
262 u16 *hi, *id;
263 u32 lo;
264
265 if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4)
266 return 0;
267
268 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
269
270 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
271 return 0;
272
273 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
274 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
275
276 memcpy(&lo, &hi[1], sizeof(lo));
277
278 return (uid_hi == ntohs(*hi) &&
279 uid_lo == ntohl(lo) &&
280 seqid == ntohs(*id));
281}
282
283static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
284{
285 struct skb_shared_hwtstamps *shhwtstamps;
286 struct ixp46x_ts_regs *regs;
287 u64 ns;
288 u32 ch, hi, lo, val;
289 u16 uid, seq;
290
291 if (!port->hwts_rx_en)
292 return;
293
294 ch = PORT2CHANNEL(port);
295
296 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
297
298 val = __raw_readl(®s->channel[ch].ch_event);
299
300 if (!(val & RX_SNAPSHOT_LOCKED))
301 return;
302
303 lo = __raw_readl(®s->channel[ch].src_uuid_lo);
304 hi = __raw_readl(®s->channel[ch].src_uuid_hi);
305
306 uid = hi & 0xffff;
307 seq = (hi >> 16) & 0xffff;
308
309 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
310 goto out;
311
312 lo = __raw_readl(®s->channel[ch].rx_snap_lo);
313 hi = __raw_readl(®s->channel[ch].rx_snap_hi);
314 ns = ((u64) hi) << 32;
315 ns |= lo;
316 ns <<= TICKS_NS_SHIFT;
317
318 shhwtstamps = skb_hwtstamps(skb);
319 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
320 shhwtstamps->hwtstamp = ns_to_ktime(ns);
321out:
322 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
323}
324
325static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
326{
327 struct skb_shared_hwtstamps shhwtstamps;
328 struct ixp46x_ts_regs *regs;
329 struct skb_shared_info *shtx;
330 u64 ns;
331 u32 ch, cnt, hi, lo, val;
332
333 shtx = skb_shinfo(skb);
334 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
335 shtx->tx_flags |= SKBTX_IN_PROGRESS;
336 else
337 return;
338
339 ch = PORT2CHANNEL(port);
340
341 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
342
343 /*
344 * This really stinks, but we have to poll for the Tx time stamp.
345 * Usually, the time stamp is ready after 4 to 6 microseconds.
346 */
347 for (cnt = 0; cnt < 100; cnt++) {
348 val = __raw_readl(®s->channel[ch].ch_event);
349 if (val & TX_SNAPSHOT_LOCKED)
350 break;
351 udelay(1);
352 }
353 if (!(val & TX_SNAPSHOT_LOCKED)) {
354 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
355 return;
356 }
357
358 lo = __raw_readl(®s->channel[ch].tx_snap_lo);
359 hi = __raw_readl(®s->channel[ch].tx_snap_hi);
360 ns = ((u64) hi) << 32;
361 ns |= lo;
362 ns <<= TICKS_NS_SHIFT;
363
364 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
365 shhwtstamps.hwtstamp = ns_to_ktime(ns);
366 skb_tstamp_tx(skb, &shhwtstamps);
367
368 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
369}
370
371static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
372{
373 struct hwtstamp_config cfg;
374 struct ixp46x_ts_regs *regs;
375 struct port *port = netdev_priv(netdev);
376 int ch;
377
378 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
379 return -EFAULT;
380
381 if (cfg.flags) /* reserved for future extensions */
382 return -EINVAL;
383
384 ch = PORT2CHANNEL(port);
385 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
386
387 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
388 return -ERANGE;
389
390 switch (cfg.rx_filter) {
391 case HWTSTAMP_FILTER_NONE:
392 port->hwts_rx_en = 0;
393 break;
394 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
395 port->hwts_rx_en = PTP_SLAVE_MODE;
396 __raw_writel(0, ®s->channel[ch].ch_control);
397 break;
398 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
399 port->hwts_rx_en = PTP_MASTER_MODE;
400 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control);
401 break;
402 default:
403 return -ERANGE;
404 }
405
406 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
407
408 /* Clear out any old time stamps. */
409 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
410 ®s->channel[ch].ch_event);
411
412 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
413}
414
415static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
416{
417 struct hwtstamp_config cfg;
418 struct port *port = netdev_priv(netdev);
419
420 cfg.flags = 0;
421 cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
422
423 switch (port->hwts_rx_en) {
424 case 0:
425 cfg.rx_filter = HWTSTAMP_FILTER_NONE;
426 break;
427 case PTP_SLAVE_MODE:
428 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
429 break;
430 case PTP_MASTER_MODE:
431 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
432 break;
433 default:
434 WARN_ON_ONCE(1);
435 return -ERANGE;
436 }
437
438 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
439}
440
441static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
442 int write, u16 cmd)
443{
444 int cycles = 0;
445
446 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
447 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
448 return -1;
449 }
450
451 if (write) {
452 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
453 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
454 }
455 __raw_writel(((phy_id << 5) | location) & 0xFF,
456 &mdio_regs->mdio_command[2]);
457 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
458 &mdio_regs->mdio_command[3]);
459
460 while ((cycles < MAX_MDIO_RETRIES) &&
461 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
462 udelay(1);
463 cycles++;
464 }
465
466 if (cycles == MAX_MDIO_RETRIES) {
467 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
468 phy_id);
469 return -1;
470 }
471
472#if DEBUG_MDIO
473 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
474 phy_id, write ? "write" : "read", cycles);
475#endif
476
477 if (write)
478 return 0;
479
480 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
481#if DEBUG_MDIO
482 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
483 phy_id);
484#endif
485 return 0xFFFF; /* don't return error */
486 }
487
488 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
489 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
490}
491
492static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
493{
494 unsigned long flags;
495 int ret;
496
497 spin_lock_irqsave(&mdio_lock, flags);
498 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
499 spin_unlock_irqrestore(&mdio_lock, flags);
500#if DEBUG_MDIO
501 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
502 phy_id, location, ret);
503#endif
504 return ret;
505}
506
507static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
508 u16 val)
509{
510 unsigned long flags;
511 int ret;
512
513 spin_lock_irqsave(&mdio_lock, flags);
514 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
515 spin_unlock_irqrestore(&mdio_lock, flags);
516#if DEBUG_MDIO
517 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
518 bus->name, phy_id, location, val, ret);
519#endif
520 return ret;
521}
522
523static int ixp4xx_mdio_register(void)
524{
525 int err;
526
527 if (!(mdio_bus = mdiobus_alloc()))
528 return -ENOMEM;
529
530 if (cpu_is_ixp43x()) {
531 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
532 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
533 return -ENODEV;
534 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
535 } else {
536 /* All MII PHY accesses use NPE-B Ethernet registers */
537 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
538 return -ENODEV;
539 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
540 }
541
542 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
543 spin_lock_init(&mdio_lock);
544 mdio_bus->name = "IXP4xx MII Bus";
545 mdio_bus->read = &ixp4xx_mdio_read;
546 mdio_bus->write = &ixp4xx_mdio_write;
547 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
548
549 if ((err = mdiobus_register(mdio_bus)))
550 mdiobus_free(mdio_bus);
551 return err;
552}
553
554static void ixp4xx_mdio_remove(void)
555{
556 mdiobus_unregister(mdio_bus);
557 mdiobus_free(mdio_bus);
558}
559
560
561static void ixp4xx_adjust_link(struct net_device *dev)
562{
563 struct port *port = netdev_priv(dev);
564 struct phy_device *phydev = dev->phydev;
565
566 if (!phydev->link) {
567 if (port->speed) {
568 port->speed = 0;
569 printk(KERN_INFO "%s: link down\n", dev->name);
570 }
571 return;
572 }
573
574 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
575 return;
576
577 port->speed = phydev->speed;
578 port->duplex = phydev->duplex;
579
580 if (port->duplex)
581 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
582 &port->regs->tx_control[0]);
583 else
584 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
585 &port->regs->tx_control[0]);
586
587 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
588 dev->name, port->speed, port->duplex ? "full" : "half");
589}
590
591
592static inline void debug_pkt(struct net_device *dev, const char *func,
593 u8 *data, int len)
594{
595#if DEBUG_PKT_BYTES
596 int i;
597
598 printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
599 for (i = 0; i < len; i++) {
600 if (i >= DEBUG_PKT_BYTES)
601 break;
602 printk("%s%02X",
603 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
604 data[i]);
605 }
606 printk("\n");
607#endif
608}
609
610
611static inline void debug_desc(u32 phys, struct desc *desc)
612{
613#if DEBUG_DESC
614 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
615 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
616 phys, desc->next, desc->buf_len, desc->pkt_len,
617 desc->data, desc->dest_id, desc->src_id, desc->flags,
618 desc->qos, desc->padlen, desc->vlan_tci,
619 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
620 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
621 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
622 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
623#endif
624}
625
626static inline int queue_get_desc(unsigned int queue, struct port *port,
627 int is_tx)
628{
629 u32 phys, tab_phys, n_desc;
630 struct desc *tab;
631
632 if (!(phys = qmgr_get_entry(queue)))
633 return -1;
634
635 phys &= ~0x1F; /* mask out non-address bits */
636 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
637 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
638 n_desc = (phys - tab_phys) / sizeof(struct desc);
639 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
640 debug_desc(phys, &tab[n_desc]);
641 BUG_ON(tab[n_desc].next);
642 return n_desc;
643}
644
645static inline void queue_put_desc(unsigned int queue, u32 phys,
646 struct desc *desc)
647{
648 debug_desc(phys, desc);
649 BUG_ON(phys & 0x1F);
650 qmgr_put_entry(queue, phys);
651 /* Don't check for queue overflow here, we've allocated sufficient
652 length and queues >= 32 don't support this check anyway. */
653}
654
655
656static inline void dma_unmap_tx(struct port *port, struct desc *desc)
657{
658#ifdef __ARMEB__
659 dma_unmap_single(&port->netdev->dev, desc->data,
660 desc->buf_len, DMA_TO_DEVICE);
661#else
662 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
663 ALIGN((desc->data & 3) + desc->buf_len, 4),
664 DMA_TO_DEVICE);
665#endif
666}
667
668
669static void eth_rx_irq(void *pdev)
670{
671 struct net_device *dev = pdev;
672 struct port *port = netdev_priv(dev);
673
674#if DEBUG_RX
675 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
676#endif
677 qmgr_disable_irq(port->plat->rxq);
678 napi_schedule(&port->napi);
679}
680
681static int eth_poll(struct napi_struct *napi, int budget)
682{
683 struct port *port = container_of(napi, struct port, napi);
684 struct net_device *dev = port->netdev;
685 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
686 int received = 0;
687
688#if DEBUG_RX
689 printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
690#endif
691
692 while (received < budget) {
693 struct sk_buff *skb;
694 struct desc *desc;
695 int n;
696#ifdef __ARMEB__
697 struct sk_buff *temp;
698 u32 phys;
699#endif
700
701 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
702#if DEBUG_RX
703 printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
704 dev->name);
705#endif
706 napi_complete(napi);
707 qmgr_enable_irq(rxq);
708 if (!qmgr_stat_below_low_watermark(rxq) &&
709 napi_reschedule(napi)) { /* not empty again */
710#if DEBUG_RX
711 printk(KERN_DEBUG "%s: eth_poll napi_reschedule succeeded\n",
712 dev->name);
713#endif
714 qmgr_disable_irq(rxq);
715 continue;
716 }
717#if DEBUG_RX
718 printk(KERN_DEBUG "%s: eth_poll all done\n",
719 dev->name);
720#endif
721 return received; /* all work done */
722 }
723
724 desc = rx_desc_ptr(port, n);
725
726#ifdef __ARMEB__
727 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
728 phys = dma_map_single(&dev->dev, skb->data,
729 RX_BUFF_SIZE, DMA_FROM_DEVICE);
730 if (dma_mapping_error(&dev->dev, phys)) {
731 dev_kfree_skb(skb);
732 skb = NULL;
733 }
734 }
735#else
736 skb = netdev_alloc_skb(dev,
737 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
738#endif
739
740 if (!skb) {
741 dev->stats.rx_dropped++;
742 /* put the desc back on RX-ready queue */
743 desc->buf_len = MAX_MRU;
744 desc->pkt_len = 0;
745 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
746 continue;
747 }
748
749 /* process received frame */
750#ifdef __ARMEB__
751 temp = skb;
752 skb = port->rx_buff_tab[n];
753 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
754 RX_BUFF_SIZE, DMA_FROM_DEVICE);
755#else
756 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
757 RX_BUFF_SIZE, DMA_FROM_DEVICE);
758 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
759 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
760#endif
761 skb_reserve(skb, NET_IP_ALIGN);
762 skb_put(skb, desc->pkt_len);
763
764 debug_pkt(dev, "eth_poll", skb->data, skb->len);
765
766 ixp_rx_timestamp(port, skb);
767 skb->protocol = eth_type_trans(skb, dev);
768 dev->stats.rx_packets++;
769 dev->stats.rx_bytes += skb->len;
770 netif_receive_skb(skb);
771
772 /* put the new buffer on RX-free queue */
773#ifdef __ARMEB__
774 port->rx_buff_tab[n] = temp;
775 desc->data = phys + NET_IP_ALIGN;
776#endif
777 desc->buf_len = MAX_MRU;
778 desc->pkt_len = 0;
779 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
780 received++;
781 }
782
783#if DEBUG_RX
784 printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
785#endif
786 return received; /* not all work done */
787}
788
789
790static void eth_txdone_irq(void *unused)
791{
792 u32 phys;
793
794#if DEBUG_TX
795 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
796#endif
797 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
798 u32 npe_id, n_desc;
799 struct port *port;
800 struct desc *desc;
801 int start;
802
803 npe_id = phys & 3;
804 BUG_ON(npe_id >= MAX_NPES);
805 port = npe_port_tab[npe_id];
806 BUG_ON(!port);
807 phys &= ~0x1F; /* mask out non-address bits */
808 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
809 BUG_ON(n_desc >= TX_DESCS);
810 desc = tx_desc_ptr(port, n_desc);
811 debug_desc(phys, desc);
812
813 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
814 port->netdev->stats.tx_packets++;
815 port->netdev->stats.tx_bytes += desc->pkt_len;
816
817 dma_unmap_tx(port, desc);
818#if DEBUG_TX
819 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
820 port->netdev->name, port->tx_buff_tab[n_desc]);
821#endif
822 free_buffer_irq(port->tx_buff_tab[n_desc]);
823 port->tx_buff_tab[n_desc] = NULL;
824 }
825
826 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
827 queue_put_desc(port->plat->txreadyq, phys, desc);
828 if (start) { /* TX-ready queue was empty */
829#if DEBUG_TX
830 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
831 port->netdev->name);
832#endif
833 netif_wake_queue(port->netdev);
834 }
835 }
836}
837
838static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
839{
840 struct port *port = netdev_priv(dev);
841 unsigned int txreadyq = port->plat->txreadyq;
842 int len, offset, bytes, n;
843 void *mem;
844 u32 phys;
845 struct desc *desc;
846
847#if DEBUG_TX
848 printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
849#endif
850
851 if (unlikely(skb->len > MAX_MRU)) {
852 dev_kfree_skb(skb);
853 dev->stats.tx_errors++;
854 return NETDEV_TX_OK;
855 }
856
857 debug_pkt(dev, "eth_xmit", skb->data, skb->len);
858
859 len = skb->len;
860#ifdef __ARMEB__
861 offset = 0; /* no need to keep alignment */
862 bytes = len;
863 mem = skb->data;
864#else
865 offset = (int)skb->data & 3; /* keep 32-bit alignment */
866 bytes = ALIGN(offset + len, 4);
867 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
868 dev_kfree_skb(skb);
869 dev->stats.tx_dropped++;
870 return NETDEV_TX_OK;
871 }
872 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
873#endif
874
875 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
876 if (dma_mapping_error(&dev->dev, phys)) {
877 dev_kfree_skb(skb);
878#ifndef __ARMEB__
879 kfree(mem);
880#endif
881 dev->stats.tx_dropped++;
882 return NETDEV_TX_OK;
883 }
884
885 n = queue_get_desc(txreadyq, port, 1);
886 BUG_ON(n < 0);
887 desc = tx_desc_ptr(port, n);
888
889#ifdef __ARMEB__
890 port->tx_buff_tab[n] = skb;
891#else
892 port->tx_buff_tab[n] = mem;
893#endif
894 desc->data = phys + offset;
895 desc->buf_len = desc->pkt_len = len;
896
897 /* NPE firmware pads short frames with zeros internally */
898 wmb();
899 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
900
901 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
902#if DEBUG_TX
903 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
904#endif
905 netif_stop_queue(dev);
906 /* we could miss TX ready interrupt */
907 /* really empty in fact */
908 if (!qmgr_stat_below_low_watermark(txreadyq)) {
909#if DEBUG_TX
910 printk(KERN_DEBUG "%s: eth_xmit ready again\n",
911 dev->name);
912#endif
913 netif_wake_queue(dev);
914 }
915 }
916
917#if DEBUG_TX
918 printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
919#endif
920
921 ixp_tx_timestamp(port, skb);
922 skb_tx_timestamp(skb);
923
924#ifndef __ARMEB__
925 dev_kfree_skb(skb);
926#endif
927 return NETDEV_TX_OK;
928}
929
930
931static void eth_set_mcast_list(struct net_device *dev)
932{
933 struct port *port = netdev_priv(dev);
934 struct netdev_hw_addr *ha;
935 u8 diffs[ETH_ALEN], *addr;
936 int i;
937 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
938
939 if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) {
940 for (i = 0; i < ETH_ALEN; i++) {
941 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
942 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
943 }
944 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
945 &port->regs->rx_control[0]);
946 return;
947 }
948
949 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
950 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
951 &port->regs->rx_control[0]);
952 return;
953 }
954
955 eth_zero_addr(diffs);
956
957 addr = NULL;
958 netdev_for_each_mc_addr(ha, dev) {
959 if (!addr)
960 addr = ha->addr; /* first MAC address */
961 for (i = 0; i < ETH_ALEN; i++)
962 diffs[i] |= addr[i] ^ ha->addr[i];
963 }
964
965 for (i = 0; i < ETH_ALEN; i++) {
966 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
967 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
968 }
969
970 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
971 &port->regs->rx_control[0]);
972}
973
974
975static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
976{
977 if (!netif_running(dev))
978 return -EINVAL;
979
980 if (cpu_is_ixp46x()) {
981 if (cmd == SIOCSHWTSTAMP)
982 return hwtstamp_set(dev, req);
983 if (cmd == SIOCGHWTSTAMP)
984 return hwtstamp_get(dev, req);
985 }
986
987 return phy_mii_ioctl(dev->phydev, req, cmd);
988}
989
990/* ethtool support */
991
992static void ixp4xx_get_drvinfo(struct net_device *dev,
993 struct ethtool_drvinfo *info)
994{
995 struct port *port = netdev_priv(dev);
996
997 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
998 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
999 port->firmware[0], port->firmware[1],
1000 port->firmware[2], port->firmware[3]);
1001 strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
1002}
1003
1004int ixp46x_phc_index = -1;
1005EXPORT_SYMBOL_GPL(ixp46x_phc_index);
1006
1007static int ixp4xx_get_ts_info(struct net_device *dev,
1008 struct ethtool_ts_info *info)
1009{
1010 if (!cpu_is_ixp46x()) {
1011 info->so_timestamping =
1012 SOF_TIMESTAMPING_TX_SOFTWARE |
1013 SOF_TIMESTAMPING_RX_SOFTWARE |
1014 SOF_TIMESTAMPING_SOFTWARE;
1015 info->phc_index = -1;
1016 return 0;
1017 }
1018 info->so_timestamping =
1019 SOF_TIMESTAMPING_TX_HARDWARE |
1020 SOF_TIMESTAMPING_RX_HARDWARE |
1021 SOF_TIMESTAMPING_RAW_HARDWARE;
1022 info->phc_index = ixp46x_phc_index;
1023 info->tx_types =
1024 (1 << HWTSTAMP_TX_OFF) |
1025 (1 << HWTSTAMP_TX_ON);
1026 info->rx_filters =
1027 (1 << HWTSTAMP_FILTER_NONE) |
1028 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1029 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1030 return 0;
1031}
1032
1033static const struct ethtool_ops ixp4xx_ethtool_ops = {
1034 .get_drvinfo = ixp4xx_get_drvinfo,
1035 .nway_reset = phy_ethtool_nway_reset,
1036 .get_link = ethtool_op_get_link,
1037 .get_ts_info = ixp4xx_get_ts_info,
1038 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1039 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1040};
1041
1042
1043static int request_queues(struct port *port)
1044{
1045 int err;
1046
1047 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1048 "%s:RX-free", port->netdev->name);
1049 if (err)
1050 return err;
1051
1052 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1053 "%s:RX", port->netdev->name);
1054 if (err)
1055 goto rel_rxfree;
1056
1057 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1058 "%s:TX", port->netdev->name);
1059 if (err)
1060 goto rel_rx;
1061
1062 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1063 "%s:TX-ready", port->netdev->name);
1064 if (err)
1065 goto rel_tx;
1066
1067 /* TX-done queue handles skbs sent out by the NPEs */
1068 if (!ports_open) {
1069 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1070 "%s:TX-done", DRV_NAME);
1071 if (err)
1072 goto rel_txready;
1073 }
1074 return 0;
1075
1076rel_txready:
1077 qmgr_release_queue(port->plat->txreadyq);
1078rel_tx:
1079 qmgr_release_queue(TX_QUEUE(port->id));
1080rel_rx:
1081 qmgr_release_queue(port->plat->rxq);
1082rel_rxfree:
1083 qmgr_release_queue(RXFREE_QUEUE(port->id));
1084 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1085 port->netdev->name);
1086 return err;
1087}
1088
1089static void release_queues(struct port *port)
1090{
1091 qmgr_release_queue(RXFREE_QUEUE(port->id));
1092 qmgr_release_queue(port->plat->rxq);
1093 qmgr_release_queue(TX_QUEUE(port->id));
1094 qmgr_release_queue(port->plat->txreadyq);
1095
1096 if (!ports_open)
1097 qmgr_release_queue(TXDONE_QUEUE);
1098}
1099
1100static int init_queues(struct port *port)
1101{
1102 int i;
1103
1104 if (!ports_open) {
1105 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1106 POOL_ALLOC_SIZE, 32, 0);
1107 if (!dma_pool)
1108 return -ENOMEM;
1109 }
1110
1111 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1112 &port->desc_tab_phys)))
1113 return -ENOMEM;
1114 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1115 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1116 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1117
1118 /* Setup RX buffers */
1119 for (i = 0; i < RX_DESCS; i++) {
1120 struct desc *desc = rx_desc_ptr(port, i);
1121 buffer_t *buff; /* skb or kmalloc()ated memory */
1122 void *data;
1123#ifdef __ARMEB__
1124 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1125 return -ENOMEM;
1126 data = buff->data;
1127#else
1128 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1129 return -ENOMEM;
1130 data = buff;
1131#endif
1132 desc->buf_len = MAX_MRU;
1133 desc->data = dma_map_single(&port->netdev->dev, data,
1134 RX_BUFF_SIZE, DMA_FROM_DEVICE);
1135 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1136 free_buffer(buff);
1137 return -EIO;
1138 }
1139 desc->data += NET_IP_ALIGN;
1140 port->rx_buff_tab[i] = buff;
1141 }
1142
1143 return 0;
1144}
1145
1146static void destroy_queues(struct port *port)
1147{
1148 int i;
1149
1150 if (port->desc_tab) {
1151 for (i = 0; i < RX_DESCS; i++) {
1152 struct desc *desc = rx_desc_ptr(port, i);
1153 buffer_t *buff = port->rx_buff_tab[i];
1154 if (buff) {
1155 dma_unmap_single(&port->netdev->dev,
1156 desc->data - NET_IP_ALIGN,
1157 RX_BUFF_SIZE, DMA_FROM_DEVICE);
1158 free_buffer(buff);
1159 }
1160 }
1161 for (i = 0; i < TX_DESCS; i++) {
1162 struct desc *desc = tx_desc_ptr(port, i);
1163 buffer_t *buff = port->tx_buff_tab[i];
1164 if (buff) {
1165 dma_unmap_tx(port, desc);
1166 free_buffer(buff);
1167 }
1168 }
1169 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1170 port->desc_tab = NULL;
1171 }
1172
1173 if (!ports_open && dma_pool) {
1174 dma_pool_destroy(dma_pool);
1175 dma_pool = NULL;
1176 }
1177}
1178
1179static int eth_open(struct net_device *dev)
1180{
1181 struct port *port = netdev_priv(dev);
1182 struct npe *npe = port->npe;
1183 struct msg msg;
1184 int i, err;
1185
1186 if (!npe_running(npe)) {
1187 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1188 if (err)
1189 return err;
1190
1191 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1192 printk(KERN_ERR "%s: %s not responding\n", dev->name,
1193 npe_name(npe));
1194 return -EIO;
1195 }
1196 port->firmware[0] = msg.byte4;
1197 port->firmware[1] = msg.byte5;
1198 port->firmware[2] = msg.byte6;
1199 port->firmware[3] = msg.byte7;
1200 }
1201
1202 memset(&msg, 0, sizeof(msg));
1203 msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1204 msg.eth_id = port->id;
1205 msg.byte5 = port->plat->rxq | 0x80;
1206 msg.byte7 = port->plat->rxq << 4;
1207 for (i = 0; i < 8; i++) {
1208 msg.byte3 = i;
1209 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1210 return -EIO;
1211 }
1212
1213 msg.cmd = NPE_EDB_SETPORTADDRESS;
1214 msg.eth_id = PHYSICAL_ID(port->id);
1215 msg.byte2 = dev->dev_addr[0];
1216 msg.byte3 = dev->dev_addr[1];
1217 msg.byte4 = dev->dev_addr[2];
1218 msg.byte5 = dev->dev_addr[3];
1219 msg.byte6 = dev->dev_addr[4];
1220 msg.byte7 = dev->dev_addr[5];
1221 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1222 return -EIO;
1223
1224 memset(&msg, 0, sizeof(msg));
1225 msg.cmd = NPE_FW_SETFIREWALLMODE;
1226 msg.eth_id = port->id;
1227 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1228 return -EIO;
1229
1230 if ((err = request_queues(port)) != 0)
1231 return err;
1232
1233 if ((err = init_queues(port)) != 0) {
1234 destroy_queues(port);
1235 release_queues(port);
1236 return err;
1237 }
1238
1239 port->speed = 0; /* force "link up" message */
1240 phy_start(dev->phydev);
1241
1242 for (i = 0; i < ETH_ALEN; i++)
1243 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1244 __raw_writel(0x08, &port->regs->random_seed);
1245 __raw_writel(0x12, &port->regs->partial_empty_threshold);
1246 __raw_writel(0x30, &port->regs->partial_full_threshold);
1247 __raw_writel(0x08, &port->regs->tx_start_bytes);
1248 __raw_writel(0x15, &port->regs->tx_deferral);
1249 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1250 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1251 __raw_writel(0x80, &port->regs->slot_time);
1252 __raw_writel(0x01, &port->regs->int_clock_threshold);
1253
1254 /* Populate queues with buffers, no failure after this point */
1255 for (i = 0; i < TX_DESCS; i++)
1256 queue_put_desc(port->plat->txreadyq,
1257 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1258
1259 for (i = 0; i < RX_DESCS; i++)
1260 queue_put_desc(RXFREE_QUEUE(port->id),
1261 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1262
1263 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1264 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1265 __raw_writel(0, &port->regs->rx_control[1]);
1266 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1267
1268 napi_enable(&port->napi);
1269 eth_set_mcast_list(dev);
1270 netif_start_queue(dev);
1271
1272 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1273 eth_rx_irq, dev);
1274 if (!ports_open) {
1275 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1276 eth_txdone_irq, NULL);
1277 qmgr_enable_irq(TXDONE_QUEUE);
1278 }
1279 ports_open++;
1280 /* we may already have RX data, enables IRQ */
1281 napi_schedule(&port->napi);
1282 return 0;
1283}
1284
1285static int eth_close(struct net_device *dev)
1286{
1287 struct port *port = netdev_priv(dev);
1288 struct msg msg;
1289 int buffs = RX_DESCS; /* allocated RX buffers */
1290 int i;
1291
1292 ports_open--;
1293 qmgr_disable_irq(port->plat->rxq);
1294 napi_disable(&port->napi);
1295 netif_stop_queue(dev);
1296
1297 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1298 buffs--;
1299
1300 memset(&msg, 0, sizeof(msg));
1301 msg.cmd = NPE_SETLOOPBACK_MODE;
1302 msg.eth_id = port->id;
1303 msg.byte3 = 1;
1304 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1305 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1306
1307 i = 0;
1308 do { /* drain RX buffers */
1309 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1310 buffs--;
1311 if (!buffs)
1312 break;
1313 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1314 /* we have to inject some packet */
1315 struct desc *desc;
1316 u32 phys;
1317 int n = queue_get_desc(port->plat->txreadyq, port, 1);
1318 BUG_ON(n < 0);
1319 desc = tx_desc_ptr(port, n);
1320 phys = tx_desc_phys(port, n);
1321 desc->buf_len = desc->pkt_len = 1;
1322 wmb();
1323 queue_put_desc(TX_QUEUE(port->id), phys, desc);
1324 }
1325 udelay(1);
1326 } while (++i < MAX_CLOSE_WAIT);
1327
1328 if (buffs)
1329 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1330 " left in NPE\n", dev->name, buffs);
1331#if DEBUG_CLOSE
1332 if (!buffs)
1333 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1334#endif
1335
1336 buffs = TX_DESCS;
1337 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1338 buffs--; /* cancel TX */
1339
1340 i = 0;
1341 do {
1342 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1343 buffs--;
1344 if (!buffs)
1345 break;
1346 } while (++i < MAX_CLOSE_WAIT);
1347
1348 if (buffs)
1349 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1350 "left in NPE\n", dev->name, buffs);
1351#if DEBUG_CLOSE
1352 if (!buffs)
1353 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1354#endif
1355
1356 msg.byte3 = 0;
1357 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1358 printk(KERN_CRIT "%s: unable to disable loopback\n",
1359 dev->name);
1360
1361 phy_stop(dev->phydev);
1362
1363 if (!ports_open)
1364 qmgr_disable_irq(TXDONE_QUEUE);
1365 destroy_queues(port);
1366 release_queues(port);
1367 return 0;
1368}
1369
1370static const struct net_device_ops ixp4xx_netdev_ops = {
1371 .ndo_open = eth_open,
1372 .ndo_stop = eth_close,
1373 .ndo_start_xmit = eth_xmit,
1374 .ndo_set_rx_mode = eth_set_mcast_list,
1375 .ndo_do_ioctl = eth_ioctl,
1376 .ndo_set_mac_address = eth_mac_addr,
1377 .ndo_validate_addr = eth_validate_addr,
1378};
1379
1380static int eth_init_one(struct platform_device *pdev)
1381{
1382 struct port *port;
1383 struct net_device *dev;
1384 struct eth_plat_info *plat = dev_get_platdata(&pdev->dev);
1385 struct phy_device *phydev = NULL;
1386 u32 regs_phys;
1387 char phy_id[MII_BUS_ID_SIZE + 3];
1388 int err;
1389
1390 if (!(dev = alloc_etherdev(sizeof(struct port))))
1391 return -ENOMEM;
1392
1393 SET_NETDEV_DEV(dev, &pdev->dev);
1394 port = netdev_priv(dev);
1395 port->netdev = dev;
1396 port->id = pdev->id;
1397
1398 switch (port->id) {
1399 case IXP4XX_ETH_NPEA:
1400 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1401 regs_phys = IXP4XX_EthA_BASE_PHYS;
1402 break;
1403 case IXP4XX_ETH_NPEB:
1404 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1405 regs_phys = IXP4XX_EthB_BASE_PHYS;
1406 break;
1407 case IXP4XX_ETH_NPEC:
1408 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1409 regs_phys = IXP4XX_EthC_BASE_PHYS;
1410 break;
1411 default:
1412 err = -ENODEV;
1413 goto err_free;
1414 }
1415
1416 dev->netdev_ops = &ixp4xx_netdev_ops;
1417 dev->ethtool_ops = &ixp4xx_ethtool_ops;
1418 dev->tx_queue_len = 100;
1419
1420 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1421
1422 if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1423 err = -EIO;
1424 goto err_free;
1425 }
1426
1427 port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1428 if (!port->mem_res) {
1429 err = -EBUSY;
1430 goto err_npe_rel;
1431 }
1432
1433 port->plat = plat;
1434 npe_port_tab[NPE_ID(port->id)] = port;
1435 memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1436
1437 platform_set_drvdata(pdev, dev);
1438
1439 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1440 &port->regs->core_control);
1441 udelay(50);
1442 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1443 udelay(50);
1444
1445 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
1446 mdio_bus->id, plat->phy);
1447 phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link,
1448 PHY_INTERFACE_MODE_MII);
1449 if (IS_ERR(phydev)) {
1450 err = PTR_ERR(phydev);
1451 goto err_free_mem;
1452 }
1453
1454 phydev->irq = PHY_POLL;
1455
1456 if ((err = register_netdev(dev)))
1457 goto err_phy_dis;
1458
1459 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1460 npe_name(port->npe));
1461
1462 return 0;
1463
1464err_phy_dis:
1465 phy_disconnect(phydev);
1466err_free_mem:
1467 npe_port_tab[NPE_ID(port->id)] = NULL;
1468 release_resource(port->mem_res);
1469err_npe_rel:
1470 npe_release(port->npe);
1471err_free:
1472 free_netdev(dev);
1473 return err;
1474}
1475
1476static int eth_remove_one(struct platform_device *pdev)
1477{
1478 struct net_device *dev = platform_get_drvdata(pdev);
1479 struct phy_device *phydev = dev->phydev;
1480 struct port *port = netdev_priv(dev);
1481
1482 unregister_netdev(dev);
1483 phy_disconnect(phydev);
1484 npe_port_tab[NPE_ID(port->id)] = NULL;
1485 npe_release(port->npe);
1486 release_resource(port->mem_res);
1487 free_netdev(dev);
1488 return 0;
1489}
1490
1491static struct platform_driver ixp4xx_eth_driver = {
1492 .driver.name = DRV_NAME,
1493 .probe = eth_init_one,
1494 .remove = eth_remove_one,
1495};
1496
1497static int __init eth_init_module(void)
1498{
1499 int err;
1500 if ((err = ixp4xx_mdio_register()))
1501 return err;
1502 return platform_driver_register(&ixp4xx_eth_driver);
1503}
1504
1505static void __exit eth_cleanup_module(void)
1506{
1507 platform_driver_unregister(&ixp4xx_eth_driver);
1508 ixp4xx_mdio_remove();
1509}
1510
1511MODULE_AUTHOR("Krzysztof Halasa");
1512MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1513MODULE_LICENSE("GPL v2");
1514MODULE_ALIAS("platform:ixp4xx_eth");
1515module_init(eth_init_module);
1516module_exit(eth_cleanup_module);