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1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2016 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe.h"
34#include "ixgbe_phy.h"
35#include "ixgbe_x540.h"
36
37#define IXGBE_X540_MAX_TX_QUEUES 128
38#define IXGBE_X540_MAX_RX_QUEUES 128
39#define IXGBE_X540_RAR_ENTRIES 128
40#define IXGBE_X540_MC_TBL_SIZE 128
41#define IXGBE_X540_VFT_TBL_SIZE 128
42#define IXGBE_X540_RX_PB_SIZE 384
43
44static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
45static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
46static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
48
49enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
50{
51 return ixgbe_media_type_copper;
52}
53
54s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
55{
56 struct ixgbe_mac_info *mac = &hw->mac;
57 struct ixgbe_phy_info *phy = &hw->phy;
58
59 /* set_phy_power was set by default to NULL */
60 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
61
62 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
63 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
64 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
65 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
66 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
67 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
68 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
69
70 return 0;
71}
72
73/**
74 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
75 * @hw: pointer to hardware structure
76 * @speed: new link speed
77 * @autoneg_wait_to_complete: true when waiting for completion is needed
78 **/
79s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
80 bool autoneg_wait_to_complete)
81{
82 return hw->phy.ops.setup_link_speed(hw, speed,
83 autoneg_wait_to_complete);
84}
85
86/**
87 * ixgbe_reset_hw_X540 - Perform hardware reset
88 * @hw: pointer to hardware structure
89 *
90 * Resets the hardware by resetting the transmit and receive units, masks
91 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
92 * reset.
93 **/
94s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
95{
96 s32 status;
97 u32 ctrl, i;
98 u32 swfw_mask = hw->phy.phy_semaphore_mask;
99
100 /* Call adapter stop to disable tx/rx and clear interrupts */
101 status = hw->mac.ops.stop_adapter(hw);
102 if (status)
103 return status;
104
105 /* flush pending Tx transactions */
106 ixgbe_clear_tx_pending(hw);
107
108mac_reset_top:
109 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
110 if (status) {
111 hw_dbg(hw, "semaphore failed with %d", status);
112 return IXGBE_ERR_SWFW_SYNC;
113 }
114
115 ctrl = IXGBE_CTRL_RST;
116 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
117 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
118 IXGBE_WRITE_FLUSH(hw);
119 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
120 usleep_range(1000, 1200);
121
122 /* Poll for reset bit to self-clear indicating reset is complete */
123 for (i = 0; i < 10; i++) {
124 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
125 if (!(ctrl & IXGBE_CTRL_RST_MASK))
126 break;
127 udelay(1);
128 }
129
130 if (ctrl & IXGBE_CTRL_RST_MASK) {
131 status = IXGBE_ERR_RESET_FAILED;
132 hw_dbg(hw, "Reset polling failed to complete.\n");
133 }
134 msleep(100);
135
136 /*
137 * Double resets are required for recovery from certain error
138 * conditions. Between resets, it is necessary to stall to allow time
139 * for any pending HW events to complete.
140 */
141 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
142 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
143 goto mac_reset_top;
144 }
145
146 /* Set the Rx packet buffer size. */
147 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
148
149 /* Store the permanent mac address */
150 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
151
152 /*
153 * Store MAC address from RAR0, clear receive address registers, and
154 * clear the multicast table. Also reset num_rar_entries to 128,
155 * since we modify this value when programming the SAN MAC address.
156 */
157 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
158 hw->mac.ops.init_rx_addrs(hw);
159
160 /* Store the permanent SAN mac address */
161 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
162
163 /* Add the SAN MAC address to the RAR only if it's a valid address */
164 if (is_valid_ether_addr(hw->mac.san_addr)) {
165 /* Save the SAN MAC RAR index */
166 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
167
168 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
169 hw->mac.san_addr, 0, IXGBE_RAH_AV);
170
171 /* clear VMDq pool/queue selection for this RAR */
172 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
173 IXGBE_CLEAR_VMDQ_ALL);
174
175 /* Reserve the last RAR for the SAN MAC address */
176 hw->mac.num_rar_entries--;
177 }
178
179 /* Store the alternative WWNN/WWPN prefix */
180 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
181 &hw->mac.wwpn_prefix);
182
183 return status;
184}
185
186/**
187 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
188 * @hw: pointer to hardware structure
189 *
190 * Starts the hardware using the generic start_hw function
191 * and the generation start_hw function.
192 * Then performs revision-specific operations, if any.
193 **/
194s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
195{
196 s32 ret_val;
197
198 ret_val = ixgbe_start_hw_generic(hw);
199 if (ret_val)
200 return ret_val;
201
202 return ixgbe_start_hw_gen2(hw);
203}
204
205/**
206 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
207 * @hw: pointer to hardware structure
208 *
209 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
210 * ixgbe_hw struct in order to set up EEPROM access.
211 **/
212s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
213{
214 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
215 u32 eec;
216 u16 eeprom_size;
217
218 if (eeprom->type == ixgbe_eeprom_uninitialized) {
219 eeprom->semaphore_delay = 10;
220 eeprom->type = ixgbe_flash;
221
222 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
223 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
224 IXGBE_EEC_SIZE_SHIFT);
225 eeprom->word_size = BIT(eeprom_size +
226 IXGBE_EEPROM_WORD_SIZE_SHIFT);
227
228 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
229 eeprom->type, eeprom->word_size);
230 }
231
232 return 0;
233}
234
235/**
236 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
237 * @hw: pointer to hardware structure
238 * @offset: offset of word in the EEPROM to read
239 * @data: word read from the EEPROM
240 *
241 * Reads a 16 bit word from the EEPROM using the EERD register.
242 **/
243static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
244{
245 s32 status;
246
247 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
248 return IXGBE_ERR_SWFW_SYNC;
249
250 status = ixgbe_read_eerd_generic(hw, offset, data);
251
252 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
253 return status;
254}
255
256/**
257 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
258 * @hw: pointer to hardware structure
259 * @offset: offset of word in the EEPROM to read
260 * @words: number of words
261 * @data: word(s) read from the EEPROM
262 *
263 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
264 **/
265static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
266 u16 offset, u16 words, u16 *data)
267{
268 s32 status;
269
270 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
271 return IXGBE_ERR_SWFW_SYNC;
272
273 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
274
275 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
276 return status;
277}
278
279/**
280 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
281 * @hw: pointer to hardware structure
282 * @offset: offset of word in the EEPROM to write
283 * @data: word write to the EEPROM
284 *
285 * Write a 16 bit word to the EEPROM using the EEWR register.
286 **/
287static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
288{
289 s32 status;
290
291 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
292 return IXGBE_ERR_SWFW_SYNC;
293
294 status = ixgbe_write_eewr_generic(hw, offset, data);
295
296 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
297 return status;
298}
299
300/**
301 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
302 * @hw: pointer to hardware structure
303 * @offset: offset of word in the EEPROM to write
304 * @words: number of words
305 * @data: word(s) write to the EEPROM
306 *
307 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
308 **/
309static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
310 u16 offset, u16 words, u16 *data)
311{
312 s32 status;
313
314 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
315 return IXGBE_ERR_SWFW_SYNC;
316
317 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
318
319 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
320 return status;
321}
322
323/**
324 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
325 *
326 * This function does not use synchronization for EERD and EEWR. It can
327 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
328 *
329 * @hw: pointer to hardware structure
330 **/
331static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
332{
333 u16 i;
334 u16 j;
335 u16 checksum = 0;
336 u16 length = 0;
337 u16 pointer = 0;
338 u16 word = 0;
339 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
340 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
341
342 /*
343 * Do not use hw->eeprom.ops.read because we do not want to take
344 * the synchronization semaphores here. Instead use
345 * ixgbe_read_eerd_generic
346 */
347
348 /* Include 0x0-0x3F in the checksum */
349 for (i = 0; i < checksum_last_word; i++) {
350 if (ixgbe_read_eerd_generic(hw, i, &word)) {
351 hw_dbg(hw, "EEPROM read failed\n");
352 return IXGBE_ERR_EEPROM;
353 }
354 checksum += word;
355 }
356
357 /*
358 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
359 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
360 */
361 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
362 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
363 continue;
364
365 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
366 hw_dbg(hw, "EEPROM read failed\n");
367 break;
368 }
369
370 /* Skip pointer section if the pointer is invalid. */
371 if (pointer == 0xFFFF || pointer == 0 ||
372 pointer >= hw->eeprom.word_size)
373 continue;
374
375 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
376 hw_dbg(hw, "EEPROM read failed\n");
377 return IXGBE_ERR_EEPROM;
378 break;
379 }
380
381 /* Skip pointer section if length is invalid. */
382 if (length == 0xFFFF || length == 0 ||
383 (pointer + length) >= hw->eeprom.word_size)
384 continue;
385
386 for (j = pointer + 1; j <= pointer + length; j++) {
387 if (ixgbe_read_eerd_generic(hw, j, &word)) {
388 hw_dbg(hw, "EEPROM read failed\n");
389 return IXGBE_ERR_EEPROM;
390 }
391 checksum += word;
392 }
393 }
394
395 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
396
397 return (s32)checksum;
398}
399
400/**
401 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
402 * @hw: pointer to hardware structure
403 * @checksum_val: calculated checksum
404 *
405 * Performs checksum calculation and validates the EEPROM checksum. If the
406 * caller does not need checksum_val, the value can be NULL.
407 **/
408static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
409 u16 *checksum_val)
410{
411 s32 status;
412 u16 checksum;
413 u16 read_checksum = 0;
414
415 /* Read the first word from the EEPROM. If this times out or fails, do
416 * not continue or we could be in for a very long wait while every
417 * EEPROM read fails
418 */
419 status = hw->eeprom.ops.read(hw, 0, &checksum);
420 if (status) {
421 hw_dbg(hw, "EEPROM read failed\n");
422 return status;
423 }
424
425 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
426 return IXGBE_ERR_SWFW_SYNC;
427
428 status = hw->eeprom.ops.calc_checksum(hw);
429 if (status < 0)
430 goto out;
431
432 checksum = (u16)(status & 0xffff);
433
434 /* Do not use hw->eeprom.ops.read because we do not want to take
435 * the synchronization semaphores twice here.
436 */
437 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
438 &read_checksum);
439 if (status)
440 goto out;
441
442 /* Verify read checksum from EEPROM is the same as
443 * calculated checksum
444 */
445 if (read_checksum != checksum) {
446 hw_dbg(hw, "Invalid EEPROM checksum");
447 status = IXGBE_ERR_EEPROM_CHECKSUM;
448 }
449
450 /* If the user cares, return the calculated checksum */
451 if (checksum_val)
452 *checksum_val = checksum;
453
454out:
455 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
456
457 return status;
458}
459
460/**
461 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
462 * @hw: pointer to hardware structure
463 *
464 * After writing EEPROM to shadow RAM using EEWR register, software calculates
465 * checksum and updates the EEPROM and instructs the hardware to update
466 * the flash.
467 **/
468static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
469{
470 s32 status;
471 u16 checksum;
472
473 /* Read the first word from the EEPROM. If this times out or fails, do
474 * not continue or we could be in for a very long wait while every
475 * EEPROM read fails
476 */
477 status = hw->eeprom.ops.read(hw, 0, &checksum);
478 if (status) {
479 hw_dbg(hw, "EEPROM read failed\n");
480 return status;
481 }
482
483 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
484 return IXGBE_ERR_SWFW_SYNC;
485
486 status = hw->eeprom.ops.calc_checksum(hw);
487 if (status < 0)
488 goto out;
489
490 checksum = (u16)(status & 0xffff);
491
492 /* Do not use hw->eeprom.ops.write because we do not want to
493 * take the synchronization semaphores twice here.
494 */
495 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
496 if (status)
497 goto out;
498
499 status = ixgbe_update_flash_X540(hw);
500
501out:
502 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
503 return status;
504}
505
506/**
507 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
508 * @hw: pointer to hardware structure
509 *
510 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
511 * EEPROM from shadow RAM to the flash device.
512 **/
513static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
514{
515 u32 flup;
516 s32 status;
517
518 status = ixgbe_poll_flash_update_done_X540(hw);
519 if (status == IXGBE_ERR_EEPROM) {
520 hw_dbg(hw, "Flash update time out\n");
521 return status;
522 }
523
524 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
525 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
526
527 status = ixgbe_poll_flash_update_done_X540(hw);
528 if (status == 0)
529 hw_dbg(hw, "Flash update complete\n");
530 else
531 hw_dbg(hw, "Flash update time out\n");
532
533 if (hw->revision_id == 0) {
534 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
535
536 if (flup & IXGBE_EEC_SEC1VAL) {
537 flup |= IXGBE_EEC_FLUP;
538 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
539 }
540
541 status = ixgbe_poll_flash_update_done_X540(hw);
542 if (status == 0)
543 hw_dbg(hw, "Flash update complete\n");
544 else
545 hw_dbg(hw, "Flash update time out\n");
546 }
547
548 return status;
549}
550
551/**
552 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
553 * @hw: pointer to hardware structure
554 *
555 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
556 * flash update is done.
557 **/
558static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
559{
560 u32 i;
561 u32 reg;
562
563 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
564 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
565 if (reg & IXGBE_EEC_FLUDONE)
566 return 0;
567 udelay(5);
568 }
569 return IXGBE_ERR_EEPROM;
570}
571
572/**
573 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
574 * @hw: pointer to hardware structure
575 * @mask: Mask to specify which semaphore to acquire
576 *
577 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
578 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
579 **/
580s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
581{
582 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
583 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
584 u32 fwmask = swmask << 5;
585 u32 timeout = 200;
586 u32 hwmask = 0;
587 u32 swfw_sync;
588 u32 i;
589
590 if (swmask & IXGBE_GSSR_EEP_SM)
591 hwmask = IXGBE_GSSR_FLASH_SM;
592
593 /* SW only mask does not have FW bit pair */
594 if (mask & IXGBE_GSSR_SW_MNG_SM)
595 swmask |= IXGBE_GSSR_SW_MNG_SM;
596
597 swmask |= swi2c_mask;
598 fwmask |= swi2c_mask << 2;
599 for (i = 0; i < timeout; i++) {
600 /* SW NVM semaphore bit is used for access to all
601 * SW_FW_SYNC bits (not just NVM)
602 */
603 if (ixgbe_get_swfw_sync_semaphore(hw))
604 return IXGBE_ERR_SWFW_SYNC;
605
606 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
607 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
608 swfw_sync |= swmask;
609 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
610 ixgbe_release_swfw_sync_semaphore(hw);
611 usleep_range(5000, 6000);
612 return 0;
613 }
614 /* Firmware currently using resource (fwmask), hardware
615 * currently using resource (hwmask), or other software
616 * thread currently using resource (swmask)
617 */
618 ixgbe_release_swfw_sync_semaphore(hw);
619 usleep_range(5000, 10000);
620 }
621
622 /* If the resource is not released by the FW/HW the SW can assume that
623 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
624 * of the requested resource(s) while ignoring the corresponding FW/HW
625 * bits in the SW_FW_SYNC register.
626 */
627 if (ixgbe_get_swfw_sync_semaphore(hw))
628 return IXGBE_ERR_SWFW_SYNC;
629 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
630 if (swfw_sync & (fwmask | hwmask)) {
631 swfw_sync |= swmask;
632 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
633 ixgbe_release_swfw_sync_semaphore(hw);
634 usleep_range(5000, 6000);
635 return 0;
636 }
637 /* If the resource is not released by other SW the SW can assume that
638 * the other SW malfunctions. In that case the SW should clear all SW
639 * flags that it does not own and then repeat the whole process once
640 * again.
641 */
642 if (swfw_sync & swmask) {
643 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
644 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
645 IXGBE_GSSR_SW_MNG_SM;
646
647 if (swi2c_mask)
648 rmask |= IXGBE_GSSR_I2C_MASK;
649 ixgbe_release_swfw_sync_X540(hw, rmask);
650 ixgbe_release_swfw_sync_semaphore(hw);
651 return IXGBE_ERR_SWFW_SYNC;
652 }
653 ixgbe_release_swfw_sync_semaphore(hw);
654
655 return IXGBE_ERR_SWFW_SYNC;
656}
657
658/**
659 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
660 * @hw: pointer to hardware structure
661 * @mask: Mask to specify which semaphore to release
662 *
663 * Releases the SWFW semaphore through the SW_FW_SYNC register
664 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
665 **/
666void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
667{
668 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
669 u32 swfw_sync;
670
671 if (mask & IXGBE_GSSR_I2C_MASK)
672 swmask |= mask & IXGBE_GSSR_I2C_MASK;
673 ixgbe_get_swfw_sync_semaphore(hw);
674
675 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
676 swfw_sync &= ~swmask;
677 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
678
679 ixgbe_release_swfw_sync_semaphore(hw);
680 usleep_range(5000, 6000);
681}
682
683/**
684 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
685 * @hw: pointer to hardware structure
686 *
687 * Sets the hardware semaphores so SW/FW can gain control of shared resources
688 */
689static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
690{
691 u32 timeout = 2000;
692 u32 i;
693 u32 swsm;
694
695 /* Get SMBI software semaphore between device drivers first */
696 for (i = 0; i < timeout; i++) {
697 /* If the SMBI bit is 0 when we read it, then the bit will be
698 * set and we have the semaphore
699 */
700 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
701 if (!(swsm & IXGBE_SWSM_SMBI))
702 break;
703 usleep_range(50, 100);
704 }
705
706 if (i == timeout) {
707 hw_dbg(hw,
708 "Software semaphore SMBI between device drivers not granted.\n");
709 return IXGBE_ERR_EEPROM;
710 }
711
712 /* Now get the semaphore between SW/FW through the REGSMP bit */
713 for (i = 0; i < timeout; i++) {
714 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
715 if (!(swsm & IXGBE_SWFW_REGSMP))
716 return 0;
717
718 usleep_range(50, 100);
719 }
720
721 /* Release semaphores and return error if SW NVM semaphore
722 * was not granted because we do not have access to the EEPROM
723 */
724 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
725 ixgbe_release_swfw_sync_semaphore(hw);
726 return IXGBE_ERR_EEPROM;
727}
728
729/**
730 * ixgbe_release_nvm_semaphore - Release hardware semaphore
731 * @hw: pointer to hardware structure
732 *
733 * This function clears hardware semaphore bits.
734 **/
735static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
736{
737 u32 swsm;
738
739 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
740
741 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
742 swsm &= ~IXGBE_SWFW_REGSMP;
743 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
744
745 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
746 swsm &= ~IXGBE_SWSM_SMBI;
747 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
748
749 IXGBE_WRITE_FLUSH(hw);
750}
751
752/**
753 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
754 * @hw: pointer to hardware structure
755 *
756 * This function reset hardware semaphore bits for a semaphore that may
757 * have be left locked due to a catastrophic failure.
758 **/
759void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
760{
761 u32 rmask;
762
763 /* First try to grab the semaphore but we don't need to bother
764 * looking to see whether we got the lock or not since we do
765 * the same thing regardless of whether we got the lock or not.
766 * We got the lock - we release it.
767 * We timeout trying to get the lock - we force its release.
768 */
769 ixgbe_get_swfw_sync_semaphore(hw);
770 ixgbe_release_swfw_sync_semaphore(hw);
771
772 /* Acquire and release all software resources. */
773 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
774 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
775 IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_I2C_MASK;
776
777 ixgbe_acquire_swfw_sync_X540(hw, rmask);
778 ixgbe_release_swfw_sync_X540(hw, rmask);
779}
780
781/**
782 * ixgbe_blink_led_start_X540 - Blink LED based on index.
783 * @hw: pointer to hardware structure
784 * @index: led number to blink
785 *
786 * Devices that implement the version 2 interface:
787 * X540
788 **/
789s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
790{
791 u32 macc_reg;
792 u32 ledctl_reg;
793 ixgbe_link_speed speed;
794 bool link_up;
795
796 if (index > 3)
797 return IXGBE_ERR_PARAM;
798
799 /* Link should be up in order for the blink bit in the LED control
800 * register to work. Force link and speed in the MAC if link is down.
801 * This will be reversed when we stop the blinking.
802 */
803 hw->mac.ops.check_link(hw, &speed, &link_up, false);
804 if (!link_up) {
805 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
806 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
807 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
808 }
809 /* Set the LED to LINK_UP + BLINK. */
810 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
811 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
812 ledctl_reg |= IXGBE_LED_BLINK(index);
813 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
814 IXGBE_WRITE_FLUSH(hw);
815
816 return 0;
817}
818
819/**
820 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
821 * @hw: pointer to hardware structure
822 * @index: led number to stop blinking
823 *
824 * Devices that implement the version 2 interface:
825 * X540
826 **/
827s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
828{
829 u32 macc_reg;
830 u32 ledctl_reg;
831
832 if (index > 3)
833 return IXGBE_ERR_PARAM;
834
835 /* Restore the LED to its default value. */
836 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
837 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
838 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
839 ledctl_reg &= ~IXGBE_LED_BLINK(index);
840 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
841
842 /* Unforce link and speed in the MAC. */
843 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
844 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
845 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
846 IXGBE_WRITE_FLUSH(hw);
847
848 return 0;
849}
850static const struct ixgbe_mac_operations mac_ops_X540 = {
851 .init_hw = &ixgbe_init_hw_generic,
852 .reset_hw = &ixgbe_reset_hw_X540,
853 .start_hw = &ixgbe_start_hw_X540,
854 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
855 .get_media_type = &ixgbe_get_media_type_X540,
856 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
857 .get_mac_addr = &ixgbe_get_mac_addr_generic,
858 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
859 .get_device_caps = &ixgbe_get_device_caps_generic,
860 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
861 .stop_adapter = &ixgbe_stop_adapter_generic,
862 .get_bus_info = &ixgbe_get_bus_info_generic,
863 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
864 .read_analog_reg8 = NULL,
865 .write_analog_reg8 = NULL,
866 .setup_link = &ixgbe_setup_mac_link_X540,
867 .set_rxpba = &ixgbe_set_rxpba_generic,
868 .check_link = &ixgbe_check_mac_link_generic,
869 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
870 .led_on = &ixgbe_led_on_generic,
871 .led_off = &ixgbe_led_off_generic,
872 .init_led_link_act = ixgbe_init_led_link_act_generic,
873 .blink_led_start = &ixgbe_blink_led_start_X540,
874 .blink_led_stop = &ixgbe_blink_led_stop_X540,
875 .set_rar = &ixgbe_set_rar_generic,
876 .clear_rar = &ixgbe_clear_rar_generic,
877 .set_vmdq = &ixgbe_set_vmdq_generic,
878 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
879 .clear_vmdq = &ixgbe_clear_vmdq_generic,
880 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
881 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
882 .enable_mc = &ixgbe_enable_mc_generic,
883 .disable_mc = &ixgbe_disable_mc_generic,
884 .clear_vfta = &ixgbe_clear_vfta_generic,
885 .set_vfta = &ixgbe_set_vfta_generic,
886 .fc_enable = &ixgbe_fc_enable_generic,
887 .setup_fc = ixgbe_setup_fc_generic,
888 .fc_autoneg = ixgbe_fc_autoneg,
889 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
890 .init_uta_tables = &ixgbe_init_uta_tables_generic,
891 .setup_sfp = NULL,
892 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
893 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
894 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
895 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
896 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
897 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
898 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
899 .get_thermal_sensor_data = NULL,
900 .init_thermal_sensor_thresh = NULL,
901 .prot_autoc_read = &prot_autoc_read_generic,
902 .prot_autoc_write = &prot_autoc_write_generic,
903 .enable_rx = &ixgbe_enable_rx_generic,
904 .disable_rx = &ixgbe_disable_rx_generic,
905};
906
907static const struct ixgbe_eeprom_operations eeprom_ops_X540 = {
908 .init_params = &ixgbe_init_eeprom_params_X540,
909 .read = &ixgbe_read_eerd_X540,
910 .read_buffer = &ixgbe_read_eerd_buffer_X540,
911 .write = &ixgbe_write_eewr_X540,
912 .write_buffer = &ixgbe_write_eewr_buffer_X540,
913 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
914 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
915 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
916};
917
918static const struct ixgbe_phy_operations phy_ops_X540 = {
919 .identify = &ixgbe_identify_phy_generic,
920 .identify_sfp = &ixgbe_identify_sfp_module_generic,
921 .init = NULL,
922 .reset = NULL,
923 .read_reg = &ixgbe_read_phy_reg_generic,
924 .write_reg = &ixgbe_write_phy_reg_generic,
925 .setup_link = &ixgbe_setup_phy_link_generic,
926 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
927 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
928 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
929 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
930 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
931 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
932 .check_overtemp = &ixgbe_tn_check_overtemp,
933 .set_phy_power = &ixgbe_set_copper_phy_power,
934};
935
936static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
937 IXGBE_MVALS_INIT(X540)
938};
939
940const struct ixgbe_info ixgbe_X540_info = {
941 .mac = ixgbe_mac_X540,
942 .get_invariants = &ixgbe_get_invariants_X540,
943 .mac_ops = &mac_ops_X540,
944 .eeprom_ops = &eeprom_ops_X540,
945 .phy_ops = &phy_ops_X540,
946 .mbx_ops = &mbx_ops_generic,
947 .mvals = ixgbe_mvals_X540,
948};