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1/*
2 * Copyright 2010 Broadcom
3 * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
16 *
17 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
18 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
19 * to look in the bank 1 status register for more information.
20 *
21 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
22 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
23 * status register, but bank 0 bit 8 is _not_ set.
24 *
25 * Quirk 2: You can't mask the register 1/2 pending interrupts
26 *
27 * In a proper cascaded interrupt controller, the interrupt lines with
28 * cascaded interrupt controllers on them are just normal interrupt lines.
29 * You can mask the interrupts and get on with things. With this controller
30 * you can't do that.
31 *
32 * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
33 *
34 * Those interrupts that have shortcuts can only be masked/unmasked in
35 * their respective banks' enable/disable registers. Doing so in the bank 0
36 * enable/disable registers has no effect.
37 *
38 * The FIQ control register:
39 * Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
40 * Bit 7: Enable FIQ generation
41 * Bits 8+: Unused
42 *
43 * An interrupt must be disabled before configuring it for FIQ generation
44 * otherwise both handlers will fire at the same time!
45 */
46
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/of_address.h>
50#include <linux/of_irq.h>
51#include <linux/irqchip.h>
52#include <linux/irqdomain.h>
53
54#include <asm/exception.h>
55
56/* Put the bank and irq (32 bits) into the hwirq */
57#define MAKE_HWIRQ(b, n) ((b << 5) | (n))
58#define HWIRQ_BANK(i) (i >> 5)
59#define HWIRQ_BIT(i) BIT(i & 0x1f)
60
61#define NR_IRQS_BANK0 8
62#define BANK0_HWIRQ_MASK 0xff
63/* Shortcuts can't be disabled so any unknown new ones need to be masked */
64#define SHORTCUT1_MASK 0x00007c00
65#define SHORTCUT2_MASK 0x001f8000
66#define SHORTCUT_SHIFT 10
67#define BANK1_HWIRQ BIT(8)
68#define BANK2_HWIRQ BIT(9)
69#define BANK0_VALID_MASK (BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
70 | SHORTCUT1_MASK | SHORTCUT2_MASK)
71
72#define REG_FIQ_CONTROL 0x0c
73
74#define NR_BANKS 3
75#define IRQS_PER_BANK 32
76
77static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
78static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
79static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
80static const int bank_irqs[] __initconst = { 8, 32, 32 };
81
82static const int shortcuts[] = {
83 7, 9, 10, 18, 19, /* Bank 1 */
84 21, 22, 23, 24, 25, 30 /* Bank 2 */
85};
86
87struct armctrl_ic {
88 void __iomem *base;
89 void __iomem *pending[NR_BANKS];
90 void __iomem *enable[NR_BANKS];
91 void __iomem *disable[NR_BANKS];
92 struct irq_domain *domain;
93};
94
95static struct armctrl_ic intc __read_mostly;
96static void __exception_irq_entry bcm2835_handle_irq(
97 struct pt_regs *regs);
98static void bcm2836_chained_handle_irq(struct irq_desc *desc);
99
100static void armctrl_mask_irq(struct irq_data *d)
101{
102 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
103}
104
105static void armctrl_unmask_irq(struct irq_data *d)
106{
107 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
108}
109
110static struct irq_chip armctrl_chip = {
111 .name = "ARMCTRL-level",
112 .irq_mask = armctrl_mask_irq,
113 .irq_unmask = armctrl_unmask_irq
114};
115
116static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
117 const u32 *intspec, unsigned int intsize,
118 unsigned long *out_hwirq, unsigned int *out_type)
119{
120 if (WARN_ON(intsize != 2))
121 return -EINVAL;
122
123 if (WARN_ON(intspec[0] >= NR_BANKS))
124 return -EINVAL;
125
126 if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
127 return -EINVAL;
128
129 if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
130 return -EINVAL;
131
132 *out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
133 *out_type = IRQ_TYPE_NONE;
134 return 0;
135}
136
137static const struct irq_domain_ops armctrl_ops = {
138 .xlate = armctrl_xlate
139};
140
141static int __init armctrl_of_init(struct device_node *node,
142 struct device_node *parent,
143 bool is_2836)
144{
145 void __iomem *base;
146 int irq, b, i;
147
148 base = of_iomap(node, 0);
149 if (!base)
150 panic("%pOF: unable to map IC registers\n", node);
151
152 intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
153 &armctrl_ops, NULL);
154 if (!intc.domain)
155 panic("%pOF: unable to create IRQ domain\n", node);
156
157 for (b = 0; b < NR_BANKS; b++) {
158 intc.pending[b] = base + reg_pending[b];
159 intc.enable[b] = base + reg_enable[b];
160 intc.disable[b] = base + reg_disable[b];
161
162 for (i = 0; i < bank_irqs[b]; i++) {
163 irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
164 BUG_ON(irq <= 0);
165 irq_set_chip_and_handler(irq, &armctrl_chip,
166 handle_level_irq);
167 irq_set_probe(irq);
168 }
169 }
170
171 if (is_2836) {
172 int parent_irq = irq_of_parse_and_map(node, 0);
173
174 if (!parent_irq) {
175 panic("%pOF: unable to get parent interrupt.\n",
176 node);
177 }
178 irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
179 } else {
180 set_handle_irq(bcm2835_handle_irq);
181 }
182
183 return 0;
184}
185
186static int __init bcm2835_armctrl_of_init(struct device_node *node,
187 struct device_node *parent)
188{
189 return armctrl_of_init(node, parent, false);
190}
191
192static int __init bcm2836_armctrl_of_init(struct device_node *node,
193 struct device_node *parent)
194{
195 return armctrl_of_init(node, parent, true);
196}
197
198
199/*
200 * Handle each interrupt across the entire interrupt controller. This reads the
201 * status register before handling each interrupt, which is necessary given that
202 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
203 */
204
205static u32 armctrl_translate_bank(int bank)
206{
207 u32 stat = readl_relaxed(intc.pending[bank]);
208
209 return MAKE_HWIRQ(bank, ffs(stat) - 1);
210}
211
212static u32 armctrl_translate_shortcut(int bank, u32 stat)
213{
214 return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
215}
216
217static u32 get_next_armctrl_hwirq(void)
218{
219 u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
220
221 if (stat == 0)
222 return ~0;
223 else if (stat & BANK0_HWIRQ_MASK)
224 return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
225 else if (stat & SHORTCUT1_MASK)
226 return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
227 else if (stat & SHORTCUT2_MASK)
228 return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
229 else if (stat & BANK1_HWIRQ)
230 return armctrl_translate_bank(1);
231 else if (stat & BANK2_HWIRQ)
232 return armctrl_translate_bank(2);
233 else
234 BUG();
235}
236
237static void __exception_irq_entry bcm2835_handle_irq(
238 struct pt_regs *regs)
239{
240 u32 hwirq;
241
242 while ((hwirq = get_next_armctrl_hwirq()) != ~0)
243 handle_domain_irq(intc.domain, hwirq, regs);
244}
245
246static void bcm2836_chained_handle_irq(struct irq_desc *desc)
247{
248 u32 hwirq;
249
250 while ((hwirq = get_next_armctrl_hwirq()) != ~0)
251 generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
252}
253
254IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
255 bcm2835_armctrl_of_init);
256IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
257 bcm2836_armctrl_of_init);