Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright(c) 2016 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47#if !defined(__RVT_TRACE_TX_H) || defined(TRACE_HEADER_MULTI_READ)
48#define __RVT_TRACE_TX_H
49
50#include <linux/tracepoint.h>
51#include <linux/trace_seq.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/rdma_vt.h>
55
56#undef TRACE_SYSTEM
57#define TRACE_SYSTEM rvt_tx
58
59#define wr_opcode_name(opcode) { IB_WR_##opcode, #opcode }
60#define show_wr_opcode(opcode) \
61__print_symbolic(opcode, \
62 wr_opcode_name(RDMA_WRITE), \
63 wr_opcode_name(RDMA_WRITE_WITH_IMM), \
64 wr_opcode_name(SEND), \
65 wr_opcode_name(SEND_WITH_IMM), \
66 wr_opcode_name(RDMA_READ), \
67 wr_opcode_name(ATOMIC_CMP_AND_SWP), \
68 wr_opcode_name(ATOMIC_FETCH_AND_ADD), \
69 wr_opcode_name(LSO), \
70 wr_opcode_name(SEND_WITH_INV), \
71 wr_opcode_name(RDMA_READ_WITH_INV), \
72 wr_opcode_name(LOCAL_INV), \
73 wr_opcode_name(MASKED_ATOMIC_CMP_AND_SWP), \
74 wr_opcode_name(MASKED_ATOMIC_FETCH_AND_ADD), \
75 wr_opcode_name(RESERVED1), \
76 wr_opcode_name(RESERVED2), \
77 wr_opcode_name(RESERVED3), \
78 wr_opcode_name(RESERVED4), \
79 wr_opcode_name(RESERVED5), \
80 wr_opcode_name(RESERVED6), \
81 wr_opcode_name(RESERVED7), \
82 wr_opcode_name(RESERVED8), \
83 wr_opcode_name(RESERVED9), \
84 wr_opcode_name(RESERVED10))
85
86#define POS_PRN \
87"[%s] wqe %p wr_id %llx send_flags %x qpn %x qpt %u psn %x lpsn %x ssn %x length %u opcode 0x%.2x,%s size %u avail %u head %u last %u pid %u num_sge %u wr_num_sge %u"
88
89TRACE_EVENT(
90 rvt_post_one_wr,
91 TP_PROTO(struct rvt_qp *qp, struct rvt_swqe *wqe, int wr_num_sge),
92 TP_ARGS(qp, wqe, wr_num_sge),
93 TP_STRUCT__entry(
94 RDI_DEV_ENTRY(ib_to_rvt(qp->ibqp.device))
95 __field(u64, wr_id)
96 __field(struct rvt_swqe *, wqe)
97 __field(u32, qpn)
98 __field(u32, qpt)
99 __field(u32, psn)
100 __field(u32, lpsn)
101 __field(u32, length)
102 __field(u32, opcode)
103 __field(u32, size)
104 __field(u32, avail)
105 __field(u32, head)
106 __field(u32, last)
107 __field(u32, ssn)
108 __field(int, send_flags)
109 __field(pid_t, pid)
110 __field(int, num_sge)
111 __field(int, wr_num_sge)
112 ),
113 TP_fast_assign(
114 RDI_DEV_ASSIGN(ib_to_rvt(qp->ibqp.device))
115 __entry->wqe = wqe;
116 __entry->wr_id = wqe->wr.wr_id;
117 __entry->qpn = qp->ibqp.qp_num;
118 __entry->qpt = qp->ibqp.qp_type;
119 __entry->psn = wqe->psn;
120 __entry->lpsn = wqe->lpsn;
121 __entry->length = wqe->length;
122 __entry->opcode = wqe->wr.opcode;
123 __entry->size = qp->s_size;
124 __entry->avail = qp->s_avail;
125 __entry->head = qp->s_head;
126 __entry->last = qp->s_last;
127 __entry->pid = qp->pid;
128 __entry->ssn = wqe->ssn;
129 __entry->send_flags = wqe->wr.send_flags;
130 __entry->num_sge = wqe->wr.num_sge;
131 __entry->wr_num_sge = wr_num_sge;
132 ),
133 TP_printk(
134 POS_PRN,
135 __get_str(dev),
136 __entry->wqe,
137 __entry->wr_id,
138 __entry->send_flags,
139 __entry->qpn,
140 __entry->qpt,
141 __entry->psn,
142 __entry->lpsn,
143 __entry->ssn,
144 __entry->length,
145 __entry->opcode, show_wr_opcode(__entry->opcode),
146 __entry->size,
147 __entry->avail,
148 __entry->head,
149 __entry->last,
150 __entry->pid,
151 __entry->num_sge,
152 __entry->wr_num_sge
153 )
154);
155
156#endif /* __RVT_TRACE_TX_H */
157
158#undef TRACE_INCLUDE_PATH
159#undef TRACE_INCLUDE_FILE
160#define TRACE_INCLUDE_PATH .
161#define TRACE_INCLUDE_FILE trace_tx
162#include <trace/define_trace.h>
163