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1/*
2 * Copyright (c) 2015, NVIDIA Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
10#include <linux/host1x.h>
11#include <linux/iommu.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/of_platform.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/reset.h>
19
20#include <soc/tegra/pmc.h>
21
22#include "drm.h"
23#include "falcon.h"
24#include "vic.h"
25
26struct vic_config {
27 const char *firmware;
28};
29
30struct vic {
31 struct falcon falcon;
32 bool booted;
33
34 void __iomem *regs;
35 struct tegra_drm_client client;
36 struct host1x_channel *channel;
37 struct iommu_domain *domain;
38 struct device *dev;
39 struct clk *clk;
40
41 /* Platform configuration */
42 const struct vic_config *config;
43};
44
45static inline struct vic *to_vic(struct tegra_drm_client *client)
46{
47 return container_of(client, struct vic, client);
48}
49
50static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
51{
52 writel(value, vic->regs + offset);
53}
54
55static int vic_runtime_resume(struct device *dev)
56{
57 struct vic *vic = dev_get_drvdata(dev);
58
59 return clk_prepare_enable(vic->clk);
60}
61
62static int vic_runtime_suspend(struct device *dev)
63{
64 struct vic *vic = dev_get_drvdata(dev);
65
66 clk_disable_unprepare(vic->clk);
67
68 vic->booted = false;
69
70 return 0;
71}
72
73static int vic_boot(struct vic *vic)
74{
75 u32 fce_ucode_size, fce_bin_data_offset;
76 void *hdr;
77 int err = 0;
78
79 if (vic->booted)
80 return 0;
81
82 /* setup clockgating registers */
83 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
84 CG_IDLE_CG_EN |
85 CG_WAKEUP_DLY_CNT(4),
86 NV_PVIC_MISC_PRI_VIC_CG);
87
88 err = falcon_boot(&vic->falcon);
89 if (err < 0)
90 return err;
91
92 hdr = vic->falcon.firmware.vaddr;
93 fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
94 hdr = vic->falcon.firmware.vaddr +
95 *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
96 fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
97
98 falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1);
99 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
100 fce_ucode_size);
101 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
102 (vic->falcon.firmware.paddr + fce_bin_data_offset)
103 >> 8);
104
105 err = falcon_wait_idle(&vic->falcon);
106 if (err < 0) {
107 dev_err(vic->dev,
108 "failed to set application ID and FCE base\n");
109 return err;
110 }
111
112 vic->booted = true;
113
114 return 0;
115}
116
117static void *vic_falcon_alloc(struct falcon *falcon, size_t size,
118 dma_addr_t *iova)
119{
120 struct tegra_drm *tegra = falcon->data;
121
122 return tegra_drm_alloc(tegra, size, iova);
123}
124
125static void vic_falcon_free(struct falcon *falcon, size_t size,
126 dma_addr_t iova, void *va)
127{
128 struct tegra_drm *tegra = falcon->data;
129
130 return tegra_drm_free(tegra, size, va, iova);
131}
132
133static const struct falcon_ops vic_falcon_ops = {
134 .alloc = vic_falcon_alloc,
135 .free = vic_falcon_free
136};
137
138static int vic_init(struct host1x_client *client)
139{
140 struct tegra_drm_client *drm = host1x_to_drm_client(client);
141 struct iommu_group *group = iommu_group_get(client->dev);
142 struct drm_device *dev = dev_get_drvdata(client->parent);
143 struct tegra_drm *tegra = dev->dev_private;
144 struct vic *vic = to_vic(drm);
145 int err;
146
147 if (group && tegra->domain) {
148 err = iommu_attach_group(tegra->domain, group);
149 if (err < 0) {
150 dev_err(vic->dev, "failed to attach to domain: %d\n",
151 err);
152 return err;
153 }
154
155 vic->domain = tegra->domain;
156 }
157
158 if (!vic->falcon.data) {
159 vic->falcon.data = tegra;
160 err = falcon_load_firmware(&vic->falcon);
161 if (err < 0)
162 goto detach;
163 }
164
165 vic->channel = host1x_channel_request(client->dev);
166 if (!vic->channel) {
167 err = -ENOMEM;
168 goto detach;
169 }
170
171 client->syncpts[0] = host1x_syncpt_request(client, 0);
172 if (!client->syncpts[0]) {
173 err = -ENOMEM;
174 goto free_channel;
175 }
176
177 err = tegra_drm_register_client(tegra, drm);
178 if (err < 0)
179 goto free_syncpt;
180
181 return 0;
182
183free_syncpt:
184 host1x_syncpt_free(client->syncpts[0]);
185free_channel:
186 host1x_channel_put(vic->channel);
187detach:
188 if (group && tegra->domain)
189 iommu_detach_group(tegra->domain, group);
190
191 return err;
192}
193
194static int vic_exit(struct host1x_client *client)
195{
196 struct tegra_drm_client *drm = host1x_to_drm_client(client);
197 struct iommu_group *group = iommu_group_get(client->dev);
198 struct drm_device *dev = dev_get_drvdata(client->parent);
199 struct tegra_drm *tegra = dev->dev_private;
200 struct vic *vic = to_vic(drm);
201 int err;
202
203 err = tegra_drm_unregister_client(tegra, drm);
204 if (err < 0)
205 return err;
206
207 host1x_syncpt_free(client->syncpts[0]);
208 host1x_channel_put(vic->channel);
209
210 if (vic->domain) {
211 iommu_detach_group(vic->domain, group);
212 vic->domain = NULL;
213 }
214
215 return 0;
216}
217
218static const struct host1x_client_ops vic_client_ops = {
219 .init = vic_init,
220 .exit = vic_exit,
221};
222
223static int vic_open_channel(struct tegra_drm_client *client,
224 struct tegra_drm_context *context)
225{
226 struct vic *vic = to_vic(client);
227 int err;
228
229 err = pm_runtime_get_sync(vic->dev);
230 if (err < 0)
231 return err;
232
233 err = vic_boot(vic);
234 if (err < 0) {
235 pm_runtime_put(vic->dev);
236 return err;
237 }
238
239 context->channel = host1x_channel_get(vic->channel);
240 if (!context->channel) {
241 pm_runtime_put(vic->dev);
242 return -ENOMEM;
243 }
244
245 return 0;
246}
247
248static void vic_close_channel(struct tegra_drm_context *context)
249{
250 struct vic *vic = to_vic(context->client);
251
252 host1x_channel_put(context->channel);
253
254 pm_runtime_put(vic->dev);
255}
256
257static const struct tegra_drm_client_ops vic_ops = {
258 .open_channel = vic_open_channel,
259 .close_channel = vic_close_channel,
260 .submit = tegra_drm_submit,
261};
262
263#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
264
265static const struct vic_config vic_t124_config = {
266 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
267};
268
269#define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
270
271static const struct vic_config vic_t210_config = {
272 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
273};
274
275#define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
276
277static const struct vic_config vic_t186_config = {
278 .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
279};
280
281static const struct of_device_id vic_match[] = {
282 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
283 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
284 { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
285 { },
286};
287
288static int vic_probe(struct platform_device *pdev)
289{
290 struct device *dev = &pdev->dev;
291 struct host1x_syncpt **syncpts;
292 struct resource *regs;
293 struct vic *vic;
294 int err;
295
296 vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
297 if (!vic)
298 return -ENOMEM;
299
300 vic->config = of_device_get_match_data(dev);
301
302 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
303 if (!syncpts)
304 return -ENOMEM;
305
306 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
307 if (!regs) {
308 dev_err(&pdev->dev, "failed to get registers\n");
309 return -ENXIO;
310 }
311
312 vic->regs = devm_ioremap_resource(dev, regs);
313 if (IS_ERR(vic->regs))
314 return PTR_ERR(vic->regs);
315
316 vic->clk = devm_clk_get(dev, NULL);
317 if (IS_ERR(vic->clk)) {
318 dev_err(&pdev->dev, "failed to get clock\n");
319 return PTR_ERR(vic->clk);
320 }
321
322 vic->falcon.dev = dev;
323 vic->falcon.regs = vic->regs;
324 vic->falcon.ops = &vic_falcon_ops;
325
326 err = falcon_init(&vic->falcon);
327 if (err < 0)
328 return err;
329
330 err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
331 if (err < 0)
332 goto exit_falcon;
333
334 platform_set_drvdata(pdev, vic);
335
336 INIT_LIST_HEAD(&vic->client.base.list);
337 vic->client.base.ops = &vic_client_ops;
338 vic->client.base.dev = dev;
339 vic->client.base.class = HOST1X_CLASS_VIC;
340 vic->client.base.syncpts = syncpts;
341 vic->client.base.num_syncpts = 1;
342 vic->dev = dev;
343
344 INIT_LIST_HEAD(&vic->client.list);
345 vic->client.ops = &vic_ops;
346
347 err = host1x_client_register(&vic->client.base);
348 if (err < 0) {
349 dev_err(dev, "failed to register host1x client: %d\n", err);
350 platform_set_drvdata(pdev, NULL);
351 goto exit_falcon;
352 }
353
354 pm_runtime_enable(&pdev->dev);
355 if (!pm_runtime_enabled(&pdev->dev)) {
356 err = vic_runtime_resume(&pdev->dev);
357 if (err < 0)
358 goto unregister_client;
359 }
360
361 return 0;
362
363unregister_client:
364 host1x_client_unregister(&vic->client.base);
365exit_falcon:
366 falcon_exit(&vic->falcon);
367
368 return err;
369}
370
371static int vic_remove(struct platform_device *pdev)
372{
373 struct vic *vic = platform_get_drvdata(pdev);
374 int err;
375
376 err = host1x_client_unregister(&vic->client.base);
377 if (err < 0) {
378 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
379 err);
380 return err;
381 }
382
383 if (pm_runtime_enabled(&pdev->dev))
384 pm_runtime_disable(&pdev->dev);
385 else
386 vic_runtime_suspend(&pdev->dev);
387
388 falcon_exit(&vic->falcon);
389
390 return 0;
391}
392
393static const struct dev_pm_ops vic_pm_ops = {
394 SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
395};
396
397struct platform_driver tegra_vic_driver = {
398 .driver = {
399 .name = "tegra-vic",
400 .of_match_table = vic_match,
401 .pm = &vic_pm_ops
402 },
403 .probe = vic_probe,
404 .remove = vic_remove,
405};
406
407#if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
408MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
409#endif
410#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
411MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
412#endif
413#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
414MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
415#endif