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1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include "drmP.h"
33#include "drm.h"
34#include "radeon_drm.h"
35#include "radeon_drv.h"
36
37#include "drm_pciids.h"
38#include <linux/console.h>
39
40
41/*
42 * KMS wrapper.
43 * - 2.0.0 - initial interface
44 * - 2.1.0 - add square tiling interface
45 * - 2.2.0 - add r6xx/r7xx const buffer support
46 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
47 * - 2.4.0 - add crtc id query
48 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
49 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
50 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
51 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
52 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
53 * 2.10.0 - fusion 2D tiling
54 * 2.11.0 - backend map, initial compute support for the CS checker
55 */
56#define KMS_DRIVER_MAJOR 2
57#define KMS_DRIVER_MINOR 11
58#define KMS_DRIVER_PATCHLEVEL 0
59int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
60int radeon_driver_unload_kms(struct drm_device *dev);
61int radeon_driver_firstopen_kms(struct drm_device *dev);
62void radeon_driver_lastclose_kms(struct drm_device *dev);
63int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
64void radeon_driver_postclose_kms(struct drm_device *dev,
65 struct drm_file *file_priv);
66void radeon_driver_preclose_kms(struct drm_device *dev,
67 struct drm_file *file_priv);
68int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
69int radeon_resume_kms(struct drm_device *dev);
70u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
71int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
72void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
73int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
74 int *max_error,
75 struct timeval *vblank_time,
76 unsigned flags);
77void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
78int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
79void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
80irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS);
81int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
82 struct drm_file *file_priv);
83int radeon_gem_object_init(struct drm_gem_object *obj);
84void radeon_gem_object_free(struct drm_gem_object *obj);
85extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
86 int *vpos, int *hpos);
87extern struct drm_ioctl_desc radeon_ioctls_kms[];
88extern int radeon_max_kms_ioctl;
89int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
90int radeon_mode_dumb_mmap(struct drm_file *filp,
91 struct drm_device *dev,
92 uint32_t handle, uint64_t *offset_p);
93int radeon_mode_dumb_create(struct drm_file *file_priv,
94 struct drm_device *dev,
95 struct drm_mode_create_dumb *args);
96int radeon_mode_dumb_destroy(struct drm_file *file_priv,
97 struct drm_device *dev,
98 uint32_t handle);
99
100#if defined(CONFIG_DEBUG_FS)
101int radeon_debugfs_init(struct drm_minor *minor);
102void radeon_debugfs_cleanup(struct drm_minor *minor);
103#endif
104
105
106int radeon_no_wb;
107int radeon_modeset = -1;
108int radeon_dynclks = -1;
109int radeon_r4xx_atom = 0;
110int radeon_agpmode = 0;
111int radeon_vram_limit = 0;
112int radeon_gart_size = 512; /* default gart size */
113int radeon_benchmarking = 0;
114int radeon_testing = 0;
115int radeon_connector_table = 0;
116int radeon_tv = 1;
117int radeon_audio = 0;
118int radeon_disp_priority = 0;
119int radeon_hw_i2c = 0;
120int radeon_pcie_gen2 = 0;
121
122MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
123module_param_named(no_wb, radeon_no_wb, int, 0444);
124
125MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
126module_param_named(modeset, radeon_modeset, int, 0400);
127
128MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
129module_param_named(dynclks, radeon_dynclks, int, 0444);
130
131MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
132module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
133
134MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing");
135module_param_named(vramlimit, radeon_vram_limit, int, 0600);
136
137MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
138module_param_named(agpmode, radeon_agpmode, int, 0444);
139
140MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32,64, etc)\n");
141module_param_named(gartsize, radeon_gart_size, int, 0600);
142
143MODULE_PARM_DESC(benchmark, "Run benchmark");
144module_param_named(benchmark, radeon_benchmarking, int, 0444);
145
146MODULE_PARM_DESC(test, "Run tests");
147module_param_named(test, radeon_testing, int, 0444);
148
149MODULE_PARM_DESC(connector_table, "Force connector table");
150module_param_named(connector_table, radeon_connector_table, int, 0444);
151
152MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
153module_param_named(tv, radeon_tv, int, 0444);
154
155MODULE_PARM_DESC(audio, "Audio enable (1 = enable)");
156module_param_named(audio, radeon_audio, int, 0444);
157
158MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
159module_param_named(disp_priority, radeon_disp_priority, int, 0444);
160
161MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
162module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
163
164MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (1 = enable)");
165module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
166
167static int radeon_suspend(struct drm_device *dev, pm_message_t state)
168{
169 drm_radeon_private_t *dev_priv = dev->dev_private;
170
171 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
172 return 0;
173
174 /* Disable *all* interrupts */
175 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
176 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
177 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
178 return 0;
179}
180
181static int radeon_resume(struct drm_device *dev)
182{
183 drm_radeon_private_t *dev_priv = dev->dev_private;
184
185 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
186 return 0;
187
188 /* Restore interrupt registers */
189 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
190 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
191 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
192 return 0;
193}
194
195static struct pci_device_id pciidlist[] = {
196 radeon_PCI_IDS
197};
198
199#if defined(CONFIG_DRM_RADEON_KMS)
200MODULE_DEVICE_TABLE(pci, pciidlist);
201#endif
202
203static struct drm_driver driver_old = {
204 .driver_features =
205 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
206 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
207 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
208 .load = radeon_driver_load,
209 .firstopen = radeon_driver_firstopen,
210 .open = radeon_driver_open,
211 .preclose = radeon_driver_preclose,
212 .postclose = radeon_driver_postclose,
213 .lastclose = radeon_driver_lastclose,
214 .unload = radeon_driver_unload,
215 .suspend = radeon_suspend,
216 .resume = radeon_resume,
217 .get_vblank_counter = radeon_get_vblank_counter,
218 .enable_vblank = radeon_enable_vblank,
219 .disable_vblank = radeon_disable_vblank,
220 .master_create = radeon_master_create,
221 .master_destroy = radeon_master_destroy,
222 .irq_preinstall = radeon_driver_irq_preinstall,
223 .irq_postinstall = radeon_driver_irq_postinstall,
224 .irq_uninstall = radeon_driver_irq_uninstall,
225 .irq_handler = radeon_driver_irq_handler,
226 .reclaim_buffers = drm_core_reclaim_buffers,
227 .ioctls = radeon_ioctls,
228 .dma_ioctl = radeon_cp_buffers,
229 .fops = {
230 .owner = THIS_MODULE,
231 .open = drm_open,
232 .release = drm_release,
233 .unlocked_ioctl = drm_ioctl,
234 .mmap = drm_mmap,
235 .poll = drm_poll,
236 .fasync = drm_fasync,
237 .read = drm_read,
238#ifdef CONFIG_COMPAT
239 .compat_ioctl = radeon_compat_ioctl,
240#endif
241 .llseek = noop_llseek,
242 },
243
244 .name = DRIVER_NAME,
245 .desc = DRIVER_DESC,
246 .date = DRIVER_DATE,
247 .major = DRIVER_MAJOR,
248 .minor = DRIVER_MINOR,
249 .patchlevel = DRIVER_PATCHLEVEL,
250};
251
252static struct drm_driver kms_driver;
253
254static void radeon_kick_out_firmware_fb(struct pci_dev *pdev)
255{
256 struct apertures_struct *ap;
257 bool primary = false;
258
259 ap = alloc_apertures(1);
260 ap->ranges[0].base = pci_resource_start(pdev, 0);
261 ap->ranges[0].size = pci_resource_len(pdev, 0);
262
263#ifdef CONFIG_X86
264 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
265#endif
266 remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
267 kfree(ap);
268}
269
270static int __devinit
271radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
272{
273 /* Get rid of things like offb */
274 radeon_kick_out_firmware_fb(pdev);
275
276 return drm_get_pci_dev(pdev, ent, &kms_driver);
277}
278
279static void
280radeon_pci_remove(struct pci_dev *pdev)
281{
282 struct drm_device *dev = pci_get_drvdata(pdev);
283
284 drm_put_dev(dev);
285}
286
287static int
288radeon_pci_suspend(struct pci_dev *pdev, pm_message_t state)
289{
290 struct drm_device *dev = pci_get_drvdata(pdev);
291 return radeon_suspend_kms(dev, state);
292}
293
294static int
295radeon_pci_resume(struct pci_dev *pdev)
296{
297 struct drm_device *dev = pci_get_drvdata(pdev);
298 return radeon_resume_kms(dev);
299}
300
301static struct drm_driver kms_driver = {
302 .driver_features =
303 DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
304 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM,
305 .dev_priv_size = 0,
306 .load = radeon_driver_load_kms,
307 .firstopen = radeon_driver_firstopen_kms,
308 .open = radeon_driver_open_kms,
309 .preclose = radeon_driver_preclose_kms,
310 .postclose = radeon_driver_postclose_kms,
311 .lastclose = radeon_driver_lastclose_kms,
312 .unload = radeon_driver_unload_kms,
313 .suspend = radeon_suspend_kms,
314 .resume = radeon_resume_kms,
315 .get_vblank_counter = radeon_get_vblank_counter_kms,
316 .enable_vblank = radeon_enable_vblank_kms,
317 .disable_vblank = radeon_disable_vblank_kms,
318 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
319 .get_scanout_position = radeon_get_crtc_scanoutpos,
320#if defined(CONFIG_DEBUG_FS)
321 .debugfs_init = radeon_debugfs_init,
322 .debugfs_cleanup = radeon_debugfs_cleanup,
323#endif
324 .irq_preinstall = radeon_driver_irq_preinstall_kms,
325 .irq_postinstall = radeon_driver_irq_postinstall_kms,
326 .irq_uninstall = radeon_driver_irq_uninstall_kms,
327 .irq_handler = radeon_driver_irq_handler_kms,
328 .reclaim_buffers = drm_core_reclaim_buffers,
329 .ioctls = radeon_ioctls_kms,
330 .gem_init_object = radeon_gem_object_init,
331 .gem_free_object = radeon_gem_object_free,
332 .dma_ioctl = radeon_dma_ioctl_kms,
333 .dumb_create = radeon_mode_dumb_create,
334 .dumb_map_offset = radeon_mode_dumb_mmap,
335 .dumb_destroy = radeon_mode_dumb_destroy,
336 .fops = {
337 .owner = THIS_MODULE,
338 .open = drm_open,
339 .release = drm_release,
340 .unlocked_ioctl = drm_ioctl,
341 .mmap = radeon_mmap,
342 .poll = drm_poll,
343 .fasync = drm_fasync,
344 .read = drm_read,
345#ifdef CONFIG_COMPAT
346 .compat_ioctl = radeon_kms_compat_ioctl,
347#endif
348 },
349
350 .name = DRIVER_NAME,
351 .desc = DRIVER_DESC,
352 .date = DRIVER_DATE,
353 .major = KMS_DRIVER_MAJOR,
354 .minor = KMS_DRIVER_MINOR,
355 .patchlevel = KMS_DRIVER_PATCHLEVEL,
356};
357
358static struct drm_driver *driver;
359static struct pci_driver *pdriver;
360
361static struct pci_driver radeon_pci_driver = {
362 .name = DRIVER_NAME,
363 .id_table = pciidlist,
364};
365
366static struct pci_driver radeon_kms_pci_driver = {
367 .name = DRIVER_NAME,
368 .id_table = pciidlist,
369 .probe = radeon_pci_probe,
370 .remove = radeon_pci_remove,
371 .suspend = radeon_pci_suspend,
372 .resume = radeon_pci_resume,
373};
374
375static int __init radeon_init(void)
376{
377 driver = &driver_old;
378 pdriver = &radeon_pci_driver;
379 driver->num_ioctls = radeon_max_ioctl;
380#ifdef CONFIG_VGA_CONSOLE
381 if (vgacon_text_force() && radeon_modeset == -1) {
382 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
383 driver = &driver_old;
384 pdriver = &radeon_pci_driver;
385 driver->driver_features &= ~DRIVER_MODESET;
386 radeon_modeset = 0;
387 }
388#endif
389 /* if enabled by default */
390 if (radeon_modeset == -1) {
391#ifdef CONFIG_DRM_RADEON_KMS
392 DRM_INFO("radeon defaulting to kernel modesetting.\n");
393 radeon_modeset = 1;
394#else
395 DRM_INFO("radeon defaulting to userspace modesetting.\n");
396 radeon_modeset = 0;
397#endif
398 }
399 if (radeon_modeset == 1) {
400 DRM_INFO("radeon kernel modesetting enabled.\n");
401 driver = &kms_driver;
402 pdriver = &radeon_kms_pci_driver;
403 driver->driver_features |= DRIVER_MODESET;
404 driver->num_ioctls = radeon_max_kms_ioctl;
405 radeon_register_atpx_handler();
406 }
407 /* if the vga console setting is enabled still
408 * let modprobe override it */
409 return drm_pci_init(driver, pdriver);
410}
411
412static void __exit radeon_exit(void)
413{
414 drm_pci_exit(driver, pdriver);
415 radeon_unregister_atpx_handler();
416}
417
418module_init(radeon_init);
419module_exit(radeon_exit);
420
421MODULE_AUTHOR(DRIVER_AUTHOR);
422MODULE_DESCRIPTION(DRIVER_DESC);
423MODULE_LICENSE("GPL and additional rights");
1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
34#include "radeon_drv.h"
35
36#include <drm/drm_pciids.h>
37#include <linux/console.h>
38#include <linux/module.h>
39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
41#include <linux/compat.h>
42#include <drm/drm_gem.h>
43#include <drm/drm_fb_helper.h>
44
45#include <drm/drm_crtc_helper.h>
46
47/*
48 * KMS wrapper.
49 * - 2.0.0 - initial interface
50 * - 2.1.0 - add square tiling interface
51 * - 2.2.0 - add r6xx/r7xx const buffer support
52 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
53 * - 2.4.0 - add crtc id query
54 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
55 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
56 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
57 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
58 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
59 * 2.10.0 - fusion 2D tiling
60 * 2.11.0 - backend map, initial compute support for the CS checker
61 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
62 * 2.13.0 - virtual memory support, streamout
63 * 2.14.0 - add evergreen tiling informations
64 * 2.15.0 - add max_pipes query
65 * 2.16.0 - fix evergreen 2D tiled surface calculation
66 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
67 * 2.18.0 - r600-eg: allow "invalid" DB formats
68 * 2.19.0 - r600-eg: MSAA textures
69 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
70 * 2.21.0 - r600-r700: FMASK and CMASK
71 * 2.22.0 - r600 only: RESOLVE_BOX allowed
72 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
73 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
74 * 2.25.0 - eg+: new info request for num SE and num SH
75 * 2.26.0 - r600-eg: fix htile size computation
76 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
77 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
78 * 2.29.0 - R500 FP16 color clear registers
79 * 2.30.0 - fix for FMASK texturing
80 * 2.31.0 - Add fastfb support for rs690
81 * 2.32.0 - new info request for rings working
82 * 2.33.0 - Add SI tiling mode array query
83 * 2.34.0 - Add CIK tiling mode array query
84 * 2.35.0 - Add CIK macrotile mode array query
85 * 2.36.0 - Fix CIK DCE tiling setup
86 * 2.37.0 - allow GS ring setup on r6xx/r7xx
87 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
88 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
89 * 2.39.0 - Add INFO query for number of active CUs
90 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
91 * CS to GPU on >= r600
92 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
93 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
94 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
95 * 2.44.0 - SET_APPEND_CNT packet3 support
96 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
97 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
98 * 2.47.0 - Add UVD_NO_OP register support
99 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
100 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
101 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
102 */
103#define KMS_DRIVER_MAJOR 2
104#define KMS_DRIVER_MINOR 50
105#define KMS_DRIVER_PATCHLEVEL 0
106int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
107void radeon_driver_unload_kms(struct drm_device *dev);
108void radeon_driver_lastclose_kms(struct drm_device *dev);
109int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
110void radeon_driver_postclose_kms(struct drm_device *dev,
111 struct drm_file *file_priv);
112int radeon_suspend_kms(struct drm_device *dev, bool suspend,
113 bool fbcon, bool freeze);
114int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
115u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
116int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
117void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
118void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
119int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
120void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
121irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
122void radeon_gem_object_free(struct drm_gem_object *obj);
123int radeon_gem_object_open(struct drm_gem_object *obj,
124 struct drm_file *file_priv);
125void radeon_gem_object_close(struct drm_gem_object *obj,
126 struct drm_file *file_priv);
127struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
128 struct drm_gem_object *gobj,
129 int flags);
130extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
131 unsigned int flags, int *vpos, int *hpos,
132 ktime_t *stime, ktime_t *etime,
133 const struct drm_display_mode *mode);
134extern bool radeon_is_px(struct drm_device *dev);
135extern const struct drm_ioctl_desc radeon_ioctls_kms[];
136extern int radeon_max_kms_ioctl;
137int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
138int radeon_mode_dumb_mmap(struct drm_file *filp,
139 struct drm_device *dev,
140 uint32_t handle, uint64_t *offset_p);
141int radeon_mode_dumb_create(struct drm_file *file_priv,
142 struct drm_device *dev,
143 struct drm_mode_create_dumb *args);
144struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
145struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
146 struct dma_buf_attachment *,
147 struct sg_table *sg);
148int radeon_gem_prime_pin(struct drm_gem_object *obj);
149void radeon_gem_prime_unpin(struct drm_gem_object *obj);
150struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
151void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
152void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
153
154/* atpx handler */
155#if defined(CONFIG_VGA_SWITCHEROO)
156void radeon_register_atpx_handler(void);
157void radeon_unregister_atpx_handler(void);
158bool radeon_has_atpx_dgpu_power_cntl(void);
159bool radeon_is_atpx_hybrid(void);
160#else
161static inline void radeon_register_atpx_handler(void) {}
162static inline void radeon_unregister_atpx_handler(void) {}
163static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
164static inline bool radeon_is_atpx_hybrid(void) { return false; }
165#endif
166
167int radeon_no_wb;
168int radeon_modeset = -1;
169int radeon_dynclks = -1;
170int radeon_r4xx_atom = 0;
171int radeon_agpmode = 0;
172int radeon_vram_limit = 0;
173int radeon_gart_size = -1; /* auto */
174int radeon_benchmarking = 0;
175int radeon_testing = 0;
176int radeon_connector_table = 0;
177int radeon_tv = 1;
178int radeon_audio = -1;
179int radeon_disp_priority = 0;
180int radeon_hw_i2c = 0;
181int radeon_pcie_gen2 = -1;
182int radeon_msi = -1;
183int radeon_lockup_timeout = 10000;
184int radeon_fastfb = 0;
185int radeon_dpm = -1;
186int radeon_aspm = -1;
187int radeon_runtime_pm = -1;
188int radeon_hard_reset = 0;
189int radeon_vm_size = 8;
190int radeon_vm_block_size = -1;
191int radeon_deep_color = 0;
192int radeon_use_pflipirq = 2;
193int radeon_bapm = -1;
194int radeon_backlight = -1;
195int radeon_auxch = -1;
196int radeon_mst = 0;
197int radeon_uvd = 1;
198int radeon_vce = 1;
199
200MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
201module_param_named(no_wb, radeon_no_wb, int, 0444);
202
203MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
204module_param_named(modeset, radeon_modeset, int, 0400);
205
206MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
207module_param_named(dynclks, radeon_dynclks, int, 0444);
208
209MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
210module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
211
212MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
213module_param_named(vramlimit, radeon_vram_limit, int, 0600);
214
215MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
216module_param_named(agpmode, radeon_agpmode, int, 0444);
217
218MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
219module_param_named(gartsize, radeon_gart_size, int, 0600);
220
221MODULE_PARM_DESC(benchmark, "Run benchmark");
222module_param_named(benchmark, radeon_benchmarking, int, 0444);
223
224MODULE_PARM_DESC(test, "Run tests");
225module_param_named(test, radeon_testing, int, 0444);
226
227MODULE_PARM_DESC(connector_table, "Force connector table");
228module_param_named(connector_table, radeon_connector_table, int, 0444);
229
230MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
231module_param_named(tv, radeon_tv, int, 0444);
232
233MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
234module_param_named(audio, radeon_audio, int, 0444);
235
236MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
237module_param_named(disp_priority, radeon_disp_priority, int, 0444);
238
239MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
240module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
241
242MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
243module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
244
245MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
246module_param_named(msi, radeon_msi, int, 0444);
247
248MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
249module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
250
251MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
252module_param_named(fastfb, radeon_fastfb, int, 0444);
253
254MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
255module_param_named(dpm, radeon_dpm, int, 0444);
256
257MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
258module_param_named(aspm, radeon_aspm, int, 0444);
259
260MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
261module_param_named(runpm, radeon_runtime_pm, int, 0444);
262
263MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
264module_param_named(hard_reset, radeon_hard_reset, int, 0444);
265
266MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
267module_param_named(vm_size, radeon_vm_size, int, 0444);
268
269MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
270module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
271
272MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
273module_param_named(deep_color, radeon_deep_color, int, 0444);
274
275MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
276module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
277
278MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
279module_param_named(bapm, radeon_bapm, int, 0444);
280
281MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
282module_param_named(backlight, radeon_backlight, int, 0444);
283
284MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
285module_param_named(auxch, radeon_auxch, int, 0444);
286
287MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
288module_param_named(mst, radeon_mst, int, 0444);
289
290MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
291module_param_named(uvd, radeon_uvd, int, 0444);
292
293MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
294module_param_named(vce, radeon_vce, int, 0444);
295
296int radeon_si_support = 1;
297MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
298module_param_named(si_support, radeon_si_support, int, 0444);
299
300int radeon_cik_support = 1;
301MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
302module_param_named(cik_support, radeon_cik_support, int, 0444);
303
304static struct pci_device_id pciidlist[] = {
305 radeon_PCI_IDS
306};
307
308MODULE_DEVICE_TABLE(pci, pciidlist);
309
310static struct drm_driver kms_driver;
311
312bool radeon_device_is_virtual(void);
313
314static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
315{
316 struct apertures_struct *ap;
317 bool primary = false;
318
319 ap = alloc_apertures(1);
320 if (!ap)
321 return -ENOMEM;
322
323 ap->ranges[0].base = pci_resource_start(pdev, 0);
324 ap->ranges[0].size = pci_resource_len(pdev, 0);
325
326#ifdef CONFIG_X86
327 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
328#endif
329 drm_fb_helper_remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
330 kfree(ap);
331
332 return 0;
333}
334
335static int radeon_pci_probe(struct pci_dev *pdev,
336 const struct pci_device_id *ent)
337{
338 int ret;
339
340 if (vga_switcheroo_client_probe_defer(pdev))
341 return -EPROBE_DEFER;
342
343 /* Get rid of things like offb */
344 ret = radeon_kick_out_firmware_fb(pdev);
345 if (ret)
346 return ret;
347
348 return drm_get_pci_dev(pdev, ent, &kms_driver);
349}
350
351static void
352radeon_pci_remove(struct pci_dev *pdev)
353{
354 struct drm_device *dev = pci_get_drvdata(pdev);
355
356 drm_put_dev(dev);
357}
358
359static void
360radeon_pci_shutdown(struct pci_dev *pdev)
361{
362 /* if we are running in a VM, make sure the device
363 * torn down properly on reboot/shutdown
364 */
365 if (radeon_device_is_virtual())
366 radeon_pci_remove(pdev);
367}
368
369static int radeon_pmops_suspend(struct device *dev)
370{
371 struct pci_dev *pdev = to_pci_dev(dev);
372 struct drm_device *drm_dev = pci_get_drvdata(pdev);
373 return radeon_suspend_kms(drm_dev, true, true, false);
374}
375
376static int radeon_pmops_resume(struct device *dev)
377{
378 struct pci_dev *pdev = to_pci_dev(dev);
379 struct drm_device *drm_dev = pci_get_drvdata(pdev);
380
381 /* GPU comes up enabled by the bios on resume */
382 if (radeon_is_px(drm_dev)) {
383 pm_runtime_disable(dev);
384 pm_runtime_set_active(dev);
385 pm_runtime_enable(dev);
386 }
387
388 return radeon_resume_kms(drm_dev, true, true);
389}
390
391static int radeon_pmops_freeze(struct device *dev)
392{
393 struct pci_dev *pdev = to_pci_dev(dev);
394 struct drm_device *drm_dev = pci_get_drvdata(pdev);
395 return radeon_suspend_kms(drm_dev, false, true, true);
396}
397
398static int radeon_pmops_thaw(struct device *dev)
399{
400 struct pci_dev *pdev = to_pci_dev(dev);
401 struct drm_device *drm_dev = pci_get_drvdata(pdev);
402 return radeon_resume_kms(drm_dev, false, true);
403}
404
405static int radeon_pmops_runtime_suspend(struct device *dev)
406{
407 struct pci_dev *pdev = to_pci_dev(dev);
408 struct drm_device *drm_dev = pci_get_drvdata(pdev);
409 int ret;
410
411 if (!radeon_is_px(drm_dev)) {
412 pm_runtime_forbid(dev);
413 return -EBUSY;
414 }
415
416 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
417 drm_kms_helper_poll_disable(drm_dev);
418
419 ret = radeon_suspend_kms(drm_dev, false, false, false);
420 pci_save_state(pdev);
421 pci_disable_device(pdev);
422 pci_ignore_hotplug(pdev);
423 if (radeon_is_atpx_hybrid())
424 pci_set_power_state(pdev, PCI_D3cold);
425 else if (!radeon_has_atpx_dgpu_power_cntl())
426 pci_set_power_state(pdev, PCI_D3hot);
427 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
428
429 return 0;
430}
431
432static int radeon_pmops_runtime_resume(struct device *dev)
433{
434 struct pci_dev *pdev = to_pci_dev(dev);
435 struct drm_device *drm_dev = pci_get_drvdata(pdev);
436 int ret;
437
438 if (!radeon_is_px(drm_dev))
439 return -EINVAL;
440
441 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
442
443 if (radeon_is_atpx_hybrid() ||
444 !radeon_has_atpx_dgpu_power_cntl())
445 pci_set_power_state(pdev, PCI_D0);
446 pci_restore_state(pdev);
447 ret = pci_enable_device(pdev);
448 if (ret)
449 return ret;
450 pci_set_master(pdev);
451
452 ret = radeon_resume_kms(drm_dev, false, false);
453 drm_kms_helper_poll_enable(drm_dev);
454 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
455 return 0;
456}
457
458static int radeon_pmops_runtime_idle(struct device *dev)
459{
460 struct pci_dev *pdev = to_pci_dev(dev);
461 struct drm_device *drm_dev = pci_get_drvdata(pdev);
462 struct drm_crtc *crtc;
463
464 if (!radeon_is_px(drm_dev)) {
465 pm_runtime_forbid(dev);
466 return -EBUSY;
467 }
468
469 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
470 if (crtc->enabled) {
471 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
472 return -EBUSY;
473 }
474 }
475
476 pm_runtime_mark_last_busy(dev);
477 pm_runtime_autosuspend(dev);
478 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
479 return 1;
480}
481
482long radeon_drm_ioctl(struct file *filp,
483 unsigned int cmd, unsigned long arg)
484{
485 struct drm_file *file_priv = filp->private_data;
486 struct drm_device *dev;
487 long ret;
488 dev = file_priv->minor->dev;
489 ret = pm_runtime_get_sync(dev->dev);
490 if (ret < 0)
491 return ret;
492
493 ret = drm_ioctl(filp, cmd, arg);
494
495 pm_runtime_mark_last_busy(dev->dev);
496 pm_runtime_put_autosuspend(dev->dev);
497 return ret;
498}
499
500#ifdef CONFIG_COMPAT
501static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
502{
503 unsigned int nr = DRM_IOCTL_NR(cmd);
504 int ret;
505
506 if (nr < DRM_COMMAND_BASE)
507 return drm_compat_ioctl(filp, cmd, arg);
508
509 ret = radeon_drm_ioctl(filp, cmd, arg);
510
511 return ret;
512}
513#endif
514
515static const struct dev_pm_ops radeon_pm_ops = {
516 .suspend = radeon_pmops_suspend,
517 .resume = radeon_pmops_resume,
518 .freeze = radeon_pmops_freeze,
519 .thaw = radeon_pmops_thaw,
520 .poweroff = radeon_pmops_freeze,
521 .restore = radeon_pmops_resume,
522 .runtime_suspend = radeon_pmops_runtime_suspend,
523 .runtime_resume = radeon_pmops_runtime_resume,
524 .runtime_idle = radeon_pmops_runtime_idle,
525};
526
527static const struct file_operations radeon_driver_kms_fops = {
528 .owner = THIS_MODULE,
529 .open = drm_open,
530 .release = drm_release,
531 .unlocked_ioctl = radeon_drm_ioctl,
532 .mmap = radeon_mmap,
533 .poll = drm_poll,
534 .read = drm_read,
535#ifdef CONFIG_COMPAT
536 .compat_ioctl = radeon_kms_compat_ioctl,
537#endif
538};
539
540static bool
541radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
542 bool in_vblank_irq, int *vpos, int *hpos,
543 ktime_t *stime, ktime_t *etime,
544 const struct drm_display_mode *mode)
545{
546 return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
547 stime, etime, mode);
548}
549
550static struct drm_driver kms_driver = {
551 .driver_features =
552 DRIVER_USE_AGP |
553 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
554 DRIVER_PRIME | DRIVER_RENDER,
555 .load = radeon_driver_load_kms,
556 .open = radeon_driver_open_kms,
557 .postclose = radeon_driver_postclose_kms,
558 .lastclose = radeon_driver_lastclose_kms,
559 .unload = radeon_driver_unload_kms,
560 .get_vblank_counter = radeon_get_vblank_counter_kms,
561 .enable_vblank = radeon_enable_vblank_kms,
562 .disable_vblank = radeon_disable_vblank_kms,
563 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
564 .get_scanout_position = radeon_get_crtc_scanout_position,
565 .irq_preinstall = radeon_driver_irq_preinstall_kms,
566 .irq_postinstall = radeon_driver_irq_postinstall_kms,
567 .irq_uninstall = radeon_driver_irq_uninstall_kms,
568 .irq_handler = radeon_driver_irq_handler_kms,
569 .ioctls = radeon_ioctls_kms,
570 .gem_free_object_unlocked = radeon_gem_object_free,
571 .gem_open_object = radeon_gem_object_open,
572 .gem_close_object = radeon_gem_object_close,
573 .dumb_create = radeon_mode_dumb_create,
574 .dumb_map_offset = radeon_mode_dumb_mmap,
575 .fops = &radeon_driver_kms_fops,
576
577 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
578 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
579 .gem_prime_export = radeon_gem_prime_export,
580 .gem_prime_import = drm_gem_prime_import,
581 .gem_prime_pin = radeon_gem_prime_pin,
582 .gem_prime_unpin = radeon_gem_prime_unpin,
583 .gem_prime_res_obj = radeon_gem_prime_res_obj,
584 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
585 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
586 .gem_prime_vmap = radeon_gem_prime_vmap,
587 .gem_prime_vunmap = radeon_gem_prime_vunmap,
588
589 .name = DRIVER_NAME,
590 .desc = DRIVER_DESC,
591 .date = DRIVER_DATE,
592 .major = KMS_DRIVER_MAJOR,
593 .minor = KMS_DRIVER_MINOR,
594 .patchlevel = KMS_DRIVER_PATCHLEVEL,
595};
596
597static struct drm_driver *driver;
598static struct pci_driver *pdriver;
599
600static struct pci_driver radeon_kms_pci_driver = {
601 .name = DRIVER_NAME,
602 .id_table = pciidlist,
603 .probe = radeon_pci_probe,
604 .remove = radeon_pci_remove,
605 .shutdown = radeon_pci_shutdown,
606 .driver.pm = &radeon_pm_ops,
607};
608
609static int __init radeon_init(void)
610{
611 if (vgacon_text_force() && radeon_modeset == -1) {
612 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
613 radeon_modeset = 0;
614 }
615 /* set to modesetting by default if not nomodeset */
616 if (radeon_modeset == -1)
617 radeon_modeset = 1;
618
619 if (radeon_modeset == 1) {
620 DRM_INFO("radeon kernel modesetting enabled.\n");
621 driver = &kms_driver;
622 pdriver = &radeon_kms_pci_driver;
623 driver->driver_features |= DRIVER_MODESET;
624 driver->num_ioctls = radeon_max_kms_ioctl;
625 radeon_register_atpx_handler();
626
627 } else {
628 DRM_ERROR("No UMS support in radeon module!\n");
629 return -EINVAL;
630 }
631
632 return pci_register_driver(pdriver);
633}
634
635static void __exit radeon_exit(void)
636{
637 pci_unregister_driver(pdriver);
638 radeon_unregister_atpx_handler();
639}
640
641module_init(radeon_init);
642module_exit(radeon_exit);
643
644MODULE_AUTHOR(DRIVER_AUTHOR);
645MODULE_DESCRIPTION(DRIVER_DESC);
646MODULE_LICENSE("GPL and additional rights");