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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon_reg.h"
30#include "radeon.h"
31#include "atom.h"
32
33#include <linux/vga_switcheroo.h>
34#include <linux/slab.h>
35/*
36 * BIOS.
37 */
38
39/* If you boot an IGP board with a discrete card as the primary,
40 * the IGP rom is not accessible via the rom bar as the IGP rom is
41 * part of the system bios. On boot, the system bios puts a
42 * copy of the igp rom at the start of vram if a discrete card is
43 * present.
44 */
45static bool igp_read_bios_from_vram(struct radeon_device *rdev)
46{
47 uint8_t __iomem *bios;
48 resource_size_t vram_base;
49 resource_size_t size = 256 * 1024; /* ??? */
50
51 if (!(rdev->flags & RADEON_IS_IGP))
52 if (!radeon_card_posted(rdev))
53 return false;
54
55 rdev->bios = NULL;
56 vram_base = pci_resource_start(rdev->pdev, 0);
57 bios = ioremap(vram_base, size);
58 if (!bios) {
59 return false;
60 }
61
62 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
63 iounmap(bios);
64 return false;
65 }
66 rdev->bios = kmalloc(size, GFP_KERNEL);
67 if (rdev->bios == NULL) {
68 iounmap(bios);
69 return false;
70 }
71 memcpy_fromio(rdev->bios, bios, size);
72 iounmap(bios);
73 return true;
74}
75
76static bool radeon_read_bios(struct radeon_device *rdev)
77{
78 uint8_t __iomem *bios;
79 size_t size;
80
81 rdev->bios = NULL;
82 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
83 bios = pci_map_rom(rdev->pdev, &size);
84 if (!bios) {
85 return false;
86 }
87
88 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
89 pci_unmap_rom(rdev->pdev, bios);
90 return false;
91 }
92 rdev->bios = kmemdup(bios, size, GFP_KERNEL);
93 if (rdev->bios == NULL) {
94 pci_unmap_rom(rdev->pdev, bios);
95 return false;
96 }
97 pci_unmap_rom(rdev->pdev, bios);
98 return true;
99}
100
101/* ATRM is used to get the BIOS on the discrete cards in
102 * dual-gpu systems.
103 */
104static bool radeon_atrm_get_bios(struct radeon_device *rdev)
105{
106 int ret;
107 int size = 256 * 1024;
108 int i;
109
110 if (!radeon_atrm_supported(rdev->pdev))
111 return false;
112
113 rdev->bios = kmalloc(size, GFP_KERNEL);
114 if (!rdev->bios) {
115 DRM_ERROR("Unable to allocate bios\n");
116 return false;
117 }
118
119 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
120 ret = radeon_atrm_get_bios_chunk(rdev->bios,
121 (i * ATRM_BIOS_PAGE),
122 ATRM_BIOS_PAGE);
123 if (ret <= 0)
124 break;
125 }
126
127 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
128 kfree(rdev->bios);
129 return false;
130 }
131 return true;
132}
133
134static bool ni_read_disabled_bios(struct radeon_device *rdev)
135{
136 u32 bus_cntl;
137 u32 d1vga_control;
138 u32 d2vga_control;
139 u32 vga_render_control;
140 u32 rom_cntl;
141 bool r;
142
143 bus_cntl = RREG32(R600_BUS_CNTL);
144 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
145 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
146 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
147 rom_cntl = RREG32(R600_ROM_CNTL);
148
149 /* enable the rom */
150 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
151 /* Disable VGA mode */
152 WREG32(AVIVO_D1VGA_CONTROL,
153 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
154 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
155 WREG32(AVIVO_D2VGA_CONTROL,
156 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
157 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
158 WREG32(AVIVO_VGA_RENDER_CONTROL,
159 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
160 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
161
162 r = radeon_read_bios(rdev);
163
164 /* restore regs */
165 WREG32(R600_BUS_CNTL, bus_cntl);
166 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
167 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
168 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
169 WREG32(R600_ROM_CNTL, rom_cntl);
170 return r;
171}
172
173static bool r700_read_disabled_bios(struct radeon_device *rdev)
174{
175 uint32_t viph_control;
176 uint32_t bus_cntl;
177 uint32_t d1vga_control;
178 uint32_t d2vga_control;
179 uint32_t vga_render_control;
180 uint32_t rom_cntl;
181 uint32_t cg_spll_func_cntl = 0;
182 uint32_t cg_spll_status;
183 bool r;
184
185 viph_control = RREG32(RADEON_VIPH_CONTROL);
186 bus_cntl = RREG32(R600_BUS_CNTL);
187 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
188 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
189 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
190 rom_cntl = RREG32(R600_ROM_CNTL);
191
192 /* disable VIP */
193 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
194 /* enable the rom */
195 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
196 /* Disable VGA mode */
197 WREG32(AVIVO_D1VGA_CONTROL,
198 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
199 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
200 WREG32(AVIVO_D2VGA_CONTROL,
201 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
202 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
203 WREG32(AVIVO_VGA_RENDER_CONTROL,
204 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
205
206 if (rdev->family == CHIP_RV730) {
207 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
208
209 /* enable bypass mode */
210 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
211 R600_SPLL_BYPASS_EN));
212
213 /* wait for SPLL_CHG_STATUS to change to 1 */
214 cg_spll_status = 0;
215 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
216 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
217
218 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
219 } else
220 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
221
222 r = radeon_read_bios(rdev);
223
224 /* restore regs */
225 if (rdev->family == CHIP_RV730) {
226 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
227
228 /* wait for SPLL_CHG_STATUS to change to 1 */
229 cg_spll_status = 0;
230 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
231 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
232 }
233 WREG32(RADEON_VIPH_CONTROL, viph_control);
234 WREG32(R600_BUS_CNTL, bus_cntl);
235 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
236 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
237 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
238 WREG32(R600_ROM_CNTL, rom_cntl);
239 return r;
240}
241
242static bool r600_read_disabled_bios(struct radeon_device *rdev)
243{
244 uint32_t viph_control;
245 uint32_t bus_cntl;
246 uint32_t d1vga_control;
247 uint32_t d2vga_control;
248 uint32_t vga_render_control;
249 uint32_t rom_cntl;
250 uint32_t general_pwrmgt;
251 uint32_t low_vid_lower_gpio_cntl;
252 uint32_t medium_vid_lower_gpio_cntl;
253 uint32_t high_vid_lower_gpio_cntl;
254 uint32_t ctxsw_vid_lower_gpio_cntl;
255 uint32_t lower_gpio_enable;
256 bool r;
257
258 viph_control = RREG32(RADEON_VIPH_CONTROL);
259 bus_cntl = RREG32(R600_BUS_CNTL);
260 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
261 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
262 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
263 rom_cntl = RREG32(R600_ROM_CNTL);
264 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
265 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
266 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
267 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
268 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
269 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
270
271 /* disable VIP */
272 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
273 /* enable the rom */
274 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
275 /* Disable VGA mode */
276 WREG32(AVIVO_D1VGA_CONTROL,
277 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
278 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
279 WREG32(AVIVO_D2VGA_CONTROL,
280 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
281 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
282 WREG32(AVIVO_VGA_RENDER_CONTROL,
283 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
284
285 WREG32(R600_ROM_CNTL,
286 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
287 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
288 R600_SCK_OVERWRITE));
289
290 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
291 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
292 (low_vid_lower_gpio_cntl & ~0x400));
293 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
294 (medium_vid_lower_gpio_cntl & ~0x400));
295 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
296 (high_vid_lower_gpio_cntl & ~0x400));
297 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
298 (ctxsw_vid_lower_gpio_cntl & ~0x400));
299 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
300
301 r = radeon_read_bios(rdev);
302
303 /* restore regs */
304 WREG32(RADEON_VIPH_CONTROL, viph_control);
305 WREG32(R600_BUS_CNTL, bus_cntl);
306 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
307 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
308 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
309 WREG32(R600_ROM_CNTL, rom_cntl);
310 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
311 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
312 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
313 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
314 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
315 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
316 return r;
317}
318
319static bool avivo_read_disabled_bios(struct radeon_device *rdev)
320{
321 uint32_t seprom_cntl1;
322 uint32_t viph_control;
323 uint32_t bus_cntl;
324 uint32_t d1vga_control;
325 uint32_t d2vga_control;
326 uint32_t vga_render_control;
327 uint32_t gpiopad_a;
328 uint32_t gpiopad_en;
329 uint32_t gpiopad_mask;
330 bool r;
331
332 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
333 viph_control = RREG32(RADEON_VIPH_CONTROL);
334 bus_cntl = RREG32(RV370_BUS_CNTL);
335 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
336 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
337 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
338 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
339 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
340 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
341
342 WREG32(RADEON_SEPROM_CNTL1,
343 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
344 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
345 WREG32(RADEON_GPIOPAD_A, 0);
346 WREG32(RADEON_GPIOPAD_EN, 0);
347 WREG32(RADEON_GPIOPAD_MASK, 0);
348
349 /* disable VIP */
350 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
351
352 /* enable the rom */
353 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
354
355 /* Disable VGA mode */
356 WREG32(AVIVO_D1VGA_CONTROL,
357 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
358 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
359 WREG32(AVIVO_D2VGA_CONTROL,
360 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
361 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
362 WREG32(AVIVO_VGA_RENDER_CONTROL,
363 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
364
365 r = radeon_read_bios(rdev);
366
367 /* restore regs */
368 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
369 WREG32(RADEON_VIPH_CONTROL, viph_control);
370 WREG32(RV370_BUS_CNTL, bus_cntl);
371 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
372 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
373 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
374 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
375 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
376 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
377 return r;
378}
379
380static bool legacy_read_disabled_bios(struct radeon_device *rdev)
381{
382 uint32_t seprom_cntl1;
383 uint32_t viph_control;
384 uint32_t bus_cntl;
385 uint32_t crtc_gen_cntl;
386 uint32_t crtc2_gen_cntl;
387 uint32_t crtc_ext_cntl;
388 uint32_t fp2_gen_cntl;
389 bool r;
390
391 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
392 viph_control = RREG32(RADEON_VIPH_CONTROL);
393 if (rdev->flags & RADEON_IS_PCIE)
394 bus_cntl = RREG32(RV370_BUS_CNTL);
395 else
396 bus_cntl = RREG32(RADEON_BUS_CNTL);
397 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
398 crtc2_gen_cntl = 0;
399 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
400 fp2_gen_cntl = 0;
401
402 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
403 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
404 }
405
406 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
407 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
408 }
409
410 WREG32(RADEON_SEPROM_CNTL1,
411 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
412 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
413
414 /* disable VIP */
415 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
416
417 /* enable the rom */
418 if (rdev->flags & RADEON_IS_PCIE)
419 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
420 else
421 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
422
423 /* Turn off mem requests and CRTC for both controllers */
424 WREG32(RADEON_CRTC_GEN_CNTL,
425 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
426 (RADEON_CRTC_DISP_REQ_EN_B |
427 RADEON_CRTC_EXT_DISP_EN)));
428 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
429 WREG32(RADEON_CRTC2_GEN_CNTL,
430 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
431 RADEON_CRTC2_DISP_REQ_EN_B));
432 }
433 /* Turn off CRTC */
434 WREG32(RADEON_CRTC_EXT_CNTL,
435 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
436 (RADEON_CRTC_SYNC_TRISTAT |
437 RADEON_CRTC_DISPLAY_DIS)));
438
439 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
440 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
441 }
442
443 r = radeon_read_bios(rdev);
444
445 /* restore regs */
446 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
447 WREG32(RADEON_VIPH_CONTROL, viph_control);
448 if (rdev->flags & RADEON_IS_PCIE)
449 WREG32(RV370_BUS_CNTL, bus_cntl);
450 else
451 WREG32(RADEON_BUS_CNTL, bus_cntl);
452 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
453 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
454 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
455 }
456 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
457 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
458 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
459 }
460 return r;
461}
462
463static bool radeon_read_disabled_bios(struct radeon_device *rdev)
464{
465 if (rdev->flags & RADEON_IS_IGP)
466 return igp_read_bios_from_vram(rdev);
467 else if (rdev->family >= CHIP_BARTS)
468 return ni_read_disabled_bios(rdev);
469 else if (rdev->family >= CHIP_RV770)
470 return r700_read_disabled_bios(rdev);
471 else if (rdev->family >= CHIP_R600)
472 return r600_read_disabled_bios(rdev);
473 else if (rdev->family >= CHIP_RS600)
474 return avivo_read_disabled_bios(rdev);
475 else
476 return legacy_read_disabled_bios(rdev);
477}
478
479
480bool radeon_get_bios(struct radeon_device *rdev)
481{
482 bool r;
483 uint16_t tmp;
484
485 r = radeon_atrm_get_bios(rdev);
486 if (r == false)
487 r = igp_read_bios_from_vram(rdev);
488 if (r == false)
489 r = radeon_read_bios(rdev);
490 if (r == false) {
491 r = radeon_read_disabled_bios(rdev);
492 }
493 if (r == false || rdev->bios == NULL) {
494 DRM_ERROR("Unable to locate a BIOS ROM\n");
495 rdev->bios = NULL;
496 return false;
497 }
498 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
499 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
500 goto free_bios;
501 }
502
503 tmp = RBIOS16(0x18);
504 if (RBIOS8(tmp + 0x14) != 0x0) {
505 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
506 goto free_bios;
507 }
508
509 rdev->bios_header_start = RBIOS16(0x48);
510 if (!rdev->bios_header_start) {
511 goto free_bios;
512 }
513 tmp = rdev->bios_header_start + 4;
514 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
515 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
516 rdev->is_atom_bios = true;
517 } else {
518 rdev->is_atom_bios = false;
519 }
520
521 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
522 return true;
523free_bios:
524 kfree(rdev->bios);
525 rdev->bios = NULL;
526 return false;
527}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include "radeon_reg.h"
30#include "radeon.h"
31#include "atom.h"
32
33#include <linux/slab.h>
34#include <linux/acpi.h>
35/*
36 * BIOS.
37 */
38
39/* If you boot an IGP board with a discrete card as the primary,
40 * the IGP rom is not accessible via the rom bar as the IGP rom is
41 * part of the system bios. On boot, the system bios puts a
42 * copy of the igp rom at the start of vram if a discrete card is
43 * present.
44 */
45static bool igp_read_bios_from_vram(struct radeon_device *rdev)
46{
47 uint8_t __iomem *bios;
48 resource_size_t vram_base;
49 resource_size_t size = 256 * 1024; /* ??? */
50
51 if (!(rdev->flags & RADEON_IS_IGP))
52 if (!radeon_card_posted(rdev))
53 return false;
54
55 rdev->bios = NULL;
56 vram_base = pci_resource_start(rdev->pdev, 0);
57 bios = ioremap(vram_base, size);
58 if (!bios) {
59 return false;
60 }
61
62 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
63 iounmap(bios);
64 return false;
65 }
66 rdev->bios = kmalloc(size, GFP_KERNEL);
67 if (rdev->bios == NULL) {
68 iounmap(bios);
69 return false;
70 }
71 memcpy_fromio(rdev->bios, bios, size);
72 iounmap(bios);
73 return true;
74}
75
76static bool radeon_read_bios(struct radeon_device *rdev)
77{
78 uint8_t __iomem *bios, val1, val2;
79 size_t size;
80
81 rdev->bios = NULL;
82 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
83 bios = pci_map_rom(rdev->pdev, &size);
84 if (!bios) {
85 return false;
86 }
87
88 val1 = readb(&bios[0]);
89 val2 = readb(&bios[1]);
90
91 if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
92 pci_unmap_rom(rdev->pdev, bios);
93 return false;
94 }
95 rdev->bios = kzalloc(size, GFP_KERNEL);
96 if (rdev->bios == NULL) {
97 pci_unmap_rom(rdev->pdev, bios);
98 return false;
99 }
100 memcpy_fromio(rdev->bios, bios, size);
101 pci_unmap_rom(rdev->pdev, bios);
102 return true;
103}
104
105static bool radeon_read_platform_bios(struct radeon_device *rdev)
106{
107 uint8_t __iomem *bios;
108 size_t size;
109
110 rdev->bios = NULL;
111
112 bios = pci_platform_rom(rdev->pdev, &size);
113 if (!bios) {
114 return false;
115 }
116
117 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
118 return false;
119 }
120 rdev->bios = kmemdup(bios, size, GFP_KERNEL);
121 if (rdev->bios == NULL) {
122 return false;
123 }
124
125 return true;
126}
127
128#ifdef CONFIG_ACPI
129/* ATRM is used to get the BIOS on the discrete cards in
130 * dual-gpu systems.
131 */
132/* retrieve the ROM in 4k blocks */
133#define ATRM_BIOS_PAGE 4096
134/**
135 * radeon_atrm_call - fetch a chunk of the vbios
136 *
137 * @atrm_handle: acpi ATRM handle
138 * @bios: vbios image pointer
139 * @offset: offset of vbios image data to fetch
140 * @len: length of vbios image data to fetch
141 *
142 * Executes ATRM to fetch a chunk of the discrete
143 * vbios image on PX systems (all asics).
144 * Returns the length of the buffer fetched.
145 */
146static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
147 int offset, int len)
148{
149 acpi_status status;
150 union acpi_object atrm_arg_elements[2], *obj;
151 struct acpi_object_list atrm_arg;
152 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
153
154 atrm_arg.count = 2;
155 atrm_arg.pointer = &atrm_arg_elements[0];
156
157 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
158 atrm_arg_elements[0].integer.value = offset;
159
160 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
161 atrm_arg_elements[1].integer.value = len;
162
163 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
164 if (ACPI_FAILURE(status)) {
165 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
166 return -ENODEV;
167 }
168
169 obj = (union acpi_object *)buffer.pointer;
170 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
171 len = obj->buffer.length;
172 kfree(buffer.pointer);
173 return len;
174}
175
176static bool radeon_atrm_get_bios(struct radeon_device *rdev)
177{
178 int ret;
179 int size = 256 * 1024;
180 int i;
181 struct pci_dev *pdev = NULL;
182 acpi_handle dhandle, atrm_handle;
183 acpi_status status;
184 bool found = false;
185
186 /* ATRM is for the discrete card only */
187 if (rdev->flags & RADEON_IS_IGP)
188 return false;
189
190 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
191 dhandle = ACPI_HANDLE(&pdev->dev);
192 if (!dhandle)
193 continue;
194
195 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
196 if (!ACPI_FAILURE(status)) {
197 found = true;
198 break;
199 }
200 }
201
202 if (!found) {
203 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
204 dhandle = ACPI_HANDLE(&pdev->dev);
205 if (!dhandle)
206 continue;
207
208 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
209 if (!ACPI_FAILURE(status)) {
210 found = true;
211 break;
212 }
213 }
214 }
215
216 if (!found)
217 return false;
218
219 rdev->bios = kmalloc(size, GFP_KERNEL);
220 if (!rdev->bios) {
221 DRM_ERROR("Unable to allocate bios\n");
222 return false;
223 }
224
225 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
226 ret = radeon_atrm_call(atrm_handle,
227 rdev->bios,
228 (i * ATRM_BIOS_PAGE),
229 ATRM_BIOS_PAGE);
230 if (ret < ATRM_BIOS_PAGE)
231 break;
232 }
233
234 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
235 kfree(rdev->bios);
236 return false;
237 }
238 return true;
239}
240#else
241static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
242{
243 return false;
244}
245#endif
246
247static bool ni_read_disabled_bios(struct radeon_device *rdev)
248{
249 u32 bus_cntl;
250 u32 d1vga_control;
251 u32 d2vga_control;
252 u32 vga_render_control;
253 u32 rom_cntl;
254 bool r;
255
256 bus_cntl = RREG32(R600_BUS_CNTL);
257 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
258 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
259 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
260 rom_cntl = RREG32(R600_ROM_CNTL);
261
262 /* enable the rom */
263 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
264 if (!ASIC_IS_NODCE(rdev)) {
265 /* Disable VGA mode */
266 WREG32(AVIVO_D1VGA_CONTROL,
267 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
268 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
269 WREG32(AVIVO_D2VGA_CONTROL,
270 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
271 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
272 WREG32(AVIVO_VGA_RENDER_CONTROL,
273 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
274 }
275 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
276
277 r = radeon_read_bios(rdev);
278
279 /* restore regs */
280 WREG32(R600_BUS_CNTL, bus_cntl);
281 if (!ASIC_IS_NODCE(rdev)) {
282 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
283 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
284 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
285 }
286 WREG32(R600_ROM_CNTL, rom_cntl);
287 return r;
288}
289
290static bool r700_read_disabled_bios(struct radeon_device *rdev)
291{
292 uint32_t viph_control;
293 uint32_t bus_cntl;
294 uint32_t d1vga_control;
295 uint32_t d2vga_control;
296 uint32_t vga_render_control;
297 uint32_t rom_cntl;
298 uint32_t cg_spll_func_cntl = 0;
299 uint32_t cg_spll_status;
300 bool r;
301
302 viph_control = RREG32(RADEON_VIPH_CONTROL);
303 bus_cntl = RREG32(R600_BUS_CNTL);
304 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
305 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
306 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
307 rom_cntl = RREG32(R600_ROM_CNTL);
308
309 /* disable VIP */
310 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
311 /* enable the rom */
312 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
313 /* Disable VGA mode */
314 WREG32(AVIVO_D1VGA_CONTROL,
315 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
316 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
317 WREG32(AVIVO_D2VGA_CONTROL,
318 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
319 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
320 WREG32(AVIVO_VGA_RENDER_CONTROL,
321 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
322
323 if (rdev->family == CHIP_RV730) {
324 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
325
326 /* enable bypass mode */
327 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
328 R600_SPLL_BYPASS_EN));
329
330 /* wait for SPLL_CHG_STATUS to change to 1 */
331 cg_spll_status = 0;
332 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
333 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
334
335 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
336 } else
337 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
338
339 r = radeon_read_bios(rdev);
340
341 /* restore regs */
342 if (rdev->family == CHIP_RV730) {
343 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
344
345 /* wait for SPLL_CHG_STATUS to change to 1 */
346 cg_spll_status = 0;
347 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
348 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
349 }
350 WREG32(RADEON_VIPH_CONTROL, viph_control);
351 WREG32(R600_BUS_CNTL, bus_cntl);
352 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
353 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
354 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
355 WREG32(R600_ROM_CNTL, rom_cntl);
356 return r;
357}
358
359static bool r600_read_disabled_bios(struct radeon_device *rdev)
360{
361 uint32_t viph_control;
362 uint32_t bus_cntl;
363 uint32_t d1vga_control;
364 uint32_t d2vga_control;
365 uint32_t vga_render_control;
366 uint32_t rom_cntl;
367 uint32_t general_pwrmgt;
368 uint32_t low_vid_lower_gpio_cntl;
369 uint32_t medium_vid_lower_gpio_cntl;
370 uint32_t high_vid_lower_gpio_cntl;
371 uint32_t ctxsw_vid_lower_gpio_cntl;
372 uint32_t lower_gpio_enable;
373 bool r;
374
375 viph_control = RREG32(RADEON_VIPH_CONTROL);
376 bus_cntl = RREG32(R600_BUS_CNTL);
377 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
378 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
379 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
380 rom_cntl = RREG32(R600_ROM_CNTL);
381 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
382 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
383 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
384 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
385 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
386 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
387
388 /* disable VIP */
389 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
390 /* enable the rom */
391 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
392 /* Disable VGA mode */
393 WREG32(AVIVO_D1VGA_CONTROL,
394 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
395 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
396 WREG32(AVIVO_D2VGA_CONTROL,
397 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
398 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
399 WREG32(AVIVO_VGA_RENDER_CONTROL,
400 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
401
402 WREG32(R600_ROM_CNTL,
403 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
404 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
405 R600_SCK_OVERWRITE));
406
407 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
408 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
409 (low_vid_lower_gpio_cntl & ~0x400));
410 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
411 (medium_vid_lower_gpio_cntl & ~0x400));
412 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
413 (high_vid_lower_gpio_cntl & ~0x400));
414 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
415 (ctxsw_vid_lower_gpio_cntl & ~0x400));
416 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
417
418 r = radeon_read_bios(rdev);
419
420 /* restore regs */
421 WREG32(RADEON_VIPH_CONTROL, viph_control);
422 WREG32(R600_BUS_CNTL, bus_cntl);
423 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
424 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
425 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
426 WREG32(R600_ROM_CNTL, rom_cntl);
427 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
428 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
429 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
430 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
431 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
432 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
433 return r;
434}
435
436static bool avivo_read_disabled_bios(struct radeon_device *rdev)
437{
438 uint32_t seprom_cntl1;
439 uint32_t viph_control;
440 uint32_t bus_cntl;
441 uint32_t d1vga_control;
442 uint32_t d2vga_control;
443 uint32_t vga_render_control;
444 uint32_t gpiopad_a;
445 uint32_t gpiopad_en;
446 uint32_t gpiopad_mask;
447 bool r;
448
449 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
450 viph_control = RREG32(RADEON_VIPH_CONTROL);
451 bus_cntl = RREG32(RV370_BUS_CNTL);
452 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
453 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
454 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
455 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
456 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
457 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
458
459 WREG32(RADEON_SEPROM_CNTL1,
460 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
461 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
462 WREG32(RADEON_GPIOPAD_A, 0);
463 WREG32(RADEON_GPIOPAD_EN, 0);
464 WREG32(RADEON_GPIOPAD_MASK, 0);
465
466 /* disable VIP */
467 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
468
469 /* enable the rom */
470 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
471
472 /* Disable VGA mode */
473 WREG32(AVIVO_D1VGA_CONTROL,
474 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
475 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
476 WREG32(AVIVO_D2VGA_CONTROL,
477 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
478 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
479 WREG32(AVIVO_VGA_RENDER_CONTROL,
480 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
481
482 r = radeon_read_bios(rdev);
483
484 /* restore regs */
485 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
486 WREG32(RADEON_VIPH_CONTROL, viph_control);
487 WREG32(RV370_BUS_CNTL, bus_cntl);
488 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
489 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
490 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
491 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
492 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
493 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
494 return r;
495}
496
497static bool legacy_read_disabled_bios(struct radeon_device *rdev)
498{
499 uint32_t seprom_cntl1;
500 uint32_t viph_control;
501 uint32_t bus_cntl;
502 uint32_t crtc_gen_cntl;
503 uint32_t crtc2_gen_cntl;
504 uint32_t crtc_ext_cntl;
505 uint32_t fp2_gen_cntl;
506 bool r;
507
508 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
509 viph_control = RREG32(RADEON_VIPH_CONTROL);
510 if (rdev->flags & RADEON_IS_PCIE)
511 bus_cntl = RREG32(RV370_BUS_CNTL);
512 else
513 bus_cntl = RREG32(RADEON_BUS_CNTL);
514 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
515 crtc2_gen_cntl = 0;
516 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
517 fp2_gen_cntl = 0;
518
519 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
520 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
521 }
522
523 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
524 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
525 }
526
527 WREG32(RADEON_SEPROM_CNTL1,
528 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
529 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
530
531 /* disable VIP */
532 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
533
534 /* enable the rom */
535 if (rdev->flags & RADEON_IS_PCIE)
536 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
537 else
538 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
539
540 /* Turn off mem requests and CRTC for both controllers */
541 WREG32(RADEON_CRTC_GEN_CNTL,
542 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
543 (RADEON_CRTC_DISP_REQ_EN_B |
544 RADEON_CRTC_EXT_DISP_EN)));
545 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
546 WREG32(RADEON_CRTC2_GEN_CNTL,
547 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
548 RADEON_CRTC2_DISP_REQ_EN_B));
549 }
550 /* Turn off CRTC */
551 WREG32(RADEON_CRTC_EXT_CNTL,
552 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
553 (RADEON_CRTC_SYNC_TRISTAT |
554 RADEON_CRTC_DISPLAY_DIS)));
555
556 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
557 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
558 }
559
560 r = radeon_read_bios(rdev);
561
562 /* restore regs */
563 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
564 WREG32(RADEON_VIPH_CONTROL, viph_control);
565 if (rdev->flags & RADEON_IS_PCIE)
566 WREG32(RV370_BUS_CNTL, bus_cntl);
567 else
568 WREG32(RADEON_BUS_CNTL, bus_cntl);
569 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
570 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
571 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
572 }
573 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
574 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
575 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
576 }
577 return r;
578}
579
580static bool radeon_read_disabled_bios(struct radeon_device *rdev)
581{
582 if (rdev->flags & RADEON_IS_IGP)
583 return igp_read_bios_from_vram(rdev);
584 else if (rdev->family >= CHIP_BARTS)
585 return ni_read_disabled_bios(rdev);
586 else if (rdev->family >= CHIP_RV770)
587 return r700_read_disabled_bios(rdev);
588 else if (rdev->family >= CHIP_R600)
589 return r600_read_disabled_bios(rdev);
590 else if (rdev->family >= CHIP_RS600)
591 return avivo_read_disabled_bios(rdev);
592 else
593 return legacy_read_disabled_bios(rdev);
594}
595
596#ifdef CONFIG_ACPI
597static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
598{
599 struct acpi_table_header *hdr;
600 acpi_size tbl_size;
601 UEFI_ACPI_VFCT *vfct;
602 unsigned offset;
603
604 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
605 return false;
606 tbl_size = hdr->length;
607 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
608 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
609 return false;
610 }
611
612 vfct = (UEFI_ACPI_VFCT *)hdr;
613 offset = vfct->VBIOSImageOffset;
614
615 while (offset < tbl_size) {
616 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
617 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
618
619 offset += sizeof(VFCT_IMAGE_HEADER);
620 if (offset > tbl_size) {
621 DRM_ERROR("ACPI VFCT image header truncated\n");
622 return false;
623 }
624
625 offset += vhdr->ImageLength;
626 if (offset > tbl_size) {
627 DRM_ERROR("ACPI VFCT image truncated\n");
628 return false;
629 }
630
631 if (vhdr->ImageLength &&
632 vhdr->PCIBus == rdev->pdev->bus->number &&
633 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) &&
634 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) &&
635 vhdr->VendorID == rdev->pdev->vendor &&
636 vhdr->DeviceID == rdev->pdev->device) {
637 rdev->bios = kmemdup(&vbios->VbiosContent,
638 vhdr->ImageLength,
639 GFP_KERNEL);
640
641 if (!rdev->bios)
642 return false;
643 return true;
644 }
645 }
646
647 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
648 return false;
649}
650#else
651static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
652{
653 return false;
654}
655#endif
656
657bool radeon_get_bios(struct radeon_device *rdev)
658{
659 bool r;
660 uint16_t tmp;
661
662 r = radeon_atrm_get_bios(rdev);
663 if (r == false)
664 r = radeon_acpi_vfct_bios(rdev);
665 if (r == false)
666 r = igp_read_bios_from_vram(rdev);
667 if (r == false)
668 r = radeon_read_bios(rdev);
669 if (r == false)
670 r = radeon_read_disabled_bios(rdev);
671 if (r == false)
672 r = radeon_read_platform_bios(rdev);
673 if (r == false || rdev->bios == NULL) {
674 DRM_ERROR("Unable to locate a BIOS ROM\n");
675 rdev->bios = NULL;
676 return false;
677 }
678 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
679 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
680 goto free_bios;
681 }
682
683 tmp = RBIOS16(0x18);
684 if (RBIOS8(tmp + 0x14) != 0x0) {
685 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
686 goto free_bios;
687 }
688
689 rdev->bios_header_start = RBIOS16(0x48);
690 if (!rdev->bios_header_start) {
691 goto free_bios;
692 }
693 tmp = rdev->bios_header_start + 4;
694 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
695 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
696 rdev->is_atom_bios = true;
697 } else {
698 rdev->is_atom_bios = false;
699 }
700
701 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
702 return true;
703free_bios:
704 kfree(rdev->bios);
705 rdev->bios = NULL;
706 return false;
707}