Loading...
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32
33/* from radeon_encoder.c */
34extern uint32_t
35radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device, u16 caps);
41
42/* from radeon_connector.c */
43extern void
44radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd,
52 struct radeon_router *router);
53
54/* from radeon_legacy_encoder.c */
55extern void
56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
57 uint32_t supported_device);
58
59union atom_supported_devices {
60 struct _ATOM_SUPPORTED_DEVICES_INFO info;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
63};
64
65static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
66 uint8_t id)
67{
68 struct atom_context *ctx = rdev->mode_info.atom_context;
69 ATOM_GPIO_I2C_ASSIGMENT *gpio;
70 struct radeon_i2c_bus_rec i2c;
71 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
72 struct _ATOM_GPIO_I2C_INFO *i2c_info;
73 uint16_t data_offset, size;
74 int i, num_indices;
75
76 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
77 i2c.valid = false;
78
79 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
80 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81
82 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84
85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i];
87
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) &&
91 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
92 (gpio->sucI2cId.ucAccess == 0)) {
93 gpio->sucI2cId.ucAccess = 0x97;
94 gpio->ucDataMaskShift = 8;
95 gpio->ucDataEnShift = 8;
96 gpio->ucDataY_Shift = 8;
97 gpio->ucDataA_Shift = 8;
98 }
99 }
100
101 /* some DCE3 boards have bad data for this entry */
102 if (ASIC_IS_DCE3(rdev)) {
103 if ((i == 4) &&
104 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
105 (gpio->sucI2cId.ucAccess == 0x94))
106 gpio->sucI2cId.ucAccess = 0x14;
107 }
108
109 if (gpio->sucI2cId.ucAccess == id) {
110 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
111 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
112 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
113 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
114 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
115 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
116 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
117 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
118 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
119 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
120 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
121 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
122 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
123 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
124 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
125 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
126
127 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
128 i2c.hw_capable = true;
129 else
130 i2c.hw_capable = false;
131
132 if (gpio->sucI2cId.ucAccess == 0xa0)
133 i2c.mm_i2c = true;
134 else
135 i2c.mm_i2c = false;
136
137 i2c.i2c_id = gpio->sucI2cId.ucAccess;
138
139 if (i2c.mask_clk_reg)
140 i2c.valid = true;
141 break;
142 }
143 }
144 }
145
146 return i2c;
147}
148
149void radeon_atombios_i2c_init(struct radeon_device *rdev)
150{
151 struct atom_context *ctx = rdev->mode_info.atom_context;
152 ATOM_GPIO_I2C_ASSIGMENT *gpio;
153 struct radeon_i2c_bus_rec i2c;
154 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
155 struct _ATOM_GPIO_I2C_INFO *i2c_info;
156 uint16_t data_offset, size;
157 int i, num_indices;
158 char stmp[32];
159
160 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
161
162 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
163 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
164
165 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
166 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
167
168 for (i = 0; i < num_indices; i++) {
169 gpio = &i2c_info->asGPIO_Info[i];
170 i2c.valid = false;
171
172 /* some evergreen boards have bad data for this entry */
173 if (ASIC_IS_DCE4(rdev)) {
174 if ((i == 7) &&
175 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
176 (gpio->sucI2cId.ucAccess == 0)) {
177 gpio->sucI2cId.ucAccess = 0x97;
178 gpio->ucDataMaskShift = 8;
179 gpio->ucDataEnShift = 8;
180 gpio->ucDataY_Shift = 8;
181 gpio->ucDataA_Shift = 8;
182 }
183 }
184
185 /* some DCE3 boards have bad data for this entry */
186 if (ASIC_IS_DCE3(rdev)) {
187 if ((i == 4) &&
188 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
189 (gpio->sucI2cId.ucAccess == 0x94))
190 gpio->sucI2cId.ucAccess = 0x14;
191 }
192
193 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
194 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
195 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
196 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
197 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
198 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
199 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
200 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
201 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
202 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
203 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
204 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
205 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
206 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
207 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
208 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
209
210 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
211 i2c.hw_capable = true;
212 else
213 i2c.hw_capable = false;
214
215 if (gpio->sucI2cId.ucAccess == 0xa0)
216 i2c.mm_i2c = true;
217 else
218 i2c.mm_i2c = false;
219
220 i2c.i2c_id = gpio->sucI2cId.ucAccess;
221
222 if (i2c.mask_clk_reg) {
223 i2c.valid = true;
224 sprintf(stmp, "0x%x", i2c.i2c_id);
225 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
226 }
227 }
228 }
229}
230
231static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
232 u8 id)
233{
234 struct atom_context *ctx = rdev->mode_info.atom_context;
235 struct radeon_gpio_rec gpio;
236 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
237 struct _ATOM_GPIO_PIN_LUT *gpio_info;
238 ATOM_GPIO_PIN_ASSIGNMENT *pin;
239 u16 data_offset, size;
240 int i, num_indices;
241
242 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
243 gpio.valid = false;
244
245 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
246 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
247
248 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
249 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
250
251 for (i = 0; i < num_indices; i++) {
252 pin = &gpio_info->asGPIO_Pin[i];
253 if (id == pin->ucGPIO_ID) {
254 gpio.id = pin->ucGPIO_ID;
255 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
256 gpio.mask = (1 << pin->ucGpioPinBitShift);
257 gpio.valid = true;
258 break;
259 }
260 }
261 }
262
263 return gpio;
264}
265
266static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
267 struct radeon_gpio_rec *gpio)
268{
269 struct radeon_hpd hpd;
270 u32 reg;
271
272 memset(&hpd, 0, sizeof(struct radeon_hpd));
273
274 if (ASIC_IS_DCE4(rdev))
275 reg = EVERGREEN_DC_GPIO_HPD_A;
276 else
277 reg = AVIVO_DC_GPIO_HPD_A;
278
279 hpd.gpio = *gpio;
280 if (gpio->reg == reg) {
281 switch(gpio->mask) {
282 case (1 << 0):
283 hpd.hpd = RADEON_HPD_1;
284 break;
285 case (1 << 8):
286 hpd.hpd = RADEON_HPD_2;
287 break;
288 case (1 << 16):
289 hpd.hpd = RADEON_HPD_3;
290 break;
291 case (1 << 24):
292 hpd.hpd = RADEON_HPD_4;
293 break;
294 case (1 << 26):
295 hpd.hpd = RADEON_HPD_5;
296 break;
297 case (1 << 28):
298 hpd.hpd = RADEON_HPD_6;
299 break;
300 default:
301 hpd.hpd = RADEON_HPD_NONE;
302 break;
303 }
304 } else
305 hpd.hpd = RADEON_HPD_NONE;
306 return hpd;
307}
308
309static bool radeon_atom_apply_quirks(struct drm_device *dev,
310 uint32_t supported_device,
311 int *connector_type,
312 struct radeon_i2c_bus_rec *i2c_bus,
313 uint16_t *line_mux,
314 struct radeon_hpd *hpd)
315{
316
317 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
318 if ((dev->pdev->device == 0x791e) &&
319 (dev->pdev->subsystem_vendor == 0x1043) &&
320 (dev->pdev->subsystem_device == 0x826d)) {
321 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
322 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
323 *connector_type = DRM_MODE_CONNECTOR_DVID;
324 }
325
326 /* Asrock RS600 board lists the DVI port as HDMI */
327 if ((dev->pdev->device == 0x7941) &&
328 (dev->pdev->subsystem_vendor == 0x1849) &&
329 (dev->pdev->subsystem_device == 0x7941)) {
330 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
331 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
332 *connector_type = DRM_MODE_CONNECTOR_DVID;
333 }
334
335 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
336 if ((dev->pdev->device == 0x796e) &&
337 (dev->pdev->subsystem_vendor == 0x1462) &&
338 (dev->pdev->subsystem_device == 0x7302)) {
339 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
340 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
341 return false;
342 }
343
344 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
345 if ((dev->pdev->device == 0x7941) &&
346 (dev->pdev->subsystem_vendor == 0x147b) &&
347 (dev->pdev->subsystem_device == 0x2412)) {
348 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
349 return false;
350 }
351
352 /* Falcon NW laptop lists vga ddc line for LVDS */
353 if ((dev->pdev->device == 0x5653) &&
354 (dev->pdev->subsystem_vendor == 0x1462) &&
355 (dev->pdev->subsystem_device == 0x0291)) {
356 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
357 i2c_bus->valid = false;
358 *line_mux = 53;
359 }
360 }
361
362 /* HIS X1300 is DVI+VGA, not DVI+DVI */
363 if ((dev->pdev->device == 0x7146) &&
364 (dev->pdev->subsystem_vendor == 0x17af) &&
365 (dev->pdev->subsystem_device == 0x2058)) {
366 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
367 return false;
368 }
369
370 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
371 if ((dev->pdev->device == 0x7142) &&
372 (dev->pdev->subsystem_vendor == 0x1458) &&
373 (dev->pdev->subsystem_device == 0x2134)) {
374 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
375 return false;
376 }
377
378
379 /* Funky macbooks */
380 if ((dev->pdev->device == 0x71C5) &&
381 (dev->pdev->subsystem_vendor == 0x106b) &&
382 (dev->pdev->subsystem_device == 0x0080)) {
383 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
384 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
385 return false;
386 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
387 *line_mux = 0x90;
388 }
389
390 /* mac rv630, rv730, others */
391 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
392 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
393 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
394 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
395 }
396
397 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
398 if ((dev->pdev->device == 0x9598) &&
399 (dev->pdev->subsystem_vendor == 0x1043) &&
400 (dev->pdev->subsystem_device == 0x01da)) {
401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
402 *connector_type = DRM_MODE_CONNECTOR_DVII;
403 }
404 }
405
406 /* ASUS HD 3600 board lists the DVI port as HDMI */
407 if ((dev->pdev->device == 0x9598) &&
408 (dev->pdev->subsystem_vendor == 0x1043) &&
409 (dev->pdev->subsystem_device == 0x01e4)) {
410 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
411 *connector_type = DRM_MODE_CONNECTOR_DVII;
412 }
413 }
414
415 /* ASUS HD 3450 board lists the DVI port as HDMI */
416 if ((dev->pdev->device == 0x95C5) &&
417 (dev->pdev->subsystem_vendor == 0x1043) &&
418 (dev->pdev->subsystem_device == 0x01e2)) {
419 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
420 *connector_type = DRM_MODE_CONNECTOR_DVII;
421 }
422 }
423
424 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
425 * HDMI + VGA reporting as HDMI
426 */
427 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
428 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
429 *connector_type = DRM_MODE_CONNECTOR_VGA;
430 *line_mux = 0;
431 }
432 }
433
434 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
435 * on the laptop and a DVI port on the docking station and
436 * both share the same encoder, hpd pin, and ddc line.
437 * So while the bios table is technically correct,
438 * we drop the DVI port here since xrandr has no concept of
439 * encoders and will try and drive both connectors
440 * with different crtcs which isn't possible on the hardware
441 * side and leaves no crtcs for LVDS or VGA.
442 */
443 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
444 (dev->pdev->subsystem_vendor == 0x1025) &&
445 (dev->pdev->subsystem_device == 0x013c)) {
446 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
447 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
448 /* actually it's a DVI-D port not DVI-I */
449 *connector_type = DRM_MODE_CONNECTOR_DVID;
450 return false;
451 }
452 }
453
454 /* XFX Pine Group device rv730 reports no VGA DDC lines
455 * even though they are wired up to record 0x93
456 */
457 if ((dev->pdev->device == 0x9498) &&
458 (dev->pdev->subsystem_vendor == 0x1682) &&
459 (dev->pdev->subsystem_device == 0x2452)) {
460 struct radeon_device *rdev = dev->dev_private;
461 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
462 }
463 return true;
464}
465
466const int supported_devices_connector_convert[] = {
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_VGA,
469 DRM_MODE_CONNECTOR_DVII,
470 DRM_MODE_CONNECTOR_DVID,
471 DRM_MODE_CONNECTOR_DVIA,
472 DRM_MODE_CONNECTOR_SVIDEO,
473 DRM_MODE_CONNECTOR_Composite,
474 DRM_MODE_CONNECTOR_LVDS,
475 DRM_MODE_CONNECTOR_Unknown,
476 DRM_MODE_CONNECTOR_Unknown,
477 DRM_MODE_CONNECTOR_HDMIA,
478 DRM_MODE_CONNECTOR_HDMIB,
479 DRM_MODE_CONNECTOR_Unknown,
480 DRM_MODE_CONNECTOR_Unknown,
481 DRM_MODE_CONNECTOR_9PinDIN,
482 DRM_MODE_CONNECTOR_DisplayPort
483};
484
485const uint16_t supported_devices_connector_object_id_convert[] = {
486 CONNECTOR_OBJECT_ID_NONE,
487 CONNECTOR_OBJECT_ID_VGA,
488 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
489 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
490 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
491 CONNECTOR_OBJECT_ID_COMPOSITE,
492 CONNECTOR_OBJECT_ID_SVIDEO,
493 CONNECTOR_OBJECT_ID_LVDS,
494 CONNECTOR_OBJECT_ID_9PIN_DIN,
495 CONNECTOR_OBJECT_ID_9PIN_DIN,
496 CONNECTOR_OBJECT_ID_DISPLAYPORT,
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
498 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
499 CONNECTOR_OBJECT_ID_SVIDEO
500};
501
502const int object_connector_convert[] = {
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_DVII,
505 DRM_MODE_CONNECTOR_DVII,
506 DRM_MODE_CONNECTOR_DVID,
507 DRM_MODE_CONNECTOR_DVID,
508 DRM_MODE_CONNECTOR_VGA,
509 DRM_MODE_CONNECTOR_Composite,
510 DRM_MODE_CONNECTOR_SVIDEO,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_9PinDIN,
514 DRM_MODE_CONNECTOR_Unknown,
515 DRM_MODE_CONNECTOR_HDMIA,
516 DRM_MODE_CONNECTOR_HDMIB,
517 DRM_MODE_CONNECTOR_LVDS,
518 DRM_MODE_CONNECTOR_9PinDIN,
519 DRM_MODE_CONNECTOR_Unknown,
520 DRM_MODE_CONNECTOR_Unknown,
521 DRM_MODE_CONNECTOR_Unknown,
522 DRM_MODE_CONNECTOR_DisplayPort,
523 DRM_MODE_CONNECTOR_eDP,
524 DRM_MODE_CONNECTOR_Unknown
525};
526
527bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
528{
529 struct radeon_device *rdev = dev->dev_private;
530 struct radeon_mode_info *mode_info = &rdev->mode_info;
531 struct atom_context *ctx = mode_info->atom_context;
532 int index = GetIndexIntoMasterTable(DATA, Object_Header);
533 u16 size, data_offset;
534 u8 frev, crev;
535 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
536 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
537 ATOM_OBJECT_TABLE *router_obj;
538 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
539 ATOM_OBJECT_HEADER *obj_header;
540 int i, j, k, path_size, device_support;
541 int connector_type;
542 u16 igp_lane_info, conn_id, connector_object_id;
543 struct radeon_i2c_bus_rec ddc_bus;
544 struct radeon_router router;
545 struct radeon_gpio_rec gpio;
546 struct radeon_hpd hpd;
547
548 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
549 return false;
550
551 if (crev < 2)
552 return false;
553
554 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
555 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usDisplayPathTableOffset));
558 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
559 (ctx->bios + data_offset +
560 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
561 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
562 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
564 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset));
567 device_support = le16_to_cpu(obj_header->usDeviceSupport);
568
569 path_size = 0;
570 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
571 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
572 ATOM_DISPLAY_OBJECT_PATH *path;
573 addr += path_size;
574 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
575 path_size += le16_to_cpu(path->usSize);
576
577 if (device_support & le16_to_cpu(path->usDeviceTag)) {
578 uint8_t con_obj_id, con_obj_num, con_obj_type;
579
580 con_obj_id =
581 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
582 >> OBJECT_ID_SHIFT;
583 con_obj_num =
584 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
585 >> ENUM_ID_SHIFT;
586 con_obj_type =
587 (le16_to_cpu(path->usConnObjectId) &
588 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
589
590 /* TODO CV support */
591 if (le16_to_cpu(path->usDeviceTag) ==
592 ATOM_DEVICE_CV_SUPPORT)
593 continue;
594
595 /* IGP chips */
596 if ((rdev->flags & RADEON_IS_IGP) &&
597 (con_obj_id ==
598 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
599 uint16_t igp_offset = 0;
600 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
601
602 index =
603 GetIndexIntoMasterTable(DATA,
604 IntegratedSystemInfo);
605
606 if (atom_parse_data_header(ctx, index, &size, &frev,
607 &crev, &igp_offset)) {
608
609 if (crev >= 2) {
610 igp_obj =
611 (ATOM_INTEGRATED_SYSTEM_INFO_V2
612 *) (ctx->bios + igp_offset);
613
614 if (igp_obj) {
615 uint32_t slot_config, ct;
616
617 if (con_obj_num == 1)
618 slot_config =
619 igp_obj->
620 ulDDISlot1Config;
621 else
622 slot_config =
623 igp_obj->
624 ulDDISlot2Config;
625
626 ct = (slot_config >> 16) & 0xff;
627 connector_type =
628 object_connector_convert
629 [ct];
630 connector_object_id = ct;
631 igp_lane_info =
632 slot_config & 0xffff;
633 } else
634 continue;
635 } else
636 continue;
637 } else {
638 igp_lane_info = 0;
639 connector_type =
640 object_connector_convert[con_obj_id];
641 connector_object_id = con_obj_id;
642 }
643 } else {
644 igp_lane_info = 0;
645 connector_type =
646 object_connector_convert[con_obj_id];
647 connector_object_id = con_obj_id;
648 }
649
650 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
651 continue;
652
653 router.ddc_valid = false;
654 router.cd_valid = false;
655 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
656 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
657
658 grph_obj_id =
659 (le16_to_cpu(path->usGraphicObjIds[j]) &
660 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
661 grph_obj_num =
662 (le16_to_cpu(path->usGraphicObjIds[j]) &
663 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
664 grph_obj_type =
665 (le16_to_cpu(path->usGraphicObjIds[j]) &
666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
667
668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
669 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
670 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
671 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
672 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
673 (ctx->bios + data_offset +
674 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
675 ATOM_ENCODER_CAP_RECORD *cap_record;
676 u16 caps = 0;
677
678 while (record->ucRecordSize > 0 &&
679 record->ucRecordType > 0 &&
680 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
681 switch (record->ucRecordType) {
682 case ATOM_ENCODER_CAP_RECORD_TYPE:
683 cap_record =(ATOM_ENCODER_CAP_RECORD *)
684 record;
685 caps = le16_to_cpu(cap_record->usEncoderCap);
686 break;
687 }
688 record = (ATOM_COMMON_RECORD_HEADER *)
689 ((char *)record + record->ucRecordSize);
690 }
691 radeon_add_atom_encoder(dev,
692 encoder_obj,
693 le16_to_cpu
694 (path->
695 usDeviceTag),
696 caps);
697 }
698 }
699 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
700 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
701 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
702 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
703 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
704 (ctx->bios + data_offset +
705 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
706 ATOM_I2C_RECORD *i2c_record;
707 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
708 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
709 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
710 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
711 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
712 (ctx->bios + data_offset +
713 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
714 int enum_id;
715
716 router.router_id = router_obj_id;
717 for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
718 enum_id++) {
719 if (le16_to_cpu(path->usConnObjectId) ==
720 le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
721 break;
722 }
723
724 while (record->ucRecordSize > 0 &&
725 record->ucRecordType > 0 &&
726 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
727 switch (record->ucRecordType) {
728 case ATOM_I2C_RECORD_TYPE:
729 i2c_record =
730 (ATOM_I2C_RECORD *)
731 record;
732 i2c_config =
733 (ATOM_I2C_ID_CONFIG_ACCESS *)
734 &i2c_record->sucI2cId;
735 router.i2c_info =
736 radeon_lookup_i2c_gpio(rdev,
737 i2c_config->
738 ucAccess);
739 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
740 break;
741 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
742 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
743 record;
744 router.ddc_valid = true;
745 router.ddc_mux_type = ddc_path->ucMuxType;
746 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
747 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
748 break;
749 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
750 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
751 record;
752 router.cd_valid = true;
753 router.cd_mux_type = cd_path->ucMuxType;
754 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
755 router.cd_mux_state = cd_path->ucMuxState[enum_id];
756 break;
757 }
758 record = (ATOM_COMMON_RECORD_HEADER *)
759 ((char *)record + record->ucRecordSize);
760 }
761 }
762 }
763 }
764 }
765
766 /* look up gpio for ddc, hpd */
767 ddc_bus.valid = false;
768 hpd.hpd = RADEON_HPD_NONE;
769 if ((le16_to_cpu(path->usDeviceTag) &
770 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
771 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
772 if (le16_to_cpu(path->usConnObjectId) ==
773 le16_to_cpu(con_obj->asObjects[j].
774 usObjectID)) {
775 ATOM_COMMON_RECORD_HEADER
776 *record =
777 (ATOM_COMMON_RECORD_HEADER
778 *)
779 (ctx->bios + data_offset +
780 le16_to_cpu(con_obj->
781 asObjects[j].
782 usRecordOffset));
783 ATOM_I2C_RECORD *i2c_record;
784 ATOM_HPD_INT_RECORD *hpd_record;
785 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
786
787 while (record->ucRecordSize > 0 &&
788 record->ucRecordType > 0 &&
789 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
790 switch (record->ucRecordType) {
791 case ATOM_I2C_RECORD_TYPE:
792 i2c_record =
793 (ATOM_I2C_RECORD *)
794 record;
795 i2c_config =
796 (ATOM_I2C_ID_CONFIG_ACCESS *)
797 &i2c_record->sucI2cId;
798 ddc_bus = radeon_lookup_i2c_gpio(rdev,
799 i2c_config->
800 ucAccess);
801 break;
802 case ATOM_HPD_INT_RECORD_TYPE:
803 hpd_record =
804 (ATOM_HPD_INT_RECORD *)
805 record;
806 gpio = radeon_lookup_gpio(rdev,
807 hpd_record->ucHPDIntGPIOID);
808 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
809 hpd.plugged_state = hpd_record->ucPlugged_PinState;
810 break;
811 }
812 record =
813 (ATOM_COMMON_RECORD_HEADER
814 *) ((char *)record
815 +
816 record->
817 ucRecordSize);
818 }
819 break;
820 }
821 }
822 }
823
824 /* needed for aux chan transactions */
825 ddc_bus.hpd = hpd.hpd;
826
827 conn_id = le16_to_cpu(path->usConnObjectId);
828
829 if (!radeon_atom_apply_quirks
830 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
831 &ddc_bus, &conn_id, &hpd))
832 continue;
833
834 radeon_add_atom_connector(dev,
835 conn_id,
836 le16_to_cpu(path->
837 usDeviceTag),
838 connector_type, &ddc_bus,
839 igp_lane_info,
840 connector_object_id,
841 &hpd,
842 &router);
843
844 }
845 }
846
847 radeon_link_encoder_connector(dev);
848
849 return true;
850}
851
852static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
853 int connector_type,
854 uint16_t devices)
855{
856 struct radeon_device *rdev = dev->dev_private;
857
858 if (rdev->flags & RADEON_IS_IGP) {
859 return supported_devices_connector_object_id_convert
860 [connector_type];
861 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
862 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
863 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
864 struct radeon_mode_info *mode_info = &rdev->mode_info;
865 struct atom_context *ctx = mode_info->atom_context;
866 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
867 uint16_t size, data_offset;
868 uint8_t frev, crev;
869 ATOM_XTMDS_INFO *xtmds;
870
871 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
872 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
873
874 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
879 } else {
880 if (connector_type == DRM_MODE_CONNECTOR_DVII)
881 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
882 else
883 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
884 }
885 } else
886 return supported_devices_connector_object_id_convert
887 [connector_type];
888 } else {
889 return supported_devices_connector_object_id_convert
890 [connector_type];
891 }
892}
893
894struct bios_connector {
895 bool valid;
896 uint16_t line_mux;
897 uint16_t devices;
898 int connector_type;
899 struct radeon_i2c_bus_rec ddc_bus;
900 struct radeon_hpd hpd;
901};
902
903bool radeon_get_atom_connector_info_from_supported_devices_table(struct
904 drm_device
905 *dev)
906{
907 struct radeon_device *rdev = dev->dev_private;
908 struct radeon_mode_info *mode_info = &rdev->mode_info;
909 struct atom_context *ctx = mode_info->atom_context;
910 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
911 uint16_t size, data_offset;
912 uint8_t frev, crev;
913 uint16_t device_support;
914 uint8_t dac;
915 union atom_supported_devices *supported_devices;
916 int i, j, max_device;
917 struct bios_connector *bios_connectors;
918 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
919 struct radeon_router router;
920
921 router.ddc_valid = false;
922 router.cd_valid = false;
923
924 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
925 if (!bios_connectors)
926 return false;
927
928 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
929 &data_offset)) {
930 kfree(bios_connectors);
931 return false;
932 }
933
934 supported_devices =
935 (union atom_supported_devices *)(ctx->bios + data_offset);
936
937 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
938
939 if (frev > 1)
940 max_device = ATOM_MAX_SUPPORTED_DEVICE;
941 else
942 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
943
944 for (i = 0; i < max_device; i++) {
945 ATOM_CONNECTOR_INFO_I2C ci =
946 supported_devices->info.asConnInfo[i];
947
948 bios_connectors[i].valid = false;
949
950 if (!(device_support & (1 << i))) {
951 continue;
952 }
953
954 if (i == ATOM_DEVICE_CV_INDEX) {
955 DRM_DEBUG_KMS("Skipping Component Video\n");
956 continue;
957 }
958
959 bios_connectors[i].connector_type =
960 supported_devices_connector_convert[ci.sucConnectorInfo.
961 sbfAccess.
962 bfConnectorType];
963
964 if (bios_connectors[i].connector_type ==
965 DRM_MODE_CONNECTOR_Unknown)
966 continue;
967
968 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
969
970 bios_connectors[i].line_mux =
971 ci.sucI2cId.ucAccess;
972
973 /* give tv unique connector ids */
974 if (i == ATOM_DEVICE_TV1_INDEX) {
975 bios_connectors[i].ddc_bus.valid = false;
976 bios_connectors[i].line_mux = 50;
977 } else if (i == ATOM_DEVICE_TV2_INDEX) {
978 bios_connectors[i].ddc_bus.valid = false;
979 bios_connectors[i].line_mux = 51;
980 } else if (i == ATOM_DEVICE_CV_INDEX) {
981 bios_connectors[i].ddc_bus.valid = false;
982 bios_connectors[i].line_mux = 52;
983 } else
984 bios_connectors[i].ddc_bus =
985 radeon_lookup_i2c_gpio(rdev,
986 bios_connectors[i].line_mux);
987
988 if ((crev > 1) && (frev > 1)) {
989 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
990 switch (isb) {
991 case 0x4:
992 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
993 break;
994 case 0xa:
995 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
996 break;
997 default:
998 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
999 break;
1000 }
1001 } else {
1002 if (i == ATOM_DEVICE_DFP1_INDEX)
1003 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004 else if (i == ATOM_DEVICE_DFP2_INDEX)
1005 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1006 else
1007 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1008 }
1009
1010 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1011 * shared with a DVI port, we'll pick up the DVI connector when we
1012 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1013 */
1014 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1015 bios_connectors[i].connector_type =
1016 DRM_MODE_CONNECTOR_VGA;
1017
1018 if (!radeon_atom_apply_quirks
1019 (dev, (1 << i), &bios_connectors[i].connector_type,
1020 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1021 &bios_connectors[i].hpd))
1022 continue;
1023
1024 bios_connectors[i].valid = true;
1025 bios_connectors[i].devices = (1 << i);
1026
1027 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1028 radeon_add_atom_encoder(dev,
1029 radeon_get_encoder_enum(dev,
1030 (1 << i),
1031 dac),
1032 (1 << i),
1033 0);
1034 else
1035 radeon_add_legacy_encoder(dev,
1036 radeon_get_encoder_enum(dev,
1037 (1 << i),
1038 dac),
1039 (1 << i));
1040 }
1041
1042 /* combine shared connectors */
1043 for (i = 0; i < max_device; i++) {
1044 if (bios_connectors[i].valid) {
1045 for (j = 0; j < max_device; j++) {
1046 if (bios_connectors[j].valid && (i != j)) {
1047 if (bios_connectors[i].line_mux ==
1048 bios_connectors[j].line_mux) {
1049 /* make sure not to combine LVDS */
1050 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[i].line_mux = 53;
1052 bios_connectors[i].ddc_bus.valid = false;
1053 continue;
1054 }
1055 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1056 bios_connectors[j].line_mux = 53;
1057 bios_connectors[j].ddc_bus.valid = false;
1058 continue;
1059 }
1060 /* combine analog and digital for DVI-I */
1061 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1062 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1063 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1064 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1065 bios_connectors[i].devices |=
1066 bios_connectors[j].devices;
1067 bios_connectors[i].connector_type =
1068 DRM_MODE_CONNECTOR_DVII;
1069 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1070 bios_connectors[i].hpd =
1071 bios_connectors[j].hpd;
1072 bios_connectors[j].valid = false;
1073 }
1074 }
1075 }
1076 }
1077 }
1078 }
1079
1080 /* add the connectors */
1081 for (i = 0; i < max_device; i++) {
1082 if (bios_connectors[i].valid) {
1083 uint16_t connector_object_id =
1084 atombios_get_connector_object_id(dev,
1085 bios_connectors[i].connector_type,
1086 bios_connectors[i].devices);
1087 radeon_add_atom_connector(dev,
1088 bios_connectors[i].line_mux,
1089 bios_connectors[i].devices,
1090 bios_connectors[i].
1091 connector_type,
1092 &bios_connectors[i].ddc_bus,
1093 0,
1094 connector_object_id,
1095 &bios_connectors[i].hpd,
1096 &router);
1097 }
1098 }
1099
1100 radeon_link_encoder_connector(dev);
1101
1102 kfree(bios_connectors);
1103 return true;
1104}
1105
1106union firmware_info {
1107 ATOM_FIRMWARE_INFO info;
1108 ATOM_FIRMWARE_INFO_V1_2 info_12;
1109 ATOM_FIRMWARE_INFO_V1_3 info_13;
1110 ATOM_FIRMWARE_INFO_V1_4 info_14;
1111 ATOM_FIRMWARE_INFO_V2_1 info_21;
1112 ATOM_FIRMWARE_INFO_V2_2 info_22;
1113};
1114
1115bool radeon_atom_get_clock_info(struct drm_device *dev)
1116{
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1120 union firmware_info *firmware_info;
1121 uint8_t frev, crev;
1122 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1123 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1124 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1125 struct radeon_pll *spll = &rdev->clock.spll;
1126 struct radeon_pll *mpll = &rdev->clock.mpll;
1127 uint16_t data_offset;
1128
1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 firmware_info =
1132 (union firmware_info *)(mode_info->atom_context->bios +
1133 data_offset);
1134 /* pixel clocks */
1135 p1pll->reference_freq =
1136 le16_to_cpu(firmware_info->info.usReferenceClock);
1137 p1pll->reference_div = 0;
1138
1139 if (crev < 2)
1140 p1pll->pll_out_min =
1141 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1142 else
1143 p1pll->pll_out_min =
1144 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1145 p1pll->pll_out_max =
1146 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1147
1148 if (crev >= 4) {
1149 p1pll->lcd_pll_out_min =
1150 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1151 if (p1pll->lcd_pll_out_min == 0)
1152 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1153 p1pll->lcd_pll_out_max =
1154 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1155 if (p1pll->lcd_pll_out_max == 0)
1156 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1157 } else {
1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1159 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1160 }
1161
1162 if (p1pll->pll_out_min == 0) {
1163 if (ASIC_IS_AVIVO(rdev))
1164 p1pll->pll_out_min = 64800;
1165 else
1166 p1pll->pll_out_min = 20000;
1167 }
1168
1169 p1pll->pll_in_min =
1170 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1171 p1pll->pll_in_max =
1172 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1173
1174 *p2pll = *p1pll;
1175
1176 /* system clock */
1177 if (ASIC_IS_DCE4(rdev))
1178 spll->reference_freq =
1179 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1180 else
1181 spll->reference_freq =
1182 le16_to_cpu(firmware_info->info.usReferenceClock);
1183 spll->reference_div = 0;
1184
1185 spll->pll_out_min =
1186 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1187 spll->pll_out_max =
1188 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1189
1190 /* ??? */
1191 if (spll->pll_out_min == 0) {
1192 if (ASIC_IS_AVIVO(rdev))
1193 spll->pll_out_min = 64800;
1194 else
1195 spll->pll_out_min = 20000;
1196 }
1197
1198 spll->pll_in_min =
1199 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1200 spll->pll_in_max =
1201 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1202
1203 /* memory clock */
1204 if (ASIC_IS_DCE4(rdev))
1205 mpll->reference_freq =
1206 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1207 else
1208 mpll->reference_freq =
1209 le16_to_cpu(firmware_info->info.usReferenceClock);
1210 mpll->reference_div = 0;
1211
1212 mpll->pll_out_min =
1213 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1214 mpll->pll_out_max =
1215 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1216
1217 /* ??? */
1218 if (mpll->pll_out_min == 0) {
1219 if (ASIC_IS_AVIVO(rdev))
1220 mpll->pll_out_min = 64800;
1221 else
1222 mpll->pll_out_min = 20000;
1223 }
1224
1225 mpll->pll_in_min =
1226 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1227 mpll->pll_in_max =
1228 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1229
1230 rdev->clock.default_sclk =
1231 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1232 rdev->clock.default_mclk =
1233 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1234
1235 if (ASIC_IS_DCE4(rdev)) {
1236 rdev->clock.default_dispclk =
1237 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1238 if (rdev->clock.default_dispclk == 0) {
1239 if (ASIC_IS_DCE5(rdev))
1240 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1241 else
1242 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1243 }
1244 rdev->clock.dp_extclk =
1245 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1246 }
1247 *dcpll = *p1pll;
1248
1249 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1250 if (rdev->clock.max_pixel_clock == 0)
1251 rdev->clock.max_pixel_clock = 40000;
1252
1253 return true;
1254 }
1255
1256 return false;
1257}
1258
1259union igp_info {
1260 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1261 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1262};
1263
1264bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1265{
1266 struct radeon_mode_info *mode_info = &rdev->mode_info;
1267 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1268 union igp_info *igp_info;
1269 u8 frev, crev;
1270 u16 data_offset;
1271
1272 /* sideport is AMD only */
1273 if (rdev->family == CHIP_RS600)
1274 return false;
1275
1276 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1277 &frev, &crev, &data_offset)) {
1278 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1279 data_offset);
1280 switch (crev) {
1281 case 1:
1282 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1283 return true;
1284 break;
1285 case 2:
1286 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1287 return true;
1288 break;
1289 default:
1290 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1291 break;
1292 }
1293 }
1294 return false;
1295}
1296
1297bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1298 struct radeon_encoder_int_tmds *tmds)
1299{
1300 struct drm_device *dev = encoder->base.dev;
1301 struct radeon_device *rdev = dev->dev_private;
1302 struct radeon_mode_info *mode_info = &rdev->mode_info;
1303 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1304 uint16_t data_offset;
1305 struct _ATOM_TMDS_INFO *tmds_info;
1306 uint8_t frev, crev;
1307 uint16_t maxfreq;
1308 int i;
1309
1310 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1311 &frev, &crev, &data_offset)) {
1312 tmds_info =
1313 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1314 data_offset);
1315
1316 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1317 for (i = 0; i < 4; i++) {
1318 tmds->tmds_pll[i].freq =
1319 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1320 tmds->tmds_pll[i].value =
1321 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1322 tmds->tmds_pll[i].value |=
1323 (tmds_info->asMiscInfo[i].
1324 ucPLL_VCO_Gain & 0x3f) << 6;
1325 tmds->tmds_pll[i].value |=
1326 (tmds_info->asMiscInfo[i].
1327 ucPLL_DutyCycle & 0xf) << 12;
1328 tmds->tmds_pll[i].value |=
1329 (tmds_info->asMiscInfo[i].
1330 ucPLL_VoltageSwing & 0xf) << 16;
1331
1332 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1333 tmds->tmds_pll[i].freq,
1334 tmds->tmds_pll[i].value);
1335
1336 if (maxfreq == tmds->tmds_pll[i].freq) {
1337 tmds->tmds_pll[i].freq = 0xffffffff;
1338 break;
1339 }
1340 }
1341 return true;
1342 }
1343 return false;
1344}
1345
1346bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1347 struct radeon_atom_ss *ss,
1348 int id)
1349{
1350 struct radeon_mode_info *mode_info = &rdev->mode_info;
1351 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1352 uint16_t data_offset, size;
1353 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1354 uint8_t frev, crev;
1355 int i, num_indices;
1356
1357 memset(ss, 0, sizeof(struct radeon_atom_ss));
1358 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1359 &frev, &crev, &data_offset)) {
1360 ss_info =
1361 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1362
1363 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1364 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1365
1366 for (i = 0; i < num_indices; i++) {
1367 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1368 ss->percentage =
1369 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1370 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1371 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1372 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1373 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1374 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1375 return true;
1376 }
1377 }
1378 }
1379 return false;
1380}
1381
1382static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1383 struct radeon_atom_ss *ss,
1384 int id)
1385{
1386 struct radeon_mode_info *mode_info = &rdev->mode_info;
1387 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1388 u16 data_offset, size;
1389 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1390 u8 frev, crev;
1391 u16 percentage = 0, rate = 0;
1392
1393 /* get any igp specific overrides */
1394 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1395 &frev, &crev, &data_offset)) {
1396 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1397 (mode_info->atom_context->bios + data_offset);
1398 switch (id) {
1399 case ASIC_INTERNAL_SS_ON_TMDS:
1400 percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1401 rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1402 break;
1403 case ASIC_INTERNAL_SS_ON_HDMI:
1404 percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1405 rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1406 break;
1407 case ASIC_INTERNAL_SS_ON_LVDS:
1408 percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1409 rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1410 break;
1411 }
1412 if (percentage)
1413 ss->percentage = percentage;
1414 if (rate)
1415 ss->rate = rate;
1416 }
1417}
1418
1419union asic_ss_info {
1420 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1421 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1422 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1423};
1424
1425bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1426 struct radeon_atom_ss *ss,
1427 int id, u32 clock)
1428{
1429 struct radeon_mode_info *mode_info = &rdev->mode_info;
1430 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1431 uint16_t data_offset, size;
1432 union asic_ss_info *ss_info;
1433 uint8_t frev, crev;
1434 int i, num_indices;
1435
1436 memset(ss, 0, sizeof(struct radeon_atom_ss));
1437 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1438 &frev, &crev, &data_offset)) {
1439
1440 ss_info =
1441 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1442
1443 switch (frev) {
1444 case 1:
1445 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1446 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1447
1448 for (i = 0; i < num_indices; i++) {
1449 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1450 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1451 ss->percentage =
1452 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1453 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1454 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1455 return true;
1456 }
1457 }
1458 break;
1459 case 2:
1460 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1461 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1462 for (i = 0; i < num_indices; i++) {
1463 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1464 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1465 ss->percentage =
1466 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1467 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1468 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1469 return true;
1470 }
1471 }
1472 break;
1473 case 3:
1474 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1475 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1476 for (i = 0; i < num_indices; i++) {
1477 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1478 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1479 ss->percentage =
1480 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1481 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1482 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1483 if (rdev->flags & RADEON_IS_IGP)
1484 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1485 return true;
1486 }
1487 }
1488 break;
1489 default:
1490 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1491 break;
1492 }
1493
1494 }
1495 return false;
1496}
1497
1498union lvds_info {
1499 struct _ATOM_LVDS_INFO info;
1500 struct _ATOM_LVDS_INFO_V12 info_12;
1501};
1502
1503struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1504 radeon_encoder
1505 *encoder)
1506{
1507 struct drm_device *dev = encoder->base.dev;
1508 struct radeon_device *rdev = dev->dev_private;
1509 struct radeon_mode_info *mode_info = &rdev->mode_info;
1510 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1511 uint16_t data_offset, misc;
1512 union lvds_info *lvds_info;
1513 uint8_t frev, crev;
1514 struct radeon_encoder_atom_dig *lvds = NULL;
1515 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1516
1517 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1518 &frev, &crev, &data_offset)) {
1519 lvds_info =
1520 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1521 lvds =
1522 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1523
1524 if (!lvds)
1525 return NULL;
1526
1527 lvds->native_mode.clock =
1528 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1529 lvds->native_mode.hdisplay =
1530 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1531 lvds->native_mode.vdisplay =
1532 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1533 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1534 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1535 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1536 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1537 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1538 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1539 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1540 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1541 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1542 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1543 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1544 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1545 lvds->panel_pwr_delay =
1546 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1547 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1548
1549 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1550 if (misc & ATOM_VSYNC_POLARITY)
1551 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1552 if (misc & ATOM_HSYNC_POLARITY)
1553 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1554 if (misc & ATOM_COMPOSITESYNC)
1555 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1556 if (misc & ATOM_INTERLACE)
1557 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1558 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1559 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1560
1561 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1562 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1563
1564 /* set crtc values */
1565 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1566
1567 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1568
1569 encoder->native_mode = lvds->native_mode;
1570
1571 if (encoder_enum == 2)
1572 lvds->linkb = true;
1573 else
1574 lvds->linkb = false;
1575
1576 /* parse the lcd record table */
1577 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1578 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1579 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1580 bool bad_record = false;
1581 u8 *record;
1582
1583 if ((frev == 1) && (crev < 2))
1584 /* absolute */
1585 record = (u8 *)(mode_info->atom_context->bios +
1586 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1587 else
1588 /* relative */
1589 record = (u8 *)(mode_info->atom_context->bios +
1590 data_offset +
1591 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1592 while (*record != ATOM_RECORD_END_TYPE) {
1593 switch (*record) {
1594 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1595 record += sizeof(ATOM_PATCH_RECORD_MODE);
1596 break;
1597 case LCD_RTS_RECORD_TYPE:
1598 record += sizeof(ATOM_LCD_RTS_RECORD);
1599 break;
1600 case LCD_CAP_RECORD_TYPE:
1601 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1602 break;
1603 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1604 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1605 if (fake_edid_record->ucFakeEDIDLength) {
1606 struct edid *edid;
1607 int edid_size =
1608 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1609 edid = kmalloc(edid_size, GFP_KERNEL);
1610 if (edid) {
1611 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1612 fake_edid_record->ucFakeEDIDLength);
1613
1614 if (drm_edid_is_valid(edid)) {
1615 rdev->mode_info.bios_hardcoded_edid = edid;
1616 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1617 } else
1618 kfree(edid);
1619 }
1620 }
1621 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1622 break;
1623 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1624 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1625 lvds->native_mode.width_mm = panel_res_record->usHSize;
1626 lvds->native_mode.height_mm = panel_res_record->usVSize;
1627 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1628 break;
1629 default:
1630 DRM_ERROR("Bad LCD record %d\n", *record);
1631 bad_record = true;
1632 break;
1633 }
1634 if (bad_record)
1635 break;
1636 }
1637 }
1638 }
1639 return lvds;
1640}
1641
1642struct radeon_encoder_primary_dac *
1643radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1644{
1645 struct drm_device *dev = encoder->base.dev;
1646 struct radeon_device *rdev = dev->dev_private;
1647 struct radeon_mode_info *mode_info = &rdev->mode_info;
1648 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1649 uint16_t data_offset;
1650 struct _COMPASSIONATE_DATA *dac_info;
1651 uint8_t frev, crev;
1652 uint8_t bg, dac;
1653 struct radeon_encoder_primary_dac *p_dac = NULL;
1654
1655 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1656 &frev, &crev, &data_offset)) {
1657 dac_info = (struct _COMPASSIONATE_DATA *)
1658 (mode_info->atom_context->bios + data_offset);
1659
1660 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1661
1662 if (!p_dac)
1663 return NULL;
1664
1665 bg = dac_info->ucDAC1_BG_Adjustment;
1666 dac = dac_info->ucDAC1_DAC_Adjustment;
1667 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1668
1669 }
1670 return p_dac;
1671}
1672
1673bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1674 struct drm_display_mode *mode)
1675{
1676 struct radeon_mode_info *mode_info = &rdev->mode_info;
1677 ATOM_ANALOG_TV_INFO *tv_info;
1678 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1679 ATOM_DTD_FORMAT *dtd_timings;
1680 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1681 u8 frev, crev;
1682 u16 data_offset, misc;
1683
1684 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1685 &frev, &crev, &data_offset))
1686 return false;
1687
1688 switch (crev) {
1689 case 1:
1690 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1691 if (index >= MAX_SUPPORTED_TV_TIMING)
1692 return false;
1693
1694 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1695 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1696 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1697 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1698 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1699
1700 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1701 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1702 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1703 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1704 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1705
1706 mode->flags = 0;
1707 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1708 if (misc & ATOM_VSYNC_POLARITY)
1709 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1710 if (misc & ATOM_HSYNC_POLARITY)
1711 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1712 if (misc & ATOM_COMPOSITESYNC)
1713 mode->flags |= DRM_MODE_FLAG_CSYNC;
1714 if (misc & ATOM_INTERLACE)
1715 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1716 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1717 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1718
1719 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1720
1721 if (index == 1) {
1722 /* PAL timings appear to have wrong values for totals */
1723 mode->crtc_htotal -= 1;
1724 mode->crtc_vtotal -= 1;
1725 }
1726 break;
1727 case 2:
1728 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1729 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1730 return false;
1731
1732 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1733 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1734 le16_to_cpu(dtd_timings->usHBlanking_Time);
1735 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1736 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1737 le16_to_cpu(dtd_timings->usHSyncOffset);
1738 mode->crtc_hsync_end = mode->crtc_hsync_start +
1739 le16_to_cpu(dtd_timings->usHSyncWidth);
1740
1741 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1742 le16_to_cpu(dtd_timings->usVBlanking_Time);
1743 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1744 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1745 le16_to_cpu(dtd_timings->usVSyncOffset);
1746 mode->crtc_vsync_end = mode->crtc_vsync_start +
1747 le16_to_cpu(dtd_timings->usVSyncWidth);
1748
1749 mode->flags = 0;
1750 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1751 if (misc & ATOM_VSYNC_POLARITY)
1752 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1753 if (misc & ATOM_HSYNC_POLARITY)
1754 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1755 if (misc & ATOM_COMPOSITESYNC)
1756 mode->flags |= DRM_MODE_FLAG_CSYNC;
1757 if (misc & ATOM_INTERLACE)
1758 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1759 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1760 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1761
1762 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1763 break;
1764 }
1765 return true;
1766}
1767
1768enum radeon_tv_std
1769radeon_atombios_get_tv_info(struct radeon_device *rdev)
1770{
1771 struct radeon_mode_info *mode_info = &rdev->mode_info;
1772 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1773 uint16_t data_offset;
1774 uint8_t frev, crev;
1775 struct _ATOM_ANALOG_TV_INFO *tv_info;
1776 enum radeon_tv_std tv_std = TV_STD_NTSC;
1777
1778 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1779 &frev, &crev, &data_offset)) {
1780
1781 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1782 (mode_info->atom_context->bios + data_offset);
1783
1784 switch (tv_info->ucTV_BootUpDefaultStandard) {
1785 case ATOM_TV_NTSC:
1786 tv_std = TV_STD_NTSC;
1787 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1788 break;
1789 case ATOM_TV_NTSCJ:
1790 tv_std = TV_STD_NTSC_J;
1791 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1792 break;
1793 case ATOM_TV_PAL:
1794 tv_std = TV_STD_PAL;
1795 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1796 break;
1797 case ATOM_TV_PALM:
1798 tv_std = TV_STD_PAL_M;
1799 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1800 break;
1801 case ATOM_TV_PALN:
1802 tv_std = TV_STD_PAL_N;
1803 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1804 break;
1805 case ATOM_TV_PALCN:
1806 tv_std = TV_STD_PAL_CN;
1807 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1808 break;
1809 case ATOM_TV_PAL60:
1810 tv_std = TV_STD_PAL_60;
1811 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1812 break;
1813 case ATOM_TV_SECAM:
1814 tv_std = TV_STD_SECAM;
1815 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1816 break;
1817 default:
1818 tv_std = TV_STD_NTSC;
1819 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1820 break;
1821 }
1822 }
1823 return tv_std;
1824}
1825
1826struct radeon_encoder_tv_dac *
1827radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1828{
1829 struct drm_device *dev = encoder->base.dev;
1830 struct radeon_device *rdev = dev->dev_private;
1831 struct radeon_mode_info *mode_info = &rdev->mode_info;
1832 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1833 uint16_t data_offset;
1834 struct _COMPASSIONATE_DATA *dac_info;
1835 uint8_t frev, crev;
1836 uint8_t bg, dac;
1837 struct radeon_encoder_tv_dac *tv_dac = NULL;
1838
1839 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1840 &frev, &crev, &data_offset)) {
1841
1842 dac_info = (struct _COMPASSIONATE_DATA *)
1843 (mode_info->atom_context->bios + data_offset);
1844
1845 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1846
1847 if (!tv_dac)
1848 return NULL;
1849
1850 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1851 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1852 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1853
1854 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1855 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1856 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1857
1858 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1859 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1860 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1861
1862 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1863 }
1864 return tv_dac;
1865}
1866
1867static const char *thermal_controller_names[] = {
1868 "NONE",
1869 "lm63",
1870 "adm1032",
1871 "adm1030",
1872 "max6649",
1873 "lm64",
1874 "f75375",
1875 "asc7xxx",
1876};
1877
1878static const char *pp_lib_thermal_controller_names[] = {
1879 "NONE",
1880 "lm63",
1881 "adm1032",
1882 "adm1030",
1883 "max6649",
1884 "lm64",
1885 "f75375",
1886 "RV6xx",
1887 "RV770",
1888 "adt7473",
1889 "NONE",
1890 "External GPIO",
1891 "Evergreen",
1892 "emc2103",
1893 "Sumo",
1894 "Northern Islands",
1895};
1896
1897union power_info {
1898 struct _ATOM_POWERPLAY_INFO info;
1899 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1900 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1901 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1902 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1903 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1904};
1905
1906union pplib_clock_info {
1907 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1908 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1909 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1910 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1911};
1912
1913union pplib_power_state {
1914 struct _ATOM_PPLIB_STATE v1;
1915 struct _ATOM_PPLIB_STATE_V2 v2;
1916};
1917
1918static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1919 int state_index,
1920 u32 misc, u32 misc2)
1921{
1922 rdev->pm.power_state[state_index].misc = misc;
1923 rdev->pm.power_state[state_index].misc2 = misc2;
1924 /* order matters! */
1925 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1926 rdev->pm.power_state[state_index].type =
1927 POWER_STATE_TYPE_POWERSAVE;
1928 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1929 rdev->pm.power_state[state_index].type =
1930 POWER_STATE_TYPE_BATTERY;
1931 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1932 rdev->pm.power_state[state_index].type =
1933 POWER_STATE_TYPE_BATTERY;
1934 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1935 rdev->pm.power_state[state_index].type =
1936 POWER_STATE_TYPE_BALANCED;
1937 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1938 rdev->pm.power_state[state_index].type =
1939 POWER_STATE_TYPE_PERFORMANCE;
1940 rdev->pm.power_state[state_index].flags &=
1941 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1942 }
1943 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1944 rdev->pm.power_state[state_index].type =
1945 POWER_STATE_TYPE_BALANCED;
1946 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1947 rdev->pm.power_state[state_index].type =
1948 POWER_STATE_TYPE_DEFAULT;
1949 rdev->pm.default_power_state_index = state_index;
1950 rdev->pm.power_state[state_index].default_clock_mode =
1951 &rdev->pm.power_state[state_index].clock_info[0];
1952 } else if (state_index == 0) {
1953 rdev->pm.power_state[state_index].clock_info[0].flags |=
1954 RADEON_PM_MODE_NO_DISPLAY;
1955 }
1956}
1957
1958static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1959{
1960 struct radeon_mode_info *mode_info = &rdev->mode_info;
1961 u32 misc, misc2 = 0;
1962 int num_modes = 0, i;
1963 int state_index = 0;
1964 struct radeon_i2c_bus_rec i2c_bus;
1965 union power_info *power_info;
1966 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1967 u16 data_offset;
1968 u8 frev, crev;
1969
1970 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1971 &frev, &crev, &data_offset))
1972 return state_index;
1973 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1974
1975 /* add the i2c bus for thermal/fan chip */
1976 if (power_info->info.ucOverdriveThermalController > 0) {
1977 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1978 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1979 power_info->info.ucOverdriveControllerAddress >> 1);
1980 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1981 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1982 if (rdev->pm.i2c_bus) {
1983 struct i2c_board_info info = { };
1984 const char *name = thermal_controller_names[power_info->info.
1985 ucOverdriveThermalController];
1986 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1987 strlcpy(info.type, name, sizeof(info.type));
1988 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1989 }
1990 }
1991 num_modes = power_info->info.ucNumOfPowerModeEntries;
1992 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1993 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1994 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
1995 if (!rdev->pm.power_state)
1996 return state_index;
1997 /* last mode is usually default, array is low to high */
1998 for (i = 0; i < num_modes; i++) {
1999 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2000 switch (frev) {
2001 case 1:
2002 rdev->pm.power_state[state_index].num_clock_modes = 1;
2003 rdev->pm.power_state[state_index].clock_info[0].mclk =
2004 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2005 rdev->pm.power_state[state_index].clock_info[0].sclk =
2006 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2007 /* skip invalid modes */
2008 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2009 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2010 continue;
2011 rdev->pm.power_state[state_index].pcie_lanes =
2012 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2013 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2014 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2015 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2016 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2017 VOLTAGE_GPIO;
2018 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2019 radeon_lookup_gpio(rdev,
2020 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2021 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2022 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2023 true;
2024 else
2025 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2026 false;
2027 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2028 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2029 VOLTAGE_VDDC;
2030 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2031 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2032 }
2033 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2034 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2035 state_index++;
2036 break;
2037 case 2:
2038 rdev->pm.power_state[state_index].num_clock_modes = 1;
2039 rdev->pm.power_state[state_index].clock_info[0].mclk =
2040 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2041 rdev->pm.power_state[state_index].clock_info[0].sclk =
2042 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2043 /* skip invalid modes */
2044 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2045 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2046 continue;
2047 rdev->pm.power_state[state_index].pcie_lanes =
2048 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2049 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2050 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2051 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2052 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2053 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2054 VOLTAGE_GPIO;
2055 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2056 radeon_lookup_gpio(rdev,
2057 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2058 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2059 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2060 true;
2061 else
2062 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2063 false;
2064 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2065 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2066 VOLTAGE_VDDC;
2067 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2068 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2069 }
2070 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2071 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2072 state_index++;
2073 break;
2074 case 3:
2075 rdev->pm.power_state[state_index].num_clock_modes = 1;
2076 rdev->pm.power_state[state_index].clock_info[0].mclk =
2077 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2078 rdev->pm.power_state[state_index].clock_info[0].sclk =
2079 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2080 /* skip invalid modes */
2081 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2082 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2083 continue;
2084 rdev->pm.power_state[state_index].pcie_lanes =
2085 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2086 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2087 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2088 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2089 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2090 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2091 VOLTAGE_GPIO;
2092 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2093 radeon_lookup_gpio(rdev,
2094 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2095 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2096 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2097 true;
2098 else
2099 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2100 false;
2101 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2102 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2103 VOLTAGE_VDDC;
2104 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2105 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2106 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2107 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2108 true;
2109 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2110 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2111 }
2112 }
2113 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2114 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2115 state_index++;
2116 break;
2117 }
2118 }
2119 /* last mode is usually default */
2120 if (rdev->pm.default_power_state_index == -1) {
2121 rdev->pm.power_state[state_index - 1].type =
2122 POWER_STATE_TYPE_DEFAULT;
2123 rdev->pm.default_power_state_index = state_index - 1;
2124 rdev->pm.power_state[state_index - 1].default_clock_mode =
2125 &rdev->pm.power_state[state_index - 1].clock_info[0];
2126 rdev->pm.power_state[state_index].flags &=
2127 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2128 rdev->pm.power_state[state_index].misc = 0;
2129 rdev->pm.power_state[state_index].misc2 = 0;
2130 }
2131 return state_index;
2132}
2133
2134static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2135 ATOM_PPLIB_THERMALCONTROLLER *controller)
2136{
2137 struct radeon_i2c_bus_rec i2c_bus;
2138
2139 /* add the i2c bus for thermal/fan chip */
2140 if (controller->ucType > 0) {
2141 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2142 DRM_INFO("Internal thermal controller %s fan control\n",
2143 (controller->ucFanParameters &
2144 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2145 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2146 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2147 DRM_INFO("Internal thermal controller %s fan control\n",
2148 (controller->ucFanParameters &
2149 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2150 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2151 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2152 DRM_INFO("Internal thermal controller %s fan control\n",
2153 (controller->ucFanParameters &
2154 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2155 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2156 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2157 DRM_INFO("Internal thermal controller %s fan control\n",
2158 (controller->ucFanParameters &
2159 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2160 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2161 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2162 DRM_INFO("Internal thermal controller %s fan control\n",
2163 (controller->ucFanParameters &
2164 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2165 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2166 } else if ((controller->ucType ==
2167 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2168 (controller->ucType ==
2169 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2170 (controller->ucType ==
2171 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2172 DRM_INFO("Special thermal controller config\n");
2173 } else {
2174 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2175 pp_lib_thermal_controller_names[controller->ucType],
2176 controller->ucI2cAddress >> 1,
2177 (controller->ucFanParameters &
2178 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2179 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2180 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2181 if (rdev->pm.i2c_bus) {
2182 struct i2c_board_info info = { };
2183 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2184 info.addr = controller->ucI2cAddress >> 1;
2185 strlcpy(info.type, name, sizeof(info.type));
2186 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2187 }
2188 }
2189 }
2190}
2191
2192static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2193 u16 *vddc, u16 *vddci)
2194{
2195 struct radeon_mode_info *mode_info = &rdev->mode_info;
2196 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2197 u8 frev, crev;
2198 u16 data_offset;
2199 union firmware_info *firmware_info;
2200
2201 *vddc = 0;
2202 *vddci = 0;
2203
2204 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2205 &frev, &crev, &data_offset)) {
2206 firmware_info =
2207 (union firmware_info *)(mode_info->atom_context->bios +
2208 data_offset);
2209 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2210 if ((frev == 2) && (crev >= 2))
2211 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2212 }
2213}
2214
2215static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2216 int state_index, int mode_index,
2217 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2218{
2219 int j;
2220 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2221 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2222 u16 vddc, vddci;
2223
2224 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2225
2226 rdev->pm.power_state[state_index].misc = misc;
2227 rdev->pm.power_state[state_index].misc2 = misc2;
2228 rdev->pm.power_state[state_index].pcie_lanes =
2229 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2230 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2231 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2232 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2233 rdev->pm.power_state[state_index].type =
2234 POWER_STATE_TYPE_BATTERY;
2235 break;
2236 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2237 rdev->pm.power_state[state_index].type =
2238 POWER_STATE_TYPE_BALANCED;
2239 break;
2240 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2241 rdev->pm.power_state[state_index].type =
2242 POWER_STATE_TYPE_PERFORMANCE;
2243 break;
2244 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2245 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2246 rdev->pm.power_state[state_index].type =
2247 POWER_STATE_TYPE_PERFORMANCE;
2248 break;
2249 }
2250 rdev->pm.power_state[state_index].flags = 0;
2251 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2252 rdev->pm.power_state[state_index].flags |=
2253 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2254 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2255 rdev->pm.power_state[state_index].type =
2256 POWER_STATE_TYPE_DEFAULT;
2257 rdev->pm.default_power_state_index = state_index;
2258 rdev->pm.power_state[state_index].default_clock_mode =
2259 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2260 if (ASIC_IS_DCE5(rdev)) {
2261 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2262 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2263 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2264 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2265 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2266 } else {
2267 /* patch the table values with the default slck/mclk from firmware info */
2268 for (j = 0; j < mode_index; j++) {
2269 rdev->pm.power_state[state_index].clock_info[j].mclk =
2270 rdev->clock.default_mclk;
2271 rdev->pm.power_state[state_index].clock_info[j].sclk =
2272 rdev->clock.default_sclk;
2273 if (vddc)
2274 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2275 vddc;
2276 }
2277 }
2278 }
2279}
2280
2281static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2282 int state_index, int mode_index,
2283 union pplib_clock_info *clock_info)
2284{
2285 u32 sclk, mclk;
2286
2287 if (rdev->flags & RADEON_IS_IGP) {
2288 if (rdev->family >= CHIP_PALM) {
2289 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2290 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2291 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2292 } else {
2293 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2294 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2295 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2296 }
2297 } else if (ASIC_IS_DCE4(rdev)) {
2298 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2299 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2300 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2301 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2302 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2303 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2304 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2305 VOLTAGE_SW;
2306 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2307 le16_to_cpu(clock_info->evergreen.usVDDC);
2308 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2309 le16_to_cpu(clock_info->evergreen.usVDDCI);
2310 } else {
2311 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2312 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2313 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2314 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2315 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2316 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2317 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2318 VOLTAGE_SW;
2319 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2320 le16_to_cpu(clock_info->r600.usVDDC);
2321 }
2322
2323 /* patch up vddc if necessary */
2324 if (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage == 0xff01) {
2325 u16 vddc;
2326
2327 if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
2328 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2329 }
2330
2331 if (rdev->flags & RADEON_IS_IGP) {
2332 /* skip invalid modes */
2333 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2334 return false;
2335 } else {
2336 /* skip invalid modes */
2337 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2338 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2339 return false;
2340 }
2341 return true;
2342}
2343
2344static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2345{
2346 struct radeon_mode_info *mode_info = &rdev->mode_info;
2347 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2348 union pplib_power_state *power_state;
2349 int i, j;
2350 int state_index = 0, mode_index = 0;
2351 union pplib_clock_info *clock_info;
2352 bool valid;
2353 union power_info *power_info;
2354 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2355 u16 data_offset;
2356 u8 frev, crev;
2357
2358 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2359 &frev, &crev, &data_offset))
2360 return state_index;
2361 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2362
2363 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2364 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2365 power_info->pplib.ucNumStates, GFP_KERNEL);
2366 if (!rdev->pm.power_state)
2367 return state_index;
2368 /* first mode is usually default, followed by low to high */
2369 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2370 mode_index = 0;
2371 power_state = (union pplib_power_state *)
2372 (mode_info->atom_context->bios + data_offset +
2373 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2374 i * power_info->pplib.ucStateEntrySize);
2375 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2376 (mode_info->atom_context->bios + data_offset +
2377 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2378 (power_state->v1.ucNonClockStateIndex *
2379 power_info->pplib.ucNonClockSize));
2380 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2381 clock_info = (union pplib_clock_info *)
2382 (mode_info->atom_context->bios + data_offset +
2383 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2384 (power_state->v1.ucClockStateIndices[j] *
2385 power_info->pplib.ucClockInfoSize));
2386 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2387 state_index, mode_index,
2388 clock_info);
2389 if (valid)
2390 mode_index++;
2391 }
2392 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2393 if (mode_index) {
2394 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2395 non_clock_info);
2396 state_index++;
2397 }
2398 }
2399 /* if multiple clock modes, mark the lowest as no display */
2400 for (i = 0; i < state_index; i++) {
2401 if (rdev->pm.power_state[i].num_clock_modes > 1)
2402 rdev->pm.power_state[i].clock_info[0].flags |=
2403 RADEON_PM_MODE_NO_DISPLAY;
2404 }
2405 /* first mode is usually default */
2406 if (rdev->pm.default_power_state_index == -1) {
2407 rdev->pm.power_state[0].type =
2408 POWER_STATE_TYPE_DEFAULT;
2409 rdev->pm.default_power_state_index = 0;
2410 rdev->pm.power_state[0].default_clock_mode =
2411 &rdev->pm.power_state[0].clock_info[0];
2412 }
2413 return state_index;
2414}
2415
2416static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2417{
2418 struct radeon_mode_info *mode_info = &rdev->mode_info;
2419 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2420 union pplib_power_state *power_state;
2421 int i, j, non_clock_array_index, clock_array_index;
2422 int state_index = 0, mode_index = 0;
2423 union pplib_clock_info *clock_info;
2424 struct StateArray *state_array;
2425 struct ClockInfoArray *clock_info_array;
2426 struct NonClockInfoArray *non_clock_info_array;
2427 bool valid;
2428 union power_info *power_info;
2429 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2430 u16 data_offset;
2431 u8 frev, crev;
2432
2433 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2434 &frev, &crev, &data_offset))
2435 return state_index;
2436 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2437
2438 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2439 state_array = (struct StateArray *)
2440 (mode_info->atom_context->bios + data_offset +
2441 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2442 clock_info_array = (struct ClockInfoArray *)
2443 (mode_info->atom_context->bios + data_offset +
2444 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2445 non_clock_info_array = (struct NonClockInfoArray *)
2446 (mode_info->atom_context->bios + data_offset +
2447 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2448 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2449 state_array->ucNumEntries, GFP_KERNEL);
2450 if (!rdev->pm.power_state)
2451 return state_index;
2452 for (i = 0; i < state_array->ucNumEntries; i++) {
2453 mode_index = 0;
2454 power_state = (union pplib_power_state *)&state_array->states[i];
2455 /* XXX this might be an inagua bug... */
2456 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2457 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2458 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2459 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2460 clock_array_index = power_state->v2.clockInfoIndex[j];
2461 /* XXX this might be an inagua bug... */
2462 if (clock_array_index >= clock_info_array->ucNumEntries)
2463 continue;
2464 clock_info = (union pplib_clock_info *)
2465 &clock_info_array->clockInfo[clock_array_index];
2466 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2467 state_index, mode_index,
2468 clock_info);
2469 if (valid)
2470 mode_index++;
2471 }
2472 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2473 if (mode_index) {
2474 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2475 non_clock_info);
2476 state_index++;
2477 }
2478 }
2479 /* if multiple clock modes, mark the lowest as no display */
2480 for (i = 0; i < state_index; i++) {
2481 if (rdev->pm.power_state[i].num_clock_modes > 1)
2482 rdev->pm.power_state[i].clock_info[0].flags |=
2483 RADEON_PM_MODE_NO_DISPLAY;
2484 }
2485 /* first mode is usually default */
2486 if (rdev->pm.default_power_state_index == -1) {
2487 rdev->pm.power_state[0].type =
2488 POWER_STATE_TYPE_DEFAULT;
2489 rdev->pm.default_power_state_index = 0;
2490 rdev->pm.power_state[0].default_clock_mode =
2491 &rdev->pm.power_state[0].clock_info[0];
2492 }
2493 return state_index;
2494}
2495
2496void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2497{
2498 struct radeon_mode_info *mode_info = &rdev->mode_info;
2499 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2500 u16 data_offset;
2501 u8 frev, crev;
2502 int state_index = 0;
2503
2504 rdev->pm.default_power_state_index = -1;
2505
2506 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2507 &frev, &crev, &data_offset)) {
2508 switch (frev) {
2509 case 1:
2510 case 2:
2511 case 3:
2512 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2513 break;
2514 case 4:
2515 case 5:
2516 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2517 break;
2518 case 6:
2519 state_index = radeon_atombios_parse_power_table_6(rdev);
2520 break;
2521 default:
2522 break;
2523 }
2524 } else {
2525 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2526 if (rdev->pm.power_state) {
2527 /* add the default mode */
2528 rdev->pm.power_state[state_index].type =
2529 POWER_STATE_TYPE_DEFAULT;
2530 rdev->pm.power_state[state_index].num_clock_modes = 1;
2531 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2532 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2533 rdev->pm.power_state[state_index].default_clock_mode =
2534 &rdev->pm.power_state[state_index].clock_info[0];
2535 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2536 rdev->pm.power_state[state_index].pcie_lanes = 16;
2537 rdev->pm.default_power_state_index = state_index;
2538 rdev->pm.power_state[state_index].flags = 0;
2539 state_index++;
2540 }
2541 }
2542
2543 rdev->pm.num_power_states = state_index;
2544
2545 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2546 rdev->pm.current_clock_mode_index = 0;
2547 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2548}
2549
2550void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2551{
2552 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2553 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2554
2555 args.ucEnable = enable;
2556
2557 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2558}
2559
2560uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2561{
2562 GET_ENGINE_CLOCK_PS_ALLOCATION args;
2563 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2564
2565 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2566 return le32_to_cpu(args.ulReturnEngineClock);
2567}
2568
2569uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2570{
2571 GET_MEMORY_CLOCK_PS_ALLOCATION args;
2572 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2573
2574 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2575 return le32_to_cpu(args.ulReturnMemoryClock);
2576}
2577
2578void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2579 uint32_t eng_clock)
2580{
2581 SET_ENGINE_CLOCK_PS_ALLOCATION args;
2582 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2583
2584 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
2585
2586 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2587}
2588
2589void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2590 uint32_t mem_clock)
2591{
2592 SET_MEMORY_CLOCK_PS_ALLOCATION args;
2593 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2594
2595 if (rdev->flags & RADEON_IS_IGP)
2596 return;
2597
2598 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
2599
2600 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2601}
2602
2603union set_voltage {
2604 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2605 struct _SET_VOLTAGE_PARAMETERS v1;
2606 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2607};
2608
2609void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2610{
2611 union set_voltage args;
2612 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2613 u8 frev, crev, volt_index = voltage_level;
2614
2615 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2616 return;
2617
2618 /* 0xff01 is a flag rather then an actual voltage */
2619 if (voltage_level == 0xff01)
2620 return;
2621
2622 switch (crev) {
2623 case 1:
2624 args.v1.ucVoltageType = voltage_type;
2625 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2626 args.v1.ucVoltageIndex = volt_index;
2627 break;
2628 case 2:
2629 args.v2.ucVoltageType = voltage_type;
2630 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2631 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2632 break;
2633 default:
2634 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2635 return;
2636 }
2637
2638 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2639}
2640
2641int radeon_atom_get_max_vddc(struct radeon_device *rdev,
2642 u16 *voltage)
2643{
2644 union set_voltage args;
2645 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2646 u8 frev, crev;
2647
2648 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2649 return -EINVAL;
2650
2651 switch (crev) {
2652 case 1:
2653 return -EINVAL;
2654 case 2:
2655 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2656 args.v2.ucVoltageMode = 0;
2657 args.v2.usVoltageLevel = 0;
2658
2659 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2660
2661 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2662 break;
2663 default:
2664 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2665 return -EINVAL;
2666 }
2667
2668 return 0;
2669}
2670
2671void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2672{
2673 struct radeon_device *rdev = dev->dev_private;
2674 uint32_t bios_2_scratch, bios_6_scratch;
2675
2676 if (rdev->family >= CHIP_R600) {
2677 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2678 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2679 } else {
2680 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2681 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2682 }
2683
2684 /* let the bios control the backlight */
2685 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2686
2687 /* tell the bios not to handle mode switching */
2688 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2689
2690 if (rdev->family >= CHIP_R600) {
2691 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2692 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2693 } else {
2694 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2695 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2696 }
2697
2698}
2699
2700void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2701{
2702 uint32_t scratch_reg;
2703 int i;
2704
2705 if (rdev->family >= CHIP_R600)
2706 scratch_reg = R600_BIOS_0_SCRATCH;
2707 else
2708 scratch_reg = RADEON_BIOS_0_SCRATCH;
2709
2710 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2711 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2712}
2713
2714void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2715{
2716 uint32_t scratch_reg;
2717 int i;
2718
2719 if (rdev->family >= CHIP_R600)
2720 scratch_reg = R600_BIOS_0_SCRATCH;
2721 else
2722 scratch_reg = RADEON_BIOS_0_SCRATCH;
2723
2724 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2725 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2726}
2727
2728void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2729{
2730 struct drm_device *dev = encoder->dev;
2731 struct radeon_device *rdev = dev->dev_private;
2732 uint32_t bios_6_scratch;
2733
2734 if (rdev->family >= CHIP_R600)
2735 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2736 else
2737 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2738
2739 if (lock) {
2740 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2741 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2742 } else {
2743 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2744 bios_6_scratch |= ATOM_S6_ACC_MODE;
2745 }
2746
2747 if (rdev->family >= CHIP_R600)
2748 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2749 else
2750 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2751}
2752
2753/* at some point we may want to break this out into individual functions */
2754void
2755radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2756 struct drm_encoder *encoder,
2757 bool connected)
2758{
2759 struct drm_device *dev = connector->dev;
2760 struct radeon_device *rdev = dev->dev_private;
2761 struct radeon_connector *radeon_connector =
2762 to_radeon_connector(connector);
2763 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2764 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2765
2766 if (rdev->family >= CHIP_R600) {
2767 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2768 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2769 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2770 } else {
2771 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2772 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2773 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2774 }
2775
2776 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2777 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2778 if (connected) {
2779 DRM_DEBUG_KMS("TV1 connected\n");
2780 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2781 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2782 } else {
2783 DRM_DEBUG_KMS("TV1 disconnected\n");
2784 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2785 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2786 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2787 }
2788 }
2789 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2790 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2791 if (connected) {
2792 DRM_DEBUG_KMS("CV connected\n");
2793 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2794 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2795 } else {
2796 DRM_DEBUG_KMS("CV disconnected\n");
2797 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2798 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2799 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2800 }
2801 }
2802 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2803 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2804 if (connected) {
2805 DRM_DEBUG_KMS("LCD1 connected\n");
2806 bios_0_scratch |= ATOM_S0_LCD1;
2807 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2808 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2809 } else {
2810 DRM_DEBUG_KMS("LCD1 disconnected\n");
2811 bios_0_scratch &= ~ATOM_S0_LCD1;
2812 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2813 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2814 }
2815 }
2816 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2817 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2818 if (connected) {
2819 DRM_DEBUG_KMS("CRT1 connected\n");
2820 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2821 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2822 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2823 } else {
2824 DRM_DEBUG_KMS("CRT1 disconnected\n");
2825 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2826 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2827 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2828 }
2829 }
2830 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2831 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2832 if (connected) {
2833 DRM_DEBUG_KMS("CRT2 connected\n");
2834 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2835 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2836 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2837 } else {
2838 DRM_DEBUG_KMS("CRT2 disconnected\n");
2839 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2840 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2841 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2842 }
2843 }
2844 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2845 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2846 if (connected) {
2847 DRM_DEBUG_KMS("DFP1 connected\n");
2848 bios_0_scratch |= ATOM_S0_DFP1;
2849 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2850 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2851 } else {
2852 DRM_DEBUG_KMS("DFP1 disconnected\n");
2853 bios_0_scratch &= ~ATOM_S0_DFP1;
2854 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2855 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2856 }
2857 }
2858 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2859 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2860 if (connected) {
2861 DRM_DEBUG_KMS("DFP2 connected\n");
2862 bios_0_scratch |= ATOM_S0_DFP2;
2863 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2864 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2865 } else {
2866 DRM_DEBUG_KMS("DFP2 disconnected\n");
2867 bios_0_scratch &= ~ATOM_S0_DFP2;
2868 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2869 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2870 }
2871 }
2872 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2873 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2874 if (connected) {
2875 DRM_DEBUG_KMS("DFP3 connected\n");
2876 bios_0_scratch |= ATOM_S0_DFP3;
2877 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2878 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2879 } else {
2880 DRM_DEBUG_KMS("DFP3 disconnected\n");
2881 bios_0_scratch &= ~ATOM_S0_DFP3;
2882 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2883 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2884 }
2885 }
2886 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2887 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2888 if (connected) {
2889 DRM_DEBUG_KMS("DFP4 connected\n");
2890 bios_0_scratch |= ATOM_S0_DFP4;
2891 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2892 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2893 } else {
2894 DRM_DEBUG_KMS("DFP4 disconnected\n");
2895 bios_0_scratch &= ~ATOM_S0_DFP4;
2896 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2897 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2898 }
2899 }
2900 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2901 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2902 if (connected) {
2903 DRM_DEBUG_KMS("DFP5 connected\n");
2904 bios_0_scratch |= ATOM_S0_DFP5;
2905 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2906 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2907 } else {
2908 DRM_DEBUG_KMS("DFP5 disconnected\n");
2909 bios_0_scratch &= ~ATOM_S0_DFP5;
2910 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2911 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2912 }
2913 }
2914
2915 if (rdev->family >= CHIP_R600) {
2916 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2917 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2918 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2919 } else {
2920 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2921 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2922 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2923 }
2924}
2925
2926void
2927radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2928{
2929 struct drm_device *dev = encoder->dev;
2930 struct radeon_device *rdev = dev->dev_private;
2931 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2932 uint32_t bios_3_scratch;
2933
2934 if (rdev->family >= CHIP_R600)
2935 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2936 else
2937 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2938
2939 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2940 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2941 bios_3_scratch |= (crtc << 18);
2942 }
2943 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2944 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2945 bios_3_scratch |= (crtc << 24);
2946 }
2947 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2948 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2949 bios_3_scratch |= (crtc << 16);
2950 }
2951 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2952 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2953 bios_3_scratch |= (crtc << 20);
2954 }
2955 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2956 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2957 bios_3_scratch |= (crtc << 17);
2958 }
2959 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2960 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2961 bios_3_scratch |= (crtc << 19);
2962 }
2963 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2964 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2965 bios_3_scratch |= (crtc << 23);
2966 }
2967 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2968 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2969 bios_3_scratch |= (crtc << 25);
2970 }
2971
2972 if (rdev->family >= CHIP_R600)
2973 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2974 else
2975 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2976}
2977
2978void
2979radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2980{
2981 struct drm_device *dev = encoder->dev;
2982 struct radeon_device *rdev = dev->dev_private;
2983 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2984 uint32_t bios_2_scratch;
2985
2986 if (rdev->family >= CHIP_R600)
2987 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2988 else
2989 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2990
2991 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2992 if (on)
2993 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2994 else
2995 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2996 }
2997 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2998 if (on)
2999 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3000 else
3001 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3002 }
3003 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3004 if (on)
3005 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3006 else
3007 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3008 }
3009 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3010 if (on)
3011 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3012 else
3013 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3014 }
3015 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3016 if (on)
3017 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3018 else
3019 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3020 }
3021 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3022 if (on)
3023 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3024 else
3025 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3026 }
3027 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3028 if (on)
3029 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3030 else
3031 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3032 }
3033 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3034 if (on)
3035 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3036 else
3037 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3038 }
3039 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3040 if (on)
3041 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3042 else
3043 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3044 }
3045 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3046 if (on)
3047 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3048 else
3049 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3050 }
3051
3052 if (rdev->family >= CHIP_R600)
3053 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3054 else
3055 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3056}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
28#include "radeon.h"
29
30#include "atom.h"
31#include "atom-bits.h"
32#include "radeon_asic.h"
33
34extern void
35radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
36 uint32_t supported_device, u16 caps);
37
38/* from radeon_legacy_encoder.c */
39extern void
40radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
41 uint32_t supported_device);
42
43union atom_supported_devices {
44 struct _ATOM_SUPPORTED_DEVICES_INFO info;
45 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
46 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
47};
48
49static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
50 ATOM_GPIO_I2C_ASSIGMENT *gpio,
51 u8 index)
52{
53 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
54 if ((rdev->family == CHIP_R420) ||
55 (rdev->family == CHIP_R423) ||
56 (rdev->family == CHIP_RV410)) {
57 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
58 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
59 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
60 gpio->ucClkMaskShift = 0x19;
61 gpio->ucDataMaskShift = 0x18;
62 }
63 }
64
65 /* some evergreen boards have bad data for this entry */
66 if (ASIC_IS_DCE4(rdev)) {
67 if ((index == 7) &&
68 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
69 (gpio->sucI2cId.ucAccess == 0)) {
70 gpio->sucI2cId.ucAccess = 0x97;
71 gpio->ucDataMaskShift = 8;
72 gpio->ucDataEnShift = 8;
73 gpio->ucDataY_Shift = 8;
74 gpio->ucDataA_Shift = 8;
75 }
76 }
77
78 /* some DCE3 boards have bad data for this entry */
79 if (ASIC_IS_DCE3(rdev)) {
80 if ((index == 4) &&
81 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
82 (gpio->sucI2cId.ucAccess == 0x94))
83 gpio->sucI2cId.ucAccess = 0x14;
84 }
85}
86
87static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
88{
89 struct radeon_i2c_bus_rec i2c;
90
91 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
92
93 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
94 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
95 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
96 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
97 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
98 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
99 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
100 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
101 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
102 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
103 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
104 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
105 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
106 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
107 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
108 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
109
110 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
111 i2c.hw_capable = true;
112 else
113 i2c.hw_capable = false;
114
115 if (gpio->sucI2cId.ucAccess == 0xa0)
116 i2c.mm_i2c = true;
117 else
118 i2c.mm_i2c = false;
119
120 i2c.i2c_id = gpio->sucI2cId.ucAccess;
121
122 if (i2c.mask_clk_reg)
123 i2c.valid = true;
124 else
125 i2c.valid = false;
126
127 return i2c;
128}
129
130static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
131 uint8_t id)
132{
133 struct atom_context *ctx = rdev->mode_info.atom_context;
134 ATOM_GPIO_I2C_ASSIGMENT *gpio;
135 struct radeon_i2c_bus_rec i2c;
136 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
137 struct _ATOM_GPIO_I2C_INFO *i2c_info;
138 uint16_t data_offset, size;
139 int i, num_indices;
140
141 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
142 i2c.valid = false;
143
144 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
145 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
146
147 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
148 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
149
150 gpio = &i2c_info->asGPIO_Info[0];
151 for (i = 0; i < num_indices; i++) {
152
153 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
154
155 if (gpio->sucI2cId.ucAccess == id) {
156 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
157 break;
158 }
159 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
160 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
161 }
162 }
163
164 return i2c;
165}
166
167void radeon_atombios_i2c_init(struct radeon_device *rdev)
168{
169 struct atom_context *ctx = rdev->mode_info.atom_context;
170 ATOM_GPIO_I2C_ASSIGMENT *gpio;
171 struct radeon_i2c_bus_rec i2c;
172 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
173 struct _ATOM_GPIO_I2C_INFO *i2c_info;
174 uint16_t data_offset, size;
175 int i, num_indices;
176 char stmp[32];
177
178 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
179 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
180
181 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
182 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
183
184 gpio = &i2c_info->asGPIO_Info[0];
185 for (i = 0; i < num_indices; i++) {
186 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
187
188 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
189
190 if (i2c.valid) {
191 sprintf(stmp, "0x%x", i2c.i2c_id);
192 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
193 }
194 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
195 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
196 }
197 }
198}
199
200struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
201 u8 id)
202{
203 struct atom_context *ctx = rdev->mode_info.atom_context;
204 struct radeon_gpio_rec gpio;
205 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
206 struct _ATOM_GPIO_PIN_LUT *gpio_info;
207 ATOM_GPIO_PIN_ASSIGNMENT *pin;
208 u16 data_offset, size;
209 int i, num_indices;
210
211 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
212 gpio.valid = false;
213
214 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
215 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
216
217 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
218 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
219
220 pin = gpio_info->asGPIO_Pin;
221 for (i = 0; i < num_indices; i++) {
222 if (id == pin->ucGPIO_ID) {
223 gpio.id = pin->ucGPIO_ID;
224 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
225 gpio.shift = pin->ucGpioPinBitShift;
226 gpio.mask = (1 << pin->ucGpioPinBitShift);
227 gpio.valid = true;
228 break;
229 }
230 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
231 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
232 }
233 }
234
235 return gpio;
236}
237
238static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
239 struct radeon_gpio_rec *gpio)
240{
241 struct radeon_hpd hpd;
242 u32 reg;
243
244 memset(&hpd, 0, sizeof(struct radeon_hpd));
245
246 if (ASIC_IS_DCE6(rdev))
247 reg = SI_DC_GPIO_HPD_A;
248 else if (ASIC_IS_DCE4(rdev))
249 reg = EVERGREEN_DC_GPIO_HPD_A;
250 else
251 reg = AVIVO_DC_GPIO_HPD_A;
252
253 hpd.gpio = *gpio;
254 if (gpio->reg == reg) {
255 switch(gpio->mask) {
256 case (1 << 0):
257 hpd.hpd = RADEON_HPD_1;
258 break;
259 case (1 << 8):
260 hpd.hpd = RADEON_HPD_2;
261 break;
262 case (1 << 16):
263 hpd.hpd = RADEON_HPD_3;
264 break;
265 case (1 << 24):
266 hpd.hpd = RADEON_HPD_4;
267 break;
268 case (1 << 26):
269 hpd.hpd = RADEON_HPD_5;
270 break;
271 case (1 << 28):
272 hpd.hpd = RADEON_HPD_6;
273 break;
274 default:
275 hpd.hpd = RADEON_HPD_NONE;
276 break;
277 }
278 } else
279 hpd.hpd = RADEON_HPD_NONE;
280 return hpd;
281}
282
283static bool radeon_atom_apply_quirks(struct drm_device *dev,
284 uint32_t supported_device,
285 int *connector_type,
286 struct radeon_i2c_bus_rec *i2c_bus,
287 uint16_t *line_mux,
288 struct radeon_hpd *hpd)
289{
290
291 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
292 if ((dev->pdev->device == 0x791e) &&
293 (dev->pdev->subsystem_vendor == 0x1043) &&
294 (dev->pdev->subsystem_device == 0x826d)) {
295 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
296 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
297 *connector_type = DRM_MODE_CONNECTOR_DVID;
298 }
299
300 /* Asrock RS600 board lists the DVI port as HDMI */
301 if ((dev->pdev->device == 0x7941) &&
302 (dev->pdev->subsystem_vendor == 0x1849) &&
303 (dev->pdev->subsystem_device == 0x7941)) {
304 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
305 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
306 *connector_type = DRM_MODE_CONNECTOR_DVID;
307 }
308
309 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
310 if ((dev->pdev->device == 0x796e) &&
311 (dev->pdev->subsystem_vendor == 0x1462) &&
312 (dev->pdev->subsystem_device == 0x7302)) {
313 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
314 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
315 return false;
316 }
317
318 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
319 if ((dev->pdev->device == 0x7941) &&
320 (dev->pdev->subsystem_vendor == 0x147b) &&
321 (dev->pdev->subsystem_device == 0x2412)) {
322 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
323 return false;
324 }
325
326 /* Falcon NW laptop lists vga ddc line for LVDS */
327 if ((dev->pdev->device == 0x5653) &&
328 (dev->pdev->subsystem_vendor == 0x1462) &&
329 (dev->pdev->subsystem_device == 0x0291)) {
330 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
331 i2c_bus->valid = false;
332 *line_mux = 53;
333 }
334 }
335
336 /* HIS X1300 is DVI+VGA, not DVI+DVI */
337 if ((dev->pdev->device == 0x7146) &&
338 (dev->pdev->subsystem_vendor == 0x17af) &&
339 (dev->pdev->subsystem_device == 0x2058)) {
340 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
341 return false;
342 }
343
344 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
345 if ((dev->pdev->device == 0x7142) &&
346 (dev->pdev->subsystem_vendor == 0x1458) &&
347 (dev->pdev->subsystem_device == 0x2134)) {
348 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
349 return false;
350 }
351
352
353 /* Funky macbooks */
354 if ((dev->pdev->device == 0x71C5) &&
355 (dev->pdev->subsystem_vendor == 0x106b) &&
356 (dev->pdev->subsystem_device == 0x0080)) {
357 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
358 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
359 return false;
360 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
361 *line_mux = 0x90;
362 }
363
364 /* mac rv630, rv730, others */
365 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
366 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
367 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
368 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
369 }
370
371 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
372 if ((dev->pdev->device == 0x9598) &&
373 (dev->pdev->subsystem_vendor == 0x1043) &&
374 (dev->pdev->subsystem_device == 0x01da)) {
375 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
376 *connector_type = DRM_MODE_CONNECTOR_DVII;
377 }
378 }
379
380 /* ASUS HD 3600 board lists the DVI port as HDMI */
381 if ((dev->pdev->device == 0x9598) &&
382 (dev->pdev->subsystem_vendor == 0x1043) &&
383 (dev->pdev->subsystem_device == 0x01e4)) {
384 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
385 *connector_type = DRM_MODE_CONNECTOR_DVII;
386 }
387 }
388
389 /* ASUS HD 3450 board lists the DVI port as HDMI */
390 if ((dev->pdev->device == 0x95C5) &&
391 (dev->pdev->subsystem_vendor == 0x1043) &&
392 (dev->pdev->subsystem_device == 0x01e2)) {
393 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
394 *connector_type = DRM_MODE_CONNECTOR_DVII;
395 }
396 }
397
398 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
399 * HDMI + VGA reporting as HDMI
400 */
401 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
402 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
403 *connector_type = DRM_MODE_CONNECTOR_VGA;
404 *line_mux = 0;
405 }
406 }
407
408 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
409 * on the laptop and a DVI port on the docking station and
410 * both share the same encoder, hpd pin, and ddc line.
411 * So while the bios table is technically correct,
412 * we drop the DVI port here since xrandr has no concept of
413 * encoders and will try and drive both connectors
414 * with different crtcs which isn't possible on the hardware
415 * side and leaves no crtcs for LVDS or VGA.
416 */
417 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) &&
418 (dev->pdev->subsystem_vendor == 0x1025) &&
419 (dev->pdev->subsystem_device == 0x013c)) {
420 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
421 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
422 /* actually it's a DVI-D port not DVI-I */
423 *connector_type = DRM_MODE_CONNECTOR_DVID;
424 return false;
425 }
426 }
427
428 /* XFX Pine Group device rv730 reports no VGA DDC lines
429 * even though they are wired up to record 0x93
430 */
431 if ((dev->pdev->device == 0x9498) &&
432 (dev->pdev->subsystem_vendor == 0x1682) &&
433 (dev->pdev->subsystem_device == 0x2452) &&
434 (i2c_bus->valid == false) &&
435 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
436 struct radeon_device *rdev = dev->dev_private;
437 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
438 }
439
440 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
441 if (((dev->pdev->device == 0x9802) ||
442 (dev->pdev->device == 0x9805) ||
443 (dev->pdev->device == 0x9806)) &&
444 (dev->pdev->subsystem_vendor == 0x1734) &&
445 (dev->pdev->subsystem_device == 0x11bd)) {
446 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
447 *connector_type = DRM_MODE_CONNECTOR_DVII;
448 *line_mux = 0x3103;
449 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
450 *connector_type = DRM_MODE_CONNECTOR_DVII;
451 }
452 }
453
454 return true;
455}
456
457static const int supported_devices_connector_convert[] = {
458 DRM_MODE_CONNECTOR_Unknown,
459 DRM_MODE_CONNECTOR_VGA,
460 DRM_MODE_CONNECTOR_DVII,
461 DRM_MODE_CONNECTOR_DVID,
462 DRM_MODE_CONNECTOR_DVIA,
463 DRM_MODE_CONNECTOR_SVIDEO,
464 DRM_MODE_CONNECTOR_Composite,
465 DRM_MODE_CONNECTOR_LVDS,
466 DRM_MODE_CONNECTOR_Unknown,
467 DRM_MODE_CONNECTOR_Unknown,
468 DRM_MODE_CONNECTOR_HDMIA,
469 DRM_MODE_CONNECTOR_HDMIB,
470 DRM_MODE_CONNECTOR_Unknown,
471 DRM_MODE_CONNECTOR_Unknown,
472 DRM_MODE_CONNECTOR_9PinDIN,
473 DRM_MODE_CONNECTOR_DisplayPort
474};
475
476static const uint16_t supported_devices_connector_object_id_convert[] = {
477 CONNECTOR_OBJECT_ID_NONE,
478 CONNECTOR_OBJECT_ID_VGA,
479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
480 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
481 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
482 CONNECTOR_OBJECT_ID_COMPOSITE,
483 CONNECTOR_OBJECT_ID_SVIDEO,
484 CONNECTOR_OBJECT_ID_LVDS,
485 CONNECTOR_OBJECT_ID_9PIN_DIN,
486 CONNECTOR_OBJECT_ID_9PIN_DIN,
487 CONNECTOR_OBJECT_ID_DISPLAYPORT,
488 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
489 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
490 CONNECTOR_OBJECT_ID_SVIDEO
491};
492
493static const int object_connector_convert[] = {
494 DRM_MODE_CONNECTOR_Unknown,
495 DRM_MODE_CONNECTOR_DVII,
496 DRM_MODE_CONNECTOR_DVII,
497 DRM_MODE_CONNECTOR_DVID,
498 DRM_MODE_CONNECTOR_DVID,
499 DRM_MODE_CONNECTOR_VGA,
500 DRM_MODE_CONNECTOR_Composite,
501 DRM_MODE_CONNECTOR_SVIDEO,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_9PinDIN,
505 DRM_MODE_CONNECTOR_Unknown,
506 DRM_MODE_CONNECTOR_HDMIA,
507 DRM_MODE_CONNECTOR_HDMIB,
508 DRM_MODE_CONNECTOR_LVDS,
509 DRM_MODE_CONNECTOR_9PinDIN,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_Unknown,
513 DRM_MODE_CONNECTOR_DisplayPort,
514 DRM_MODE_CONNECTOR_eDP,
515 DRM_MODE_CONNECTOR_Unknown
516};
517
518bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
519{
520 struct radeon_device *rdev = dev->dev_private;
521 struct radeon_mode_info *mode_info = &rdev->mode_info;
522 struct atom_context *ctx = mode_info->atom_context;
523 int index = GetIndexIntoMasterTable(DATA, Object_Header);
524 u16 size, data_offset;
525 u8 frev, crev;
526 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
527 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
528 ATOM_OBJECT_TABLE *router_obj;
529 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
530 ATOM_OBJECT_HEADER *obj_header;
531 int i, j, k, path_size, device_support;
532 int connector_type;
533 u16 igp_lane_info, conn_id, connector_object_id;
534 struct radeon_i2c_bus_rec ddc_bus;
535 struct radeon_router router;
536 struct radeon_gpio_rec gpio;
537 struct radeon_hpd hpd;
538
539 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
540 return false;
541
542 if (crev < 2)
543 return false;
544
545 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
546 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
547 (ctx->bios + data_offset +
548 le16_to_cpu(obj_header->usDisplayPathTableOffset));
549 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
550 (ctx->bios + data_offset +
551 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
552 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
553 (ctx->bios + data_offset +
554 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
555 router_obj = (ATOM_OBJECT_TABLE *)
556 (ctx->bios + data_offset +
557 le16_to_cpu(obj_header->usRouterObjectTableOffset));
558 device_support = le16_to_cpu(obj_header->usDeviceSupport);
559
560 path_size = 0;
561 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
562 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
563 ATOM_DISPLAY_OBJECT_PATH *path;
564 addr += path_size;
565 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
566 path_size += le16_to_cpu(path->usSize);
567
568 if (device_support & le16_to_cpu(path->usDeviceTag)) {
569 uint8_t con_obj_id, con_obj_num, con_obj_type;
570
571 con_obj_id =
572 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
573 >> OBJECT_ID_SHIFT;
574 con_obj_num =
575 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
576 >> ENUM_ID_SHIFT;
577 con_obj_type =
578 (le16_to_cpu(path->usConnObjectId) &
579 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
580
581 /* TODO CV support */
582 if (le16_to_cpu(path->usDeviceTag) ==
583 ATOM_DEVICE_CV_SUPPORT)
584 continue;
585
586 /* IGP chips */
587 if ((rdev->flags & RADEON_IS_IGP) &&
588 (con_obj_id ==
589 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
590 uint16_t igp_offset = 0;
591 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
592
593 index =
594 GetIndexIntoMasterTable(DATA,
595 IntegratedSystemInfo);
596
597 if (atom_parse_data_header(ctx, index, &size, &frev,
598 &crev, &igp_offset)) {
599
600 if (crev >= 2) {
601 igp_obj =
602 (ATOM_INTEGRATED_SYSTEM_INFO_V2
603 *) (ctx->bios + igp_offset);
604
605 if (igp_obj) {
606 uint32_t slot_config, ct;
607
608 if (con_obj_num == 1)
609 slot_config =
610 igp_obj->
611 ulDDISlot1Config;
612 else
613 slot_config =
614 igp_obj->
615 ulDDISlot2Config;
616
617 ct = (slot_config >> 16) & 0xff;
618 connector_type =
619 object_connector_convert
620 [ct];
621 connector_object_id = ct;
622 igp_lane_info =
623 slot_config & 0xffff;
624 } else
625 continue;
626 } else
627 continue;
628 } else {
629 igp_lane_info = 0;
630 connector_type =
631 object_connector_convert[con_obj_id];
632 connector_object_id = con_obj_id;
633 }
634 } else {
635 igp_lane_info = 0;
636 connector_type =
637 object_connector_convert[con_obj_id];
638 connector_object_id = con_obj_id;
639 }
640
641 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
642 continue;
643
644 router.ddc_valid = false;
645 router.cd_valid = false;
646 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
647 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
648
649 grph_obj_id =
650 (le16_to_cpu(path->usGraphicObjIds[j]) &
651 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
652 grph_obj_num =
653 (le16_to_cpu(path->usGraphicObjIds[j]) &
654 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
655 grph_obj_type =
656 (le16_to_cpu(path->usGraphicObjIds[j]) &
657 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
658
659 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
660 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
661 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
662 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
663 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
664 (ctx->bios + data_offset +
665 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
666 ATOM_ENCODER_CAP_RECORD *cap_record;
667 u16 caps = 0;
668
669 while (record->ucRecordSize > 0 &&
670 record->ucRecordType > 0 &&
671 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
672 switch (record->ucRecordType) {
673 case ATOM_ENCODER_CAP_RECORD_TYPE:
674 cap_record =(ATOM_ENCODER_CAP_RECORD *)
675 record;
676 caps = le16_to_cpu(cap_record->usEncoderCap);
677 break;
678 }
679 record = (ATOM_COMMON_RECORD_HEADER *)
680 ((char *)record + record->ucRecordSize);
681 }
682 radeon_add_atom_encoder(dev,
683 encoder_obj,
684 le16_to_cpu
685 (path->
686 usDeviceTag),
687 caps);
688 }
689 }
690 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
691 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
692 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
693 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
694 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
695 (ctx->bios + data_offset +
696 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
697 ATOM_I2C_RECORD *i2c_record;
698 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
699 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
700 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
701 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
702 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
703 (ctx->bios + data_offset +
704 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
705 u8 *num_dst_objs = (u8 *)
706 ((u8 *)router_src_dst_table + 1 +
707 (router_src_dst_table->ucNumberOfSrc * 2));
708 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
709 int enum_id;
710
711 router.router_id = router_obj_id;
712 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
713 if (le16_to_cpu(path->usConnObjectId) ==
714 le16_to_cpu(dst_objs[enum_id]))
715 break;
716 }
717
718 while (record->ucRecordSize > 0 &&
719 record->ucRecordType > 0 &&
720 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
721 switch (record->ucRecordType) {
722 case ATOM_I2C_RECORD_TYPE:
723 i2c_record =
724 (ATOM_I2C_RECORD *)
725 record;
726 i2c_config =
727 (ATOM_I2C_ID_CONFIG_ACCESS *)
728 &i2c_record->sucI2cId;
729 router.i2c_info =
730 radeon_lookup_i2c_gpio(rdev,
731 i2c_config->
732 ucAccess);
733 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
734 break;
735 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
736 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
737 record;
738 router.ddc_valid = true;
739 router.ddc_mux_type = ddc_path->ucMuxType;
740 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
741 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
742 break;
743 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
744 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
745 record;
746 router.cd_valid = true;
747 router.cd_mux_type = cd_path->ucMuxType;
748 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
749 router.cd_mux_state = cd_path->ucMuxState[enum_id];
750 break;
751 }
752 record = (ATOM_COMMON_RECORD_HEADER *)
753 ((char *)record + record->ucRecordSize);
754 }
755 }
756 }
757 }
758 }
759
760 /* look up gpio for ddc, hpd */
761 ddc_bus.valid = false;
762 hpd.hpd = RADEON_HPD_NONE;
763 if ((le16_to_cpu(path->usDeviceTag) &
764 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
765 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
766 if (le16_to_cpu(path->usConnObjectId) ==
767 le16_to_cpu(con_obj->asObjects[j].
768 usObjectID)) {
769 ATOM_COMMON_RECORD_HEADER
770 *record =
771 (ATOM_COMMON_RECORD_HEADER
772 *)
773 (ctx->bios + data_offset +
774 le16_to_cpu(con_obj->
775 asObjects[j].
776 usRecordOffset));
777 ATOM_I2C_RECORD *i2c_record;
778 ATOM_HPD_INT_RECORD *hpd_record;
779 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
780
781 while (record->ucRecordSize > 0 &&
782 record->ucRecordType > 0 &&
783 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
784 switch (record->ucRecordType) {
785 case ATOM_I2C_RECORD_TYPE:
786 i2c_record =
787 (ATOM_I2C_RECORD *)
788 record;
789 i2c_config =
790 (ATOM_I2C_ID_CONFIG_ACCESS *)
791 &i2c_record->sucI2cId;
792 ddc_bus = radeon_lookup_i2c_gpio(rdev,
793 i2c_config->
794 ucAccess);
795 break;
796 case ATOM_HPD_INT_RECORD_TYPE:
797 hpd_record =
798 (ATOM_HPD_INT_RECORD *)
799 record;
800 gpio = radeon_atombios_lookup_gpio(rdev,
801 hpd_record->ucHPDIntGPIOID);
802 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
803 hpd.plugged_state = hpd_record->ucPlugged_PinState;
804 break;
805 }
806 record =
807 (ATOM_COMMON_RECORD_HEADER
808 *) ((char *)record
809 +
810 record->
811 ucRecordSize);
812 }
813 break;
814 }
815 }
816 }
817
818 /* needed for aux chan transactions */
819 ddc_bus.hpd = hpd.hpd;
820
821 conn_id = le16_to_cpu(path->usConnObjectId);
822
823 if (!radeon_atom_apply_quirks
824 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
825 &ddc_bus, &conn_id, &hpd))
826 continue;
827
828 radeon_add_atom_connector(dev,
829 conn_id,
830 le16_to_cpu(path->
831 usDeviceTag),
832 connector_type, &ddc_bus,
833 igp_lane_info,
834 connector_object_id,
835 &hpd,
836 &router);
837
838 }
839 }
840
841 radeon_link_encoder_connector(dev);
842
843 radeon_setup_mst_connector(dev);
844 return true;
845}
846
847static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
848 int connector_type,
849 uint16_t devices)
850{
851 struct radeon_device *rdev = dev->dev_private;
852
853 if (rdev->flags & RADEON_IS_IGP) {
854 return supported_devices_connector_object_id_convert
855 [connector_type];
856 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
857 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
858 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
859 struct radeon_mode_info *mode_info = &rdev->mode_info;
860 struct atom_context *ctx = mode_info->atom_context;
861 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
862 uint16_t size, data_offset;
863 uint8_t frev, crev;
864 ATOM_XTMDS_INFO *xtmds;
865
866 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
867 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
868
869 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
870 if (connector_type == DRM_MODE_CONNECTOR_DVII)
871 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
872 else
873 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
874 } else {
875 if (connector_type == DRM_MODE_CONNECTOR_DVII)
876 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
877 else
878 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
879 }
880 } else
881 return supported_devices_connector_object_id_convert
882 [connector_type];
883 } else {
884 return supported_devices_connector_object_id_convert
885 [connector_type];
886 }
887}
888
889struct bios_connector {
890 bool valid;
891 uint16_t line_mux;
892 uint16_t devices;
893 int connector_type;
894 struct radeon_i2c_bus_rec ddc_bus;
895 struct radeon_hpd hpd;
896};
897
898bool radeon_get_atom_connector_info_from_supported_devices_table(struct
899 drm_device
900 *dev)
901{
902 struct radeon_device *rdev = dev->dev_private;
903 struct radeon_mode_info *mode_info = &rdev->mode_info;
904 struct atom_context *ctx = mode_info->atom_context;
905 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
906 uint16_t size, data_offset;
907 uint8_t frev, crev;
908 uint16_t device_support;
909 uint8_t dac;
910 union atom_supported_devices *supported_devices;
911 int i, j, max_device;
912 struct bios_connector *bios_connectors;
913 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
914 struct radeon_router router;
915
916 router.ddc_valid = false;
917 router.cd_valid = false;
918
919 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
920 if (!bios_connectors)
921 return false;
922
923 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
924 &data_offset)) {
925 kfree(bios_connectors);
926 return false;
927 }
928
929 supported_devices =
930 (union atom_supported_devices *)(ctx->bios + data_offset);
931
932 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
933
934 if (frev > 1)
935 max_device = ATOM_MAX_SUPPORTED_DEVICE;
936 else
937 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
938
939 for (i = 0; i < max_device; i++) {
940 ATOM_CONNECTOR_INFO_I2C ci =
941 supported_devices->info.asConnInfo[i];
942
943 bios_connectors[i].valid = false;
944
945 if (!(device_support & (1 << i))) {
946 continue;
947 }
948
949 if (i == ATOM_DEVICE_CV_INDEX) {
950 DRM_DEBUG_KMS("Skipping Component Video\n");
951 continue;
952 }
953
954 bios_connectors[i].connector_type =
955 supported_devices_connector_convert[ci.sucConnectorInfo.
956 sbfAccess.
957 bfConnectorType];
958
959 if (bios_connectors[i].connector_type ==
960 DRM_MODE_CONNECTOR_Unknown)
961 continue;
962
963 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
964
965 bios_connectors[i].line_mux =
966 ci.sucI2cId.ucAccess;
967
968 /* give tv unique connector ids */
969 if (i == ATOM_DEVICE_TV1_INDEX) {
970 bios_connectors[i].ddc_bus.valid = false;
971 bios_connectors[i].line_mux = 50;
972 } else if (i == ATOM_DEVICE_TV2_INDEX) {
973 bios_connectors[i].ddc_bus.valid = false;
974 bios_connectors[i].line_mux = 51;
975 } else if (i == ATOM_DEVICE_CV_INDEX) {
976 bios_connectors[i].ddc_bus.valid = false;
977 bios_connectors[i].line_mux = 52;
978 } else
979 bios_connectors[i].ddc_bus =
980 radeon_lookup_i2c_gpio(rdev,
981 bios_connectors[i].line_mux);
982
983 if ((crev > 1) && (frev > 1)) {
984 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
985 switch (isb) {
986 case 0x4:
987 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
988 break;
989 case 0xa:
990 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
991 break;
992 default:
993 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
994 break;
995 }
996 } else {
997 if (i == ATOM_DEVICE_DFP1_INDEX)
998 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
999 else if (i == ATOM_DEVICE_DFP2_INDEX)
1000 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1001 else
1002 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1003 }
1004
1005 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1006 * shared with a DVI port, we'll pick up the DVI connector when we
1007 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
1008 */
1009 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1010 bios_connectors[i].connector_type =
1011 DRM_MODE_CONNECTOR_VGA;
1012
1013 if (!radeon_atom_apply_quirks
1014 (dev, (1 << i), &bios_connectors[i].connector_type,
1015 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1016 &bios_connectors[i].hpd))
1017 continue;
1018
1019 bios_connectors[i].valid = true;
1020 bios_connectors[i].devices = (1 << i);
1021
1022 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1023 radeon_add_atom_encoder(dev,
1024 radeon_get_encoder_enum(dev,
1025 (1 << i),
1026 dac),
1027 (1 << i),
1028 0);
1029 else
1030 radeon_add_legacy_encoder(dev,
1031 radeon_get_encoder_enum(dev,
1032 (1 << i),
1033 dac),
1034 (1 << i));
1035 }
1036
1037 /* combine shared connectors */
1038 for (i = 0; i < max_device; i++) {
1039 if (bios_connectors[i].valid) {
1040 for (j = 0; j < max_device; j++) {
1041 if (bios_connectors[j].valid && (i != j)) {
1042 if (bios_connectors[i].line_mux ==
1043 bios_connectors[j].line_mux) {
1044 /* make sure not to combine LVDS */
1045 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1046 bios_connectors[i].line_mux = 53;
1047 bios_connectors[i].ddc_bus.valid = false;
1048 continue;
1049 }
1050 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1051 bios_connectors[j].line_mux = 53;
1052 bios_connectors[j].ddc_bus.valid = false;
1053 continue;
1054 }
1055 /* combine analog and digital for DVI-I */
1056 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1057 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1058 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1059 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1060 bios_connectors[i].devices |=
1061 bios_connectors[j].devices;
1062 bios_connectors[i].connector_type =
1063 DRM_MODE_CONNECTOR_DVII;
1064 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1065 bios_connectors[i].hpd =
1066 bios_connectors[j].hpd;
1067 bios_connectors[j].valid = false;
1068 }
1069 }
1070 }
1071 }
1072 }
1073 }
1074
1075 /* add the connectors */
1076 for (i = 0; i < max_device; i++) {
1077 if (bios_connectors[i].valid) {
1078 uint16_t connector_object_id =
1079 atombios_get_connector_object_id(dev,
1080 bios_connectors[i].connector_type,
1081 bios_connectors[i].devices);
1082 radeon_add_atom_connector(dev,
1083 bios_connectors[i].line_mux,
1084 bios_connectors[i].devices,
1085 bios_connectors[i].
1086 connector_type,
1087 &bios_connectors[i].ddc_bus,
1088 0,
1089 connector_object_id,
1090 &bios_connectors[i].hpd,
1091 &router);
1092 }
1093 }
1094
1095 radeon_link_encoder_connector(dev);
1096
1097 kfree(bios_connectors);
1098 return true;
1099}
1100
1101union firmware_info {
1102 ATOM_FIRMWARE_INFO info;
1103 ATOM_FIRMWARE_INFO_V1_2 info_12;
1104 ATOM_FIRMWARE_INFO_V1_3 info_13;
1105 ATOM_FIRMWARE_INFO_V1_4 info_14;
1106 ATOM_FIRMWARE_INFO_V2_1 info_21;
1107 ATOM_FIRMWARE_INFO_V2_2 info_22;
1108};
1109
1110union igp_info {
1111 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1112 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1113 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1114 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1115 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1116};
1117
1118static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1119{
1120 struct radeon_mode_info *mode_info = &rdev->mode_info;
1121 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1122 union igp_info *igp_info;
1123 u8 frev, crev;
1124 u16 data_offset;
1125
1126 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1127 &frev, &crev, &data_offset)) {
1128 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1129 data_offset);
1130 rdev->clock.vco_freq =
1131 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1132 }
1133}
1134
1135bool radeon_atom_get_clock_info(struct drm_device *dev)
1136{
1137 struct radeon_device *rdev = dev->dev_private;
1138 struct radeon_mode_info *mode_info = &rdev->mode_info;
1139 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1140 union firmware_info *firmware_info;
1141 uint8_t frev, crev;
1142 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1143 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1144 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1145 struct radeon_pll *spll = &rdev->clock.spll;
1146 struct radeon_pll *mpll = &rdev->clock.mpll;
1147 uint16_t data_offset;
1148
1149 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1150 &frev, &crev, &data_offset)) {
1151 firmware_info =
1152 (union firmware_info *)(mode_info->atom_context->bios +
1153 data_offset);
1154 /* pixel clocks */
1155 p1pll->reference_freq =
1156 le16_to_cpu(firmware_info->info.usReferenceClock);
1157 p1pll->reference_div = 0;
1158
1159 if ((frev < 2) && (crev < 2))
1160 p1pll->pll_out_min =
1161 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1162 else
1163 p1pll->pll_out_min =
1164 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1165 p1pll->pll_out_max =
1166 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1167
1168 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1169 p1pll->lcd_pll_out_min =
1170 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1171 if (p1pll->lcd_pll_out_min == 0)
1172 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1173 p1pll->lcd_pll_out_max =
1174 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1175 if (p1pll->lcd_pll_out_max == 0)
1176 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1177 } else {
1178 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1179 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1180 }
1181
1182 if (p1pll->pll_out_min == 0) {
1183 if (ASIC_IS_AVIVO(rdev))
1184 p1pll->pll_out_min = 64800;
1185 else
1186 p1pll->pll_out_min = 20000;
1187 }
1188
1189 p1pll->pll_in_min =
1190 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1191 p1pll->pll_in_max =
1192 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1193
1194 *p2pll = *p1pll;
1195
1196 /* system clock */
1197 if (ASIC_IS_DCE4(rdev))
1198 spll->reference_freq =
1199 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1200 else
1201 spll->reference_freq =
1202 le16_to_cpu(firmware_info->info.usReferenceClock);
1203 spll->reference_div = 0;
1204
1205 spll->pll_out_min =
1206 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1207 spll->pll_out_max =
1208 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1209
1210 /* ??? */
1211 if (spll->pll_out_min == 0) {
1212 if (ASIC_IS_AVIVO(rdev))
1213 spll->pll_out_min = 64800;
1214 else
1215 spll->pll_out_min = 20000;
1216 }
1217
1218 spll->pll_in_min =
1219 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1220 spll->pll_in_max =
1221 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1222
1223 /* memory clock */
1224 if (ASIC_IS_DCE4(rdev))
1225 mpll->reference_freq =
1226 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1227 else
1228 mpll->reference_freq =
1229 le16_to_cpu(firmware_info->info.usReferenceClock);
1230 mpll->reference_div = 0;
1231
1232 mpll->pll_out_min =
1233 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1234 mpll->pll_out_max =
1235 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1236
1237 /* ??? */
1238 if (mpll->pll_out_min == 0) {
1239 if (ASIC_IS_AVIVO(rdev))
1240 mpll->pll_out_min = 64800;
1241 else
1242 mpll->pll_out_min = 20000;
1243 }
1244
1245 mpll->pll_in_min =
1246 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1247 mpll->pll_in_max =
1248 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1249
1250 rdev->clock.default_sclk =
1251 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1252 rdev->clock.default_mclk =
1253 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1254
1255 if (ASIC_IS_DCE4(rdev)) {
1256 rdev->clock.default_dispclk =
1257 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1258 if (rdev->clock.default_dispclk == 0) {
1259 if (ASIC_IS_DCE6(rdev))
1260 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1261 else if (ASIC_IS_DCE5(rdev))
1262 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1263 else
1264 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1265 }
1266 /* set a reasonable default for DP */
1267 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1268 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1269 rdev->clock.default_dispclk / 100);
1270 rdev->clock.default_dispclk = 60000;
1271 }
1272 rdev->clock.dp_extclk =
1273 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1274 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1275 }
1276 *dcpll = *p1pll;
1277
1278 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1279 if (rdev->clock.max_pixel_clock == 0)
1280 rdev->clock.max_pixel_clock = 40000;
1281
1282 /* not technically a clock, but... */
1283 rdev->mode_info.firmware_flags =
1284 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1285
1286 if (ASIC_IS_DCE8(rdev))
1287 rdev->clock.vco_freq =
1288 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1289 else if (ASIC_IS_DCE5(rdev))
1290 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1291 else if (ASIC_IS_DCE41(rdev))
1292 radeon_atombios_get_dentist_vco_freq(rdev);
1293 else
1294 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1295
1296 if (rdev->clock.vco_freq == 0)
1297 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1298
1299 return true;
1300 }
1301
1302 return false;
1303}
1304
1305bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1306{
1307 struct radeon_mode_info *mode_info = &rdev->mode_info;
1308 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1309 union igp_info *igp_info;
1310 u8 frev, crev;
1311 u16 data_offset;
1312
1313 /* sideport is AMD only */
1314 if (rdev->family == CHIP_RS600)
1315 return false;
1316
1317 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1318 &frev, &crev, &data_offset)) {
1319 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1320 data_offset);
1321 switch (crev) {
1322 case 1:
1323 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1324 return true;
1325 break;
1326 case 2:
1327 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1328 return true;
1329 break;
1330 default:
1331 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1332 break;
1333 }
1334 }
1335 return false;
1336}
1337
1338bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1339 struct radeon_encoder_int_tmds *tmds)
1340{
1341 struct drm_device *dev = encoder->base.dev;
1342 struct radeon_device *rdev = dev->dev_private;
1343 struct radeon_mode_info *mode_info = &rdev->mode_info;
1344 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1345 uint16_t data_offset;
1346 struct _ATOM_TMDS_INFO *tmds_info;
1347 uint8_t frev, crev;
1348 uint16_t maxfreq;
1349 int i;
1350
1351 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1352 &frev, &crev, &data_offset)) {
1353 tmds_info =
1354 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1355 data_offset);
1356
1357 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1358 for (i = 0; i < 4; i++) {
1359 tmds->tmds_pll[i].freq =
1360 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1361 tmds->tmds_pll[i].value =
1362 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1363 tmds->tmds_pll[i].value |=
1364 (tmds_info->asMiscInfo[i].
1365 ucPLL_VCO_Gain & 0x3f) << 6;
1366 tmds->tmds_pll[i].value |=
1367 (tmds_info->asMiscInfo[i].
1368 ucPLL_DutyCycle & 0xf) << 12;
1369 tmds->tmds_pll[i].value |=
1370 (tmds_info->asMiscInfo[i].
1371 ucPLL_VoltageSwing & 0xf) << 16;
1372
1373 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1374 tmds->tmds_pll[i].freq,
1375 tmds->tmds_pll[i].value);
1376
1377 if (maxfreq == tmds->tmds_pll[i].freq) {
1378 tmds->tmds_pll[i].freq = 0xffffffff;
1379 break;
1380 }
1381 }
1382 return true;
1383 }
1384 return false;
1385}
1386
1387bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1388 struct radeon_atom_ss *ss,
1389 int id)
1390{
1391 struct radeon_mode_info *mode_info = &rdev->mode_info;
1392 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1393 uint16_t data_offset, size;
1394 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1395 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1396 uint8_t frev, crev;
1397 int i, num_indices;
1398
1399 memset(ss, 0, sizeof(struct radeon_atom_ss));
1400 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1401 &frev, &crev, &data_offset)) {
1402 ss_info =
1403 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1404
1405 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1406 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1407 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1408 ((u8 *)&ss_info->asSS_Info[0]);
1409 for (i = 0; i < num_indices; i++) {
1410 if (ss_assign->ucSS_Id == id) {
1411 ss->percentage =
1412 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1413 ss->type = ss_assign->ucSpreadSpectrumType;
1414 ss->step = ss_assign->ucSS_Step;
1415 ss->delay = ss_assign->ucSS_Delay;
1416 ss->range = ss_assign->ucSS_Range;
1417 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1418 return true;
1419 }
1420 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1421 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1422 }
1423 }
1424 return false;
1425}
1426
1427static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1428 struct radeon_atom_ss *ss,
1429 int id)
1430{
1431 struct radeon_mode_info *mode_info = &rdev->mode_info;
1432 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1433 u16 data_offset, size;
1434 union igp_info *igp_info;
1435 u8 frev, crev;
1436 u16 percentage = 0, rate = 0;
1437
1438 /* get any igp specific overrides */
1439 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1440 &frev, &crev, &data_offset)) {
1441 igp_info = (union igp_info *)
1442 (mode_info->atom_context->bios + data_offset);
1443 switch (crev) {
1444 case 6:
1445 switch (id) {
1446 case ASIC_INTERNAL_SS_ON_TMDS:
1447 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1448 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1449 break;
1450 case ASIC_INTERNAL_SS_ON_HDMI:
1451 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1452 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1453 break;
1454 case ASIC_INTERNAL_SS_ON_LVDS:
1455 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1456 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1457 break;
1458 }
1459 break;
1460 case 7:
1461 switch (id) {
1462 case ASIC_INTERNAL_SS_ON_TMDS:
1463 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1464 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1465 break;
1466 case ASIC_INTERNAL_SS_ON_HDMI:
1467 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1468 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1469 break;
1470 case ASIC_INTERNAL_SS_ON_LVDS:
1471 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1472 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1473 break;
1474 }
1475 break;
1476 case 8:
1477 switch (id) {
1478 case ASIC_INTERNAL_SS_ON_TMDS:
1479 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1480 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1481 break;
1482 case ASIC_INTERNAL_SS_ON_HDMI:
1483 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1484 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1485 break;
1486 case ASIC_INTERNAL_SS_ON_LVDS:
1487 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1488 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1489 break;
1490 }
1491 break;
1492 default:
1493 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1494 break;
1495 }
1496 if (percentage)
1497 ss->percentage = percentage;
1498 if (rate)
1499 ss->rate = rate;
1500 }
1501}
1502
1503union asic_ss_info {
1504 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1505 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1506 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1507};
1508
1509union asic_ss_assignment {
1510 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1511 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1512 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1513};
1514
1515bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1516 struct radeon_atom_ss *ss,
1517 int id, u32 clock)
1518{
1519 struct radeon_mode_info *mode_info = &rdev->mode_info;
1520 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1521 uint16_t data_offset, size;
1522 union asic_ss_info *ss_info;
1523 union asic_ss_assignment *ss_assign;
1524 uint8_t frev, crev;
1525 int i, num_indices;
1526
1527 if (id == ASIC_INTERNAL_MEMORY_SS) {
1528 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1529 return false;
1530 }
1531 if (id == ASIC_INTERNAL_ENGINE_SS) {
1532 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1533 return false;
1534 }
1535
1536 memset(ss, 0, sizeof(struct radeon_atom_ss));
1537 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1538 &frev, &crev, &data_offset)) {
1539
1540 ss_info =
1541 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1542
1543 switch (frev) {
1544 case 1:
1545 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1546 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1547
1548 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1549 for (i = 0; i < num_indices; i++) {
1550 if ((ss_assign->v1.ucClockIndication == id) &&
1551 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1552 ss->percentage =
1553 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1554 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1555 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1556 ss->percentage_divider = 100;
1557 return true;
1558 }
1559 ss_assign = (union asic_ss_assignment *)
1560 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1561 }
1562 break;
1563 case 2:
1564 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1565 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1566 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1567 for (i = 0; i < num_indices; i++) {
1568 if ((ss_assign->v2.ucClockIndication == id) &&
1569 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1570 ss->percentage =
1571 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1572 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1573 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1574 ss->percentage_divider = 100;
1575 if ((crev == 2) &&
1576 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1577 (id == ASIC_INTERNAL_MEMORY_SS)))
1578 ss->rate /= 100;
1579 return true;
1580 }
1581 ss_assign = (union asic_ss_assignment *)
1582 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1583 }
1584 break;
1585 case 3:
1586 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1587 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1588 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1589 for (i = 0; i < num_indices; i++) {
1590 if ((ss_assign->v3.ucClockIndication == id) &&
1591 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1592 ss->percentage =
1593 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1594 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1595 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1596 if (ss_assign->v3.ucSpreadSpectrumMode &
1597 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1598 ss->percentage_divider = 1000;
1599 else
1600 ss->percentage_divider = 100;
1601 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1602 (id == ASIC_INTERNAL_MEMORY_SS))
1603 ss->rate /= 100;
1604 if (rdev->flags & RADEON_IS_IGP)
1605 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1606 return true;
1607 }
1608 ss_assign = (union asic_ss_assignment *)
1609 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1610 }
1611 break;
1612 default:
1613 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1614 break;
1615 }
1616
1617 }
1618 return false;
1619}
1620
1621union lvds_info {
1622 struct _ATOM_LVDS_INFO info;
1623 struct _ATOM_LVDS_INFO_V12 info_12;
1624};
1625
1626struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1627 radeon_encoder
1628 *encoder)
1629{
1630 struct drm_device *dev = encoder->base.dev;
1631 struct radeon_device *rdev = dev->dev_private;
1632 struct radeon_mode_info *mode_info = &rdev->mode_info;
1633 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1634 uint16_t data_offset, misc;
1635 union lvds_info *lvds_info;
1636 uint8_t frev, crev;
1637 struct radeon_encoder_atom_dig *lvds = NULL;
1638 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1639
1640 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1641 &frev, &crev, &data_offset)) {
1642 lvds_info =
1643 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1644 lvds =
1645 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1646
1647 if (!lvds)
1648 return NULL;
1649
1650 lvds->native_mode.clock =
1651 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1652 lvds->native_mode.hdisplay =
1653 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1654 lvds->native_mode.vdisplay =
1655 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1656 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1657 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1658 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1659 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1660 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1661 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1662 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1663 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1664 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1665 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1666 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1667 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1668 lvds->panel_pwr_delay =
1669 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1670 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1671
1672 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1673 if (misc & ATOM_VSYNC_POLARITY)
1674 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1675 if (misc & ATOM_HSYNC_POLARITY)
1676 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1677 if (misc & ATOM_COMPOSITESYNC)
1678 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1679 if (misc & ATOM_INTERLACE)
1680 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1681 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1682 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1683
1684 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1685 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1686
1687 /* set crtc values */
1688 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1689
1690 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1691
1692 encoder->native_mode = lvds->native_mode;
1693
1694 if (encoder_enum == 2)
1695 lvds->linkb = true;
1696 else
1697 lvds->linkb = false;
1698
1699 /* parse the lcd record table */
1700 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1701 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1702 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1703 bool bad_record = false;
1704 u8 *record;
1705
1706 if ((frev == 1) && (crev < 2))
1707 /* absolute */
1708 record = (u8 *)(mode_info->atom_context->bios +
1709 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1710 else
1711 /* relative */
1712 record = (u8 *)(mode_info->atom_context->bios +
1713 data_offset +
1714 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1715 while (*record != ATOM_RECORD_END_TYPE) {
1716 switch (*record) {
1717 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1718 record += sizeof(ATOM_PATCH_RECORD_MODE);
1719 break;
1720 case LCD_RTS_RECORD_TYPE:
1721 record += sizeof(ATOM_LCD_RTS_RECORD);
1722 break;
1723 case LCD_CAP_RECORD_TYPE:
1724 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1725 break;
1726 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1727 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1728 if (fake_edid_record->ucFakeEDIDLength) {
1729 struct edid *edid;
1730 int edid_size =
1731 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1732 edid = kmalloc(edid_size, GFP_KERNEL);
1733 if (edid) {
1734 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1735 fake_edid_record->ucFakeEDIDLength);
1736
1737 if (drm_edid_is_valid(edid)) {
1738 rdev->mode_info.bios_hardcoded_edid = edid;
1739 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1740 } else
1741 kfree(edid);
1742 }
1743 }
1744 record += fake_edid_record->ucFakeEDIDLength ?
1745 fake_edid_record->ucFakeEDIDLength + 2 :
1746 sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1747 break;
1748 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1749 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1750 lvds->native_mode.width_mm = panel_res_record->usHSize;
1751 lvds->native_mode.height_mm = panel_res_record->usVSize;
1752 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1753 break;
1754 default:
1755 DRM_ERROR("Bad LCD record %d\n", *record);
1756 bad_record = true;
1757 break;
1758 }
1759 if (bad_record)
1760 break;
1761 }
1762 }
1763 }
1764 return lvds;
1765}
1766
1767struct radeon_encoder_primary_dac *
1768radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1769{
1770 struct drm_device *dev = encoder->base.dev;
1771 struct radeon_device *rdev = dev->dev_private;
1772 struct radeon_mode_info *mode_info = &rdev->mode_info;
1773 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1774 uint16_t data_offset;
1775 struct _COMPASSIONATE_DATA *dac_info;
1776 uint8_t frev, crev;
1777 uint8_t bg, dac;
1778 struct radeon_encoder_primary_dac *p_dac = NULL;
1779
1780 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1781 &frev, &crev, &data_offset)) {
1782 dac_info = (struct _COMPASSIONATE_DATA *)
1783 (mode_info->atom_context->bios + data_offset);
1784
1785 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1786
1787 if (!p_dac)
1788 return NULL;
1789
1790 bg = dac_info->ucDAC1_BG_Adjustment;
1791 dac = dac_info->ucDAC1_DAC_Adjustment;
1792 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1793
1794 }
1795 return p_dac;
1796}
1797
1798bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1799 struct drm_display_mode *mode)
1800{
1801 struct radeon_mode_info *mode_info = &rdev->mode_info;
1802 ATOM_ANALOG_TV_INFO *tv_info;
1803 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1804 ATOM_DTD_FORMAT *dtd_timings;
1805 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1806 u8 frev, crev;
1807 u16 data_offset, misc;
1808
1809 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1810 &frev, &crev, &data_offset))
1811 return false;
1812
1813 switch (crev) {
1814 case 1:
1815 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1816 if (index >= MAX_SUPPORTED_TV_TIMING)
1817 return false;
1818
1819 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1820 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1821 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1822 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1823 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1824
1825 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1826 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1827 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1828 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1829 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1830
1831 mode->flags = 0;
1832 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1833 if (misc & ATOM_VSYNC_POLARITY)
1834 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1835 if (misc & ATOM_HSYNC_POLARITY)
1836 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1837 if (misc & ATOM_COMPOSITESYNC)
1838 mode->flags |= DRM_MODE_FLAG_CSYNC;
1839 if (misc & ATOM_INTERLACE)
1840 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1841 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1842 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1843
1844 mode->crtc_clock = mode->clock =
1845 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1846
1847 if (index == 1) {
1848 /* PAL timings appear to have wrong values for totals */
1849 mode->crtc_htotal -= 1;
1850 mode->crtc_vtotal -= 1;
1851 }
1852 break;
1853 case 2:
1854 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1855 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1856 return false;
1857
1858 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1859 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1860 le16_to_cpu(dtd_timings->usHBlanking_Time);
1861 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1862 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1863 le16_to_cpu(dtd_timings->usHSyncOffset);
1864 mode->crtc_hsync_end = mode->crtc_hsync_start +
1865 le16_to_cpu(dtd_timings->usHSyncWidth);
1866
1867 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1868 le16_to_cpu(dtd_timings->usVBlanking_Time);
1869 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1870 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1871 le16_to_cpu(dtd_timings->usVSyncOffset);
1872 mode->crtc_vsync_end = mode->crtc_vsync_start +
1873 le16_to_cpu(dtd_timings->usVSyncWidth);
1874
1875 mode->flags = 0;
1876 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1877 if (misc & ATOM_VSYNC_POLARITY)
1878 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1879 if (misc & ATOM_HSYNC_POLARITY)
1880 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1881 if (misc & ATOM_COMPOSITESYNC)
1882 mode->flags |= DRM_MODE_FLAG_CSYNC;
1883 if (misc & ATOM_INTERLACE)
1884 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1885 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1886 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1887
1888 mode->crtc_clock = mode->clock =
1889 le16_to_cpu(dtd_timings->usPixClk) * 10;
1890 break;
1891 }
1892 return true;
1893}
1894
1895enum radeon_tv_std
1896radeon_atombios_get_tv_info(struct radeon_device *rdev)
1897{
1898 struct radeon_mode_info *mode_info = &rdev->mode_info;
1899 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1900 uint16_t data_offset;
1901 uint8_t frev, crev;
1902 struct _ATOM_ANALOG_TV_INFO *tv_info;
1903 enum radeon_tv_std tv_std = TV_STD_NTSC;
1904
1905 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1906 &frev, &crev, &data_offset)) {
1907
1908 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1909 (mode_info->atom_context->bios + data_offset);
1910
1911 switch (tv_info->ucTV_BootUpDefaultStandard) {
1912 case ATOM_TV_NTSC:
1913 tv_std = TV_STD_NTSC;
1914 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1915 break;
1916 case ATOM_TV_NTSCJ:
1917 tv_std = TV_STD_NTSC_J;
1918 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1919 break;
1920 case ATOM_TV_PAL:
1921 tv_std = TV_STD_PAL;
1922 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1923 break;
1924 case ATOM_TV_PALM:
1925 tv_std = TV_STD_PAL_M;
1926 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1927 break;
1928 case ATOM_TV_PALN:
1929 tv_std = TV_STD_PAL_N;
1930 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1931 break;
1932 case ATOM_TV_PALCN:
1933 tv_std = TV_STD_PAL_CN;
1934 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1935 break;
1936 case ATOM_TV_PAL60:
1937 tv_std = TV_STD_PAL_60;
1938 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1939 break;
1940 case ATOM_TV_SECAM:
1941 tv_std = TV_STD_SECAM;
1942 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1943 break;
1944 default:
1945 tv_std = TV_STD_NTSC;
1946 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1947 break;
1948 }
1949 }
1950 return tv_std;
1951}
1952
1953struct radeon_encoder_tv_dac *
1954radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1955{
1956 struct drm_device *dev = encoder->base.dev;
1957 struct radeon_device *rdev = dev->dev_private;
1958 struct radeon_mode_info *mode_info = &rdev->mode_info;
1959 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1960 uint16_t data_offset;
1961 struct _COMPASSIONATE_DATA *dac_info;
1962 uint8_t frev, crev;
1963 uint8_t bg, dac;
1964 struct radeon_encoder_tv_dac *tv_dac = NULL;
1965
1966 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1967 &frev, &crev, &data_offset)) {
1968
1969 dac_info = (struct _COMPASSIONATE_DATA *)
1970 (mode_info->atom_context->bios + data_offset);
1971
1972 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1973
1974 if (!tv_dac)
1975 return NULL;
1976
1977 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1978 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1979 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1980
1981 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1982 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1983 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1984
1985 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1986 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1987 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1988
1989 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1990 }
1991 return tv_dac;
1992}
1993
1994static const char *thermal_controller_names[] = {
1995 "NONE",
1996 "lm63",
1997 "adm1032",
1998 "adm1030",
1999 "max6649",
2000 "lm63", /* lm64 */
2001 "f75375",
2002 "asc7xxx",
2003};
2004
2005static const char *pp_lib_thermal_controller_names[] = {
2006 "NONE",
2007 "lm63",
2008 "adm1032",
2009 "adm1030",
2010 "max6649",
2011 "lm63", /* lm64 */
2012 "f75375",
2013 "RV6xx",
2014 "RV770",
2015 "adt7473",
2016 "NONE",
2017 "External GPIO",
2018 "Evergreen",
2019 "emc2103",
2020 "Sumo",
2021 "Northern Islands",
2022 "Southern Islands",
2023 "lm96163",
2024 "Sea Islands",
2025};
2026
2027union power_info {
2028 struct _ATOM_POWERPLAY_INFO info;
2029 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2030 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2031 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2032 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2033 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2034};
2035
2036union pplib_clock_info {
2037 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2038 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2039 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2040 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2041 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2042 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2043};
2044
2045union pplib_power_state {
2046 struct _ATOM_PPLIB_STATE v1;
2047 struct _ATOM_PPLIB_STATE_V2 v2;
2048};
2049
2050static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2051 int state_index,
2052 u32 misc, u32 misc2)
2053{
2054 rdev->pm.power_state[state_index].misc = misc;
2055 rdev->pm.power_state[state_index].misc2 = misc2;
2056 /* order matters! */
2057 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2058 rdev->pm.power_state[state_index].type =
2059 POWER_STATE_TYPE_POWERSAVE;
2060 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2061 rdev->pm.power_state[state_index].type =
2062 POWER_STATE_TYPE_BATTERY;
2063 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2064 rdev->pm.power_state[state_index].type =
2065 POWER_STATE_TYPE_BATTERY;
2066 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2067 rdev->pm.power_state[state_index].type =
2068 POWER_STATE_TYPE_BALANCED;
2069 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2070 rdev->pm.power_state[state_index].type =
2071 POWER_STATE_TYPE_PERFORMANCE;
2072 rdev->pm.power_state[state_index].flags &=
2073 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2074 }
2075 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2076 rdev->pm.power_state[state_index].type =
2077 POWER_STATE_TYPE_BALANCED;
2078 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2079 rdev->pm.power_state[state_index].type =
2080 POWER_STATE_TYPE_DEFAULT;
2081 rdev->pm.default_power_state_index = state_index;
2082 rdev->pm.power_state[state_index].default_clock_mode =
2083 &rdev->pm.power_state[state_index].clock_info[0];
2084 } else if (state_index == 0) {
2085 rdev->pm.power_state[state_index].clock_info[0].flags |=
2086 RADEON_PM_MODE_NO_DISPLAY;
2087 }
2088}
2089
2090static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2091{
2092 struct radeon_mode_info *mode_info = &rdev->mode_info;
2093 u32 misc, misc2 = 0;
2094 int num_modes = 0, i;
2095 int state_index = 0;
2096 struct radeon_i2c_bus_rec i2c_bus;
2097 union power_info *power_info;
2098 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2099 u16 data_offset;
2100 u8 frev, crev;
2101
2102 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2103 &frev, &crev, &data_offset))
2104 return state_index;
2105 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2106
2107 /* add the i2c bus for thermal/fan chip */
2108 if ((power_info->info.ucOverdriveThermalController > 0) &&
2109 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2110 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2111 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2112 power_info->info.ucOverdriveControllerAddress >> 1);
2113 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2114 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2115 if (rdev->pm.i2c_bus) {
2116 struct i2c_board_info info = { };
2117 const char *name = thermal_controller_names[power_info->info.
2118 ucOverdriveThermalController];
2119 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2120 strlcpy(info.type, name, sizeof(info.type));
2121 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2122 }
2123 }
2124 num_modes = power_info->info.ucNumOfPowerModeEntries;
2125 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2126 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2127 if (num_modes == 0)
2128 return state_index;
2129 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
2130 if (!rdev->pm.power_state)
2131 return state_index;
2132 /* last mode is usually default, array is low to high */
2133 for (i = 0; i < num_modes; i++) {
2134 rdev->pm.power_state[state_index].clock_info =
2135 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2136 if (!rdev->pm.power_state[state_index].clock_info)
2137 return state_index;
2138 rdev->pm.power_state[state_index].num_clock_modes = 1;
2139 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2140 switch (frev) {
2141 case 1:
2142 rdev->pm.power_state[state_index].clock_info[0].mclk =
2143 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2144 rdev->pm.power_state[state_index].clock_info[0].sclk =
2145 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2146 /* skip invalid modes */
2147 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2148 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2149 continue;
2150 rdev->pm.power_state[state_index].pcie_lanes =
2151 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2152 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2153 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2154 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2155 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2156 VOLTAGE_GPIO;
2157 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2158 radeon_atombios_lookup_gpio(rdev,
2159 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2160 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2161 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2162 true;
2163 else
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2165 false;
2166 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2167 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2168 VOLTAGE_VDDC;
2169 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2170 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2171 }
2172 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2173 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2174 state_index++;
2175 break;
2176 case 2:
2177 rdev->pm.power_state[state_index].clock_info[0].mclk =
2178 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2179 rdev->pm.power_state[state_index].clock_info[0].sclk =
2180 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2181 /* skip invalid modes */
2182 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2183 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2184 continue;
2185 rdev->pm.power_state[state_index].pcie_lanes =
2186 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2187 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2188 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2189 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2190 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2191 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2192 VOLTAGE_GPIO;
2193 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2194 radeon_atombios_lookup_gpio(rdev,
2195 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2196 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2197 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2198 true;
2199 else
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2201 false;
2202 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2203 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2204 VOLTAGE_VDDC;
2205 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2206 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2207 }
2208 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2209 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2210 state_index++;
2211 break;
2212 case 3:
2213 rdev->pm.power_state[state_index].clock_info[0].mclk =
2214 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2215 rdev->pm.power_state[state_index].clock_info[0].sclk =
2216 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2217 /* skip invalid modes */
2218 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2219 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2220 continue;
2221 rdev->pm.power_state[state_index].pcie_lanes =
2222 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2223 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2224 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2225 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2226 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2227 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2228 VOLTAGE_GPIO;
2229 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2230 radeon_atombios_lookup_gpio(rdev,
2231 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2232 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2233 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2234 true;
2235 else
2236 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2237 false;
2238 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2239 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2240 VOLTAGE_VDDC;
2241 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2242 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2243 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2244 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2245 true;
2246 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2247 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2248 }
2249 }
2250 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2251 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2252 state_index++;
2253 break;
2254 }
2255 }
2256 /* last mode is usually default */
2257 if (rdev->pm.default_power_state_index == -1) {
2258 rdev->pm.power_state[state_index - 1].type =
2259 POWER_STATE_TYPE_DEFAULT;
2260 rdev->pm.default_power_state_index = state_index - 1;
2261 rdev->pm.power_state[state_index - 1].default_clock_mode =
2262 &rdev->pm.power_state[state_index - 1].clock_info[0];
2263 rdev->pm.power_state[state_index].flags &=
2264 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2265 rdev->pm.power_state[state_index].misc = 0;
2266 rdev->pm.power_state[state_index].misc2 = 0;
2267 }
2268 return state_index;
2269}
2270
2271static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2272 ATOM_PPLIB_THERMALCONTROLLER *controller)
2273{
2274 struct radeon_i2c_bus_rec i2c_bus;
2275
2276 /* add the i2c bus for thermal/fan chip */
2277 if (controller->ucType > 0) {
2278 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2279 rdev->pm.no_fan = true;
2280 rdev->pm.fan_pulses_per_revolution =
2281 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2282 if (rdev->pm.fan_pulses_per_revolution) {
2283 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2284 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2285 }
2286 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2287 DRM_INFO("Internal thermal controller %s fan control\n",
2288 (controller->ucFanParameters &
2289 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2290 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2291 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2292 DRM_INFO("Internal thermal controller %s fan control\n",
2293 (controller->ucFanParameters &
2294 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2295 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2296 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2297 DRM_INFO("Internal thermal controller %s fan control\n",
2298 (controller->ucFanParameters &
2299 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2300 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2301 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2302 DRM_INFO("Internal thermal controller %s fan control\n",
2303 (controller->ucFanParameters &
2304 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2305 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2306 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2307 DRM_INFO("Internal thermal controller %s fan control\n",
2308 (controller->ucFanParameters &
2309 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2310 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2311 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2312 DRM_INFO("Internal thermal controller %s fan control\n",
2313 (controller->ucFanParameters &
2314 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2315 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2316 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2317 DRM_INFO("Internal thermal controller %s fan control\n",
2318 (controller->ucFanParameters &
2319 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2320 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2321 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2322 DRM_INFO("Internal thermal controller %s fan control\n",
2323 (controller->ucFanParameters &
2324 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2325 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2326 } else if (controller->ucType ==
2327 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2328 DRM_INFO("External GPIO thermal controller %s fan control\n",
2329 (controller->ucFanParameters &
2330 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2331 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2332 } else if (controller->ucType ==
2333 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2334 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2335 (controller->ucFanParameters &
2336 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2337 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2338 } else if (controller->ucType ==
2339 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2340 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2341 (controller->ucFanParameters &
2342 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2343 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2344 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2345 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2346 pp_lib_thermal_controller_names[controller->ucType],
2347 controller->ucI2cAddress >> 1,
2348 (controller->ucFanParameters &
2349 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2350 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2351 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2352 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2353 if (rdev->pm.i2c_bus) {
2354 struct i2c_board_info info = { };
2355 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2356 info.addr = controller->ucI2cAddress >> 1;
2357 strlcpy(info.type, name, sizeof(info.type));
2358 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2359 }
2360 } else {
2361 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2362 controller->ucType,
2363 controller->ucI2cAddress >> 1,
2364 (controller->ucFanParameters &
2365 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2366 }
2367 }
2368}
2369
2370void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2371 u16 *vddc, u16 *vddci, u16 *mvdd)
2372{
2373 struct radeon_mode_info *mode_info = &rdev->mode_info;
2374 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2375 u8 frev, crev;
2376 u16 data_offset;
2377 union firmware_info *firmware_info;
2378
2379 *vddc = 0;
2380 *vddci = 0;
2381 *mvdd = 0;
2382
2383 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2384 &frev, &crev, &data_offset)) {
2385 firmware_info =
2386 (union firmware_info *)(mode_info->atom_context->bios +
2387 data_offset);
2388 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2389 if ((frev == 2) && (crev >= 2)) {
2390 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2391 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2392 }
2393 }
2394}
2395
2396static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2397 int state_index, int mode_index,
2398 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2399{
2400 int j;
2401 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2402 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2403 u16 vddc, vddci, mvdd;
2404
2405 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2406
2407 rdev->pm.power_state[state_index].misc = misc;
2408 rdev->pm.power_state[state_index].misc2 = misc2;
2409 rdev->pm.power_state[state_index].pcie_lanes =
2410 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2411 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2412 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2413 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2414 rdev->pm.power_state[state_index].type =
2415 POWER_STATE_TYPE_BATTERY;
2416 break;
2417 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2418 rdev->pm.power_state[state_index].type =
2419 POWER_STATE_TYPE_BALANCED;
2420 break;
2421 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2422 rdev->pm.power_state[state_index].type =
2423 POWER_STATE_TYPE_PERFORMANCE;
2424 break;
2425 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2426 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2427 rdev->pm.power_state[state_index].type =
2428 POWER_STATE_TYPE_PERFORMANCE;
2429 break;
2430 }
2431 rdev->pm.power_state[state_index].flags = 0;
2432 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2433 rdev->pm.power_state[state_index].flags |=
2434 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2435 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2436 rdev->pm.power_state[state_index].type =
2437 POWER_STATE_TYPE_DEFAULT;
2438 rdev->pm.default_power_state_index = state_index;
2439 rdev->pm.power_state[state_index].default_clock_mode =
2440 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2441 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2442 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2443 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2444 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2445 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2446 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2447 } else {
2448 u16 max_vddci = 0;
2449
2450 if (ASIC_IS_DCE4(rdev))
2451 radeon_atom_get_max_voltage(rdev,
2452 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2453 &max_vddci);
2454 /* patch the table values with the default sclk/mclk from firmware info */
2455 for (j = 0; j < mode_index; j++) {
2456 rdev->pm.power_state[state_index].clock_info[j].mclk =
2457 rdev->clock.default_mclk;
2458 rdev->pm.power_state[state_index].clock_info[j].sclk =
2459 rdev->clock.default_sclk;
2460 if (vddc)
2461 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2462 vddc;
2463 if (max_vddci)
2464 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2465 max_vddci;
2466 }
2467 }
2468 }
2469}
2470
2471static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2472 int state_index, int mode_index,
2473 union pplib_clock_info *clock_info)
2474{
2475 u32 sclk, mclk;
2476 u16 vddc;
2477
2478 if (rdev->flags & RADEON_IS_IGP) {
2479 if (rdev->family >= CHIP_PALM) {
2480 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2481 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2482 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2483 } else {
2484 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2485 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2486 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2487 }
2488 } else if (rdev->family >= CHIP_BONAIRE) {
2489 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2490 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2491 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2492 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2493 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2494 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2495 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2496 VOLTAGE_NONE;
2497 } else if (rdev->family >= CHIP_TAHITI) {
2498 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2499 sclk |= clock_info->si.ucEngineClockHigh << 16;
2500 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2501 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2502 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2503 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2504 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2505 VOLTAGE_SW;
2506 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2507 le16_to_cpu(clock_info->si.usVDDC);
2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2509 le16_to_cpu(clock_info->si.usVDDCI);
2510 } else if (rdev->family >= CHIP_CEDAR) {
2511 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2512 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2513 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2514 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2515 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2516 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2517 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2518 VOLTAGE_SW;
2519 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2520 le16_to_cpu(clock_info->evergreen.usVDDC);
2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2522 le16_to_cpu(clock_info->evergreen.usVDDCI);
2523 } else {
2524 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2525 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2526 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2527 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2528 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2529 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2530 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2531 VOLTAGE_SW;
2532 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2533 le16_to_cpu(clock_info->r600.usVDDC);
2534 }
2535
2536 /* patch up vddc if necessary */
2537 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2538 case ATOM_VIRTUAL_VOLTAGE_ID0:
2539 case ATOM_VIRTUAL_VOLTAGE_ID1:
2540 case ATOM_VIRTUAL_VOLTAGE_ID2:
2541 case ATOM_VIRTUAL_VOLTAGE_ID3:
2542 case ATOM_VIRTUAL_VOLTAGE_ID4:
2543 case ATOM_VIRTUAL_VOLTAGE_ID5:
2544 case ATOM_VIRTUAL_VOLTAGE_ID6:
2545 case ATOM_VIRTUAL_VOLTAGE_ID7:
2546 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2547 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2548 &vddc) == 0)
2549 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2550 break;
2551 default:
2552 break;
2553 }
2554
2555 if (rdev->flags & RADEON_IS_IGP) {
2556 /* skip invalid modes */
2557 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2558 return false;
2559 } else {
2560 /* skip invalid modes */
2561 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2562 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2563 return false;
2564 }
2565 return true;
2566}
2567
2568static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2569{
2570 struct radeon_mode_info *mode_info = &rdev->mode_info;
2571 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2572 union pplib_power_state *power_state;
2573 int i, j;
2574 int state_index = 0, mode_index = 0;
2575 union pplib_clock_info *clock_info;
2576 bool valid;
2577 union power_info *power_info;
2578 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2579 u16 data_offset;
2580 u8 frev, crev;
2581
2582 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2583 &frev, &crev, &data_offset))
2584 return state_index;
2585 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2586
2587 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2588 if (power_info->pplib.ucNumStates == 0)
2589 return state_index;
2590 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2591 power_info->pplib.ucNumStates, GFP_KERNEL);
2592 if (!rdev->pm.power_state)
2593 return state_index;
2594 /* first mode is usually default, followed by low to high */
2595 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2596 mode_index = 0;
2597 power_state = (union pplib_power_state *)
2598 (mode_info->atom_context->bios + data_offset +
2599 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2600 i * power_info->pplib.ucStateEntrySize);
2601 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2602 (mode_info->atom_context->bios + data_offset +
2603 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2604 (power_state->v1.ucNonClockStateIndex *
2605 power_info->pplib.ucNonClockSize));
2606 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2607 ((power_info->pplib.ucStateEntrySize - 1) ?
2608 (power_info->pplib.ucStateEntrySize - 1) : 1),
2609 GFP_KERNEL);
2610 if (!rdev->pm.power_state[i].clock_info)
2611 return state_index;
2612 if (power_info->pplib.ucStateEntrySize - 1) {
2613 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2614 clock_info = (union pplib_clock_info *)
2615 (mode_info->atom_context->bios + data_offset +
2616 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2617 (power_state->v1.ucClockStateIndices[j] *
2618 power_info->pplib.ucClockInfoSize));
2619 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2620 state_index, mode_index,
2621 clock_info);
2622 if (valid)
2623 mode_index++;
2624 }
2625 } else {
2626 rdev->pm.power_state[state_index].clock_info[0].mclk =
2627 rdev->clock.default_mclk;
2628 rdev->pm.power_state[state_index].clock_info[0].sclk =
2629 rdev->clock.default_sclk;
2630 mode_index++;
2631 }
2632 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2633 if (mode_index) {
2634 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2635 non_clock_info);
2636 state_index++;
2637 }
2638 }
2639 /* if multiple clock modes, mark the lowest as no display */
2640 for (i = 0; i < state_index; i++) {
2641 if (rdev->pm.power_state[i].num_clock_modes > 1)
2642 rdev->pm.power_state[i].clock_info[0].flags |=
2643 RADEON_PM_MODE_NO_DISPLAY;
2644 }
2645 /* first mode is usually default */
2646 if (rdev->pm.default_power_state_index == -1) {
2647 rdev->pm.power_state[0].type =
2648 POWER_STATE_TYPE_DEFAULT;
2649 rdev->pm.default_power_state_index = 0;
2650 rdev->pm.power_state[0].default_clock_mode =
2651 &rdev->pm.power_state[0].clock_info[0];
2652 }
2653 return state_index;
2654}
2655
2656static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2657{
2658 struct radeon_mode_info *mode_info = &rdev->mode_info;
2659 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2660 union pplib_power_state *power_state;
2661 int i, j, non_clock_array_index, clock_array_index;
2662 int state_index = 0, mode_index = 0;
2663 union pplib_clock_info *clock_info;
2664 struct _StateArray *state_array;
2665 struct _ClockInfoArray *clock_info_array;
2666 struct _NonClockInfoArray *non_clock_info_array;
2667 bool valid;
2668 union power_info *power_info;
2669 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2670 u16 data_offset;
2671 u8 frev, crev;
2672 u8 *power_state_offset;
2673
2674 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2675 &frev, &crev, &data_offset))
2676 return state_index;
2677 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2678
2679 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2680 state_array = (struct _StateArray *)
2681 (mode_info->atom_context->bios + data_offset +
2682 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2683 clock_info_array = (struct _ClockInfoArray *)
2684 (mode_info->atom_context->bios + data_offset +
2685 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2686 non_clock_info_array = (struct _NonClockInfoArray *)
2687 (mode_info->atom_context->bios + data_offset +
2688 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2689 if (state_array->ucNumEntries == 0)
2690 return state_index;
2691 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
2692 state_array->ucNumEntries, GFP_KERNEL);
2693 if (!rdev->pm.power_state)
2694 return state_index;
2695 power_state_offset = (u8 *)state_array->states;
2696 for (i = 0; i < state_array->ucNumEntries; i++) {
2697 mode_index = 0;
2698 power_state = (union pplib_power_state *)power_state_offset;
2699 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2700 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2701 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2702 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2703 (power_state->v2.ucNumDPMLevels ?
2704 power_state->v2.ucNumDPMLevels : 1),
2705 GFP_KERNEL);
2706 if (!rdev->pm.power_state[i].clock_info)
2707 return state_index;
2708 if (power_state->v2.ucNumDPMLevels) {
2709 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2710 clock_array_index = power_state->v2.clockInfoIndex[j];
2711 clock_info = (union pplib_clock_info *)
2712 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2713 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2714 state_index, mode_index,
2715 clock_info);
2716 if (valid)
2717 mode_index++;
2718 }
2719 } else {
2720 rdev->pm.power_state[state_index].clock_info[0].mclk =
2721 rdev->clock.default_mclk;
2722 rdev->pm.power_state[state_index].clock_info[0].sclk =
2723 rdev->clock.default_sclk;
2724 mode_index++;
2725 }
2726 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2727 if (mode_index) {
2728 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2729 non_clock_info);
2730 state_index++;
2731 }
2732 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2733 }
2734 /* if multiple clock modes, mark the lowest as no display */
2735 for (i = 0; i < state_index; i++) {
2736 if (rdev->pm.power_state[i].num_clock_modes > 1)
2737 rdev->pm.power_state[i].clock_info[0].flags |=
2738 RADEON_PM_MODE_NO_DISPLAY;
2739 }
2740 /* first mode is usually default */
2741 if (rdev->pm.default_power_state_index == -1) {
2742 rdev->pm.power_state[0].type =
2743 POWER_STATE_TYPE_DEFAULT;
2744 rdev->pm.default_power_state_index = 0;
2745 rdev->pm.power_state[0].default_clock_mode =
2746 &rdev->pm.power_state[0].clock_info[0];
2747 }
2748 return state_index;
2749}
2750
2751void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2752{
2753 struct radeon_mode_info *mode_info = &rdev->mode_info;
2754 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2755 u16 data_offset;
2756 u8 frev, crev;
2757 int state_index = 0;
2758
2759 rdev->pm.default_power_state_index = -1;
2760
2761 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2762 &frev, &crev, &data_offset)) {
2763 switch (frev) {
2764 case 1:
2765 case 2:
2766 case 3:
2767 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2768 break;
2769 case 4:
2770 case 5:
2771 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2772 break;
2773 case 6:
2774 state_index = radeon_atombios_parse_power_table_6(rdev);
2775 break;
2776 default:
2777 break;
2778 }
2779 }
2780
2781 if (state_index == 0) {
2782 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2783 if (rdev->pm.power_state) {
2784 rdev->pm.power_state[0].clock_info =
2785 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2786 if (rdev->pm.power_state[0].clock_info) {
2787 /* add the default mode */
2788 rdev->pm.power_state[state_index].type =
2789 POWER_STATE_TYPE_DEFAULT;
2790 rdev->pm.power_state[state_index].num_clock_modes = 1;
2791 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2792 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2793 rdev->pm.power_state[state_index].default_clock_mode =
2794 &rdev->pm.power_state[state_index].clock_info[0];
2795 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2796 rdev->pm.power_state[state_index].pcie_lanes = 16;
2797 rdev->pm.default_power_state_index = state_index;
2798 rdev->pm.power_state[state_index].flags = 0;
2799 state_index++;
2800 }
2801 }
2802 }
2803
2804 rdev->pm.num_power_states = state_index;
2805
2806 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2807 rdev->pm.current_clock_mode_index = 0;
2808 if (rdev->pm.default_power_state_index >= 0)
2809 rdev->pm.current_vddc =
2810 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2811 else
2812 rdev->pm.current_vddc = 0;
2813}
2814
2815union get_clock_dividers {
2816 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2817 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2818 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2819 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2820 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2821 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2822 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2823};
2824
2825int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2826 u8 clock_type,
2827 u32 clock,
2828 bool strobe_mode,
2829 struct atom_clock_dividers *dividers)
2830{
2831 union get_clock_dividers args;
2832 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2833 u8 frev, crev;
2834
2835 memset(&args, 0, sizeof(args));
2836 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2837
2838 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2839 return -EINVAL;
2840
2841 switch (crev) {
2842 case 1:
2843 /* r4xx, r5xx */
2844 args.v1.ucAction = clock_type;
2845 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2846
2847 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2848
2849 dividers->post_div = args.v1.ucPostDiv;
2850 dividers->fb_div = args.v1.ucFbDiv;
2851 dividers->enable_post_div = true;
2852 break;
2853 case 2:
2854 case 3:
2855 case 5:
2856 /* r6xx, r7xx, evergreen, ni, si */
2857 if (rdev->family <= CHIP_RV770) {
2858 args.v2.ucAction = clock_type;
2859 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2860
2861 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2862
2863 dividers->post_div = args.v2.ucPostDiv;
2864 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2865 dividers->ref_div = args.v2.ucAction;
2866 if (rdev->family == CHIP_RV770) {
2867 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2868 true : false;
2869 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2870 } else
2871 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2872 } else {
2873 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2874 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2875
2876 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2877
2878 dividers->post_div = args.v3.ucPostDiv;
2879 dividers->enable_post_div = (args.v3.ucCntlFlag &
2880 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2881 dividers->enable_dithen = (args.v3.ucCntlFlag &
2882 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2883 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2884 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2885 dividers->ref_div = args.v3.ucRefDiv;
2886 dividers->vco_mode = (args.v3.ucCntlFlag &
2887 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2888 } else {
2889 /* for SI we use ComputeMemoryClockParam for memory plls */
2890 if (rdev->family >= CHIP_TAHITI)
2891 return -EINVAL;
2892 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2893 if (strobe_mode)
2894 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2895
2896 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2897
2898 dividers->post_div = args.v5.ucPostDiv;
2899 dividers->enable_post_div = (args.v5.ucCntlFlag &
2900 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2901 dividers->enable_dithen = (args.v5.ucCntlFlag &
2902 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2903 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2904 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2905 dividers->ref_div = args.v5.ucRefDiv;
2906 dividers->vco_mode = (args.v5.ucCntlFlag &
2907 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2908 }
2909 }
2910 break;
2911 case 4:
2912 /* fusion */
2913 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2914
2915 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2916
2917 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2918 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2919 break;
2920 case 6:
2921 /* CI */
2922 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2923 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2924 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2925
2926 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2927
2928 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2929 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2930 dividers->ref_div = args.v6_out.ucPllRefDiv;
2931 dividers->post_div = args.v6_out.ucPllPostDiv;
2932 dividers->flags = args.v6_out.ucPllCntlFlag;
2933 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2934 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2935 break;
2936 default:
2937 return -EINVAL;
2938 }
2939 return 0;
2940}
2941
2942int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2943 u32 clock,
2944 bool strobe_mode,
2945 struct atom_mpll_param *mpll_param)
2946{
2947 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2948 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2949 u8 frev, crev;
2950
2951 memset(&args, 0, sizeof(args));
2952 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2953
2954 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2955 return -EINVAL;
2956
2957 switch (frev) {
2958 case 2:
2959 switch (crev) {
2960 case 1:
2961 /* SI */
2962 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2963 args.ucInputFlag = 0;
2964 if (strobe_mode)
2965 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2966
2967 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2968
2969 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2970 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2971 mpll_param->post_div = args.ucPostDiv;
2972 mpll_param->dll_speed = args.ucDllSpeed;
2973 mpll_param->bwcntl = args.ucBWCntl;
2974 mpll_param->vco_mode =
2975 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2976 mpll_param->yclk_sel =
2977 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2978 mpll_param->qdr =
2979 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2980 mpll_param->half_rate =
2981 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2982 break;
2983 default:
2984 return -EINVAL;
2985 }
2986 break;
2987 default:
2988 return -EINVAL;
2989 }
2990 return 0;
2991}
2992
2993void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2994{
2995 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2996 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2997
2998 args.ucEnable = enable;
2999
3000 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3001}
3002
3003uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3004{
3005 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3006 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3007
3008 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3009 return le32_to_cpu(args.ulReturnEngineClock);
3010}
3011
3012uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3013{
3014 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3015 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3016
3017 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3018 return le32_to_cpu(args.ulReturnMemoryClock);
3019}
3020
3021void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3022 uint32_t eng_clock)
3023{
3024 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3025 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3026
3027 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3028
3029 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3030}
3031
3032void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3033 uint32_t mem_clock)
3034{
3035 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3036 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3037
3038 if (rdev->flags & RADEON_IS_IGP)
3039 return;
3040
3041 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3042
3043 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3044}
3045
3046void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3047 u32 eng_clock, u32 mem_clock)
3048{
3049 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3050 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3051 u32 tmp;
3052
3053 memset(&args, 0, sizeof(args));
3054
3055 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3056 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3057
3058 args.ulTargetEngineClock = cpu_to_le32(tmp);
3059 if (mem_clock)
3060 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3061
3062 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3063}
3064
3065void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3066 u32 mem_clock)
3067{
3068 u32 args;
3069 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3070
3071 args = cpu_to_le32(mem_clock); /* 10 khz */
3072
3073 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3074}
3075
3076void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3077 u32 mem_clock)
3078{
3079 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3080 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3081 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3082
3083 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3084
3085 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3086}
3087
3088union set_voltage {
3089 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3090 struct _SET_VOLTAGE_PARAMETERS v1;
3091 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3092 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3093};
3094
3095void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3096{
3097 union set_voltage args;
3098 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3099 u8 frev, crev, volt_index = voltage_level;
3100
3101 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3102 return;
3103
3104 /* 0xff01 is a flag rather then an actual voltage */
3105 if (voltage_level == 0xff01)
3106 return;
3107
3108 switch (crev) {
3109 case 1:
3110 args.v1.ucVoltageType = voltage_type;
3111 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3112 args.v1.ucVoltageIndex = volt_index;
3113 break;
3114 case 2:
3115 args.v2.ucVoltageType = voltage_type;
3116 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3117 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3118 break;
3119 case 3:
3120 args.v3.ucVoltageType = voltage_type;
3121 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3122 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3123 break;
3124 default:
3125 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3126 return;
3127 }
3128
3129 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3130}
3131
3132int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3133 u16 voltage_id, u16 *voltage)
3134{
3135 union set_voltage args;
3136 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3137 u8 frev, crev;
3138
3139 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3140 return -EINVAL;
3141
3142 switch (crev) {
3143 case 1:
3144 return -EINVAL;
3145 case 2:
3146 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3147 args.v2.ucVoltageMode = 0;
3148 args.v2.usVoltageLevel = 0;
3149
3150 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3151
3152 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3153 break;
3154 case 3:
3155 args.v3.ucVoltageType = voltage_type;
3156 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3157 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3158
3159 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3160
3161 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3162 break;
3163 default:
3164 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3165 return -EINVAL;
3166 }
3167
3168 return 0;
3169}
3170
3171int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3172 u16 *voltage,
3173 u16 leakage_idx)
3174{
3175 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3176}
3177
3178int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3179 u16 *leakage_id)
3180{
3181 union set_voltage args;
3182 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3183 u8 frev, crev;
3184
3185 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3186 return -EINVAL;
3187
3188 switch (crev) {
3189 case 3:
3190 case 4:
3191 args.v3.ucVoltageType = 0;
3192 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3193 args.v3.usVoltageLevel = 0;
3194
3195 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3196
3197 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3198 break;
3199 default:
3200 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3201 return -EINVAL;
3202 }
3203
3204 return 0;
3205}
3206
3207int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3208 u16 *vddc, u16 *vddci,
3209 u16 virtual_voltage_id,
3210 u16 vbios_voltage_id)
3211{
3212 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3213 u8 frev, crev;
3214 u16 data_offset, size;
3215 int i, j;
3216 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3217 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3218
3219 *vddc = 0;
3220 *vddci = 0;
3221
3222 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3223 &frev, &crev, &data_offset))
3224 return -EINVAL;
3225
3226 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3227 (rdev->mode_info.atom_context->bios + data_offset);
3228
3229 switch (frev) {
3230 case 1:
3231 return -EINVAL;
3232 case 2:
3233 switch (crev) {
3234 case 1:
3235 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3236 return -EINVAL;
3237 leakage_bin = (u16 *)
3238 (rdev->mode_info.atom_context->bios + data_offset +
3239 le16_to_cpu(profile->usLeakageBinArrayOffset));
3240 vddc_id_buf = (u16 *)
3241 (rdev->mode_info.atom_context->bios + data_offset +
3242 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3243 vddc_buf = (u16 *)
3244 (rdev->mode_info.atom_context->bios + data_offset +
3245 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3246 vddci_id_buf = (u16 *)
3247 (rdev->mode_info.atom_context->bios + data_offset +
3248 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3249 vddci_buf = (u16 *)
3250 (rdev->mode_info.atom_context->bios + data_offset +
3251 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3252
3253 if (profile->ucElbVDDC_Num > 0) {
3254 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3255 if (vddc_id_buf[i] == virtual_voltage_id) {
3256 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3257 if (vbios_voltage_id <= leakage_bin[j]) {
3258 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3259 break;
3260 }
3261 }
3262 break;
3263 }
3264 }
3265 }
3266 if (profile->ucElbVDDCI_Num > 0) {
3267 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3268 if (vddci_id_buf[i] == virtual_voltage_id) {
3269 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3270 if (vbios_voltage_id <= leakage_bin[j]) {
3271 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3272 break;
3273 }
3274 }
3275 break;
3276 }
3277 }
3278 }
3279 break;
3280 default:
3281 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3282 return -EINVAL;
3283 }
3284 break;
3285 default:
3286 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3287 return -EINVAL;
3288 }
3289
3290 return 0;
3291}
3292
3293union get_voltage_info {
3294 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3295 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3296};
3297
3298int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3299 u16 virtual_voltage_id,
3300 u16 *voltage)
3301{
3302 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3303 u32 entry_id;
3304 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3305 union get_voltage_info args;
3306
3307 for (entry_id = 0; entry_id < count; entry_id++) {
3308 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3309 virtual_voltage_id)
3310 break;
3311 }
3312
3313 if (entry_id >= count)
3314 return -EINVAL;
3315
3316 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3317 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3318 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3319 args.in.ulSCLKFreq =
3320 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3321
3322 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3323
3324 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3325
3326 return 0;
3327}
3328
3329int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3330 u16 voltage_level, u8 voltage_type,
3331 u32 *gpio_value, u32 *gpio_mask)
3332{
3333 union set_voltage args;
3334 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3335 u8 frev, crev;
3336
3337 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3338 return -EINVAL;
3339
3340 switch (crev) {
3341 case 1:
3342 return -EINVAL;
3343 case 2:
3344 args.v2.ucVoltageType = voltage_type;
3345 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3346 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3347
3348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3349
3350 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3351
3352 args.v2.ucVoltageType = voltage_type;
3353 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3354 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3355
3356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3357
3358 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3359 break;
3360 default:
3361 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3362 return -EINVAL;
3363 }
3364
3365 return 0;
3366}
3367
3368union voltage_object_info {
3369 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3370 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3371 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3372};
3373
3374union voltage_object {
3375 struct _ATOM_VOLTAGE_OBJECT v1;
3376 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3377 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3378};
3379
3380static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3381 u8 voltage_type)
3382{
3383 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3384 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3385 u8 *start = (u8 *)v1;
3386
3387 while (offset < size) {
3388 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3389 if (vo->ucVoltageType == voltage_type)
3390 return vo;
3391 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3392 vo->asFormula.ucNumOfVoltageEntries;
3393 }
3394 return NULL;
3395}
3396
3397static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3398 u8 voltage_type)
3399{
3400 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3401 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3402 u8 *start = (u8*)v2;
3403
3404 while (offset < size) {
3405 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3406 if (vo->ucVoltageType == voltage_type)
3407 return vo;
3408 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3409 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3410 }
3411 return NULL;
3412}
3413
3414static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3415 u8 voltage_type, u8 voltage_mode)
3416{
3417 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3418 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3419 u8 *start = (u8*)v3;
3420
3421 while (offset < size) {
3422 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3423 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3424 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3425 return vo;
3426 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3427 }
3428 return NULL;
3429}
3430
3431bool
3432radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3433 u8 voltage_type, u8 voltage_mode)
3434{
3435 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3436 u8 frev, crev;
3437 u16 data_offset, size;
3438 union voltage_object_info *voltage_info;
3439 union voltage_object *voltage_object = NULL;
3440
3441 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3442 &frev, &crev, &data_offset)) {
3443 voltage_info = (union voltage_object_info *)
3444 (rdev->mode_info.atom_context->bios + data_offset);
3445
3446 switch (frev) {
3447 case 1:
3448 case 2:
3449 switch (crev) {
3450 case 1:
3451 voltage_object = (union voltage_object *)
3452 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3453 if (voltage_object &&
3454 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3455 return true;
3456 break;
3457 case 2:
3458 voltage_object = (union voltage_object *)
3459 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3460 if (voltage_object &&
3461 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3462 return true;
3463 break;
3464 default:
3465 DRM_ERROR("unknown voltage object table\n");
3466 return false;
3467 }
3468 break;
3469 case 3:
3470 switch (crev) {
3471 case 1:
3472 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3473 voltage_type, voltage_mode))
3474 return true;
3475 break;
3476 default:
3477 DRM_ERROR("unknown voltage object table\n");
3478 return false;
3479 }
3480 break;
3481 default:
3482 DRM_ERROR("unknown voltage object table\n");
3483 return false;
3484 }
3485
3486 }
3487 return false;
3488}
3489
3490int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3491 u8 voltage_type,
3492 u8 *svd_gpio_id, u8 *svc_gpio_id)
3493{
3494 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3495 u8 frev, crev;
3496 u16 data_offset, size;
3497 union voltage_object_info *voltage_info;
3498 union voltage_object *voltage_object = NULL;
3499
3500 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3501 &frev, &crev, &data_offset)) {
3502 voltage_info = (union voltage_object_info *)
3503 (rdev->mode_info.atom_context->bios + data_offset);
3504
3505 switch (frev) {
3506 case 3:
3507 switch (crev) {
3508 case 1:
3509 voltage_object = (union voltage_object *)
3510 atom_lookup_voltage_object_v3(&voltage_info->v3,
3511 voltage_type,
3512 VOLTAGE_OBJ_SVID2);
3513 if (voltage_object) {
3514 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3515 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3516 } else {
3517 return -EINVAL;
3518 }
3519 break;
3520 default:
3521 DRM_ERROR("unknown voltage object table\n");
3522 return -EINVAL;
3523 }
3524 break;
3525 default:
3526 DRM_ERROR("unknown voltage object table\n");
3527 return -EINVAL;
3528 }
3529
3530 }
3531 return 0;
3532}
3533
3534int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3535 u8 voltage_type, u16 *max_voltage)
3536{
3537 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3538 u8 frev, crev;
3539 u16 data_offset, size;
3540 union voltage_object_info *voltage_info;
3541 union voltage_object *voltage_object = NULL;
3542
3543 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3544 &frev, &crev, &data_offset)) {
3545 voltage_info = (union voltage_object_info *)
3546 (rdev->mode_info.atom_context->bios + data_offset);
3547
3548 switch (crev) {
3549 case 1:
3550 voltage_object = (union voltage_object *)
3551 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3552 if (voltage_object) {
3553 ATOM_VOLTAGE_FORMULA *formula =
3554 &voltage_object->v1.asFormula;
3555 if (formula->ucFlag & 1)
3556 *max_voltage =
3557 le16_to_cpu(formula->usVoltageBaseLevel) +
3558 formula->ucNumOfVoltageEntries / 2 *
3559 le16_to_cpu(formula->usVoltageStep);
3560 else
3561 *max_voltage =
3562 le16_to_cpu(formula->usVoltageBaseLevel) +
3563 (formula->ucNumOfVoltageEntries - 1) *
3564 le16_to_cpu(formula->usVoltageStep);
3565 return 0;
3566 }
3567 break;
3568 case 2:
3569 voltage_object = (union voltage_object *)
3570 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3571 if (voltage_object) {
3572 ATOM_VOLTAGE_FORMULA_V2 *formula =
3573 &voltage_object->v2.asFormula;
3574 if (formula->ucNumOfVoltageEntries) {
3575 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3576 ((u8 *)&formula->asVIDAdjustEntries[0] +
3577 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3578 *max_voltage =
3579 le16_to_cpu(lut->usVoltageValue);
3580 return 0;
3581 }
3582 }
3583 break;
3584 default:
3585 DRM_ERROR("unknown voltage object table\n");
3586 return -EINVAL;
3587 }
3588
3589 }
3590 return -EINVAL;
3591}
3592
3593int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3594 u8 voltage_type, u16 *min_voltage)
3595{
3596 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3597 u8 frev, crev;
3598 u16 data_offset, size;
3599 union voltage_object_info *voltage_info;
3600 union voltage_object *voltage_object = NULL;
3601
3602 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3603 &frev, &crev, &data_offset)) {
3604 voltage_info = (union voltage_object_info *)
3605 (rdev->mode_info.atom_context->bios + data_offset);
3606
3607 switch (crev) {
3608 case 1:
3609 voltage_object = (union voltage_object *)
3610 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3611 if (voltage_object) {
3612 ATOM_VOLTAGE_FORMULA *formula =
3613 &voltage_object->v1.asFormula;
3614 *min_voltage =
3615 le16_to_cpu(formula->usVoltageBaseLevel);
3616 return 0;
3617 }
3618 break;
3619 case 2:
3620 voltage_object = (union voltage_object *)
3621 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3622 if (voltage_object) {
3623 ATOM_VOLTAGE_FORMULA_V2 *formula =
3624 &voltage_object->v2.asFormula;
3625 if (formula->ucNumOfVoltageEntries) {
3626 *min_voltage =
3627 le16_to_cpu(formula->asVIDAdjustEntries[
3628 0
3629 ].usVoltageValue);
3630 return 0;
3631 }
3632 }
3633 break;
3634 default:
3635 DRM_ERROR("unknown voltage object table\n");
3636 return -EINVAL;
3637 }
3638
3639 }
3640 return -EINVAL;
3641}
3642
3643int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3644 u8 voltage_type, u16 *voltage_step)
3645{
3646 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3647 u8 frev, crev;
3648 u16 data_offset, size;
3649 union voltage_object_info *voltage_info;
3650 union voltage_object *voltage_object = NULL;
3651
3652 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3653 &frev, &crev, &data_offset)) {
3654 voltage_info = (union voltage_object_info *)
3655 (rdev->mode_info.atom_context->bios + data_offset);
3656
3657 switch (crev) {
3658 case 1:
3659 voltage_object = (union voltage_object *)
3660 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3661 if (voltage_object) {
3662 ATOM_VOLTAGE_FORMULA *formula =
3663 &voltage_object->v1.asFormula;
3664 if (formula->ucFlag & 1)
3665 *voltage_step =
3666 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3667 else
3668 *voltage_step =
3669 le16_to_cpu(formula->usVoltageStep);
3670 return 0;
3671 }
3672 break;
3673 case 2:
3674 return -EINVAL;
3675 default:
3676 DRM_ERROR("unknown voltage object table\n");
3677 return -EINVAL;
3678 }
3679
3680 }
3681 return -EINVAL;
3682}
3683
3684int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3685 u8 voltage_type,
3686 u16 nominal_voltage,
3687 u16 *true_voltage)
3688{
3689 u16 min_voltage, max_voltage, voltage_step;
3690
3691 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3692 return -EINVAL;
3693 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3694 return -EINVAL;
3695 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3696 return -EINVAL;
3697
3698 if (nominal_voltage <= min_voltage)
3699 *true_voltage = min_voltage;
3700 else if (nominal_voltage >= max_voltage)
3701 *true_voltage = max_voltage;
3702 else
3703 *true_voltage = min_voltage +
3704 ((nominal_voltage - min_voltage) / voltage_step) *
3705 voltage_step;
3706
3707 return 0;
3708}
3709
3710int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3711 u8 voltage_type, u8 voltage_mode,
3712 struct atom_voltage_table *voltage_table)
3713{
3714 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3715 u8 frev, crev;
3716 u16 data_offset, size;
3717 int i, ret;
3718 union voltage_object_info *voltage_info;
3719 union voltage_object *voltage_object = NULL;
3720
3721 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3722 &frev, &crev, &data_offset)) {
3723 voltage_info = (union voltage_object_info *)
3724 (rdev->mode_info.atom_context->bios + data_offset);
3725
3726 switch (frev) {
3727 case 1:
3728 case 2:
3729 switch (crev) {
3730 case 1:
3731 DRM_ERROR("old table version %d, %d\n", frev, crev);
3732 return -EINVAL;
3733 case 2:
3734 voltage_object = (union voltage_object *)
3735 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3736 if (voltage_object) {
3737 ATOM_VOLTAGE_FORMULA_V2 *formula =
3738 &voltage_object->v2.asFormula;
3739 VOLTAGE_LUT_ENTRY *lut;
3740 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3741 return -EINVAL;
3742 lut = &formula->asVIDAdjustEntries[0];
3743 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3744 voltage_table->entries[i].value =
3745 le16_to_cpu(lut->usVoltageValue);
3746 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3747 voltage_table->entries[i].value,
3748 voltage_type,
3749 &voltage_table->entries[i].smio_low,
3750 &voltage_table->mask_low);
3751 if (ret)
3752 return ret;
3753 lut = (VOLTAGE_LUT_ENTRY *)
3754 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3755 }
3756 voltage_table->count = formula->ucNumOfVoltageEntries;
3757 return 0;
3758 }
3759 break;
3760 default:
3761 DRM_ERROR("unknown voltage object table\n");
3762 return -EINVAL;
3763 }
3764 break;
3765 case 3:
3766 switch (crev) {
3767 case 1:
3768 voltage_object = (union voltage_object *)
3769 atom_lookup_voltage_object_v3(&voltage_info->v3,
3770 voltage_type, voltage_mode);
3771 if (voltage_object) {
3772 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3773 &voltage_object->v3.asGpioVoltageObj;
3774 VOLTAGE_LUT_ENTRY_V2 *lut;
3775 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3776 return -EINVAL;
3777 lut = &gpio->asVolGpioLut[0];
3778 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3779 voltage_table->entries[i].value =
3780 le16_to_cpu(lut->usVoltageValue);
3781 voltage_table->entries[i].smio_low =
3782 le32_to_cpu(lut->ulVoltageId);
3783 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3784 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3785 }
3786 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3787 voltage_table->count = gpio->ucGpioEntryNum;
3788 voltage_table->phase_delay = gpio->ucPhaseDelay;
3789 return 0;
3790 }
3791 break;
3792 default:
3793 DRM_ERROR("unknown voltage object table\n");
3794 return -EINVAL;
3795 }
3796 break;
3797 default:
3798 DRM_ERROR("unknown voltage object table\n");
3799 return -EINVAL;
3800 }
3801 }
3802 return -EINVAL;
3803}
3804
3805union vram_info {
3806 struct _ATOM_VRAM_INFO_V3 v1_3;
3807 struct _ATOM_VRAM_INFO_V4 v1_4;
3808 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3809};
3810
3811int radeon_atom_get_memory_info(struct radeon_device *rdev,
3812 u8 module_index, struct atom_memory_info *mem_info)
3813{
3814 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3815 u8 frev, crev, i;
3816 u16 data_offset, size;
3817 union vram_info *vram_info;
3818
3819 memset(mem_info, 0, sizeof(struct atom_memory_info));
3820
3821 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3822 &frev, &crev, &data_offset)) {
3823 vram_info = (union vram_info *)
3824 (rdev->mode_info.atom_context->bios + data_offset);
3825 switch (frev) {
3826 case 1:
3827 switch (crev) {
3828 case 3:
3829 /* r6xx */
3830 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3831 ATOM_VRAM_MODULE_V3 *vram_module =
3832 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3833
3834 for (i = 0; i < module_index; i++) {
3835 if (le16_to_cpu(vram_module->usSize) == 0)
3836 return -EINVAL;
3837 vram_module = (ATOM_VRAM_MODULE_V3 *)
3838 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3839 }
3840 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3841 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3842 } else
3843 return -EINVAL;
3844 break;
3845 case 4:
3846 /* r7xx, evergreen */
3847 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3848 ATOM_VRAM_MODULE_V4 *vram_module =
3849 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3850
3851 for (i = 0; i < module_index; i++) {
3852 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3853 return -EINVAL;
3854 vram_module = (ATOM_VRAM_MODULE_V4 *)
3855 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3856 }
3857 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3858 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3859 } else
3860 return -EINVAL;
3861 break;
3862 default:
3863 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3864 return -EINVAL;
3865 }
3866 break;
3867 case 2:
3868 switch (crev) {
3869 case 1:
3870 /* ni */
3871 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3872 ATOM_VRAM_MODULE_V7 *vram_module =
3873 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3874
3875 for (i = 0; i < module_index; i++) {
3876 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3877 return -EINVAL;
3878 vram_module = (ATOM_VRAM_MODULE_V7 *)
3879 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3880 }
3881 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3882 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3883 } else
3884 return -EINVAL;
3885 break;
3886 default:
3887 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3888 return -EINVAL;
3889 }
3890 break;
3891 default:
3892 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3893 return -EINVAL;
3894 }
3895 return 0;
3896 }
3897 return -EINVAL;
3898}
3899
3900int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3901 bool gddr5, u8 module_index,
3902 struct atom_memory_clock_range_table *mclk_range_table)
3903{
3904 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3905 u8 frev, crev, i;
3906 u16 data_offset, size;
3907 union vram_info *vram_info;
3908 u32 mem_timing_size = gddr5 ?
3909 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3910
3911 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3912
3913 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3914 &frev, &crev, &data_offset)) {
3915 vram_info = (union vram_info *)
3916 (rdev->mode_info.atom_context->bios + data_offset);
3917 switch (frev) {
3918 case 1:
3919 switch (crev) {
3920 case 3:
3921 DRM_ERROR("old table version %d, %d\n", frev, crev);
3922 return -EINVAL;
3923 case 4:
3924 /* r7xx, evergreen */
3925 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3926 ATOM_VRAM_MODULE_V4 *vram_module =
3927 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3928 ATOM_MEMORY_TIMING_FORMAT *format;
3929
3930 for (i = 0; i < module_index; i++) {
3931 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3932 return -EINVAL;
3933 vram_module = (ATOM_VRAM_MODULE_V4 *)
3934 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3935 }
3936 mclk_range_table->num_entries = (u8)
3937 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3938 mem_timing_size);
3939 format = &vram_module->asMemTiming[0];
3940 for (i = 0; i < mclk_range_table->num_entries; i++) {
3941 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3942 format = (ATOM_MEMORY_TIMING_FORMAT *)
3943 ((u8 *)format + mem_timing_size);
3944 }
3945 } else
3946 return -EINVAL;
3947 break;
3948 default:
3949 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3950 return -EINVAL;
3951 }
3952 break;
3953 case 2:
3954 DRM_ERROR("new table version %d, %d\n", frev, crev);
3955 return -EINVAL;
3956 default:
3957 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3958 return -EINVAL;
3959 }
3960 return 0;
3961 }
3962 return -EINVAL;
3963}
3964
3965#define MEM_ID_MASK 0xff000000
3966#define MEM_ID_SHIFT 24
3967#define CLOCK_RANGE_MASK 0x00ffffff
3968#define CLOCK_RANGE_SHIFT 0
3969#define LOW_NIBBLE_MASK 0xf
3970#define DATA_EQU_PREV 0
3971#define DATA_FROM_TABLE 4
3972
3973int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3974 u8 module_index,
3975 struct atom_mc_reg_table *reg_table)
3976{
3977 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3978 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3979 u32 i = 0, j;
3980 u16 data_offset, size;
3981 union vram_info *vram_info;
3982
3983 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3984
3985 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3986 &frev, &crev, &data_offset)) {
3987 vram_info = (union vram_info *)
3988 (rdev->mode_info.atom_context->bios + data_offset);
3989 switch (frev) {
3990 case 1:
3991 DRM_ERROR("old table version %d, %d\n", frev, crev);
3992 return -EINVAL;
3993 case 2:
3994 switch (crev) {
3995 case 1:
3996 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3997 ATOM_INIT_REG_BLOCK *reg_block =
3998 (ATOM_INIT_REG_BLOCK *)
3999 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4000 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4001 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4002 ((u8 *)reg_block + (2 * sizeof(u16)) +
4003 le16_to_cpu(reg_block->usRegIndexTblSize));
4004 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4005 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4006 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4007 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4008 return -EINVAL;
4009 while (i < num_entries) {
4010 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4011 break;
4012 reg_table->mc_reg_address[i].s1 =
4013 (u16)(le16_to_cpu(format->usRegIndex));
4014 reg_table->mc_reg_address[i].pre_reg_data =
4015 (u8)(format->ucPreRegDataLength);
4016 i++;
4017 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4018 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4019 }
4020 reg_table->last = i;
4021 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4022 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4023 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4024 >> MEM_ID_SHIFT);
4025 if (module_index == t_mem_id) {
4026 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4027 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4028 >> CLOCK_RANGE_SHIFT);
4029 for (i = 0, j = 1; i < reg_table->last; i++) {
4030 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4031 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4032 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4033 j++;
4034 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4035 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4036 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4037 }
4038 }
4039 num_ranges++;
4040 }
4041 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4042 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4043 }
4044 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4045 return -EINVAL;
4046 reg_table->num_entries = num_ranges;
4047 } else
4048 return -EINVAL;
4049 break;
4050 default:
4051 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4052 return -EINVAL;
4053 }
4054 break;
4055 default:
4056 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4057 return -EINVAL;
4058 }
4059 return 0;
4060 }
4061 return -EINVAL;
4062}
4063
4064void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4065{
4066 struct radeon_device *rdev = dev->dev_private;
4067 uint32_t bios_2_scratch, bios_6_scratch;
4068
4069 if (rdev->family >= CHIP_R600) {
4070 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4071 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4072 } else {
4073 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4074 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4075 }
4076
4077 /* let the bios control the backlight */
4078 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4079
4080 /* tell the bios not to handle mode switching */
4081 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4082
4083 /* clear the vbios dpms state */
4084 if (ASIC_IS_DCE4(rdev))
4085 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4086
4087 if (rdev->family >= CHIP_R600) {
4088 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4089 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4090 } else {
4091 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4092 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4093 }
4094
4095}
4096
4097void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4098{
4099 uint32_t scratch_reg;
4100 int i;
4101
4102 if (rdev->family >= CHIP_R600)
4103 scratch_reg = R600_BIOS_0_SCRATCH;
4104 else
4105 scratch_reg = RADEON_BIOS_0_SCRATCH;
4106
4107 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4108 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4109}
4110
4111void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4112{
4113 uint32_t scratch_reg;
4114 int i;
4115
4116 if (rdev->family >= CHIP_R600)
4117 scratch_reg = R600_BIOS_0_SCRATCH;
4118 else
4119 scratch_reg = RADEON_BIOS_0_SCRATCH;
4120
4121 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4122 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4123}
4124
4125void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4126{
4127 struct drm_device *dev = encoder->dev;
4128 struct radeon_device *rdev = dev->dev_private;
4129 uint32_t bios_6_scratch;
4130
4131 if (rdev->family >= CHIP_R600)
4132 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4133 else
4134 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4135
4136 if (lock) {
4137 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4138 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4139 } else {
4140 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4141 bios_6_scratch |= ATOM_S6_ACC_MODE;
4142 }
4143
4144 if (rdev->family >= CHIP_R600)
4145 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4146 else
4147 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4148}
4149
4150/* at some point we may want to break this out into individual functions */
4151void
4152radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4153 struct drm_encoder *encoder,
4154 bool connected)
4155{
4156 struct drm_device *dev = connector->dev;
4157 struct radeon_device *rdev = dev->dev_private;
4158 struct radeon_connector *radeon_connector =
4159 to_radeon_connector(connector);
4160 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4161 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4162
4163 if (rdev->family >= CHIP_R600) {
4164 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4165 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4166 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4167 } else {
4168 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4169 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4170 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4171 }
4172
4173 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4174 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4175 if (connected) {
4176 DRM_DEBUG_KMS("TV1 connected\n");
4177 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4178 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4179 } else {
4180 DRM_DEBUG_KMS("TV1 disconnected\n");
4181 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4182 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4183 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4184 }
4185 }
4186 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4187 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4188 if (connected) {
4189 DRM_DEBUG_KMS("CV connected\n");
4190 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4191 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4192 } else {
4193 DRM_DEBUG_KMS("CV disconnected\n");
4194 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4195 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4196 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4197 }
4198 }
4199 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4200 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4201 if (connected) {
4202 DRM_DEBUG_KMS("LCD1 connected\n");
4203 bios_0_scratch |= ATOM_S0_LCD1;
4204 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4205 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4206 } else {
4207 DRM_DEBUG_KMS("LCD1 disconnected\n");
4208 bios_0_scratch &= ~ATOM_S0_LCD1;
4209 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4210 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4211 }
4212 }
4213 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4214 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4215 if (connected) {
4216 DRM_DEBUG_KMS("CRT1 connected\n");
4217 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4218 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4219 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4220 } else {
4221 DRM_DEBUG_KMS("CRT1 disconnected\n");
4222 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4223 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4224 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4225 }
4226 }
4227 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4228 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4229 if (connected) {
4230 DRM_DEBUG_KMS("CRT2 connected\n");
4231 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4232 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4233 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4234 } else {
4235 DRM_DEBUG_KMS("CRT2 disconnected\n");
4236 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4237 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4238 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4239 }
4240 }
4241 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4242 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4243 if (connected) {
4244 DRM_DEBUG_KMS("DFP1 connected\n");
4245 bios_0_scratch |= ATOM_S0_DFP1;
4246 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4247 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4248 } else {
4249 DRM_DEBUG_KMS("DFP1 disconnected\n");
4250 bios_0_scratch &= ~ATOM_S0_DFP1;
4251 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4252 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4253 }
4254 }
4255 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4256 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4257 if (connected) {
4258 DRM_DEBUG_KMS("DFP2 connected\n");
4259 bios_0_scratch |= ATOM_S0_DFP2;
4260 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4261 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4262 } else {
4263 DRM_DEBUG_KMS("DFP2 disconnected\n");
4264 bios_0_scratch &= ~ATOM_S0_DFP2;
4265 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4266 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4267 }
4268 }
4269 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4270 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4271 if (connected) {
4272 DRM_DEBUG_KMS("DFP3 connected\n");
4273 bios_0_scratch |= ATOM_S0_DFP3;
4274 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4275 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4276 } else {
4277 DRM_DEBUG_KMS("DFP3 disconnected\n");
4278 bios_0_scratch &= ~ATOM_S0_DFP3;
4279 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4280 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4281 }
4282 }
4283 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4284 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4285 if (connected) {
4286 DRM_DEBUG_KMS("DFP4 connected\n");
4287 bios_0_scratch |= ATOM_S0_DFP4;
4288 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4289 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4290 } else {
4291 DRM_DEBUG_KMS("DFP4 disconnected\n");
4292 bios_0_scratch &= ~ATOM_S0_DFP4;
4293 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4294 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4295 }
4296 }
4297 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4298 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4299 if (connected) {
4300 DRM_DEBUG_KMS("DFP5 connected\n");
4301 bios_0_scratch |= ATOM_S0_DFP5;
4302 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4303 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4304 } else {
4305 DRM_DEBUG_KMS("DFP5 disconnected\n");
4306 bios_0_scratch &= ~ATOM_S0_DFP5;
4307 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4308 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4309 }
4310 }
4311 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4312 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4313 if (connected) {
4314 DRM_DEBUG_KMS("DFP6 connected\n");
4315 bios_0_scratch |= ATOM_S0_DFP6;
4316 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4317 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4318 } else {
4319 DRM_DEBUG_KMS("DFP6 disconnected\n");
4320 bios_0_scratch &= ~ATOM_S0_DFP6;
4321 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4322 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4323 }
4324 }
4325
4326 if (rdev->family >= CHIP_R600) {
4327 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4328 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4329 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4330 } else {
4331 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4332 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4333 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4334 }
4335}
4336
4337void
4338radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4339{
4340 struct drm_device *dev = encoder->dev;
4341 struct radeon_device *rdev = dev->dev_private;
4342 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4343 uint32_t bios_3_scratch;
4344
4345 if (ASIC_IS_DCE4(rdev))
4346 return;
4347
4348 if (rdev->family >= CHIP_R600)
4349 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4350 else
4351 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4352
4353 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4354 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4355 bios_3_scratch |= (crtc << 18);
4356 }
4357 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4358 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4359 bios_3_scratch |= (crtc << 24);
4360 }
4361 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4362 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4363 bios_3_scratch |= (crtc << 16);
4364 }
4365 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4366 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4367 bios_3_scratch |= (crtc << 20);
4368 }
4369 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4370 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4371 bios_3_scratch |= (crtc << 17);
4372 }
4373 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4374 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4375 bios_3_scratch |= (crtc << 19);
4376 }
4377 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4378 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4379 bios_3_scratch |= (crtc << 23);
4380 }
4381 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4382 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4383 bios_3_scratch |= (crtc << 25);
4384 }
4385
4386 if (rdev->family >= CHIP_R600)
4387 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4388 else
4389 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4390}
4391
4392void
4393radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4394{
4395 struct drm_device *dev = encoder->dev;
4396 struct radeon_device *rdev = dev->dev_private;
4397 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4398 uint32_t bios_2_scratch;
4399
4400 if (ASIC_IS_DCE4(rdev))
4401 return;
4402
4403 if (rdev->family >= CHIP_R600)
4404 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4405 else
4406 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4407
4408 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4409 if (on)
4410 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4411 else
4412 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4413 }
4414 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4415 if (on)
4416 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4417 else
4418 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4419 }
4420 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4421 if (on)
4422 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4423 else
4424 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4425 }
4426 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4427 if (on)
4428 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4429 else
4430 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4431 }
4432 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4433 if (on)
4434 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4435 else
4436 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4437 }
4438 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4439 if (on)
4440 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4441 else
4442 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4443 }
4444 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4445 if (on)
4446 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4447 else
4448 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4449 }
4450 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4451 if (on)
4452 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4453 else
4454 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4455 }
4456 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4457 if (on)
4458 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4459 else
4460 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4461 }
4462 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4463 if (on)
4464 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4465 else
4466 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4467 }
4468
4469 if (rdev->family >= CHIP_R600)
4470 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4471 else
4472 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4473}