1/*
  2 * Copyright 2010 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Ben Skeggs
 23 */
 24
 25#include "drmP.h"
 26#include "nouveau_drv.h"
 27#include "nouveau_bios.h"
 28#include "nouveau_pm.h"
 29
 30/* This is actually a lot more complex than it appears here, but hopefully
 31 * this should be able to deal with what the VBIOS leaves for us..
 32 *
 33 * If not, well, I'll jump off that bridge when I come to it.
 34 */
 35
 36struct nva3_pm_state {
 37	enum pll_types type;
 38	u32 src0;
 39	u32 src1;
 40	u32 ctrl;
 41	u32 coef;
 42	u32 old_pnm;
 43	u32 new_pnm;
 44	u32 new_div;
 45};
 46
 47static int
 48nva3_pm_pll_offset(u32 id)
 49{
 50	static const u32 pll_map[] = {
 51		0x00, PLL_CORE,
 52		0x01, PLL_SHADER,
 53		0x02, PLL_MEMORY,
 54		0x00, 0x00
 55	};
 56	const u32 *map = pll_map;
 57
 58	while (map[1]) {
 59		if (id == map[1])
 60			return map[0];
 61		map += 2;
 62	}
 63
 64	return -ENOENT;
 65}
 66
 67int
 68nva3_pm_clock_get(struct drm_device *dev, u32 id)
 69{
 70	u32 src0, src1, ctrl, coef;
 71	struct pll_lims pll;
 72	int ret, off;
 73	int P, N, M;
 74
 75	ret = get_pll_limits(dev, id, &pll);
 76	if (ret)
 77		return ret;
 78
 79	off = nva3_pm_pll_offset(id);
 80	if (off < 0)
 81		return off;
 82
 83	src0 = nv_rd32(dev, 0x4120 + (off * 4));
 84	src1 = nv_rd32(dev, 0x4160 + (off * 4));
 85	ctrl = nv_rd32(dev, pll.reg + 0);
 86	coef = nv_rd32(dev, pll.reg + 4);
 87	NV_DEBUG(dev, "PLL %02x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 88		      id, src0, src1, ctrl, coef);
 89
 90	if (ctrl & 0x00000008) {
 91		u32 div = ((src1 & 0x003c0000) >> 18) + 1;
 92		return (pll.refclk * 2) / div;
 93	}
 94
 95	P = (coef & 0x003f0000) >> 16;
 96	N = (coef & 0x0000ff00) >> 8;
 97	M = (coef & 0x000000ff);
 98	return pll.refclk * N / M / P;
 99}
100
101void *
102nva3_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
103		  u32 id, int khz)
104{
105	struct nva3_pm_state *pll;
106	struct pll_lims limits;
107	int N, M, P, diff;
108	int ret, off;
109
110	ret = get_pll_limits(dev, id, &limits);
111	if (ret < 0)
112		return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
113
114	off = nva3_pm_pll_offset(id);
115	if (id < 0)
116		return ERR_PTR(-EINVAL);
117
118
119	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
120	if (!pll)
121		return ERR_PTR(-ENOMEM);
122	pll->type = id;
123	pll->src0 = 0x004120 + (off * 4);
124	pll->src1 = 0x004160 + (off * 4);
125	pll->ctrl = limits.reg + 0;
126	pll->coef = limits.reg + 4;
127
128	/* If target clock is within [-2, 3) MHz of a divisor, we'll
129	 * use that instead of calculating MNP values
130	 */
131	pll->new_div = min((limits.refclk * 2) / (khz - 2999), 16);
132	if (pll->new_div) {
133		diff = khz - ((limits.refclk * 2) / pll->new_div);
134		if (diff < -2000 || diff >= 3000)
135			pll->new_div = 0;
136	}
137
138	if (!pll->new_div) {
139		ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
140		if (ret < 0)
141			return ERR_PTR(ret);
142
143		pll->new_pnm = (P << 16) | (N << 8) | M;
144		pll->new_div = 2 - 1;
145	} else {
146		pll->new_pnm = 0;
147		pll->new_div--;
148	}
149
150	if ((nv_rd32(dev, pll->src1) & 0x00000101) != 0x00000101)
151		pll->old_pnm = nv_rd32(dev, pll->coef);
152	return pll;
153}
154
155void
156nva3_pm_clock_set(struct drm_device *dev, void *pre_state)
157{
158	struct nva3_pm_state *pll = pre_state;
159	u32 ctrl = 0;
160
161	/* For the memory clock, NVIDIA will build a "script" describing
162	 * the reclocking process and ask PDAEMON to execute it.
163	 */
164	if (pll->type == PLL_MEMORY) {
165		nv_wr32(dev, 0x100210, 0);
166		nv_wr32(dev, 0x1002dc, 1);
167		nv_wr32(dev, 0x004018, 0x00001000);
168		ctrl = 0x18000100;
169	}
170
171	if (pll->old_pnm || !pll->new_pnm) {
172		nv_mask(dev, pll->src1, 0x003c0101, 0x00000101 |
173						    (pll->new_div << 18));
174		nv_wr32(dev, pll->ctrl, 0x0001001d | ctrl);
175		nv_mask(dev, pll->ctrl, 0x00000001, 0x00000000);
176	}
177
178	if (pll->new_pnm) {
179		nv_mask(dev, pll->src0, 0x00000101, 0x00000101);
180		nv_wr32(dev, pll->coef, pll->new_pnm);
181		nv_wr32(dev, pll->ctrl, 0x0001001d | ctrl);
182		nv_mask(dev, pll->ctrl, 0x00000010, 0x00000000);
183		nv_mask(dev, pll->ctrl, 0x00020010, 0x00020010);
184		nv_wr32(dev, pll->ctrl, 0x00010015 | ctrl);
185		nv_mask(dev, pll->src1, 0x00000100, 0x00000000);
186		nv_mask(dev, pll->src1, 0x00000001, 0x00000000);
187		if (pll->type == PLL_MEMORY)
188			nv_wr32(dev, 0x4018, 0x10005000);
189	} else {
190		nv_mask(dev, pll->ctrl, 0x00000001, 0x00000000);
191		nv_mask(dev, pll->src0, 0x00000100, 0x00000000);
192		nv_mask(dev, pll->src0, 0x00000001, 0x00000000);
193		if (pll->type == PLL_MEMORY)
194			nv_wr32(dev, 0x4018, 0x1000d000);
195	}
196
197	if (pll->type == PLL_MEMORY) {
198		nv_wr32(dev, 0x1002dc, 0);
199		nv_wr32(dev, 0x100210, 0x80000000);
200	}
201
202	kfree(pll);
203}
204