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1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/delay.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21#include <linux/phy/phy.h>
22
23#define MIPITX_DSI_CON 0x00
24#define RG_DSI_LDOCORE_EN BIT(0)
25#define RG_DSI_CKG_LDOOUT_EN BIT(1)
26#define RG_DSI_BCLK_SEL (3 << 2)
27#define RG_DSI_LD_IDX_SEL (7 << 4)
28#define RG_DSI_PHYCLK_SEL (2 << 8)
29#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
30#define RG_DSI_LPTX_CLMP_EN BIT(11)
31
32#define MIPITX_DSI_CLOCK_LANE 0x04
33#define MIPITX_DSI_DATA_LANE0 0x08
34#define MIPITX_DSI_DATA_LANE1 0x0c
35#define MIPITX_DSI_DATA_LANE2 0x10
36#define MIPITX_DSI_DATA_LANE3 0x14
37#define RG_DSI_LNTx_LDOOUT_EN BIT(0)
38#define RG_DSI_LNTx_CKLANE_EN BIT(1)
39#define RG_DSI_LNTx_LPTX_IPLUS1 BIT(2)
40#define RG_DSI_LNTx_LPTX_IPLUS2 BIT(3)
41#define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
42#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
43#define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
44#define RG_DSI_LNTx_RT_CODE (0xf << 8)
45
46#define MIPITX_DSI_TOP_CON 0x40
47#define RG_DSI_LNT_INTR_EN BIT(0)
48#define RG_DSI_LNT_HS_BIAS_EN BIT(1)
49#define RG_DSI_LNT_IMP_CAL_EN BIT(2)
50#define RG_DSI_LNT_TESTMODE_EN BIT(3)
51#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
52#define RG_DSI_LNT_AIO_SEL (7 << 8)
53#define RG_DSI_PAD_TIE_LOW_EN BIT(11)
54#define RG_DSI_DEBUG_INPUT_EN BIT(12)
55#define RG_DSI_PRESERVE (7 << 13)
56
57#define MIPITX_DSI_BG_CON 0x44
58#define RG_DSI_BG_CORE_EN BIT(0)
59#define RG_DSI_BG_CKEN BIT(1)
60#define RG_DSI_BG_DIV (0x3 << 2)
61#define RG_DSI_BG_FAST_CHARGE BIT(4)
62#define RG_DSI_VOUT_MSK (0x3ffff << 5)
63#define RG_DSI_V12_SEL (7 << 5)
64#define RG_DSI_V10_SEL (7 << 8)
65#define RG_DSI_V072_SEL (7 << 11)
66#define RG_DSI_V04_SEL (7 << 14)
67#define RG_DSI_V032_SEL (7 << 17)
68#define RG_DSI_V02_SEL (7 << 20)
69#define RG_DSI_BG_R1_TRIM (0xf << 24)
70#define RG_DSI_BG_R2_TRIM (0xf << 28)
71
72#define MIPITX_DSI_PLL_CON0 0x50
73#define RG_DSI_MPPLL_PLL_EN BIT(0)
74#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
75#define RG_DSI_MPPLL_PREDIV (3 << 1)
76#define RG_DSI_MPPLL_TXDIV0 (3 << 3)
77#define RG_DSI_MPPLL_TXDIV1 (3 << 5)
78#define RG_DSI_MPPLL_POSDIV (7 << 7)
79#define RG_DSI_MPPLL_MONVC_EN BIT(10)
80#define RG_DSI_MPPLL_MONREF_EN BIT(11)
81#define RG_DSI_MPPLL_VOD_EN BIT(12)
82
83#define MIPITX_DSI_PLL_CON1 0x54
84#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
85#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
86#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
87#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
88
89#define MIPITX_DSI_PLL_CON2 0x58
90
91#define MIPITX_DSI_PLL_TOP 0x64
92#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
93
94#define MIPITX_DSI_PLL_PWR 0x68
95#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
96#define RG_DSI_MPPLL_SDM_ISO_EN BIT(1)
97#define RG_DSI_MPPLL_SDM_PWR_ACK BIT(8)
98
99#define MIPITX_DSI_SW_CTRL 0x80
100#define SW_CTRL_EN BIT(0)
101
102#define MIPITX_DSI_SW_CTRL_CON0 0x84
103#define SW_LNTC_LPTX_PRE_OE BIT(0)
104#define SW_LNTC_LPTX_OE BIT(1)
105#define SW_LNTC_LPTX_P BIT(2)
106#define SW_LNTC_LPTX_N BIT(3)
107#define SW_LNTC_HSTX_PRE_OE BIT(4)
108#define SW_LNTC_HSTX_OE BIT(5)
109#define SW_LNTC_HSTX_ZEROCLK BIT(6)
110#define SW_LNT0_LPTX_PRE_OE BIT(7)
111#define SW_LNT0_LPTX_OE BIT(8)
112#define SW_LNT0_LPTX_P BIT(9)
113#define SW_LNT0_LPTX_N BIT(10)
114#define SW_LNT0_HSTX_PRE_OE BIT(11)
115#define SW_LNT0_HSTX_OE BIT(12)
116#define SW_LNT0_LPRX_EN BIT(13)
117#define SW_LNT1_LPTX_PRE_OE BIT(14)
118#define SW_LNT1_LPTX_OE BIT(15)
119#define SW_LNT1_LPTX_P BIT(16)
120#define SW_LNT1_LPTX_N BIT(17)
121#define SW_LNT1_HSTX_PRE_OE BIT(18)
122#define SW_LNT1_HSTX_OE BIT(19)
123#define SW_LNT2_LPTX_PRE_OE BIT(20)
124#define SW_LNT2_LPTX_OE BIT(21)
125#define SW_LNT2_LPTX_P BIT(22)
126#define SW_LNT2_LPTX_N BIT(23)
127#define SW_LNT2_HSTX_PRE_OE BIT(24)
128#define SW_LNT2_HSTX_OE BIT(25)
129
130struct mtk_mipitx_data {
131 const u32 mppll_preserve;
132};
133
134struct mtk_mipi_tx {
135 struct device *dev;
136 void __iomem *regs;
137 u32 data_rate;
138 const struct mtk_mipitx_data *driver_data;
139 struct clk_hw pll_hw;
140 struct clk *pll;
141};
142
143static inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
144{
145 return container_of(hw, struct mtk_mipi_tx, pll_hw);
146}
147
148static void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
149 u32 bits)
150{
151 u32 temp = readl(mipi_tx->regs + offset);
152
153 writel(temp & ~bits, mipi_tx->regs + offset);
154}
155
156static void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
157 u32 bits)
158{
159 u32 temp = readl(mipi_tx->regs + offset);
160
161 writel(temp | bits, mipi_tx->regs + offset);
162}
163
164static void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
165 u32 mask, u32 data)
166{
167 u32 temp = readl(mipi_tx->regs + offset);
168
169 writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
170}
171
172static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
173{
174 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
175 u8 txdiv, txdiv0, txdiv1;
176 u64 pcw;
177
178 dev_dbg(mipi_tx->dev, "prepare: %u Hz\n", mipi_tx->data_rate);
179
180 if (mipi_tx->data_rate >= 500000000) {
181 txdiv = 1;
182 txdiv0 = 0;
183 txdiv1 = 0;
184 } else if (mipi_tx->data_rate >= 250000000) {
185 txdiv = 2;
186 txdiv0 = 1;
187 txdiv1 = 0;
188 } else if (mipi_tx->data_rate >= 125000000) {
189 txdiv = 4;
190 txdiv0 = 2;
191 txdiv1 = 0;
192 } else if (mipi_tx->data_rate > 62000000) {
193 txdiv = 8;
194 txdiv0 = 2;
195 txdiv1 = 1;
196 } else if (mipi_tx->data_rate >= 50000000) {
197 txdiv = 16;
198 txdiv0 = 2;
199 txdiv1 = 2;
200 } else {
201 return -EINVAL;
202 }
203
204 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
205 RG_DSI_VOUT_MSK |
206 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
207 (4 << 20) | (4 << 17) | (4 << 14) |
208 (4 << 11) | (4 << 8) | (4 << 5) |
209 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
210
211 usleep_range(30, 100);
212
213 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
214 RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
215 (8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
216
217 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
218 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
219
220 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
221 RG_DSI_MPPLL_SDM_PWR_ON |
222 RG_DSI_MPPLL_SDM_ISO_EN,
223 RG_DSI_MPPLL_SDM_PWR_ON);
224
225 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
226 RG_DSI_MPPLL_PLL_EN);
227
228 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
229 RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
230 RG_DSI_MPPLL_PREDIV,
231 (txdiv0 << 3) | (txdiv1 << 5));
232
233 /*
234 * PLL PCW config
235 * PCW bit 24~30 = integer part of pcw
236 * PCW bit 0~23 = fractional part of pcw
237 * pcw = data_Rate*4*txdiv/(Ref_clk*2);
238 * Post DIV =4, so need data_Rate*4
239 * Ref_clk is 26MHz
240 */
241 pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24,
242 26000000);
243 writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);
244
245 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
246 RG_DSI_MPPLL_SDM_FRA_EN);
247
248 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
249
250 usleep_range(20, 100);
251
252 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
253 RG_DSI_MPPLL_SDM_SSC_EN);
254
255 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
256 RG_DSI_MPPLL_PRESERVE,
257 mipi_tx->driver_data->mppll_preserve);
258
259 return 0;
260}
261
262static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
263{
264 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
265
266 dev_dbg(mipi_tx->dev, "unprepare\n");
267
268 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
269 RG_DSI_MPPLL_PLL_EN);
270
271 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
272 RG_DSI_MPPLL_PRESERVE, 0);
273
274 mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
275 RG_DSI_MPPLL_SDM_ISO_EN |
276 RG_DSI_MPPLL_SDM_PWR_ON,
277 RG_DSI_MPPLL_SDM_ISO_EN);
278
279 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
280 RG_DSI_LNT_HS_BIAS_EN);
281
282 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON,
283 RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
284
285 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON,
286 RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
287
288 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
289 RG_DSI_MPPLL_DIV_MSK);
290}
291
292static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
293 unsigned long *prate)
294{
295 return clamp_val(rate, 50000000, 1250000000);
296}
297
298static int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
299 unsigned long parent_rate)
300{
301 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
302
303 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
304
305 mipi_tx->data_rate = rate;
306
307 return 0;
308}
309
310static unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
311 unsigned long parent_rate)
312{
313 struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
314
315 return mipi_tx->data_rate;
316}
317
318static const struct clk_ops mtk_mipi_tx_pll_ops = {
319 .prepare = mtk_mipi_tx_pll_prepare,
320 .unprepare = mtk_mipi_tx_pll_unprepare,
321 .round_rate = mtk_mipi_tx_pll_round_rate,
322 .set_rate = mtk_mipi_tx_pll_set_rate,
323 .recalc_rate = mtk_mipi_tx_pll_recalc_rate,
324};
325
326static int mtk_mipi_tx_power_on_signal(struct phy *phy)
327{
328 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
329 u32 reg;
330
331 for (reg = MIPITX_DSI_CLOCK_LANE;
332 reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
333 mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
334
335 mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
336 RG_DSI_PAD_TIE_LOW_EN);
337
338 return 0;
339}
340
341static int mtk_mipi_tx_power_on(struct phy *phy)
342{
343 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
344 int ret;
345
346 /* Power up core and enable PLL */
347 ret = clk_prepare_enable(mipi_tx->pll);
348 if (ret < 0)
349 return ret;
350
351 /* Enable DSI Lane LDO outputs, disable pad tie low */
352 mtk_mipi_tx_power_on_signal(phy);
353
354 return 0;
355}
356
357static void mtk_mipi_tx_power_off_signal(struct phy *phy)
358{
359 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
360 u32 reg;
361
362 mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
363 RG_DSI_PAD_TIE_LOW_EN);
364
365 for (reg = MIPITX_DSI_CLOCK_LANE;
366 reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
367 mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
368}
369
370static int mtk_mipi_tx_power_off(struct phy *phy)
371{
372 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
373
374 /* Enable pad tie low, disable DSI Lane LDO outputs */
375 mtk_mipi_tx_power_off_signal(phy);
376
377 /* Disable PLL and power down core */
378 clk_disable_unprepare(mipi_tx->pll);
379
380 return 0;
381}
382
383static const struct phy_ops mtk_mipi_tx_ops = {
384 .power_on = mtk_mipi_tx_power_on,
385 .power_off = mtk_mipi_tx_power_off,
386 .owner = THIS_MODULE,
387};
388
389static int mtk_mipi_tx_probe(struct platform_device *pdev)
390{
391 struct device *dev = &pdev->dev;
392 struct mtk_mipi_tx *mipi_tx;
393 struct resource *mem;
394 struct clk *ref_clk;
395 const char *ref_clk_name;
396 struct clk_init_data clk_init = {
397 .ops = &mtk_mipi_tx_pll_ops,
398 .num_parents = 1,
399 .parent_names = (const char * const *)&ref_clk_name,
400 .flags = CLK_SET_RATE_GATE,
401 };
402 struct phy *phy;
403 struct phy_provider *phy_provider;
404 int ret;
405
406 mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
407 if (!mipi_tx)
408 return -ENOMEM;
409
410 mipi_tx->driver_data = of_device_get_match_data(dev);
411 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
412 mipi_tx->regs = devm_ioremap_resource(dev, mem);
413 if (IS_ERR(mipi_tx->regs)) {
414 ret = PTR_ERR(mipi_tx->regs);
415 dev_err(dev, "Failed to get memory resource: %d\n", ret);
416 return ret;
417 }
418
419 ref_clk = devm_clk_get(dev, NULL);
420 if (IS_ERR(ref_clk)) {
421 ret = PTR_ERR(ref_clk);
422 dev_err(dev, "Failed to get reference clock: %d\n", ret);
423 return ret;
424 }
425 ref_clk_name = __clk_get_name(ref_clk);
426
427 ret = of_property_read_string(dev->of_node, "clock-output-names",
428 &clk_init.name);
429 if (ret < 0) {
430 dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
431 return ret;
432 }
433
434 mipi_tx->pll_hw.init = &clk_init;
435 mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
436 if (IS_ERR(mipi_tx->pll)) {
437 ret = PTR_ERR(mipi_tx->pll);
438 dev_err(dev, "Failed to register PLL: %d\n", ret);
439 return ret;
440 }
441
442 phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
443 if (IS_ERR(phy)) {
444 ret = PTR_ERR(phy);
445 dev_err(dev, "Failed to create MIPI D-PHY: %d\n", ret);
446 return ret;
447 }
448 phy_set_drvdata(phy, mipi_tx);
449
450 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
451 if (IS_ERR(phy_provider)) {
452 ret = PTR_ERR(phy_provider);
453 return ret;
454 }
455
456 mipi_tx->dev = dev;
457
458 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
459 mipi_tx->pll);
460}
461
462static int mtk_mipi_tx_remove(struct platform_device *pdev)
463{
464 of_clk_del_provider(pdev->dev.of_node);
465 return 0;
466}
467
468static const struct mtk_mipitx_data mt2701_mipitx_data = {
469 .mppll_preserve = (3 << 8)
470};
471
472static const struct mtk_mipitx_data mt8173_mipitx_data = {
473 .mppll_preserve = (0 << 8)
474};
475
476static const struct of_device_id mtk_mipi_tx_match[] = {
477 { .compatible = "mediatek,mt2701-mipi-tx",
478 .data = &mt2701_mipitx_data },
479 { .compatible = "mediatek,mt8173-mipi-tx",
480 .data = &mt8173_mipitx_data },
481 {},
482};
483
484struct platform_driver mtk_mipi_tx_driver = {
485 .probe = mtk_mipi_tx_probe,
486 .remove = mtk_mipi_tx_remove,
487 .driver = {
488 .name = "mediatek-mipi-tx",
489 .of_match_table = mtk_mipi_tx_match,
490 },
491};