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1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29
30/*
31 * The Bridge device's PCI config space has information about the
32 * fb aperture size and the amount of pre-reserved memory.
33 * This is all handled in the intel-gtt.ko module. i915.ko only
34 * cares about the vga bit for the vga rbiter.
35 */
36#define INTEL_GMCH_CTRL 0x52
37#define INTEL_GMCH_VGA_DISABLE (1 << 1)
38
39/* PCI config space */
40
41#define HPLLCC 0xc0 /* 855 only */
42#define GC_CLOCK_CONTROL_MASK (0xf << 0)
43#define GC_CLOCK_133_200 (0 << 0)
44#define GC_CLOCK_100_200 (1 << 0)
45#define GC_CLOCK_100_133 (2 << 0)
46#define GC_CLOCK_166_250 (3 << 0)
47#define GCFGC2 0xda
48#define GCFGC 0xf0 /* 915+ only */
49#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
50#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
51#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
52#define GC_DISPLAY_CLOCK_MASK (7 << 4)
53#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
54#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
55#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
56#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
57#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
58#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
59#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
60#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
61#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
62#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
63#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
64#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
65#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
66#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
67#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
68#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
69#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
72#define LBB 0xf4
73
74/* Graphics reset regs */
75#define I965_GDRST 0xc0 /* PCI config register */
76#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
77#define GRDOM_FULL (0<<2)
78#define GRDOM_RENDER (1<<2)
79#define GRDOM_MEDIA (3<<2)
80
81#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
82#define GEN6_MBC_SNPCR_SHIFT 21
83#define GEN6_MBC_SNPCR_MASK (3<<21)
84#define GEN6_MBC_SNPCR_MAX (0<<21)
85#define GEN6_MBC_SNPCR_MED (1<<21)
86#define GEN6_MBC_SNPCR_LOW (2<<21)
87#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
88
89#define GEN6_GDRST 0x941c
90#define GEN6_GRDOM_FULL (1 << 0)
91#define GEN6_GRDOM_RENDER (1 << 1)
92#define GEN6_GRDOM_MEDIA (1 << 2)
93#define GEN6_GRDOM_BLT (1 << 3)
94
95/* VGA stuff */
96
97#define VGA_ST01_MDA 0x3ba
98#define VGA_ST01_CGA 0x3da
99
100#define VGA_MSR_WRITE 0x3c2
101#define VGA_MSR_READ 0x3cc
102#define VGA_MSR_MEM_EN (1<<1)
103#define VGA_MSR_CGA_MODE (1<<0)
104
105#define VGA_SR_INDEX 0x3c4
106#define VGA_SR_DATA 0x3c5
107
108#define VGA_AR_INDEX 0x3c0
109#define VGA_AR_VID_EN (1<<5)
110#define VGA_AR_DATA_WRITE 0x3c0
111#define VGA_AR_DATA_READ 0x3c1
112
113#define VGA_GR_INDEX 0x3ce
114#define VGA_GR_DATA 0x3cf
115/* GR05 */
116#define VGA_GR_MEM_READ_MODE_SHIFT 3
117#define VGA_GR_MEM_READ_MODE_PLANE 1
118/* GR06 */
119#define VGA_GR_MEM_MODE_MASK 0xc
120#define VGA_GR_MEM_MODE_SHIFT 2
121#define VGA_GR_MEM_A0000_AFFFF 0
122#define VGA_GR_MEM_A0000_BFFFF 1
123#define VGA_GR_MEM_B0000_B7FFF 2
124#define VGA_GR_MEM_B0000_BFFFF 3
125
126#define VGA_DACMASK 0x3c6
127#define VGA_DACRX 0x3c7
128#define VGA_DACWX 0x3c8
129#define VGA_DACDATA 0x3c9
130
131#define VGA_CR_INDEX_MDA 0x3b4
132#define VGA_CR_DATA_MDA 0x3b5
133#define VGA_CR_INDEX_CGA 0x3d4
134#define VGA_CR_DATA_CGA 0x3d5
135
136/*
137 * Memory interface instructions used by the kernel
138 */
139#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
140
141#define MI_NOOP MI_INSTR(0, 0)
142#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
143#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
144#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
145#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
146#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
147#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
148#define MI_FLUSH MI_INSTR(0x04, 0)
149#define MI_READ_FLUSH (1 << 0)
150#define MI_EXE_FLUSH (1 << 1)
151#define MI_NO_WRITE_FLUSH (1 << 2)
152#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
153#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
154#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
155#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
156#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
157#define MI_SUSPEND_FLUSH_EN (1<<0)
158#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
159#define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
160#define MI_OVERLAY_CONTINUE (0x0<<21)
161#define MI_OVERLAY_ON (0x1<<21)
162#define MI_OVERLAY_OFF (0x2<<21)
163#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
164#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
165#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
166#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
167#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
168#define MI_MM_SPACE_GTT (1<<8)
169#define MI_MM_SPACE_PHYSICAL (0<<8)
170#define MI_SAVE_EXT_STATE_EN (1<<3)
171#define MI_RESTORE_EXT_STATE_EN (1<<2)
172#define MI_FORCE_RESTORE (1<<1)
173#define MI_RESTORE_INHIBIT (1<<0)
174#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
175#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
176#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
177#define MI_STORE_DWORD_INDEX_SHIFT 2
178/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
179 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
180 * simply ignores the register load under certain conditions.
181 * - One can actually load arbitrary many arbitrary registers: Simply issue x
182 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
183 */
184#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
185#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
186#define MI_INVALIDATE_TLB (1<<18)
187#define MI_INVALIDATE_BSD (1<<7)
188#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
189#define MI_BATCH_NON_SECURE (1)
190#define MI_BATCH_NON_SECURE_I965 (1<<8)
191#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
192#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
193#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
194#define MI_SEMAPHORE_UPDATE (1<<21)
195#define MI_SEMAPHORE_COMPARE (1<<20)
196#define MI_SEMAPHORE_REGISTER (1<<18)
197/*
198 * 3D instructions used by the kernel
199 */
200#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
201
202#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
203#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
204#define SC_UPDATE_SCISSOR (0x1<<1)
205#define SC_ENABLE_MASK (0x1<<0)
206#define SC_ENABLE (0x1<<0)
207#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
208#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
209#define SCI_YMIN_MASK (0xffff<<16)
210#define SCI_XMIN_MASK (0xffff<<0)
211#define SCI_YMAX_MASK (0xffff<<16)
212#define SCI_XMAX_MASK (0xffff<<0)
213#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
214#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
215#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
216#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
217#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
218#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
219#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
220#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
221#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
222#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
223#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
224#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
225#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
226#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
227#define BLT_DEPTH_8 (0<<24)
228#define BLT_DEPTH_16_565 (1<<24)
229#define BLT_DEPTH_16_1555 (2<<24)
230#define BLT_DEPTH_32 (3<<24)
231#define BLT_ROP_GXCOPY (0xcc<<16)
232#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
233#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
234#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
235#define ASYNC_FLIP (1<<22)
236#define DISPLAY_PLANE_A (0<<20)
237#define DISPLAY_PLANE_B (1<<20)
238#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
239#define PIPE_CONTROL_QW_WRITE (1<<14)
240#define PIPE_CONTROL_DEPTH_STALL (1<<13)
241#define PIPE_CONTROL_WC_FLUSH (1<<12)
242#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
243#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
244#define PIPE_CONTROL_ISP_DIS (1<<9)
245#define PIPE_CONTROL_NOTIFY (1<<8)
246#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
247#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
248
249
250/*
251 * Reset registers
252 */
253#define DEBUG_RESET_I830 0x6070
254#define DEBUG_RESET_FULL (1<<7)
255#define DEBUG_RESET_RENDER (1<<8)
256#define DEBUG_RESET_DISPLAY (1<<9)
257
258
259/*
260 * Fence registers
261 */
262#define FENCE_REG_830_0 0x2000
263#define FENCE_REG_945_8 0x3000
264#define I830_FENCE_START_MASK 0x07f80000
265#define I830_FENCE_TILING_Y_SHIFT 12
266#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
267#define I830_FENCE_PITCH_SHIFT 4
268#define I830_FENCE_REG_VALID (1<<0)
269#define I915_FENCE_MAX_PITCH_VAL 4
270#define I830_FENCE_MAX_PITCH_VAL 6
271#define I830_FENCE_MAX_SIZE_VAL (1<<8)
272
273#define I915_FENCE_START_MASK 0x0ff00000
274#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
275
276#define FENCE_REG_965_0 0x03000
277#define I965_FENCE_PITCH_SHIFT 2
278#define I965_FENCE_TILING_Y_SHIFT 1
279#define I965_FENCE_REG_VALID (1<<0)
280#define I965_FENCE_MAX_PITCH_VAL 0x0400
281
282#define FENCE_REG_SANDYBRIDGE_0 0x100000
283#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
284
285/*
286 * Instruction and interrupt control regs
287 */
288#define PGTBL_ER 0x02024
289#define RENDER_RING_BASE 0x02000
290#define BSD_RING_BASE 0x04000
291#define GEN6_BSD_RING_BASE 0x12000
292#define BLT_RING_BASE 0x22000
293#define RING_TAIL(base) ((base)+0x30)
294#define RING_HEAD(base) ((base)+0x34)
295#define RING_START(base) ((base)+0x38)
296#define RING_CTL(base) ((base)+0x3c)
297#define RING_SYNC_0(base) ((base)+0x40)
298#define RING_SYNC_1(base) ((base)+0x44)
299#define RING_MAX_IDLE(base) ((base)+0x54)
300#define RING_HWS_PGA(base) ((base)+0x80)
301#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
302#define RENDER_HWS_PGA_GEN7 (0x04080)
303#define BSD_HWS_PGA_GEN7 (0x04180)
304#define BLT_HWS_PGA_GEN7 (0x04280)
305#define RING_ACTHD(base) ((base)+0x74)
306#define RING_NOPID(base) ((base)+0x94)
307#define RING_IMR(base) ((base)+0xa8)
308#define TAIL_ADDR 0x001FFFF8
309#define HEAD_WRAP_COUNT 0xFFE00000
310#define HEAD_WRAP_ONE 0x00200000
311#define HEAD_ADDR 0x001FFFFC
312#define RING_NR_PAGES 0x001FF000
313#define RING_REPORT_MASK 0x00000006
314#define RING_REPORT_64K 0x00000002
315#define RING_REPORT_128K 0x00000004
316#define RING_NO_REPORT 0x00000000
317#define RING_VALID_MASK 0x00000001
318#define RING_VALID 0x00000001
319#define RING_INVALID 0x00000000
320#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
321#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
322#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
323#if 0
324#define PRB0_TAIL 0x02030
325#define PRB0_HEAD 0x02034
326#define PRB0_START 0x02038
327#define PRB0_CTL 0x0203c
328#define PRB1_TAIL 0x02040 /* 915+ only */
329#define PRB1_HEAD 0x02044 /* 915+ only */
330#define PRB1_START 0x02048 /* 915+ only */
331#define PRB1_CTL 0x0204c /* 915+ only */
332#endif
333#define IPEIR_I965 0x02064
334#define IPEHR_I965 0x02068
335#define INSTDONE_I965 0x0206c
336#define INSTPS 0x02070 /* 965+ only */
337#define INSTDONE1 0x0207c /* 965+ only */
338#define ACTHD_I965 0x02074
339#define HWS_PGA 0x02080
340#define HWS_ADDRESS_MASK 0xfffff000
341#define HWS_START_ADDRESS_SHIFT 4
342#define PWRCTXA 0x2088 /* 965GM+ only */
343#define PWRCTX_EN (1<<0)
344#define IPEIR 0x02088
345#define IPEHR 0x0208c
346#define INSTDONE 0x02090
347#define NOPID 0x02094
348#define HWSTAM 0x02098
349#define VCS_INSTDONE 0x1206C
350#define VCS_IPEIR 0x12064
351#define VCS_IPEHR 0x12068
352#define VCS_ACTHD 0x12074
353#define BCS_INSTDONE 0x2206C
354#define BCS_IPEIR 0x22064
355#define BCS_IPEHR 0x22068
356#define BCS_ACTHD 0x22074
357
358#define ERROR_GEN6 0x040a0
359
360/* GM45+ chicken bits -- debug workaround bits that may be required
361 * for various sorts of correct behavior. The top 16 bits of each are
362 * the enables for writing to the corresponding low bit.
363 */
364#define _3D_CHICKEN 0x02084
365#define _3D_CHICKEN2 0x0208c
366/* Disables pipelining of read flushes past the SF-WIZ interface.
367 * Required on all Ironlake steppings according to the B-Spec, but the
368 * particular danger of not doing so is not specified.
369 */
370# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
371#define _3D_CHICKEN3 0x02090
372
373#define MI_MODE 0x0209c
374# define VS_TIMER_DISPATCH (1 << 6)
375# define MI_FLUSH_ENABLE (1 << 11)
376
377#define GFX_MODE 0x02520
378#define GFX_MODE_GEN7 0x0229c
379#define GFX_RUN_LIST_ENABLE (1<<15)
380#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
381#define GFX_SURFACE_FAULT_ENABLE (1<<12)
382#define GFX_REPLAY_MODE (1<<11)
383#define GFX_PSMI_GRANULARITY (1<<10)
384#define GFX_PPGTT_ENABLE (1<<9)
385
386#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
387#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
388
389#define SCPD0 0x0209c /* 915+ only */
390#define IER 0x020a0
391#define IIR 0x020a4
392#define IMR 0x020a8
393#define ISR 0x020ac
394#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
395#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
396#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
397#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
398#define I915_HWB_OOM_INTERRUPT (1<<13)
399#define I915_SYNC_STATUS_INTERRUPT (1<<12)
400#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
401#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
402#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
403#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
404#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
405#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
406#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
407#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
408#define I915_DEBUG_INTERRUPT (1<<2)
409#define I915_USER_INTERRUPT (1<<1)
410#define I915_ASLE_INTERRUPT (1<<0)
411#define I915_BSD_USER_INTERRUPT (1<<25)
412#define EIR 0x020b0
413#define EMR 0x020b4
414#define ESR 0x020b8
415#define GM45_ERROR_PAGE_TABLE (1<<5)
416#define GM45_ERROR_MEM_PRIV (1<<4)
417#define I915_ERROR_PAGE_TABLE (1<<4)
418#define GM45_ERROR_CP_PRIV (1<<3)
419#define I915_ERROR_MEMORY_REFRESH (1<<1)
420#define I915_ERROR_INSTRUCTION (1<<0)
421#define INSTPM 0x020c0
422#define INSTPM_SELF_EN (1<<12) /* 915GM only */
423#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
424 will not assert AGPBUSY# and will only
425 be delivered when out of C3. */
426#define ACTHD 0x020c8
427#define FW_BLC 0x020d8
428#define FW_BLC2 0x020dc
429#define FW_BLC_SELF 0x020e0 /* 915+ only */
430#define FW_BLC_SELF_EN_MASK (1<<31)
431#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
432#define FW_BLC_SELF_EN (1<<15) /* 945 only */
433#define MM_BURST_LENGTH 0x00700000
434#define MM_FIFO_WATERMARK 0x0001F000
435#define LM_BURST_LENGTH 0x00000700
436#define LM_FIFO_WATERMARK 0x0000001F
437#define MI_ARB_STATE 0x020e4 /* 915+ only */
438#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
439
440/* Make render/texture TLB fetches lower priorty than associated data
441 * fetches. This is not turned on by default
442 */
443#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
444
445/* Isoch request wait on GTT enable (Display A/B/C streams).
446 * Make isoch requests stall on the TLB update. May cause
447 * display underruns (test mode only)
448 */
449#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
450
451/* Block grant count for isoch requests when block count is
452 * set to a finite value.
453 */
454#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
455#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
456#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
457#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
458#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
459
460/* Enable render writes to complete in C2/C3/C4 power states.
461 * If this isn't enabled, render writes are prevented in low
462 * power states. That seems bad to me.
463 */
464#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
465
466/* This acknowledges an async flip immediately instead
467 * of waiting for 2TLB fetches.
468 */
469#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
470
471/* Enables non-sequential data reads through arbiter
472 */
473#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
474
475/* Disable FSB snooping of cacheable write cycles from binner/render
476 * command stream
477 */
478#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
479
480/* Arbiter time slice for non-isoch streams */
481#define MI_ARB_TIME_SLICE_MASK (7 << 5)
482#define MI_ARB_TIME_SLICE_1 (0 << 5)
483#define MI_ARB_TIME_SLICE_2 (1 << 5)
484#define MI_ARB_TIME_SLICE_4 (2 << 5)
485#define MI_ARB_TIME_SLICE_6 (3 << 5)
486#define MI_ARB_TIME_SLICE_8 (4 << 5)
487#define MI_ARB_TIME_SLICE_10 (5 << 5)
488#define MI_ARB_TIME_SLICE_14 (6 << 5)
489#define MI_ARB_TIME_SLICE_16 (7 << 5)
490
491/* Low priority grace period page size */
492#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
493#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
494
495/* Disable display A/B trickle feed */
496#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
497
498/* Set display plane priority */
499#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
500#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
501
502#define CACHE_MODE_0 0x02120 /* 915+ only */
503#define CM0_MASK_SHIFT 16
504#define CM0_IZ_OPT_DISABLE (1<<6)
505#define CM0_ZR_OPT_DISABLE (1<<5)
506#define CM0_DEPTH_EVICT_DISABLE (1<<4)
507#define CM0_COLOR_EVICT_DISABLE (1<<3)
508#define CM0_DEPTH_WRITE_DISABLE (1<<1)
509#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
510#define BB_ADDR 0x02140 /* 8 bytes */
511#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
512#define ECOSKPD 0x021d0
513#define ECO_GATING_CX_ONLY (1<<3)
514#define ECO_FLIP_DONE (1<<0)
515
516/* GEN6 interrupt control */
517#define GEN6_RENDER_HWSTAM 0x2098
518#define GEN6_RENDER_IMR 0x20a8
519#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
520#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
521#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
522#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
523#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
524#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
525#define GEN6_RENDER_SYNC_STATUS (1 << 2)
526#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
527#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
528
529#define GEN6_BLITTER_HWSTAM 0x22098
530#define GEN6_BLITTER_IMR 0x220a8
531#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
532#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
533#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
534#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
535
536#define GEN6_BLITTER_ECOSKPD 0x221d0
537#define GEN6_BLITTER_LOCK_SHIFT 16
538#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
539
540#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
541#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
542#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
543#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
544#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
545
546#define GEN6_BSD_HWSTAM 0x12098
547#define GEN6_BSD_IMR 0x120a8
548#define GEN6_BSD_USER_INTERRUPT (1 << 12)
549
550#define GEN6_BSD_RNCID 0x12198
551
552/*
553 * Framebuffer compression (915+ only)
554 */
555
556#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
557#define FBC_LL_BASE 0x03204 /* 4k page aligned */
558#define FBC_CONTROL 0x03208
559#define FBC_CTL_EN (1<<31)
560#define FBC_CTL_PERIODIC (1<<30)
561#define FBC_CTL_INTERVAL_SHIFT (16)
562#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
563#define FBC_CTL_C3_IDLE (1<<13)
564#define FBC_CTL_STRIDE_SHIFT (5)
565#define FBC_CTL_FENCENO (1<<0)
566#define FBC_COMMAND 0x0320c
567#define FBC_CMD_COMPRESS (1<<0)
568#define FBC_STATUS 0x03210
569#define FBC_STAT_COMPRESSING (1<<31)
570#define FBC_STAT_COMPRESSED (1<<30)
571#define FBC_STAT_MODIFIED (1<<29)
572#define FBC_STAT_CURRENT_LINE (1<<0)
573#define FBC_CONTROL2 0x03214
574#define FBC_CTL_FENCE_DBL (0<<4)
575#define FBC_CTL_IDLE_IMM (0<<2)
576#define FBC_CTL_IDLE_FULL (1<<2)
577#define FBC_CTL_IDLE_LINE (2<<2)
578#define FBC_CTL_IDLE_DEBUG (3<<2)
579#define FBC_CTL_CPU_FENCE (1<<1)
580#define FBC_CTL_PLANEA (0<<0)
581#define FBC_CTL_PLANEB (1<<0)
582#define FBC_FENCE_OFF 0x0321b
583#define FBC_TAG 0x03300
584
585#define FBC_LL_SIZE (1536)
586
587/* Framebuffer compression for GM45+ */
588#define DPFC_CB_BASE 0x3200
589#define DPFC_CONTROL 0x3208
590#define DPFC_CTL_EN (1<<31)
591#define DPFC_CTL_PLANEA (0<<30)
592#define DPFC_CTL_PLANEB (1<<30)
593#define DPFC_CTL_FENCE_EN (1<<29)
594#define DPFC_CTL_PERSISTENT_MODE (1<<25)
595#define DPFC_SR_EN (1<<10)
596#define DPFC_CTL_LIMIT_1X (0<<6)
597#define DPFC_CTL_LIMIT_2X (1<<6)
598#define DPFC_CTL_LIMIT_4X (2<<6)
599#define DPFC_RECOMP_CTL 0x320c
600#define DPFC_RECOMP_STALL_EN (1<<27)
601#define DPFC_RECOMP_STALL_WM_SHIFT (16)
602#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
603#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
604#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
605#define DPFC_STATUS 0x3210
606#define DPFC_INVAL_SEG_SHIFT (16)
607#define DPFC_INVAL_SEG_MASK (0x07ff0000)
608#define DPFC_COMP_SEG_SHIFT (0)
609#define DPFC_COMP_SEG_MASK (0x000003ff)
610#define DPFC_STATUS2 0x3214
611#define DPFC_FENCE_YOFF 0x3218
612#define DPFC_CHICKEN 0x3224
613#define DPFC_HT_MODIFY (1<<31)
614
615/* Framebuffer compression for Ironlake */
616#define ILK_DPFC_CB_BASE 0x43200
617#define ILK_DPFC_CONTROL 0x43208
618/* The bit 28-8 is reserved */
619#define DPFC_RESERVED (0x1FFFFF00)
620#define ILK_DPFC_RECOMP_CTL 0x4320c
621#define ILK_DPFC_STATUS 0x43210
622#define ILK_DPFC_FENCE_YOFF 0x43218
623#define ILK_DPFC_CHICKEN 0x43224
624#define ILK_FBC_RT_BASE 0x2128
625#define ILK_FBC_RT_VALID (1<<0)
626
627#define ILK_DISPLAY_CHICKEN1 0x42000
628#define ILK_FBCQ_DIS (1<<22)
629#define ILK_PABSTRETCH_DIS (1<<21)
630
631
632/*
633 * Framebuffer compression for Sandybridge
634 *
635 * The following two registers are of type GTTMMADR
636 */
637#define SNB_DPFC_CTL_SA 0x100100
638#define SNB_CPU_FENCE_ENABLE (1<<29)
639#define DPFC_CPU_FENCE_OFFSET 0x100104
640
641
642/*
643 * GPIO regs
644 */
645#define GPIOA 0x5010
646#define GPIOB 0x5014
647#define GPIOC 0x5018
648#define GPIOD 0x501c
649#define GPIOE 0x5020
650#define GPIOF 0x5024
651#define GPIOG 0x5028
652#define GPIOH 0x502c
653# define GPIO_CLOCK_DIR_MASK (1 << 0)
654# define GPIO_CLOCK_DIR_IN (0 << 1)
655# define GPIO_CLOCK_DIR_OUT (1 << 1)
656# define GPIO_CLOCK_VAL_MASK (1 << 2)
657# define GPIO_CLOCK_VAL_OUT (1 << 3)
658# define GPIO_CLOCK_VAL_IN (1 << 4)
659# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
660# define GPIO_DATA_DIR_MASK (1 << 8)
661# define GPIO_DATA_DIR_IN (0 << 9)
662# define GPIO_DATA_DIR_OUT (1 << 9)
663# define GPIO_DATA_VAL_MASK (1 << 10)
664# define GPIO_DATA_VAL_OUT (1 << 11)
665# define GPIO_DATA_VAL_IN (1 << 12)
666# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
667
668#define GMBUS0 0x5100 /* clock/port select */
669#define GMBUS_RATE_100KHZ (0<<8)
670#define GMBUS_RATE_50KHZ (1<<8)
671#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
672#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
673#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
674#define GMBUS_PORT_DISABLED 0
675#define GMBUS_PORT_SSC 1
676#define GMBUS_PORT_VGADDC 2
677#define GMBUS_PORT_PANEL 3
678#define GMBUS_PORT_DPC 4 /* HDMIC */
679#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
680 /* 6 reserved */
681#define GMBUS_PORT_DPD 7 /* HDMID */
682#define GMBUS_NUM_PORTS 8
683#define GMBUS1 0x5104 /* command/status */
684#define GMBUS_SW_CLR_INT (1<<31)
685#define GMBUS_SW_RDY (1<<30)
686#define GMBUS_ENT (1<<29) /* enable timeout */
687#define GMBUS_CYCLE_NONE (0<<25)
688#define GMBUS_CYCLE_WAIT (1<<25)
689#define GMBUS_CYCLE_INDEX (2<<25)
690#define GMBUS_CYCLE_STOP (4<<25)
691#define GMBUS_BYTE_COUNT_SHIFT 16
692#define GMBUS_SLAVE_INDEX_SHIFT 8
693#define GMBUS_SLAVE_ADDR_SHIFT 1
694#define GMBUS_SLAVE_READ (1<<0)
695#define GMBUS_SLAVE_WRITE (0<<0)
696#define GMBUS2 0x5108 /* status */
697#define GMBUS_INUSE (1<<15)
698#define GMBUS_HW_WAIT_PHASE (1<<14)
699#define GMBUS_STALL_TIMEOUT (1<<13)
700#define GMBUS_INT (1<<12)
701#define GMBUS_HW_RDY (1<<11)
702#define GMBUS_SATOER (1<<10)
703#define GMBUS_ACTIVE (1<<9)
704#define GMBUS3 0x510c /* data buffer bytes 3-0 */
705#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
706#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
707#define GMBUS_NAK_EN (1<<3)
708#define GMBUS_IDLE_EN (1<<2)
709#define GMBUS_HW_WAIT_EN (1<<1)
710#define GMBUS_HW_RDY_EN (1<<0)
711#define GMBUS5 0x5120 /* byte index */
712#define GMBUS_2BYTE_INDEX_EN (1<<31)
713
714/*
715 * Clock control & power management
716 */
717
718#define VGA0 0x6000
719#define VGA1 0x6004
720#define VGA_PD 0x6010
721#define VGA0_PD_P2_DIV_4 (1 << 7)
722#define VGA0_PD_P1_DIV_2 (1 << 5)
723#define VGA0_PD_P1_SHIFT 0
724#define VGA0_PD_P1_MASK (0x1f << 0)
725#define VGA1_PD_P2_DIV_4 (1 << 15)
726#define VGA1_PD_P1_DIV_2 (1 << 13)
727#define VGA1_PD_P1_SHIFT 8
728#define VGA1_PD_P1_MASK (0x1f << 8)
729#define _DPLL_A 0x06014
730#define _DPLL_B 0x06018
731#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
732#define DPLL_VCO_ENABLE (1 << 31)
733#define DPLL_DVO_HIGH_SPEED (1 << 30)
734#define DPLL_SYNCLOCK_ENABLE (1 << 29)
735#define DPLL_VGA_MODE_DIS (1 << 28)
736#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
737#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
738#define DPLL_MODE_MASK (3 << 26)
739#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
740#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
741#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
742#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
743#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
744#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
745#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
746
747#define SRX_INDEX 0x3c4
748#define SRX_DATA 0x3c5
749#define SR01 1
750#define SR01_SCREEN_OFF (1<<5)
751
752#define PPCR 0x61204
753#define PPCR_ON (1<<0)
754
755#define DVOB 0x61140
756#define DVOB_ON (1<<31)
757#define DVOC 0x61160
758#define DVOC_ON (1<<31)
759#define LVDS 0x61180
760#define LVDS_ON (1<<31)
761
762/* Scratch pad debug 0 reg:
763 */
764#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
765/*
766 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
767 * this field (only one bit may be set).
768 */
769#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
770#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
771#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
772/* i830, required in DVO non-gang */
773#define PLL_P2_DIVIDE_BY_4 (1 << 23)
774#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
775#define PLL_REF_INPUT_DREFCLK (0 << 13)
776#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
777#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
778#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
779#define PLL_REF_INPUT_MASK (3 << 13)
780#define PLL_LOAD_PULSE_PHASE_SHIFT 9
781/* Ironlake */
782# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
783# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
784# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
785# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
786# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
787
788/*
789 * Parallel to Serial Load Pulse phase selection.
790 * Selects the phase for the 10X DPLL clock for the PCIe
791 * digital display port. The range is 4 to 13; 10 or more
792 * is just a flip delay. The default is 6
793 */
794#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
795#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
796/*
797 * SDVO multiplier for 945G/GM. Not used on 965.
798 */
799#define SDVO_MULTIPLIER_MASK 0x000000ff
800#define SDVO_MULTIPLIER_SHIFT_HIRES 4
801#define SDVO_MULTIPLIER_SHIFT_VGA 0
802#define _DPLL_A_MD 0x0601c /* 965+ only */
803/*
804 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
805 *
806 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
807 */
808#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
809#define DPLL_MD_UDI_DIVIDER_SHIFT 24
810/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
811#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
812#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
813/*
814 * SDVO/UDI pixel multiplier.
815 *
816 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
817 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
818 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
819 * dummy bytes in the datastream at an increased clock rate, with both sides of
820 * the link knowing how many bytes are fill.
821 *
822 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
823 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
824 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
825 * through an SDVO command.
826 *
827 * This register field has values of multiplication factor minus 1, with
828 * a maximum multiplier of 5 for SDVO.
829 */
830#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
831#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
832/*
833 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
834 * This best be set to the default value (3) or the CRT won't work. No,
835 * I don't entirely understand what this does...
836 */
837#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
838#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
839#define _DPLL_B_MD 0x06020 /* 965+ only */
840#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
841#define _FPA0 0x06040
842#define _FPA1 0x06044
843#define _FPB0 0x06048
844#define _FPB1 0x0604c
845#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
846#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
847#define FP_N_DIV_MASK 0x003f0000
848#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
849#define FP_N_DIV_SHIFT 16
850#define FP_M1_DIV_MASK 0x00003f00
851#define FP_M1_DIV_SHIFT 8
852#define FP_M2_DIV_MASK 0x0000003f
853#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
854#define FP_M2_DIV_SHIFT 0
855#define DPLL_TEST 0x606c
856#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
857#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
858#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
859#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
860#define DPLLB_TEST_N_BYPASS (1 << 19)
861#define DPLLB_TEST_M_BYPASS (1 << 18)
862#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
863#define DPLLA_TEST_N_BYPASS (1 << 3)
864#define DPLLA_TEST_M_BYPASS (1 << 2)
865#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
866#define D_STATE 0x6104
867#define DSTATE_GFX_RESET_I830 (1<<6)
868#define DSTATE_PLL_D3_OFF (1<<3)
869#define DSTATE_GFX_CLOCK_GATING (1<<1)
870#define DSTATE_DOT_CLOCK_GATING (1<<0)
871#define DSPCLK_GATE_D 0x6200
872# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
873# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
874# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
875# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
876# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
877# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
878# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
879# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
880# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
881# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
882# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
883# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
884# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
885# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
886# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
887# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
888# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
889# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
890# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
891# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
892# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
893# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
894# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
895# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
896# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
897# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
898# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
899# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
900/**
901 * This bit must be set on the 830 to prevent hangs when turning off the
902 * overlay scaler.
903 */
904# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
905# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
906# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
907# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
908# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
909
910#define RENCLK_GATE_D1 0x6204
911# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
912# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
913# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
914# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
915# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
916# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
917# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
918# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
919# define MAG_CLOCK_GATE_DISABLE (1 << 5)
920/** This bit must be unset on 855,865 */
921# define MECI_CLOCK_GATE_DISABLE (1 << 4)
922# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
923# define MEC_CLOCK_GATE_DISABLE (1 << 2)
924# define MECO_CLOCK_GATE_DISABLE (1 << 1)
925/** This bit must be set on 855,865. */
926# define SV_CLOCK_GATE_DISABLE (1 << 0)
927# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
928# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
929# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
930# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
931# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
932# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
933# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
934# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
935# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
936# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
937# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
938# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
939# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
940# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
941# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
942# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
943# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
944
945# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
946/** This bit must always be set on 965G/965GM */
947# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
948# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
949# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
950# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
951# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
952# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
953/** This bit must always be set on 965G */
954# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
955# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
956# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
957# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
958# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
959# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
960# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
961# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
962# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
963# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
964# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
965# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
966# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
967# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
968# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
969# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
970# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
971# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
972# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
973
974#define RENCLK_GATE_D2 0x6208
975#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
976#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
977#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
978#define RAMCLK_GATE_D 0x6210 /* CRL only */
979#define DEUC 0x6214 /* CRL only */
980
981/*
982 * Palette regs
983 */
984
985#define _PALETTE_A 0x0a000
986#define _PALETTE_B 0x0a800
987#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
988
989/* MCH MMIO space */
990
991/*
992 * MCHBAR mirror.
993 *
994 * This mirrors the MCHBAR MMIO space whose location is determined by
995 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
996 * every way. It is not accessible from the CP register read instructions.
997 *
998 */
999#define MCHBAR_MIRROR_BASE 0x10000
1000
1001#define MCHBAR_MIRROR_BASE_SNB 0x140000
1002
1003/** 915-945 and GM965 MCH register controlling DRAM channel access */
1004#define DCC 0x10200
1005#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1006#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1007#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1008#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1009#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1010#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1011
1012/** Pineview MCH register contains DDR3 setting */
1013#define CSHRDDR3CTL 0x101a8
1014#define CSHRDDR3CTL_DDR3 (1 << 2)
1015
1016/** 965 MCH register controlling DRAM channel configuration */
1017#define C0DRB3 0x10206
1018#define C1DRB3 0x10606
1019
1020/* Clocking configuration register */
1021#define CLKCFG 0x10c00
1022#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1023#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1024#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1025#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1026#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1027#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1028/* Note, below two are guess */
1029#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1030#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1031#define CLKCFG_FSB_MASK (7 << 0)
1032#define CLKCFG_MEM_533 (1 << 4)
1033#define CLKCFG_MEM_667 (2 << 4)
1034#define CLKCFG_MEM_800 (3 << 4)
1035#define CLKCFG_MEM_MASK (7 << 4)
1036
1037#define TSC1 0x11001
1038#define TSE (1<<0)
1039#define TR1 0x11006
1040#define TSFS 0x11020
1041#define TSFS_SLOPE_MASK 0x0000ff00
1042#define TSFS_SLOPE_SHIFT 8
1043#define TSFS_INTR_MASK 0x000000ff
1044
1045#define CRSTANDVID 0x11100
1046#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1047#define PXVFREQ_PX_MASK 0x7f000000
1048#define PXVFREQ_PX_SHIFT 24
1049#define VIDFREQ_BASE 0x11110
1050#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1051#define VIDFREQ2 0x11114
1052#define VIDFREQ3 0x11118
1053#define VIDFREQ4 0x1111c
1054#define VIDFREQ_P0_MASK 0x1f000000
1055#define VIDFREQ_P0_SHIFT 24
1056#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1057#define VIDFREQ_P0_CSCLK_SHIFT 20
1058#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1059#define VIDFREQ_P0_CRCLK_SHIFT 16
1060#define VIDFREQ_P1_MASK 0x00001f00
1061#define VIDFREQ_P1_SHIFT 8
1062#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1063#define VIDFREQ_P1_CSCLK_SHIFT 4
1064#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1065#define INTTOEXT_BASE_ILK 0x11300
1066#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1067#define INTTOEXT_MAP3_SHIFT 24
1068#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1069#define INTTOEXT_MAP2_SHIFT 16
1070#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1071#define INTTOEXT_MAP1_SHIFT 8
1072#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1073#define INTTOEXT_MAP0_SHIFT 0
1074#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1075#define MEMSWCTL 0x11170 /* Ironlake only */
1076#define MEMCTL_CMD_MASK 0xe000
1077#define MEMCTL_CMD_SHIFT 13
1078#define MEMCTL_CMD_RCLK_OFF 0
1079#define MEMCTL_CMD_RCLK_ON 1
1080#define MEMCTL_CMD_CHFREQ 2
1081#define MEMCTL_CMD_CHVID 3
1082#define MEMCTL_CMD_VMMOFF 4
1083#define MEMCTL_CMD_VMMON 5
1084#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1085 when command complete */
1086#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1087#define MEMCTL_FREQ_SHIFT 8
1088#define MEMCTL_SFCAVM (1<<7)
1089#define MEMCTL_TGT_VID_MASK 0x007f
1090#define MEMIHYST 0x1117c
1091#define MEMINTREN 0x11180 /* 16 bits */
1092#define MEMINT_RSEXIT_EN (1<<8)
1093#define MEMINT_CX_SUPR_EN (1<<7)
1094#define MEMINT_CONT_BUSY_EN (1<<6)
1095#define MEMINT_AVG_BUSY_EN (1<<5)
1096#define MEMINT_EVAL_CHG_EN (1<<4)
1097#define MEMINT_MON_IDLE_EN (1<<3)
1098#define MEMINT_UP_EVAL_EN (1<<2)
1099#define MEMINT_DOWN_EVAL_EN (1<<1)
1100#define MEMINT_SW_CMD_EN (1<<0)
1101#define MEMINTRSTR 0x11182 /* 16 bits */
1102#define MEM_RSEXIT_MASK 0xc000
1103#define MEM_RSEXIT_SHIFT 14
1104#define MEM_CONT_BUSY_MASK 0x3000
1105#define MEM_CONT_BUSY_SHIFT 12
1106#define MEM_AVG_BUSY_MASK 0x0c00
1107#define MEM_AVG_BUSY_SHIFT 10
1108#define MEM_EVAL_CHG_MASK 0x0300
1109#define MEM_EVAL_BUSY_SHIFT 8
1110#define MEM_MON_IDLE_MASK 0x00c0
1111#define MEM_MON_IDLE_SHIFT 6
1112#define MEM_UP_EVAL_MASK 0x0030
1113#define MEM_UP_EVAL_SHIFT 4
1114#define MEM_DOWN_EVAL_MASK 0x000c
1115#define MEM_DOWN_EVAL_SHIFT 2
1116#define MEM_SW_CMD_MASK 0x0003
1117#define MEM_INT_STEER_GFX 0
1118#define MEM_INT_STEER_CMR 1
1119#define MEM_INT_STEER_SMI 2
1120#define MEM_INT_STEER_SCI 3
1121#define MEMINTRSTS 0x11184
1122#define MEMINT_RSEXIT (1<<7)
1123#define MEMINT_CONT_BUSY (1<<6)
1124#define MEMINT_AVG_BUSY (1<<5)
1125#define MEMINT_EVAL_CHG (1<<4)
1126#define MEMINT_MON_IDLE (1<<3)
1127#define MEMINT_UP_EVAL (1<<2)
1128#define MEMINT_DOWN_EVAL (1<<1)
1129#define MEMINT_SW_CMD (1<<0)
1130#define MEMMODECTL 0x11190
1131#define MEMMODE_BOOST_EN (1<<31)
1132#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1133#define MEMMODE_BOOST_FREQ_SHIFT 24
1134#define MEMMODE_IDLE_MODE_MASK 0x00030000
1135#define MEMMODE_IDLE_MODE_SHIFT 16
1136#define MEMMODE_IDLE_MODE_EVAL 0
1137#define MEMMODE_IDLE_MODE_CONT 1
1138#define MEMMODE_HWIDLE_EN (1<<15)
1139#define MEMMODE_SWMODE_EN (1<<14)
1140#define MEMMODE_RCLK_GATE (1<<13)
1141#define MEMMODE_HW_UPDATE (1<<12)
1142#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1143#define MEMMODE_FSTART_SHIFT 8
1144#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1145#define MEMMODE_FMAX_SHIFT 4
1146#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1147#define RCBMAXAVG 0x1119c
1148#define MEMSWCTL2 0x1119e /* Cantiga only */
1149#define SWMEMCMD_RENDER_OFF (0 << 13)
1150#define SWMEMCMD_RENDER_ON (1 << 13)
1151#define SWMEMCMD_SWFREQ (2 << 13)
1152#define SWMEMCMD_TARVID (3 << 13)
1153#define SWMEMCMD_VRM_OFF (4 << 13)
1154#define SWMEMCMD_VRM_ON (5 << 13)
1155#define CMDSTS (1<<12)
1156#define SFCAVM (1<<11)
1157#define SWFREQ_MASK 0x0380 /* P0-7 */
1158#define SWFREQ_SHIFT 7
1159#define TARVID_MASK 0x001f
1160#define MEMSTAT_CTG 0x111a0
1161#define RCBMINAVG 0x111a0
1162#define RCUPEI 0x111b0
1163#define RCDNEI 0x111b4
1164#define RSTDBYCTL 0x111b8
1165#define RS1EN (1<<31)
1166#define RS2EN (1<<30)
1167#define RS3EN (1<<29)
1168#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1169#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1170#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1171#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1172#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1173#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1174#define RSX_STATUS_MASK (7<<20)
1175#define RSX_STATUS_ON (0<<20)
1176#define RSX_STATUS_RC1 (1<<20)
1177#define RSX_STATUS_RC1E (2<<20)
1178#define RSX_STATUS_RS1 (3<<20)
1179#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1180#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1181#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1182#define RSX_STATUS_RSVD2 (7<<20)
1183#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1184#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1185#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1186#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1187#define RS1CONTSAV_MASK (3<<14)
1188#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1189#define RS1CONTSAV_RSVD (1<<14)
1190#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1191#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1192#define NORMSLEXLAT_MASK (3<<12)
1193#define SLOW_RS123 (0<<12)
1194#define SLOW_RS23 (1<<12)
1195#define SLOW_RS3 (2<<12)
1196#define NORMAL_RS123 (3<<12)
1197#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1198#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1199#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1200#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1201#define RS_CSTATE_MASK (3<<4)
1202#define RS_CSTATE_C367_RS1 (0<<4)
1203#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1204#define RS_CSTATE_RSVD (2<<4)
1205#define RS_CSTATE_C367_RS2 (3<<4)
1206#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1207#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1208#define VIDCTL 0x111c0
1209#define VIDSTS 0x111c8
1210#define VIDSTART 0x111cc /* 8 bits */
1211#define MEMSTAT_ILK 0x111f8
1212#define MEMSTAT_VID_MASK 0x7f00
1213#define MEMSTAT_VID_SHIFT 8
1214#define MEMSTAT_PSTATE_MASK 0x00f8
1215#define MEMSTAT_PSTATE_SHIFT 3
1216#define MEMSTAT_MON_ACTV (1<<2)
1217#define MEMSTAT_SRC_CTL_MASK 0x0003
1218#define MEMSTAT_SRC_CTL_CORE 0
1219#define MEMSTAT_SRC_CTL_TRB 1
1220#define MEMSTAT_SRC_CTL_THM 2
1221#define MEMSTAT_SRC_CTL_STDBY 3
1222#define RCPREVBSYTUPAVG 0x113b8
1223#define RCPREVBSYTDNAVG 0x113bc
1224#define PMMISC 0x11214
1225#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1226#define SDEW 0x1124c
1227#define CSIEW0 0x11250
1228#define CSIEW1 0x11254
1229#define CSIEW2 0x11258
1230#define PEW 0x1125c
1231#define DEW 0x11270
1232#define MCHAFE 0x112c0
1233#define CSIEC 0x112e0
1234#define DMIEC 0x112e4
1235#define DDREC 0x112e8
1236#define PEG0EC 0x112ec
1237#define PEG1EC 0x112f0
1238#define GFXEC 0x112f4
1239#define RPPREVBSYTUPAVG 0x113b8
1240#define RPPREVBSYTDNAVG 0x113bc
1241#define ECR 0x11600
1242#define ECR_GPFE (1<<31)
1243#define ECR_IMONE (1<<30)
1244#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1245#define OGW0 0x11608
1246#define OGW1 0x1160c
1247#define EG0 0x11610
1248#define EG1 0x11614
1249#define EG2 0x11618
1250#define EG3 0x1161c
1251#define EG4 0x11620
1252#define EG5 0x11624
1253#define EG6 0x11628
1254#define EG7 0x1162c
1255#define PXW 0x11664
1256#define PXWL 0x11680
1257#define LCFUSE02 0x116c0
1258#define LCFUSE_HIV_MASK 0x000000ff
1259#define CSIPLL0 0x12c10
1260#define DDRMPLL1 0X12c20
1261#define PEG_BAND_GAP_DATA 0x14d68
1262
1263#define GEN6_GT_PERF_STATUS 0x145948
1264#define GEN6_RP_STATE_LIMITS 0x145994
1265#define GEN6_RP_STATE_CAP 0x145998
1266
1267/*
1268 * Logical Context regs
1269 */
1270#define CCID 0x2180
1271#define CCID_EN (1<<0)
1272/*
1273 * Overlay regs
1274 */
1275
1276#define OVADD 0x30000
1277#define DOVSTA 0x30008
1278#define OC_BUF (0x3<<20)
1279#define OGAMC5 0x30010
1280#define OGAMC4 0x30014
1281#define OGAMC3 0x30018
1282#define OGAMC2 0x3001c
1283#define OGAMC1 0x30020
1284#define OGAMC0 0x30024
1285
1286/*
1287 * Display engine regs
1288 */
1289
1290/* Pipe A timing regs */
1291#define _HTOTAL_A 0x60000
1292#define _HBLANK_A 0x60004
1293#define _HSYNC_A 0x60008
1294#define _VTOTAL_A 0x6000c
1295#define _VBLANK_A 0x60010
1296#define _VSYNC_A 0x60014
1297#define _PIPEASRC 0x6001c
1298#define _BCLRPAT_A 0x60020
1299
1300/* Pipe B timing regs */
1301#define _HTOTAL_B 0x61000
1302#define _HBLANK_B 0x61004
1303#define _HSYNC_B 0x61008
1304#define _VTOTAL_B 0x6100c
1305#define _VBLANK_B 0x61010
1306#define _VSYNC_B 0x61014
1307#define _PIPEBSRC 0x6101c
1308#define _BCLRPAT_B 0x61020
1309
1310#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1311#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1312#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1313#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1314#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1315#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1316#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1317
1318/* VGA port control */
1319#define ADPA 0x61100
1320#define ADPA_DAC_ENABLE (1<<31)
1321#define ADPA_DAC_DISABLE 0
1322#define ADPA_PIPE_SELECT_MASK (1<<30)
1323#define ADPA_PIPE_A_SELECT 0
1324#define ADPA_PIPE_B_SELECT (1<<30)
1325#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1326#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1327#define ADPA_SETS_HVPOLARITY 0
1328#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1329#define ADPA_VSYNC_CNTL_ENABLE 0
1330#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1331#define ADPA_HSYNC_CNTL_ENABLE 0
1332#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1333#define ADPA_VSYNC_ACTIVE_LOW 0
1334#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1335#define ADPA_HSYNC_ACTIVE_LOW 0
1336#define ADPA_DPMS_MASK (~(3<<10))
1337#define ADPA_DPMS_ON (0<<10)
1338#define ADPA_DPMS_SUSPEND (1<<10)
1339#define ADPA_DPMS_STANDBY (2<<10)
1340#define ADPA_DPMS_OFF (3<<10)
1341
1342
1343/* Hotplug control (945+ only) */
1344#define PORT_HOTPLUG_EN 0x61110
1345#define HDMIB_HOTPLUG_INT_EN (1 << 29)
1346#define DPB_HOTPLUG_INT_EN (1 << 29)
1347#define HDMIC_HOTPLUG_INT_EN (1 << 28)
1348#define DPC_HOTPLUG_INT_EN (1 << 28)
1349#define HDMID_HOTPLUG_INT_EN (1 << 27)
1350#define DPD_HOTPLUG_INT_EN (1 << 27)
1351#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1352#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1353#define TV_HOTPLUG_INT_EN (1 << 18)
1354#define CRT_HOTPLUG_INT_EN (1 << 9)
1355#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1356#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1357/* must use period 64 on GM45 according to docs */
1358#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1359#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1360#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1361#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1362#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1363#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1364#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1365#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1366#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1367#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1368#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1369#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1370
1371#define PORT_HOTPLUG_STAT 0x61114
1372#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1373#define DPB_HOTPLUG_INT_STATUS (1 << 29)
1374#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1375#define DPC_HOTPLUG_INT_STATUS (1 << 28)
1376#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1377#define DPD_HOTPLUG_INT_STATUS (1 << 27)
1378#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1379#define TV_HOTPLUG_INT_STATUS (1 << 10)
1380#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1381#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1382#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1383#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1384#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1385#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1386
1387/* SDVO port control */
1388#define SDVOB 0x61140
1389#define SDVOC 0x61160
1390#define SDVO_ENABLE (1 << 31)
1391#define SDVO_PIPE_B_SELECT (1 << 30)
1392#define SDVO_STALL_SELECT (1 << 29)
1393#define SDVO_INTERRUPT_ENABLE (1 << 26)
1394/**
1395 * 915G/GM SDVO pixel multiplier.
1396 *
1397 * Programmed value is multiplier - 1, up to 5x.
1398 *
1399 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1400 */
1401#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1402#define SDVO_PORT_MULTIPLY_SHIFT 23
1403#define SDVO_PHASE_SELECT_MASK (15 << 19)
1404#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1405#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1406#define SDVOC_GANG_MODE (1 << 16)
1407#define SDVO_ENCODING_SDVO (0x0 << 10)
1408#define SDVO_ENCODING_HDMI (0x2 << 10)
1409/** Requird for HDMI operation */
1410#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1411#define SDVO_COLOR_RANGE_16_235 (1 << 8)
1412#define SDVO_BORDER_ENABLE (1 << 7)
1413#define SDVO_AUDIO_ENABLE (1 << 6)
1414/** New with 965, default is to be set */
1415#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1416/** New with 965, default is to be set */
1417#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1418#define SDVOB_PCIE_CONCURRENCY (1 << 3)
1419#define SDVO_DETECTED (1 << 2)
1420/* Bits to be preserved when writing */
1421#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1422#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1423
1424/* DVO port control */
1425#define DVOA 0x61120
1426#define DVOB 0x61140
1427#define DVOC 0x61160
1428#define DVO_ENABLE (1 << 31)
1429#define DVO_PIPE_B_SELECT (1 << 30)
1430#define DVO_PIPE_STALL_UNUSED (0 << 28)
1431#define DVO_PIPE_STALL (1 << 28)
1432#define DVO_PIPE_STALL_TV (2 << 28)
1433#define DVO_PIPE_STALL_MASK (3 << 28)
1434#define DVO_USE_VGA_SYNC (1 << 15)
1435#define DVO_DATA_ORDER_I740 (0 << 14)
1436#define DVO_DATA_ORDER_FP (1 << 14)
1437#define DVO_VSYNC_DISABLE (1 << 11)
1438#define DVO_HSYNC_DISABLE (1 << 10)
1439#define DVO_VSYNC_TRISTATE (1 << 9)
1440#define DVO_HSYNC_TRISTATE (1 << 8)
1441#define DVO_BORDER_ENABLE (1 << 7)
1442#define DVO_DATA_ORDER_GBRG (1 << 6)
1443#define DVO_DATA_ORDER_RGGB (0 << 6)
1444#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1445#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1446#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1447#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1448#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1449#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1450#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1451#define DVO_PRESERVE_MASK (0x7<<24)
1452#define DVOA_SRCDIM 0x61124
1453#define DVOB_SRCDIM 0x61144
1454#define DVOC_SRCDIM 0x61164
1455#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1456#define DVO_SRCDIM_VERTICAL_SHIFT 0
1457
1458/* LVDS port control */
1459#define LVDS 0x61180
1460/*
1461 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1462 * the DPLL semantics change when the LVDS is assigned to that pipe.
1463 */
1464#define LVDS_PORT_EN (1 << 31)
1465/* Selects pipe B for LVDS data. Must be set on pre-965. */
1466#define LVDS_PIPEB_SELECT (1 << 30)
1467#define LVDS_PIPE_MASK (1 << 30)
1468#define LVDS_PIPE(pipe) ((pipe) << 30)
1469/* LVDS dithering flag on 965/g4x platform */
1470#define LVDS_ENABLE_DITHER (1 << 25)
1471/* LVDS sync polarity flags. Set to invert (i.e. negative) */
1472#define LVDS_VSYNC_POLARITY (1 << 21)
1473#define LVDS_HSYNC_POLARITY (1 << 20)
1474
1475/* Enable border for unscaled (or aspect-scaled) display */
1476#define LVDS_BORDER_ENABLE (1 << 15)
1477/*
1478 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1479 * pixel.
1480 */
1481#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1482#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1483#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1484/*
1485 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1486 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1487 * on.
1488 */
1489#define LVDS_A3_POWER_MASK (3 << 6)
1490#define LVDS_A3_POWER_DOWN (0 << 6)
1491#define LVDS_A3_POWER_UP (3 << 6)
1492/*
1493 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1494 * is set.
1495 */
1496#define LVDS_CLKB_POWER_MASK (3 << 4)
1497#define LVDS_CLKB_POWER_DOWN (0 << 4)
1498#define LVDS_CLKB_POWER_UP (3 << 4)
1499/*
1500 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1501 * setting for whether we are in dual-channel mode. The B3 pair will
1502 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1503 */
1504#define LVDS_B0B3_POWER_MASK (3 << 2)
1505#define LVDS_B0B3_POWER_DOWN (0 << 2)
1506#define LVDS_B0B3_POWER_UP (3 << 2)
1507
1508/* Video Data Island Packet control */
1509#define VIDEO_DIP_DATA 0x61178
1510#define VIDEO_DIP_CTL 0x61170
1511#define VIDEO_DIP_ENABLE (1 << 31)
1512#define VIDEO_DIP_PORT_B (1 << 29)
1513#define VIDEO_DIP_PORT_C (2 << 29)
1514#define VIDEO_DIP_ENABLE_AVI (1 << 21)
1515#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1516#define VIDEO_DIP_ENABLE_SPD (8 << 21)
1517#define VIDEO_DIP_SELECT_AVI (0 << 19)
1518#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1519#define VIDEO_DIP_SELECT_SPD (3 << 19)
1520#define VIDEO_DIP_SELECT_MASK (3 << 19)
1521#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1522#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1523#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1524
1525/* Panel power sequencing */
1526#define PP_STATUS 0x61200
1527#define PP_ON (1 << 31)
1528/*
1529 * Indicates that all dependencies of the panel are on:
1530 *
1531 * - PLL enabled
1532 * - pipe enabled
1533 * - LVDS/DVOB/DVOC on
1534 */
1535#define PP_READY (1 << 30)
1536#define PP_SEQUENCE_NONE (0 << 28)
1537#define PP_SEQUENCE_ON (1 << 28)
1538#define PP_SEQUENCE_OFF (2 << 28)
1539#define PP_SEQUENCE_MASK 0x30000000
1540#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1541#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
1542#define PP_SEQUENCE_STATE_MASK 0x0000000f
1543#define PP_CONTROL 0x61204
1544#define POWER_TARGET_ON (1 << 0)
1545#define PP_ON_DELAYS 0x61208
1546#define PP_OFF_DELAYS 0x6120c
1547#define PP_DIVISOR 0x61210
1548
1549/* Panel fitting */
1550#define PFIT_CONTROL 0x61230
1551#define PFIT_ENABLE (1 << 31)
1552#define PFIT_PIPE_MASK (3 << 29)
1553#define PFIT_PIPE_SHIFT 29
1554#define VERT_INTERP_DISABLE (0 << 10)
1555#define VERT_INTERP_BILINEAR (1 << 10)
1556#define VERT_INTERP_MASK (3 << 10)
1557#define VERT_AUTO_SCALE (1 << 9)
1558#define HORIZ_INTERP_DISABLE (0 << 6)
1559#define HORIZ_INTERP_BILINEAR (1 << 6)
1560#define HORIZ_INTERP_MASK (3 << 6)
1561#define HORIZ_AUTO_SCALE (1 << 5)
1562#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1563#define PFIT_FILTER_FUZZY (0 << 24)
1564#define PFIT_SCALING_AUTO (0 << 26)
1565#define PFIT_SCALING_PROGRAMMED (1 << 26)
1566#define PFIT_SCALING_PILLAR (2 << 26)
1567#define PFIT_SCALING_LETTER (3 << 26)
1568#define PFIT_PGM_RATIOS 0x61234
1569#define PFIT_VERT_SCALE_MASK 0xfff00000
1570#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1571/* Pre-965 */
1572#define PFIT_VERT_SCALE_SHIFT 20
1573#define PFIT_VERT_SCALE_MASK 0xfff00000
1574#define PFIT_HORIZ_SCALE_SHIFT 4
1575#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1576/* 965+ */
1577#define PFIT_VERT_SCALE_SHIFT_965 16
1578#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1579#define PFIT_HORIZ_SCALE_SHIFT_965 0
1580#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1581
1582#define PFIT_AUTO_RATIOS 0x61238
1583
1584/* Backlight control */
1585#define BLC_PWM_CTL 0x61254
1586#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1587#define BLC_PWM_CTL2 0x61250 /* 965+ only */
1588#define BLM_COMBINATION_MODE (1 << 30)
1589/*
1590 * This is the most significant 15 bits of the number of backlight cycles in a
1591 * complete cycle of the modulated backlight control.
1592 *
1593 * The actual value is this field multiplied by two.
1594 */
1595#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1596#define BLM_LEGACY_MODE (1 << 16)
1597/*
1598 * This is the number of cycles out of the backlight modulation cycle for which
1599 * the backlight is on.
1600 *
1601 * This field must be no greater than the number of cycles in the complete
1602 * backlight modulation cycle.
1603 */
1604#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1605#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1606
1607#define BLC_HIST_CTL 0x61260
1608
1609/* TV port control */
1610#define TV_CTL 0x68000
1611/** Enables the TV encoder */
1612# define TV_ENC_ENABLE (1 << 31)
1613/** Sources the TV encoder input from pipe B instead of A. */
1614# define TV_ENC_PIPEB_SELECT (1 << 30)
1615/** Outputs composite video (DAC A only) */
1616# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1617/** Outputs SVideo video (DAC B/C) */
1618# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1619/** Outputs Component video (DAC A/B/C) */
1620# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1621/** Outputs Composite and SVideo (DAC A/B/C) */
1622# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1623# define TV_TRILEVEL_SYNC (1 << 21)
1624/** Enables slow sync generation (945GM only) */
1625# define TV_SLOW_SYNC (1 << 20)
1626/** Selects 4x oversampling for 480i and 576p */
1627# define TV_OVERSAMPLE_4X (0 << 18)
1628/** Selects 2x oversampling for 720p and 1080i */
1629# define TV_OVERSAMPLE_2X (1 << 18)
1630/** Selects no oversampling for 1080p */
1631# define TV_OVERSAMPLE_NONE (2 << 18)
1632/** Selects 8x oversampling */
1633# define TV_OVERSAMPLE_8X (3 << 18)
1634/** Selects progressive mode rather than interlaced */
1635# define TV_PROGRESSIVE (1 << 17)
1636/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1637# define TV_PAL_BURST (1 << 16)
1638/** Field for setting delay of Y compared to C */
1639# define TV_YC_SKEW_MASK (7 << 12)
1640/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1641# define TV_ENC_SDP_FIX (1 << 11)
1642/**
1643 * Enables a fix for the 915GM only.
1644 *
1645 * Not sure what it does.
1646 */
1647# define TV_ENC_C0_FIX (1 << 10)
1648/** Bits that must be preserved by software */
1649# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1650# define TV_FUSE_STATE_MASK (3 << 4)
1651/** Read-only state that reports all features enabled */
1652# define TV_FUSE_STATE_ENABLED (0 << 4)
1653/** Read-only state that reports that Macrovision is disabled in hardware*/
1654# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1655/** Read-only state that reports that TV-out is disabled in hardware. */
1656# define TV_FUSE_STATE_DISABLED (2 << 4)
1657/** Normal operation */
1658# define TV_TEST_MODE_NORMAL (0 << 0)
1659/** Encoder test pattern 1 - combo pattern */
1660# define TV_TEST_MODE_PATTERN_1 (1 << 0)
1661/** Encoder test pattern 2 - full screen vertical 75% color bars */
1662# define TV_TEST_MODE_PATTERN_2 (2 << 0)
1663/** Encoder test pattern 3 - full screen horizontal 75% color bars */
1664# define TV_TEST_MODE_PATTERN_3 (3 << 0)
1665/** Encoder test pattern 4 - random noise */
1666# define TV_TEST_MODE_PATTERN_4 (4 << 0)
1667/** Encoder test pattern 5 - linear color ramps */
1668# define TV_TEST_MODE_PATTERN_5 (5 << 0)
1669/**
1670 * This test mode forces the DACs to 50% of full output.
1671 *
1672 * This is used for load detection in combination with TVDAC_SENSE_MASK
1673 */
1674# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1675# define TV_TEST_MODE_MASK (7 << 0)
1676
1677#define TV_DAC 0x68004
1678# define TV_DAC_SAVE 0x00ffff00
1679/**
1680 * Reports that DAC state change logic has reported change (RO).
1681 *
1682 * This gets cleared when TV_DAC_STATE_EN is cleared
1683*/
1684# define TVDAC_STATE_CHG (1 << 31)
1685# define TVDAC_SENSE_MASK (7 << 28)
1686/** Reports that DAC A voltage is above the detect threshold */
1687# define TVDAC_A_SENSE (1 << 30)
1688/** Reports that DAC B voltage is above the detect threshold */
1689# define TVDAC_B_SENSE (1 << 29)
1690/** Reports that DAC C voltage is above the detect threshold */
1691# define TVDAC_C_SENSE (1 << 28)
1692/**
1693 * Enables DAC state detection logic, for load-based TV detection.
1694 *
1695 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1696 * to off, for load detection to work.
1697 */
1698# define TVDAC_STATE_CHG_EN (1 << 27)
1699/** Sets the DAC A sense value to high */
1700# define TVDAC_A_SENSE_CTL (1 << 26)
1701/** Sets the DAC B sense value to high */
1702# define TVDAC_B_SENSE_CTL (1 << 25)
1703/** Sets the DAC C sense value to high */
1704# define TVDAC_C_SENSE_CTL (1 << 24)
1705/** Overrides the ENC_ENABLE and DAC voltage levels */
1706# define DAC_CTL_OVERRIDE (1 << 7)
1707/** Sets the slew rate. Must be preserved in software */
1708# define ENC_TVDAC_SLEW_FAST (1 << 6)
1709# define DAC_A_1_3_V (0 << 4)
1710# define DAC_A_1_1_V (1 << 4)
1711# define DAC_A_0_7_V (2 << 4)
1712# define DAC_A_MASK (3 << 4)
1713# define DAC_B_1_3_V (0 << 2)
1714# define DAC_B_1_1_V (1 << 2)
1715# define DAC_B_0_7_V (2 << 2)
1716# define DAC_B_MASK (3 << 2)
1717# define DAC_C_1_3_V (0 << 0)
1718# define DAC_C_1_1_V (1 << 0)
1719# define DAC_C_0_7_V (2 << 0)
1720# define DAC_C_MASK (3 << 0)
1721
1722/**
1723 * CSC coefficients are stored in a floating point format with 9 bits of
1724 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1725 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1726 * -1 (0x3) being the only legal negative value.
1727 */
1728#define TV_CSC_Y 0x68010
1729# define TV_RY_MASK 0x07ff0000
1730# define TV_RY_SHIFT 16
1731# define TV_GY_MASK 0x00000fff
1732# define TV_GY_SHIFT 0
1733
1734#define TV_CSC_Y2 0x68014
1735# define TV_BY_MASK 0x07ff0000
1736# define TV_BY_SHIFT 16
1737/**
1738 * Y attenuation for component video.
1739 *
1740 * Stored in 1.9 fixed point.
1741 */
1742# define TV_AY_MASK 0x000003ff
1743# define TV_AY_SHIFT 0
1744
1745#define TV_CSC_U 0x68018
1746# define TV_RU_MASK 0x07ff0000
1747# define TV_RU_SHIFT 16
1748# define TV_GU_MASK 0x000007ff
1749# define TV_GU_SHIFT 0
1750
1751#define TV_CSC_U2 0x6801c
1752# define TV_BU_MASK 0x07ff0000
1753# define TV_BU_SHIFT 16
1754/**
1755 * U attenuation for component video.
1756 *
1757 * Stored in 1.9 fixed point.
1758 */
1759# define TV_AU_MASK 0x000003ff
1760# define TV_AU_SHIFT 0
1761
1762#define TV_CSC_V 0x68020
1763# define TV_RV_MASK 0x0fff0000
1764# define TV_RV_SHIFT 16
1765# define TV_GV_MASK 0x000007ff
1766# define TV_GV_SHIFT 0
1767
1768#define TV_CSC_V2 0x68024
1769# define TV_BV_MASK 0x07ff0000
1770# define TV_BV_SHIFT 16
1771/**
1772 * V attenuation for component video.
1773 *
1774 * Stored in 1.9 fixed point.
1775 */
1776# define TV_AV_MASK 0x000007ff
1777# define TV_AV_SHIFT 0
1778
1779#define TV_CLR_KNOBS 0x68028
1780/** 2s-complement brightness adjustment */
1781# define TV_BRIGHTNESS_MASK 0xff000000
1782# define TV_BRIGHTNESS_SHIFT 24
1783/** Contrast adjustment, as a 2.6 unsigned floating point number */
1784# define TV_CONTRAST_MASK 0x00ff0000
1785# define TV_CONTRAST_SHIFT 16
1786/** Saturation adjustment, as a 2.6 unsigned floating point number */
1787# define TV_SATURATION_MASK 0x0000ff00
1788# define TV_SATURATION_SHIFT 8
1789/** Hue adjustment, as an integer phase angle in degrees */
1790# define TV_HUE_MASK 0x000000ff
1791# define TV_HUE_SHIFT 0
1792
1793#define TV_CLR_LEVEL 0x6802c
1794/** Controls the DAC level for black */
1795# define TV_BLACK_LEVEL_MASK 0x01ff0000
1796# define TV_BLACK_LEVEL_SHIFT 16
1797/** Controls the DAC level for blanking */
1798# define TV_BLANK_LEVEL_MASK 0x000001ff
1799# define TV_BLANK_LEVEL_SHIFT 0
1800
1801#define TV_H_CTL_1 0x68030
1802/** Number of pixels in the hsync. */
1803# define TV_HSYNC_END_MASK 0x1fff0000
1804# define TV_HSYNC_END_SHIFT 16
1805/** Total number of pixels minus one in the line (display and blanking). */
1806# define TV_HTOTAL_MASK 0x00001fff
1807# define TV_HTOTAL_SHIFT 0
1808
1809#define TV_H_CTL_2 0x68034
1810/** Enables the colorburst (needed for non-component color) */
1811# define TV_BURST_ENA (1 << 31)
1812/** Offset of the colorburst from the start of hsync, in pixels minus one. */
1813# define TV_HBURST_START_SHIFT 16
1814# define TV_HBURST_START_MASK 0x1fff0000
1815/** Length of the colorburst */
1816# define TV_HBURST_LEN_SHIFT 0
1817# define TV_HBURST_LEN_MASK 0x0001fff
1818
1819#define TV_H_CTL_3 0x68038
1820/** End of hblank, measured in pixels minus one from start of hsync */
1821# define TV_HBLANK_END_SHIFT 16
1822# define TV_HBLANK_END_MASK 0x1fff0000
1823/** Start of hblank, measured in pixels minus one from start of hsync */
1824# define TV_HBLANK_START_SHIFT 0
1825# define TV_HBLANK_START_MASK 0x0001fff
1826
1827#define TV_V_CTL_1 0x6803c
1828/** XXX */
1829# define TV_NBR_END_SHIFT 16
1830# define TV_NBR_END_MASK 0x07ff0000
1831/** XXX */
1832# define TV_VI_END_F1_SHIFT 8
1833# define TV_VI_END_F1_MASK 0x00003f00
1834/** XXX */
1835# define TV_VI_END_F2_SHIFT 0
1836# define TV_VI_END_F2_MASK 0x0000003f
1837
1838#define TV_V_CTL_2 0x68040
1839/** Length of vsync, in half lines */
1840# define TV_VSYNC_LEN_MASK 0x07ff0000
1841# define TV_VSYNC_LEN_SHIFT 16
1842/** Offset of the start of vsync in field 1, measured in one less than the
1843 * number of half lines.
1844 */
1845# define TV_VSYNC_START_F1_MASK 0x00007f00
1846# define TV_VSYNC_START_F1_SHIFT 8
1847/**
1848 * Offset of the start of vsync in field 2, measured in one less than the
1849 * number of half lines.
1850 */
1851# define TV_VSYNC_START_F2_MASK 0x0000007f
1852# define TV_VSYNC_START_F2_SHIFT 0
1853
1854#define TV_V_CTL_3 0x68044
1855/** Enables generation of the equalization signal */
1856# define TV_EQUAL_ENA (1 << 31)
1857/** Length of vsync, in half lines */
1858# define TV_VEQ_LEN_MASK 0x007f0000
1859# define TV_VEQ_LEN_SHIFT 16
1860/** Offset of the start of equalization in field 1, measured in one less than
1861 * the number of half lines.
1862 */
1863# define TV_VEQ_START_F1_MASK 0x0007f00
1864# define TV_VEQ_START_F1_SHIFT 8
1865/**
1866 * Offset of the start of equalization in field 2, measured in one less than
1867 * the number of half lines.
1868 */
1869# define TV_VEQ_START_F2_MASK 0x000007f
1870# define TV_VEQ_START_F2_SHIFT 0
1871
1872#define TV_V_CTL_4 0x68048
1873/**
1874 * Offset to start of vertical colorburst, measured in one less than the
1875 * number of lines from vertical start.
1876 */
1877# define TV_VBURST_START_F1_MASK 0x003f0000
1878# define TV_VBURST_START_F1_SHIFT 16
1879/**
1880 * Offset to the end of vertical colorburst, measured in one less than the
1881 * number of lines from the start of NBR.
1882 */
1883# define TV_VBURST_END_F1_MASK 0x000000ff
1884# define TV_VBURST_END_F1_SHIFT 0
1885
1886#define TV_V_CTL_5 0x6804c
1887/**
1888 * Offset to start of vertical colorburst, measured in one less than the
1889 * number of lines from vertical start.
1890 */
1891# define TV_VBURST_START_F2_MASK 0x003f0000
1892# define TV_VBURST_START_F2_SHIFT 16
1893/**
1894 * Offset to the end of vertical colorburst, measured in one less than the
1895 * number of lines from the start of NBR.
1896 */
1897# define TV_VBURST_END_F2_MASK 0x000000ff
1898# define TV_VBURST_END_F2_SHIFT 0
1899
1900#define TV_V_CTL_6 0x68050
1901/**
1902 * Offset to start of vertical colorburst, measured in one less than the
1903 * number of lines from vertical start.
1904 */
1905# define TV_VBURST_START_F3_MASK 0x003f0000
1906# define TV_VBURST_START_F3_SHIFT 16
1907/**
1908 * Offset to the end of vertical colorburst, measured in one less than the
1909 * number of lines from the start of NBR.
1910 */
1911# define TV_VBURST_END_F3_MASK 0x000000ff
1912# define TV_VBURST_END_F3_SHIFT 0
1913
1914#define TV_V_CTL_7 0x68054
1915/**
1916 * Offset to start of vertical colorburst, measured in one less than the
1917 * number of lines from vertical start.
1918 */
1919# define TV_VBURST_START_F4_MASK 0x003f0000
1920# define TV_VBURST_START_F4_SHIFT 16
1921/**
1922 * Offset to the end of vertical colorburst, measured in one less than the
1923 * number of lines from the start of NBR.
1924 */
1925# define TV_VBURST_END_F4_MASK 0x000000ff
1926# define TV_VBURST_END_F4_SHIFT 0
1927
1928#define TV_SC_CTL_1 0x68060
1929/** Turns on the first subcarrier phase generation DDA */
1930# define TV_SC_DDA1_EN (1 << 31)
1931/** Turns on the first subcarrier phase generation DDA */
1932# define TV_SC_DDA2_EN (1 << 30)
1933/** Turns on the first subcarrier phase generation DDA */
1934# define TV_SC_DDA3_EN (1 << 29)
1935/** Sets the subcarrier DDA to reset frequency every other field */
1936# define TV_SC_RESET_EVERY_2 (0 << 24)
1937/** Sets the subcarrier DDA to reset frequency every fourth field */
1938# define TV_SC_RESET_EVERY_4 (1 << 24)
1939/** Sets the subcarrier DDA to reset frequency every eighth field */
1940# define TV_SC_RESET_EVERY_8 (2 << 24)
1941/** Sets the subcarrier DDA to never reset the frequency */
1942# define TV_SC_RESET_NEVER (3 << 24)
1943/** Sets the peak amplitude of the colorburst.*/
1944# define TV_BURST_LEVEL_MASK 0x00ff0000
1945# define TV_BURST_LEVEL_SHIFT 16
1946/** Sets the increment of the first subcarrier phase generation DDA */
1947# define TV_SCDDA1_INC_MASK 0x00000fff
1948# define TV_SCDDA1_INC_SHIFT 0
1949
1950#define TV_SC_CTL_2 0x68064
1951/** Sets the rollover for the second subcarrier phase generation DDA */
1952# define TV_SCDDA2_SIZE_MASK 0x7fff0000
1953# define TV_SCDDA2_SIZE_SHIFT 16
1954/** Sets the increent of the second subcarrier phase generation DDA */
1955# define TV_SCDDA2_INC_MASK 0x00007fff
1956# define TV_SCDDA2_INC_SHIFT 0
1957
1958#define TV_SC_CTL_3 0x68068
1959/** Sets the rollover for the third subcarrier phase generation DDA */
1960# define TV_SCDDA3_SIZE_MASK 0x7fff0000
1961# define TV_SCDDA3_SIZE_SHIFT 16
1962/** Sets the increent of the third subcarrier phase generation DDA */
1963# define TV_SCDDA3_INC_MASK 0x00007fff
1964# define TV_SCDDA3_INC_SHIFT 0
1965
1966#define TV_WIN_POS 0x68070
1967/** X coordinate of the display from the start of horizontal active */
1968# define TV_XPOS_MASK 0x1fff0000
1969# define TV_XPOS_SHIFT 16
1970/** Y coordinate of the display from the start of vertical active (NBR) */
1971# define TV_YPOS_MASK 0x00000fff
1972# define TV_YPOS_SHIFT 0
1973
1974#define TV_WIN_SIZE 0x68074
1975/** Horizontal size of the display window, measured in pixels*/
1976# define TV_XSIZE_MASK 0x1fff0000
1977# define TV_XSIZE_SHIFT 16
1978/**
1979 * Vertical size of the display window, measured in pixels.
1980 *
1981 * Must be even for interlaced modes.
1982 */
1983# define TV_YSIZE_MASK 0x00000fff
1984# define TV_YSIZE_SHIFT 0
1985
1986#define TV_FILTER_CTL_1 0x68080
1987/**
1988 * Enables automatic scaling calculation.
1989 *
1990 * If set, the rest of the registers are ignored, and the calculated values can
1991 * be read back from the register.
1992 */
1993# define TV_AUTO_SCALE (1 << 31)
1994/**
1995 * Disables the vertical filter.
1996 *
1997 * This is required on modes more than 1024 pixels wide */
1998# define TV_V_FILTER_BYPASS (1 << 29)
1999/** Enables adaptive vertical filtering */
2000# define TV_VADAPT (1 << 28)
2001# define TV_VADAPT_MODE_MASK (3 << 26)
2002/** Selects the least adaptive vertical filtering mode */
2003# define TV_VADAPT_MODE_LEAST (0 << 26)
2004/** Selects the moderately adaptive vertical filtering mode */
2005# define TV_VADAPT_MODE_MODERATE (1 << 26)
2006/** Selects the most adaptive vertical filtering mode */
2007# define TV_VADAPT_MODE_MOST (3 << 26)
2008/**
2009 * Sets the horizontal scaling factor.
2010 *
2011 * This should be the fractional part of the horizontal scaling factor divided
2012 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2013 *
2014 * (src width - 1) / ((oversample * dest width) - 1)
2015 */
2016# define TV_HSCALE_FRAC_MASK 0x00003fff
2017# define TV_HSCALE_FRAC_SHIFT 0
2018
2019#define TV_FILTER_CTL_2 0x68084
2020/**
2021 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2022 *
2023 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2024 */
2025# define TV_VSCALE_INT_MASK 0x00038000
2026# define TV_VSCALE_INT_SHIFT 15
2027/**
2028 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2029 *
2030 * \sa TV_VSCALE_INT_MASK
2031 */
2032# define TV_VSCALE_FRAC_MASK 0x00007fff
2033# define TV_VSCALE_FRAC_SHIFT 0
2034
2035#define TV_FILTER_CTL_3 0x68088
2036/**
2037 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2038 *
2039 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2040 *
2041 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2042 */
2043# define TV_VSCALE_IP_INT_MASK 0x00038000
2044# define TV_VSCALE_IP_INT_SHIFT 15
2045/**
2046 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2047 *
2048 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2049 *
2050 * \sa TV_VSCALE_IP_INT_MASK
2051 */
2052# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2053# define TV_VSCALE_IP_FRAC_SHIFT 0
2054
2055#define TV_CC_CONTROL 0x68090
2056# define TV_CC_ENABLE (1 << 31)
2057/**
2058 * Specifies which field to send the CC data in.
2059 *
2060 * CC data is usually sent in field 0.
2061 */
2062# define TV_CC_FID_MASK (1 << 27)
2063# define TV_CC_FID_SHIFT 27
2064/** Sets the horizontal position of the CC data. Usually 135. */
2065# define TV_CC_HOFF_MASK 0x03ff0000
2066# define TV_CC_HOFF_SHIFT 16
2067/** Sets the vertical position of the CC data. Usually 21 */
2068# define TV_CC_LINE_MASK 0x0000003f
2069# define TV_CC_LINE_SHIFT 0
2070
2071#define TV_CC_DATA 0x68094
2072# define TV_CC_RDY (1 << 31)
2073/** Second word of CC data to be transmitted. */
2074# define TV_CC_DATA_2_MASK 0x007f0000
2075# define TV_CC_DATA_2_SHIFT 16
2076/** First word of CC data to be transmitted. */
2077# define TV_CC_DATA_1_MASK 0x0000007f
2078# define TV_CC_DATA_1_SHIFT 0
2079
2080#define TV_H_LUMA_0 0x68100
2081#define TV_H_LUMA_59 0x681ec
2082#define TV_H_CHROMA_0 0x68200
2083#define TV_H_CHROMA_59 0x682ec
2084#define TV_V_LUMA_0 0x68300
2085#define TV_V_LUMA_42 0x683a8
2086#define TV_V_CHROMA_0 0x68400
2087#define TV_V_CHROMA_42 0x684a8
2088
2089/* Display Port */
2090#define DP_A 0x64000 /* eDP */
2091#define DP_B 0x64100
2092#define DP_C 0x64200
2093#define DP_D 0x64300
2094
2095#define DP_PORT_EN (1 << 31)
2096#define DP_PIPEB_SELECT (1 << 30)
2097#define DP_PIPE_MASK (1 << 30)
2098
2099/* Link training mode - select a suitable mode for each stage */
2100#define DP_LINK_TRAIN_PAT_1 (0 << 28)
2101#define DP_LINK_TRAIN_PAT_2 (1 << 28)
2102#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2103#define DP_LINK_TRAIN_OFF (3 << 28)
2104#define DP_LINK_TRAIN_MASK (3 << 28)
2105#define DP_LINK_TRAIN_SHIFT 28
2106
2107/* CPT Link training mode */
2108#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2109#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2110#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2111#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2112#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2113#define DP_LINK_TRAIN_SHIFT_CPT 8
2114
2115/* Signal voltages. These are mostly controlled by the other end */
2116#define DP_VOLTAGE_0_4 (0 << 25)
2117#define DP_VOLTAGE_0_6 (1 << 25)
2118#define DP_VOLTAGE_0_8 (2 << 25)
2119#define DP_VOLTAGE_1_2 (3 << 25)
2120#define DP_VOLTAGE_MASK (7 << 25)
2121#define DP_VOLTAGE_SHIFT 25
2122
2123/* Signal pre-emphasis levels, like voltages, the other end tells us what
2124 * they want
2125 */
2126#define DP_PRE_EMPHASIS_0 (0 << 22)
2127#define DP_PRE_EMPHASIS_3_5 (1 << 22)
2128#define DP_PRE_EMPHASIS_6 (2 << 22)
2129#define DP_PRE_EMPHASIS_9_5 (3 << 22)
2130#define DP_PRE_EMPHASIS_MASK (7 << 22)
2131#define DP_PRE_EMPHASIS_SHIFT 22
2132
2133/* How many wires to use. I guess 3 was too hard */
2134#define DP_PORT_WIDTH_1 (0 << 19)
2135#define DP_PORT_WIDTH_2 (1 << 19)
2136#define DP_PORT_WIDTH_4 (3 << 19)
2137#define DP_PORT_WIDTH_MASK (7 << 19)
2138
2139/* Mystic DPCD version 1.1 special mode */
2140#define DP_ENHANCED_FRAMING (1 << 18)
2141
2142/* eDP */
2143#define DP_PLL_FREQ_270MHZ (0 << 16)
2144#define DP_PLL_FREQ_160MHZ (1 << 16)
2145#define DP_PLL_FREQ_MASK (3 << 16)
2146
2147/** locked once port is enabled */
2148#define DP_PORT_REVERSAL (1 << 15)
2149
2150/* eDP */
2151#define DP_PLL_ENABLE (1 << 14)
2152
2153/** sends the clock on lane 15 of the PEG for debug */
2154#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2155
2156#define DP_SCRAMBLING_DISABLE (1 << 12)
2157#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2158
2159/** limit RGB values to avoid confusing TVs */
2160#define DP_COLOR_RANGE_16_235 (1 << 8)
2161
2162/** Turn on the audio link */
2163#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2164
2165/** vs and hs sync polarity */
2166#define DP_SYNC_VS_HIGH (1 << 4)
2167#define DP_SYNC_HS_HIGH (1 << 3)
2168
2169/** A fantasy */
2170#define DP_DETECTED (1 << 2)
2171
2172/** The aux channel provides a way to talk to the
2173 * signal sink for DDC etc. Max packet size supported
2174 * is 20 bytes in each direction, hence the 5 fixed
2175 * data registers
2176 */
2177#define DPA_AUX_CH_CTL 0x64010
2178#define DPA_AUX_CH_DATA1 0x64014
2179#define DPA_AUX_CH_DATA2 0x64018
2180#define DPA_AUX_CH_DATA3 0x6401c
2181#define DPA_AUX_CH_DATA4 0x64020
2182#define DPA_AUX_CH_DATA5 0x64024
2183
2184#define DPB_AUX_CH_CTL 0x64110
2185#define DPB_AUX_CH_DATA1 0x64114
2186#define DPB_AUX_CH_DATA2 0x64118
2187#define DPB_AUX_CH_DATA3 0x6411c
2188#define DPB_AUX_CH_DATA4 0x64120
2189#define DPB_AUX_CH_DATA5 0x64124
2190
2191#define DPC_AUX_CH_CTL 0x64210
2192#define DPC_AUX_CH_DATA1 0x64214
2193#define DPC_AUX_CH_DATA2 0x64218
2194#define DPC_AUX_CH_DATA3 0x6421c
2195#define DPC_AUX_CH_DATA4 0x64220
2196#define DPC_AUX_CH_DATA5 0x64224
2197
2198#define DPD_AUX_CH_CTL 0x64310
2199#define DPD_AUX_CH_DATA1 0x64314
2200#define DPD_AUX_CH_DATA2 0x64318
2201#define DPD_AUX_CH_DATA3 0x6431c
2202#define DPD_AUX_CH_DATA4 0x64320
2203#define DPD_AUX_CH_DATA5 0x64324
2204
2205#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2206#define DP_AUX_CH_CTL_DONE (1 << 30)
2207#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2208#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2209#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2210#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2211#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2212#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2213#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2214#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2215#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2216#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2217#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2218#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2219#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2220#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2221#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2222#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2223#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2224#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2225#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2226
2227/*
2228 * Computing GMCH M and N values for the Display Port link
2229 *
2230 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2231 *
2232 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2233 *
2234 * The GMCH value is used internally
2235 *
2236 * bytes_per_pixel is the number of bytes coming out of the plane,
2237 * which is after the LUTs, so we want the bytes for our color format.
2238 * For our current usage, this is always 3, one byte for R, G and B.
2239 */
2240#define _PIPEA_GMCH_DATA_M 0x70050
2241#define _PIPEB_GMCH_DATA_M 0x71050
2242
2243/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2244#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2245#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2246
2247#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2248
2249#define _PIPEA_GMCH_DATA_N 0x70054
2250#define _PIPEB_GMCH_DATA_N 0x71054
2251#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2252
2253/*
2254 * Computing Link M and N values for the Display Port link
2255 *
2256 * Link M / N = pixel_clock / ls_clk
2257 *
2258 * (the DP spec calls pixel_clock the 'strm_clk')
2259 *
2260 * The Link value is transmitted in the Main Stream
2261 * Attributes and VB-ID.
2262 */
2263
2264#define _PIPEA_DP_LINK_M 0x70060
2265#define _PIPEB_DP_LINK_M 0x71060
2266#define PIPEA_DP_LINK_M_MASK (0xffffff)
2267
2268#define _PIPEA_DP_LINK_N 0x70064
2269#define _PIPEB_DP_LINK_N 0x71064
2270#define PIPEA_DP_LINK_N_MASK (0xffffff)
2271
2272#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2273#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2274#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2275#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2276
2277/* Display & cursor control */
2278
2279/* Pipe A */
2280#define _PIPEADSL 0x70000
2281#define DSL_LINEMASK 0x00000fff
2282#define _PIPEACONF 0x70008
2283#define PIPECONF_ENABLE (1<<31)
2284#define PIPECONF_DISABLE 0
2285#define PIPECONF_DOUBLE_WIDE (1<<30)
2286#define I965_PIPECONF_ACTIVE (1<<30)
2287#define PIPECONF_SINGLE_WIDE 0
2288#define PIPECONF_PIPE_UNLOCKED 0
2289#define PIPECONF_PIPE_LOCKED (1<<25)
2290#define PIPECONF_PALETTE 0
2291#define PIPECONF_GAMMA (1<<24)
2292#define PIPECONF_FORCE_BORDER (1<<25)
2293#define PIPECONF_PROGRESSIVE (0 << 21)
2294#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2295#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2296#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2297#define PIPECONF_BPP_MASK (0x000000e0)
2298#define PIPECONF_BPP_8 (0<<5)
2299#define PIPECONF_BPP_10 (1<<5)
2300#define PIPECONF_BPP_6 (2<<5)
2301#define PIPECONF_BPP_12 (3<<5)
2302#define PIPECONF_DITHER_EN (1<<4)
2303#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2304#define PIPECONF_DITHER_TYPE_SP (0<<2)
2305#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2306#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2307#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2308#define _PIPEASTAT 0x70024
2309#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2310#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2311#define PIPE_CRC_DONE_ENABLE (1UL<<28)
2312#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2313#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2314#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2315#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2316#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2317#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2318#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2319#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2320#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2321#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2322#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2323#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2324#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2325#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2326#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2327#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2328#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2329#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2330#define PIPE_DPST_EVENT_STATUS (1UL<<7)
2331#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2332#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2333#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2334#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2335#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2336#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2337#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2338#define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2339#define PIPE_8BPC (0 << 5)
2340#define PIPE_10BPC (1 << 5)
2341#define PIPE_6BPC (2 << 5)
2342#define PIPE_12BPC (3 << 5)
2343
2344#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2345#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2346#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2347#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2348#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2349#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2350
2351#define DSPARB 0x70030
2352#define DSPARB_CSTART_MASK (0x7f << 7)
2353#define DSPARB_CSTART_SHIFT 7
2354#define DSPARB_BSTART_MASK (0x7f)
2355#define DSPARB_BSTART_SHIFT 0
2356#define DSPARB_BEND_SHIFT 9 /* on 855 */
2357#define DSPARB_AEND_SHIFT 0
2358
2359#define DSPFW1 0x70034
2360#define DSPFW_SR_SHIFT 23
2361#define DSPFW_SR_MASK (0x1ff<<23)
2362#define DSPFW_CURSORB_SHIFT 16
2363#define DSPFW_CURSORB_MASK (0x3f<<16)
2364#define DSPFW_PLANEB_SHIFT 8
2365#define DSPFW_PLANEB_MASK (0x7f<<8)
2366#define DSPFW_PLANEA_MASK (0x7f)
2367#define DSPFW2 0x70038
2368#define DSPFW_CURSORA_MASK 0x00003f00
2369#define DSPFW_CURSORA_SHIFT 8
2370#define DSPFW_PLANEC_MASK (0x7f)
2371#define DSPFW3 0x7003c
2372#define DSPFW_HPLL_SR_EN (1<<31)
2373#define DSPFW_CURSOR_SR_SHIFT 24
2374#define PINEVIEW_SELF_REFRESH_EN (1<<30)
2375#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2376#define DSPFW_HPLL_CURSOR_SHIFT 16
2377#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2378#define DSPFW_HPLL_SR_MASK (0x1ff)
2379
2380/* FIFO watermark sizes etc */
2381#define G4X_FIFO_LINE_SIZE 64
2382#define I915_FIFO_LINE_SIZE 64
2383#define I830_FIFO_LINE_SIZE 32
2384
2385#define G4X_FIFO_SIZE 127
2386#define I965_FIFO_SIZE 512
2387#define I945_FIFO_SIZE 127
2388#define I915_FIFO_SIZE 95
2389#define I855GM_FIFO_SIZE 127 /* In cachelines */
2390#define I830_FIFO_SIZE 95
2391
2392#define G4X_MAX_WM 0x3f
2393#define I915_MAX_WM 0x3f
2394
2395#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2396#define PINEVIEW_FIFO_LINE_SIZE 64
2397#define PINEVIEW_MAX_WM 0x1ff
2398#define PINEVIEW_DFT_WM 0x3f
2399#define PINEVIEW_DFT_HPLLOFF_WM 0
2400#define PINEVIEW_GUARD_WM 10
2401#define PINEVIEW_CURSOR_FIFO 64
2402#define PINEVIEW_CURSOR_MAX_WM 0x3f
2403#define PINEVIEW_CURSOR_DFT_WM 0
2404#define PINEVIEW_CURSOR_GUARD_WM 5
2405
2406#define I965_CURSOR_FIFO 64
2407#define I965_CURSOR_MAX_WM 32
2408#define I965_CURSOR_DFT_WM 8
2409
2410/* define the Watermark register on Ironlake */
2411#define WM0_PIPEA_ILK 0x45100
2412#define WM0_PIPE_PLANE_MASK (0x7f<<16)
2413#define WM0_PIPE_PLANE_SHIFT 16
2414#define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2415#define WM0_PIPE_SPRITE_SHIFT 8
2416#define WM0_PIPE_CURSOR_MASK (0x1f)
2417
2418#define WM0_PIPEB_ILK 0x45104
2419#define WM1_LP_ILK 0x45108
2420#define WM1_LP_SR_EN (1<<31)
2421#define WM1_LP_LATENCY_SHIFT 24
2422#define WM1_LP_LATENCY_MASK (0x7f<<24)
2423#define WM1_LP_FBC_MASK (0xf<<20)
2424#define WM1_LP_FBC_SHIFT 20
2425#define WM1_LP_SR_MASK (0x1ff<<8)
2426#define WM1_LP_SR_SHIFT 8
2427#define WM1_LP_CURSOR_MASK (0x3f)
2428#define WM2_LP_ILK 0x4510c
2429#define WM2_LP_EN (1<<31)
2430#define WM3_LP_ILK 0x45110
2431#define WM3_LP_EN (1<<31)
2432#define WM1S_LP_ILK 0x45120
2433#define WM1S_LP_EN (1<<31)
2434
2435/* Memory latency timer register */
2436#define MLTR_ILK 0x11222
2437#define MLTR_WM1_SHIFT 0
2438#define MLTR_WM2_SHIFT 8
2439/* the unit of memory self-refresh latency time is 0.5us */
2440#define ILK_SRLT_MASK 0x3f
2441#define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2442#define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2443#define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2444
2445/* define the fifo size on Ironlake */
2446#define ILK_DISPLAY_FIFO 128
2447#define ILK_DISPLAY_MAXWM 64
2448#define ILK_DISPLAY_DFTWM 8
2449#define ILK_CURSOR_FIFO 32
2450#define ILK_CURSOR_MAXWM 16
2451#define ILK_CURSOR_DFTWM 8
2452
2453#define ILK_DISPLAY_SR_FIFO 512
2454#define ILK_DISPLAY_MAX_SRWM 0x1ff
2455#define ILK_DISPLAY_DFT_SRWM 0x3f
2456#define ILK_CURSOR_SR_FIFO 64
2457#define ILK_CURSOR_MAX_SRWM 0x3f
2458#define ILK_CURSOR_DFT_SRWM 8
2459
2460#define ILK_FIFO_LINE_SIZE 64
2461
2462/* define the WM info on Sandybridge */
2463#define SNB_DISPLAY_FIFO 128
2464#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2465#define SNB_DISPLAY_DFTWM 8
2466#define SNB_CURSOR_FIFO 32
2467#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2468#define SNB_CURSOR_DFTWM 8
2469
2470#define SNB_DISPLAY_SR_FIFO 512
2471#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2472#define SNB_DISPLAY_DFT_SRWM 0x3f
2473#define SNB_CURSOR_SR_FIFO 64
2474#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2475#define SNB_CURSOR_DFT_SRWM 8
2476
2477#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2478
2479#define SNB_FIFO_LINE_SIZE 64
2480
2481
2482/* the address where we get all kinds of latency value */
2483#define SSKPD 0x5d10
2484#define SSKPD_WM_MASK 0x3f
2485#define SSKPD_WM0_SHIFT 0
2486#define SSKPD_WM1_SHIFT 8
2487#define SSKPD_WM2_SHIFT 16
2488#define SSKPD_WM3_SHIFT 24
2489
2490#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2491#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2492#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2493#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2494#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2495
2496/*
2497 * The two pipe frame counter registers are not synchronized, so
2498 * reading a stable value is somewhat tricky. The following code
2499 * should work:
2500 *
2501 * do {
2502 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2503 * PIPE_FRAME_HIGH_SHIFT;
2504 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2505 * PIPE_FRAME_LOW_SHIFT);
2506 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2507 * PIPE_FRAME_HIGH_SHIFT);
2508 * } while (high1 != high2);
2509 * frame = (high1 << 8) | low1;
2510 */
2511#define _PIPEAFRAMEHIGH 0x70040
2512#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2513#define PIPE_FRAME_HIGH_SHIFT 0
2514#define _PIPEAFRAMEPIXEL 0x70044
2515#define PIPE_FRAME_LOW_MASK 0xff000000
2516#define PIPE_FRAME_LOW_SHIFT 24
2517#define PIPE_PIXEL_MASK 0x00ffffff
2518#define PIPE_PIXEL_SHIFT 0
2519/* GM45+ just has to be different */
2520#define _PIPEA_FRMCOUNT_GM45 0x70040
2521#define _PIPEA_FLIPCOUNT_GM45 0x70044
2522#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2523
2524/* Cursor A & B regs */
2525#define _CURACNTR 0x70080
2526/* Old style CUR*CNTR flags (desktop 8xx) */
2527#define CURSOR_ENABLE 0x80000000
2528#define CURSOR_GAMMA_ENABLE 0x40000000
2529#define CURSOR_STRIDE_MASK 0x30000000
2530#define CURSOR_FORMAT_SHIFT 24
2531#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2532#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2533#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2534#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2535#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2536#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2537/* New style CUR*CNTR flags */
2538#define CURSOR_MODE 0x27
2539#define CURSOR_MODE_DISABLE 0x00
2540#define CURSOR_MODE_64_32B_AX 0x07
2541#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2542#define MCURSOR_PIPE_SELECT (1 << 28)
2543#define MCURSOR_PIPE_A 0x00
2544#define MCURSOR_PIPE_B (1 << 28)
2545#define MCURSOR_GAMMA_ENABLE (1 << 26)
2546#define _CURABASE 0x70084
2547#define _CURAPOS 0x70088
2548#define CURSOR_POS_MASK 0x007FF
2549#define CURSOR_POS_SIGN 0x8000
2550#define CURSOR_X_SHIFT 0
2551#define CURSOR_Y_SHIFT 16
2552#define CURSIZE 0x700a0
2553#define _CURBCNTR 0x700c0
2554#define _CURBBASE 0x700c4
2555#define _CURBPOS 0x700c8
2556
2557#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2558#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2559#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2560
2561/* Display A control */
2562#define _DSPACNTR 0x70180
2563#define DISPLAY_PLANE_ENABLE (1<<31)
2564#define DISPLAY_PLANE_DISABLE 0
2565#define DISPPLANE_GAMMA_ENABLE (1<<30)
2566#define DISPPLANE_GAMMA_DISABLE 0
2567#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2568#define DISPPLANE_8BPP (0x2<<26)
2569#define DISPPLANE_15_16BPP (0x4<<26)
2570#define DISPPLANE_16BPP (0x5<<26)
2571#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2572#define DISPPLANE_32BPP (0x7<<26)
2573#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2574#define DISPPLANE_STEREO_ENABLE (1<<25)
2575#define DISPPLANE_STEREO_DISABLE 0
2576#define DISPPLANE_SEL_PIPE_SHIFT 24
2577#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
2578#define DISPPLANE_SEL_PIPE_A 0
2579#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
2580#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2581#define DISPPLANE_SRC_KEY_DISABLE 0
2582#define DISPPLANE_LINE_DOUBLE (1<<20)
2583#define DISPPLANE_NO_LINE_DOUBLE 0
2584#define DISPPLANE_STEREO_POLARITY_FIRST 0
2585#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2586#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2587#define DISPPLANE_TILED (1<<10)
2588#define _DSPAADDR 0x70184
2589#define _DSPASTRIDE 0x70188
2590#define _DSPAPOS 0x7018C /* reserved */
2591#define _DSPASIZE 0x70190
2592#define _DSPASURF 0x7019C /* 965+ only */
2593#define _DSPATILEOFF 0x701A4 /* 965+ only */
2594
2595#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2596#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2597#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2598#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2599#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2600#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2601#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2602
2603/* VBIOS flags */
2604#define SWF00 0x71410
2605#define SWF01 0x71414
2606#define SWF02 0x71418
2607#define SWF03 0x7141c
2608#define SWF04 0x71420
2609#define SWF05 0x71424
2610#define SWF06 0x71428
2611#define SWF10 0x70410
2612#define SWF11 0x70414
2613#define SWF14 0x71420
2614#define SWF30 0x72414
2615#define SWF31 0x72418
2616#define SWF32 0x7241c
2617
2618/* Pipe B */
2619#define _PIPEBDSL 0x71000
2620#define _PIPEBCONF 0x71008
2621#define _PIPEBSTAT 0x71024
2622#define _PIPEBFRAMEHIGH 0x71040
2623#define _PIPEBFRAMEPIXEL 0x71044
2624#define _PIPEB_FRMCOUNT_GM45 0x71040
2625#define _PIPEB_FLIPCOUNT_GM45 0x71044
2626
2627
2628/* Display B control */
2629#define _DSPBCNTR 0x71180
2630#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2631#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2632#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2633#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2634#define _DSPBADDR 0x71184
2635#define _DSPBSTRIDE 0x71188
2636#define _DSPBPOS 0x7118C
2637#define _DSPBSIZE 0x71190
2638#define _DSPBSURF 0x7119C
2639#define _DSPBTILEOFF 0x711A4
2640
2641/* VBIOS regs */
2642#define VGACNTRL 0x71400
2643# define VGA_DISP_DISABLE (1 << 31)
2644# define VGA_2X_MODE (1 << 30)
2645# define VGA_PIPE_B_SELECT (1 << 29)
2646
2647/* Ironlake */
2648
2649#define CPU_VGACNTRL 0x41000
2650
2651#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2652#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2653#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2654#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2655#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2656#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2657#define DIGITAL_PORTA_NO_DETECT (0 << 0)
2658#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2659#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2660
2661/* refresh rate hardware control */
2662#define RR_HW_CTL 0x45300
2663#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2664#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2665
2666#define FDI_PLL_BIOS_0 0x46000
2667#define FDI_PLL_FB_CLOCK_MASK 0xff
2668#define FDI_PLL_BIOS_1 0x46004
2669#define FDI_PLL_BIOS_2 0x46008
2670#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2671#define DISPLAY_PORT_PLL_BIOS_1 0x46010
2672#define DISPLAY_PORT_PLL_BIOS_2 0x46014
2673
2674#define PCH_DSPCLK_GATE_D 0x42020
2675# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2676# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
2677# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2678# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2679
2680#define PCH_3DCGDIS0 0x46020
2681# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2682# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2683
2684#define PCH_3DCGDIS1 0x46024
2685# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2686
2687#define FDI_PLL_FREQ_CTL 0x46030
2688#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2689#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2690#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2691
2692
2693#define _PIPEA_DATA_M1 0x60030
2694#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2695#define TU_SIZE_MASK 0x7e000000
2696#define PIPE_DATA_M1_OFFSET 0
2697#define _PIPEA_DATA_N1 0x60034
2698#define PIPE_DATA_N1_OFFSET 0
2699
2700#define _PIPEA_DATA_M2 0x60038
2701#define PIPE_DATA_M2_OFFSET 0
2702#define _PIPEA_DATA_N2 0x6003c
2703#define PIPE_DATA_N2_OFFSET 0
2704
2705#define _PIPEA_LINK_M1 0x60040
2706#define PIPE_LINK_M1_OFFSET 0
2707#define _PIPEA_LINK_N1 0x60044
2708#define PIPE_LINK_N1_OFFSET 0
2709
2710#define _PIPEA_LINK_M2 0x60048
2711#define PIPE_LINK_M2_OFFSET 0
2712#define _PIPEA_LINK_N2 0x6004c
2713#define PIPE_LINK_N2_OFFSET 0
2714
2715/* PIPEB timing regs are same start from 0x61000 */
2716
2717#define _PIPEB_DATA_M1 0x61030
2718#define _PIPEB_DATA_N1 0x61034
2719
2720#define _PIPEB_DATA_M2 0x61038
2721#define _PIPEB_DATA_N2 0x6103c
2722
2723#define _PIPEB_LINK_M1 0x61040
2724#define _PIPEB_LINK_N1 0x61044
2725
2726#define _PIPEB_LINK_M2 0x61048
2727#define _PIPEB_LINK_N2 0x6104c
2728
2729#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2730#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2731#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2732#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2733#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2734#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2735#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2736#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2737
2738/* CPU panel fitter */
2739/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2740#define _PFA_CTL_1 0x68080
2741#define _PFB_CTL_1 0x68880
2742#define PF_ENABLE (1<<31)
2743#define PF_FILTER_MASK (3<<23)
2744#define PF_FILTER_PROGRAMMED (0<<23)
2745#define PF_FILTER_MED_3x3 (1<<23)
2746#define PF_FILTER_EDGE_ENHANCE (2<<23)
2747#define PF_FILTER_EDGE_SOFTEN (3<<23)
2748#define _PFA_WIN_SZ 0x68074
2749#define _PFB_WIN_SZ 0x68874
2750#define _PFA_WIN_POS 0x68070
2751#define _PFB_WIN_POS 0x68870
2752#define _PFA_VSCALE 0x68084
2753#define _PFB_VSCALE 0x68884
2754#define _PFA_HSCALE 0x68090
2755#define _PFB_HSCALE 0x68890
2756
2757#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2758#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2759#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2760#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2761#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2762
2763/* legacy palette */
2764#define _LGC_PALETTE_A 0x4a000
2765#define _LGC_PALETTE_B 0x4a800
2766#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
2767
2768/* interrupts */
2769#define DE_MASTER_IRQ_CONTROL (1 << 31)
2770#define DE_SPRITEB_FLIP_DONE (1 << 29)
2771#define DE_SPRITEA_FLIP_DONE (1 << 28)
2772#define DE_PLANEB_FLIP_DONE (1 << 27)
2773#define DE_PLANEA_FLIP_DONE (1 << 26)
2774#define DE_PCU_EVENT (1 << 25)
2775#define DE_GTT_FAULT (1 << 24)
2776#define DE_POISON (1 << 23)
2777#define DE_PERFORM_COUNTER (1 << 22)
2778#define DE_PCH_EVENT (1 << 21)
2779#define DE_AUX_CHANNEL_A (1 << 20)
2780#define DE_DP_A_HOTPLUG (1 << 19)
2781#define DE_GSE (1 << 18)
2782#define DE_PIPEB_VBLANK (1 << 15)
2783#define DE_PIPEB_EVEN_FIELD (1 << 14)
2784#define DE_PIPEB_ODD_FIELD (1 << 13)
2785#define DE_PIPEB_LINE_COMPARE (1 << 12)
2786#define DE_PIPEB_VSYNC (1 << 11)
2787#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2788#define DE_PIPEA_VBLANK (1 << 7)
2789#define DE_PIPEA_EVEN_FIELD (1 << 6)
2790#define DE_PIPEA_ODD_FIELD (1 << 5)
2791#define DE_PIPEA_LINE_COMPARE (1 << 4)
2792#define DE_PIPEA_VSYNC (1 << 3)
2793#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2794
2795/* More Ivybridge lolz */
2796#define DE_ERR_DEBUG_IVB (1<<30)
2797#define DE_GSE_IVB (1<<29)
2798#define DE_PCH_EVENT_IVB (1<<28)
2799#define DE_DP_A_HOTPLUG_IVB (1<<27)
2800#define DE_AUX_CHANNEL_A_IVB (1<<26)
2801#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
2802#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
2803#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
2804#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
2805#define DE_PIPEB_VBLANK_IVB (1<<5)
2806#define DE_PIPEA_VBLANK_IVB (1<<0)
2807
2808#define DEISR 0x44000
2809#define DEIMR 0x44004
2810#define DEIIR 0x44008
2811#define DEIER 0x4400c
2812
2813/* GT interrupt */
2814#define GT_PIPE_NOTIFY (1 << 4)
2815#define GT_SYNC_STATUS (1 << 2)
2816#define GT_USER_INTERRUPT (1 << 0)
2817#define GT_BSD_USER_INTERRUPT (1 << 5)
2818#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
2819#define GT_BLT_USER_INTERRUPT (1 << 22)
2820
2821#define GTISR 0x44010
2822#define GTIMR 0x44014
2823#define GTIIR 0x44018
2824#define GTIER 0x4401c
2825
2826#define ILK_DISPLAY_CHICKEN2 0x42004
2827/* Required on all Ironlake and Sandybridge according to the B-Spec. */
2828#define ILK_ELPIN_409_SELECT (1 << 25)
2829#define ILK_DPARB_GATE (1<<22)
2830#define ILK_VSDPFD_FULL (1<<21)
2831#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
2832#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
2833#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
2834#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
2835#define ILK_HDCP_DISABLE (1<<25)
2836#define ILK_eDP_A_DISABLE (1<<24)
2837#define ILK_DESKTOP (1<<23)
2838#define ILK_DSPCLK_GATE 0x42020
2839#define IVB_VRHUNIT_CLK_GATE (1<<28)
2840#define ILK_DPARB_CLK_GATE (1<<5)
2841#define ILK_DPFD_CLK_GATE (1<<7)
2842
2843/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
2844#define ILK_CLK_FBC (1<<7)
2845#define ILK_DPFC_DIS1 (1<<8)
2846#define ILK_DPFC_DIS2 (1<<9)
2847
2848#define DISP_ARB_CTL 0x45000
2849#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2850#define DISP_FBC_WM_DIS (1<<15)
2851
2852/* PCH */
2853
2854/* south display engine interrupt */
2855#define SDE_AUDIO_POWER_D (1 << 27)
2856#define SDE_AUDIO_POWER_C (1 << 26)
2857#define SDE_AUDIO_POWER_B (1 << 25)
2858#define SDE_AUDIO_POWER_SHIFT (25)
2859#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
2860#define SDE_GMBUS (1 << 24)
2861#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
2862#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
2863#define SDE_AUDIO_HDCP_MASK (3 << 22)
2864#define SDE_AUDIO_TRANSB (1 << 21)
2865#define SDE_AUDIO_TRANSA (1 << 20)
2866#define SDE_AUDIO_TRANS_MASK (3 << 20)
2867#define SDE_POISON (1 << 19)
2868/* 18 reserved */
2869#define SDE_FDI_RXB (1 << 17)
2870#define SDE_FDI_RXA (1 << 16)
2871#define SDE_FDI_MASK (3 << 16)
2872#define SDE_AUXD (1 << 15)
2873#define SDE_AUXC (1 << 14)
2874#define SDE_AUXB (1 << 13)
2875#define SDE_AUX_MASK (7 << 13)
2876/* 12 reserved */
2877#define SDE_CRT_HOTPLUG (1 << 11)
2878#define SDE_PORTD_HOTPLUG (1 << 10)
2879#define SDE_PORTC_HOTPLUG (1 << 9)
2880#define SDE_PORTB_HOTPLUG (1 << 8)
2881#define SDE_SDVOB_HOTPLUG (1 << 6)
2882#define SDE_HOTPLUG_MASK (0xf << 8)
2883#define SDE_TRANSB_CRC_DONE (1 << 5)
2884#define SDE_TRANSB_CRC_ERR (1 << 4)
2885#define SDE_TRANSB_FIFO_UNDER (1 << 3)
2886#define SDE_TRANSA_CRC_DONE (1 << 2)
2887#define SDE_TRANSA_CRC_ERR (1 << 1)
2888#define SDE_TRANSA_FIFO_UNDER (1 << 0)
2889#define SDE_TRANS_MASK (0x3f)
2890/* CPT */
2891#define SDE_CRT_HOTPLUG_CPT (1 << 19)
2892#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2893#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2894#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2895#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2896 SDE_PORTD_HOTPLUG_CPT | \
2897 SDE_PORTC_HOTPLUG_CPT | \
2898 SDE_PORTB_HOTPLUG_CPT)
2899
2900#define SDEISR 0xc4000
2901#define SDEIMR 0xc4004
2902#define SDEIIR 0xc4008
2903#define SDEIER 0xc400c
2904
2905/* digital port hotplug */
2906#define PCH_PORT_HOTPLUG 0xc4030
2907#define PORTD_HOTPLUG_ENABLE (1 << 20)
2908#define PORTD_PULSE_DURATION_2ms (0)
2909#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2910#define PORTD_PULSE_DURATION_6ms (2 << 18)
2911#define PORTD_PULSE_DURATION_100ms (3 << 18)
2912#define PORTD_HOTPLUG_NO_DETECT (0)
2913#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2914#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2915#define PORTC_HOTPLUG_ENABLE (1 << 12)
2916#define PORTC_PULSE_DURATION_2ms (0)
2917#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2918#define PORTC_PULSE_DURATION_6ms (2 << 10)
2919#define PORTC_PULSE_DURATION_100ms (3 << 10)
2920#define PORTC_HOTPLUG_NO_DETECT (0)
2921#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2922#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2923#define PORTB_HOTPLUG_ENABLE (1 << 4)
2924#define PORTB_PULSE_DURATION_2ms (0)
2925#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2926#define PORTB_PULSE_DURATION_6ms (2 << 2)
2927#define PORTB_PULSE_DURATION_100ms (3 << 2)
2928#define PORTB_HOTPLUG_NO_DETECT (0)
2929#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2930#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2931
2932#define PCH_GPIOA 0xc5010
2933#define PCH_GPIOB 0xc5014
2934#define PCH_GPIOC 0xc5018
2935#define PCH_GPIOD 0xc501c
2936#define PCH_GPIOE 0xc5020
2937#define PCH_GPIOF 0xc5024
2938
2939#define PCH_GMBUS0 0xc5100
2940#define PCH_GMBUS1 0xc5104
2941#define PCH_GMBUS2 0xc5108
2942#define PCH_GMBUS3 0xc510c
2943#define PCH_GMBUS4 0xc5110
2944#define PCH_GMBUS5 0xc5120
2945
2946#define _PCH_DPLL_A 0xc6014
2947#define _PCH_DPLL_B 0xc6018
2948#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
2949
2950#define _PCH_FPA0 0xc6040
2951#define FP_CB_TUNE (0x3<<22)
2952#define _PCH_FPA1 0xc6044
2953#define _PCH_FPB0 0xc6048
2954#define _PCH_FPB1 0xc604c
2955#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
2956#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
2957
2958#define PCH_DPLL_TEST 0xc606c
2959
2960#define PCH_DREF_CONTROL 0xC6200
2961#define DREF_CONTROL_MASK 0x7fc3
2962#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2963#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2964#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2965#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2966#define DREF_SSC_SOURCE_DISABLE (0<<11)
2967#define DREF_SSC_SOURCE_ENABLE (2<<11)
2968#define DREF_SSC_SOURCE_MASK (3<<11)
2969#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2970#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2971#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2972#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2973#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2974#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2975#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
2976#define DREF_SSC4_DOWNSPREAD (0<<6)
2977#define DREF_SSC4_CENTERSPREAD (1<<6)
2978#define DREF_SSC1_DISABLE (0<<1)
2979#define DREF_SSC1_ENABLE (1<<1)
2980#define DREF_SSC4_DISABLE (0)
2981#define DREF_SSC4_ENABLE (1)
2982
2983#define PCH_RAWCLK_FREQ 0xc6204
2984#define FDL_TP1_TIMER_SHIFT 12
2985#define FDL_TP1_TIMER_MASK (3<<12)
2986#define FDL_TP2_TIMER_SHIFT 10
2987#define FDL_TP2_TIMER_MASK (3<<10)
2988#define RAWCLK_FREQ_MASK 0x3ff
2989
2990#define PCH_DPLL_TMR_CFG 0xc6208
2991
2992#define PCH_SSC4_PARMS 0xc6210
2993#define PCH_SSC4_AUX_PARMS 0xc6214
2994
2995#define PCH_DPLL_SEL 0xc7000
2996#define TRANSA_DPLL_ENABLE (1<<3)
2997#define TRANSA_DPLLB_SEL (1<<0)
2998#define TRANSA_DPLLA_SEL 0
2999#define TRANSB_DPLL_ENABLE (1<<7)
3000#define TRANSB_DPLLB_SEL (1<<4)
3001#define TRANSB_DPLLA_SEL (0)
3002#define TRANSC_DPLL_ENABLE (1<<11)
3003#define TRANSC_DPLLB_SEL (1<<8)
3004#define TRANSC_DPLLA_SEL (0)
3005
3006/* transcoder */
3007
3008#define _TRANS_HTOTAL_A 0xe0000
3009#define TRANS_HTOTAL_SHIFT 16
3010#define TRANS_HACTIVE_SHIFT 0
3011#define _TRANS_HBLANK_A 0xe0004
3012#define TRANS_HBLANK_END_SHIFT 16
3013#define TRANS_HBLANK_START_SHIFT 0
3014#define _TRANS_HSYNC_A 0xe0008
3015#define TRANS_HSYNC_END_SHIFT 16
3016#define TRANS_HSYNC_START_SHIFT 0
3017#define _TRANS_VTOTAL_A 0xe000c
3018#define TRANS_VTOTAL_SHIFT 16
3019#define TRANS_VACTIVE_SHIFT 0
3020#define _TRANS_VBLANK_A 0xe0010
3021#define TRANS_VBLANK_END_SHIFT 16
3022#define TRANS_VBLANK_START_SHIFT 0
3023#define _TRANS_VSYNC_A 0xe0014
3024#define TRANS_VSYNC_END_SHIFT 16
3025#define TRANS_VSYNC_START_SHIFT 0
3026
3027#define _TRANSA_DATA_M1 0xe0030
3028#define _TRANSA_DATA_N1 0xe0034
3029#define _TRANSA_DATA_M2 0xe0038
3030#define _TRANSA_DATA_N2 0xe003c
3031#define _TRANSA_DP_LINK_M1 0xe0040
3032#define _TRANSA_DP_LINK_N1 0xe0044
3033#define _TRANSA_DP_LINK_M2 0xe0048
3034#define _TRANSA_DP_LINK_N2 0xe004c
3035
3036/* Per-transcoder DIP controls */
3037
3038#define _VIDEO_DIP_CTL_A 0xe0200
3039#define _VIDEO_DIP_DATA_A 0xe0208
3040#define _VIDEO_DIP_GCP_A 0xe0210
3041
3042#define _VIDEO_DIP_CTL_B 0xe1200
3043#define _VIDEO_DIP_DATA_B 0xe1208
3044#define _VIDEO_DIP_GCP_B 0xe1210
3045
3046#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3047#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3048#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3049
3050#define _TRANS_HTOTAL_B 0xe1000
3051#define _TRANS_HBLANK_B 0xe1004
3052#define _TRANS_HSYNC_B 0xe1008
3053#define _TRANS_VTOTAL_B 0xe100c
3054#define _TRANS_VBLANK_B 0xe1010
3055#define _TRANS_VSYNC_B 0xe1014
3056
3057#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3058#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3059#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3060#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3061#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3062#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3063
3064#define _TRANSB_DATA_M1 0xe1030
3065#define _TRANSB_DATA_N1 0xe1034
3066#define _TRANSB_DATA_M2 0xe1038
3067#define _TRANSB_DATA_N2 0xe103c
3068#define _TRANSB_DP_LINK_M1 0xe1040
3069#define _TRANSB_DP_LINK_N1 0xe1044
3070#define _TRANSB_DP_LINK_M2 0xe1048
3071#define _TRANSB_DP_LINK_N2 0xe104c
3072
3073#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3074#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3075#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3076#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3077#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3078#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3079#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3080#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3081
3082#define _TRANSACONF 0xf0008
3083#define _TRANSBCONF 0xf1008
3084#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3085#define TRANS_DISABLE (0<<31)
3086#define TRANS_ENABLE (1<<31)
3087#define TRANS_STATE_MASK (1<<30)
3088#define TRANS_STATE_DISABLE (0<<30)
3089#define TRANS_STATE_ENABLE (1<<30)
3090#define TRANS_FSYNC_DELAY_HB1 (0<<27)
3091#define TRANS_FSYNC_DELAY_HB2 (1<<27)
3092#define TRANS_FSYNC_DELAY_HB3 (2<<27)
3093#define TRANS_FSYNC_DELAY_HB4 (3<<27)
3094#define TRANS_DP_AUDIO_ONLY (1<<26)
3095#define TRANS_DP_VIDEO_AUDIO (0<<26)
3096#define TRANS_PROGRESSIVE (0<<21)
3097#define TRANS_8BPC (0<<5)
3098#define TRANS_10BPC (1<<5)
3099#define TRANS_6BPC (2<<5)
3100#define TRANS_12BPC (3<<5)
3101
3102#define _TRANSA_CHICKEN2 0xf0064
3103#define _TRANSB_CHICKEN2 0xf1064
3104#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3105#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3106
3107#define SOUTH_CHICKEN1 0xc2000
3108#define FDIA_PHASE_SYNC_SHIFT_OVR 19
3109#define FDIA_PHASE_SYNC_SHIFT_EN 18
3110#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3111#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3112#define SOUTH_CHICKEN2 0xc2004
3113#define DPLS_EDP_PPS_FIX_DIS (1<<0)
3114
3115#define _FDI_RXA_CHICKEN 0xc200c
3116#define _FDI_RXB_CHICKEN 0xc2010
3117#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3118#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3119#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3120
3121#define SOUTH_DSPCLK_GATE_D 0xc2020
3122#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3123
3124/* CPU: FDI_TX */
3125#define _FDI_TXA_CTL 0x60100
3126#define _FDI_TXB_CTL 0x61100
3127#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3128#define FDI_TX_DISABLE (0<<31)
3129#define FDI_TX_ENABLE (1<<31)
3130#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3131#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3132#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3133#define FDI_LINK_TRAIN_NONE (3<<28)
3134#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3135#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3136#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3137#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3138#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3139#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3140#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3141#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3142/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3143 SNB has different settings. */
3144/* SNB A-stepping */
3145#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3146#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3147#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3148#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3149/* SNB B-stepping */
3150#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3151#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3152#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3153#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3154#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3155#define FDI_DP_PORT_WIDTH_X1 (0<<19)
3156#define FDI_DP_PORT_WIDTH_X2 (1<<19)
3157#define FDI_DP_PORT_WIDTH_X3 (2<<19)
3158#define FDI_DP_PORT_WIDTH_X4 (3<<19)
3159#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3160/* Ironlake: hardwired to 1 */
3161#define FDI_TX_PLL_ENABLE (1<<14)
3162
3163/* Ivybridge has different bits for lolz */
3164#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3165#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3166#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3167#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3168
3169/* both Tx and Rx */
3170#define FDI_LINK_TRAIN_AUTO (1<<10)
3171#define FDI_SCRAMBLING_ENABLE (0<<7)
3172#define FDI_SCRAMBLING_DISABLE (1<<7)
3173
3174/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3175#define _FDI_RXA_CTL 0xf000c
3176#define _FDI_RXB_CTL 0xf100c
3177#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3178#define FDI_RX_ENABLE (1<<31)
3179/* train, dp width same as FDI_TX */
3180#define FDI_FS_ERRC_ENABLE (1<<27)
3181#define FDI_FE_ERRC_ENABLE (1<<26)
3182#define FDI_DP_PORT_WIDTH_X8 (7<<19)
3183#define FDI_8BPC (0<<16)
3184#define FDI_10BPC (1<<16)
3185#define FDI_6BPC (2<<16)
3186#define FDI_12BPC (3<<16)
3187#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3188#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3189#define FDI_RX_PLL_ENABLE (1<<13)
3190#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3191#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3192#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3193#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3194#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3195#define FDI_PCDCLK (1<<4)
3196/* CPT */
3197#define FDI_AUTO_TRAINING (1<<10)
3198#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3199#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3200#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3201#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3202#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3203
3204#define _FDI_RXA_MISC 0xf0010
3205#define _FDI_RXB_MISC 0xf1010
3206#define _FDI_RXA_TUSIZE1 0xf0030
3207#define _FDI_RXA_TUSIZE2 0xf0038
3208#define _FDI_RXB_TUSIZE1 0xf1030
3209#define _FDI_RXB_TUSIZE2 0xf1038
3210#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3211#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3212#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3213
3214/* FDI_RX interrupt register format */
3215#define FDI_RX_INTER_LANE_ALIGN (1<<10)
3216#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3217#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3218#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3219#define FDI_RX_FS_CODE_ERR (1<<6)
3220#define FDI_RX_FE_CODE_ERR (1<<5)
3221#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3222#define FDI_RX_HDCP_LINK_FAIL (1<<3)
3223#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3224#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3225#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3226
3227#define _FDI_RXA_IIR 0xf0014
3228#define _FDI_RXA_IMR 0xf0018
3229#define _FDI_RXB_IIR 0xf1014
3230#define _FDI_RXB_IMR 0xf1018
3231#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3232#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3233
3234#define FDI_PLL_CTL_1 0xfe000
3235#define FDI_PLL_CTL_2 0xfe004
3236
3237/* CRT */
3238#define PCH_ADPA 0xe1100
3239#define ADPA_TRANS_SELECT_MASK (1<<30)
3240#define ADPA_TRANS_A_SELECT 0
3241#define ADPA_TRANS_B_SELECT (1<<30)
3242#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3243#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3244#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3245#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3246#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3247#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3248#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3249#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3250#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3251#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3252#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3253#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3254#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3255#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3256#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3257#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3258#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3259#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3260#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3261
3262/* or SDVOB */
3263#define HDMIB 0xe1140
3264#define PORT_ENABLE (1 << 31)
3265#define TRANSCODER_A (0)
3266#define TRANSCODER_B (1 << 30)
3267#define TRANSCODER(pipe) ((pipe) << 30)
3268#define TRANSCODER_MASK (1 << 30)
3269#define COLOR_FORMAT_8bpc (0)
3270#define COLOR_FORMAT_12bpc (3 << 26)
3271#define SDVOB_HOTPLUG_ENABLE (1 << 23)
3272#define SDVO_ENCODING (0)
3273#define TMDS_ENCODING (2 << 10)
3274#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3275/* CPT */
3276#define HDMI_MODE_SELECT (1 << 9)
3277#define DVI_MODE_SELECT (0)
3278#define SDVOB_BORDER_ENABLE (1 << 7)
3279#define AUDIO_ENABLE (1 << 6)
3280#define VSYNC_ACTIVE_HIGH (1 << 4)
3281#define HSYNC_ACTIVE_HIGH (1 << 3)
3282#define PORT_DETECTED (1 << 2)
3283
3284/* PCH SDVOB multiplex with HDMIB */
3285#define PCH_SDVOB HDMIB
3286
3287#define HDMIC 0xe1150
3288#define HDMID 0xe1160
3289
3290#define PCH_LVDS 0xe1180
3291#define LVDS_DETECTED (1 << 1)
3292
3293#define BLC_PWM_CPU_CTL2 0x48250
3294#define PWM_ENABLE (1 << 31)
3295#define PWM_PIPE_A (0 << 29)
3296#define PWM_PIPE_B (1 << 29)
3297#define BLC_PWM_CPU_CTL 0x48254
3298
3299#define BLC_PWM_PCH_CTL1 0xc8250
3300#define PWM_PCH_ENABLE (1 << 31)
3301#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3302#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3303#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3304#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3305
3306#define BLC_PWM_PCH_CTL2 0xc8254
3307
3308#define PCH_PP_STATUS 0xc7200
3309#define PCH_PP_CONTROL 0xc7204
3310#define PANEL_UNLOCK_REGS (0xabcd << 16)
3311#define EDP_FORCE_VDD (1 << 3)
3312#define EDP_BLC_ENABLE (1 << 2)
3313#define PANEL_POWER_RESET (1 << 1)
3314#define PANEL_POWER_OFF (0 << 0)
3315#define PANEL_POWER_ON (1 << 0)
3316#define PCH_PP_ON_DELAYS 0xc7208
3317#define EDP_PANEL (1 << 30)
3318#define PCH_PP_OFF_DELAYS 0xc720c
3319#define PCH_PP_DIVISOR 0xc7210
3320
3321#define PCH_DP_B 0xe4100
3322#define PCH_DPB_AUX_CH_CTL 0xe4110
3323#define PCH_DPB_AUX_CH_DATA1 0xe4114
3324#define PCH_DPB_AUX_CH_DATA2 0xe4118
3325#define PCH_DPB_AUX_CH_DATA3 0xe411c
3326#define PCH_DPB_AUX_CH_DATA4 0xe4120
3327#define PCH_DPB_AUX_CH_DATA5 0xe4124
3328
3329#define PCH_DP_C 0xe4200
3330#define PCH_DPC_AUX_CH_CTL 0xe4210
3331#define PCH_DPC_AUX_CH_DATA1 0xe4214
3332#define PCH_DPC_AUX_CH_DATA2 0xe4218
3333#define PCH_DPC_AUX_CH_DATA3 0xe421c
3334#define PCH_DPC_AUX_CH_DATA4 0xe4220
3335#define PCH_DPC_AUX_CH_DATA5 0xe4224
3336
3337#define PCH_DP_D 0xe4300
3338#define PCH_DPD_AUX_CH_CTL 0xe4310
3339#define PCH_DPD_AUX_CH_DATA1 0xe4314
3340#define PCH_DPD_AUX_CH_DATA2 0xe4318
3341#define PCH_DPD_AUX_CH_DATA3 0xe431c
3342#define PCH_DPD_AUX_CH_DATA4 0xe4320
3343#define PCH_DPD_AUX_CH_DATA5 0xe4324
3344
3345/* CPT */
3346#define PORT_TRANS_A_SEL_CPT 0
3347#define PORT_TRANS_B_SEL_CPT (1<<29)
3348#define PORT_TRANS_C_SEL_CPT (2<<29)
3349#define PORT_TRANS_SEL_MASK (3<<29)
3350#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
3351
3352#define TRANS_DP_CTL_A 0xe0300
3353#define TRANS_DP_CTL_B 0xe1300
3354#define TRANS_DP_CTL_C 0xe2300
3355#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
3356#define TRANS_DP_OUTPUT_ENABLE (1<<31)
3357#define TRANS_DP_PORT_SEL_B (0<<29)
3358#define TRANS_DP_PORT_SEL_C (1<<29)
3359#define TRANS_DP_PORT_SEL_D (2<<29)
3360#define TRANS_DP_PORT_SEL_NONE (3<<29)
3361#define TRANS_DP_PORT_SEL_MASK (3<<29)
3362#define TRANS_DP_AUDIO_ONLY (1<<26)
3363#define TRANS_DP_ENH_FRAMING (1<<18)
3364#define TRANS_DP_8BPC (0<<9)
3365#define TRANS_DP_10BPC (1<<9)
3366#define TRANS_DP_6BPC (2<<9)
3367#define TRANS_DP_12BPC (3<<9)
3368#define TRANS_DP_BPC_MASK (3<<9)
3369#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3370#define TRANS_DP_VSYNC_ACTIVE_LOW 0
3371#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3372#define TRANS_DP_HSYNC_ACTIVE_LOW 0
3373#define TRANS_DP_SYNC_MASK (3<<3)
3374
3375/* SNB eDP training params */
3376/* SNB A-stepping */
3377#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3378#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3379#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3380#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3381/* SNB B-stepping */
3382#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
3383#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
3384#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
3385#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3386#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
3387#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3388
3389#define FORCEWAKE 0xA18C
3390#define FORCEWAKE_ACK 0x130090
3391
3392#define GT_FIFO_FREE_ENTRIES 0x120008
3393#define GT_FIFO_NUM_RESERVED_ENTRIES 20
3394
3395#define GEN6_RPNSWREQ 0xA008
3396#define GEN6_TURBO_DISABLE (1<<31)
3397#define GEN6_FREQUENCY(x) ((x)<<25)
3398#define GEN6_OFFSET(x) ((x)<<19)
3399#define GEN6_AGGRESSIVE_TURBO (0<<15)
3400#define GEN6_RC_VIDEO_FREQ 0xA00C
3401#define GEN6_RC_CONTROL 0xA090
3402#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3403#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3404#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3405#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3406#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3407#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3408#define GEN6_RC_CTL_HW_ENABLE (1<<31)
3409#define GEN6_RP_DOWN_TIMEOUT 0xA010
3410#define GEN6_RP_INTERRUPT_LIMITS 0xA014
3411#define GEN6_RPSTAT1 0xA01C
3412#define GEN6_CAGF_SHIFT 8
3413#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
3414#define GEN6_RP_CONTROL 0xA024
3415#define GEN6_RP_MEDIA_TURBO (1<<11)
3416#define GEN6_RP_USE_NORMAL_FREQ (1<<9)
3417#define GEN6_RP_MEDIA_IS_GFX (1<<8)
3418#define GEN6_RP_ENABLE (1<<7)
3419#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3420#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3421#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3422#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
3423#define GEN6_RP_UP_THRESHOLD 0xA02C
3424#define GEN6_RP_DOWN_THRESHOLD 0xA030
3425#define GEN6_RP_CUR_UP_EI 0xA050
3426#define GEN6_CURICONT_MASK 0xffffff
3427#define GEN6_RP_CUR_UP 0xA054
3428#define GEN6_CURBSYTAVG_MASK 0xffffff
3429#define GEN6_RP_PREV_UP 0xA058
3430#define GEN6_RP_CUR_DOWN_EI 0xA05C
3431#define GEN6_CURIAVG_MASK 0xffffff
3432#define GEN6_RP_CUR_DOWN 0xA060
3433#define GEN6_RP_PREV_DOWN 0xA064
3434#define GEN6_RP_UP_EI 0xA068
3435#define GEN6_RP_DOWN_EI 0xA06C
3436#define GEN6_RP_IDLE_HYSTERSIS 0xA070
3437#define GEN6_RC_STATE 0xA094
3438#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3439#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3440#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3441#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3442#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3443#define GEN6_RC_SLEEP 0xA0B0
3444#define GEN6_RC1e_THRESHOLD 0xA0B4
3445#define GEN6_RC6_THRESHOLD 0xA0B8
3446#define GEN6_RC6p_THRESHOLD 0xA0BC
3447#define GEN6_RC6pp_THRESHOLD 0xA0C0
3448#define GEN6_PMINTRMSK 0xA168
3449
3450#define GEN6_PMISR 0x44020
3451#define GEN6_PMIMR 0x44024 /* rps_lock */
3452#define GEN6_PMIIR 0x44028
3453#define GEN6_PMIER 0x4402C
3454#define GEN6_PM_MBOX_EVENT (1<<25)
3455#define GEN6_PM_THERMAL_EVENT (1<<24)
3456#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3457#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3458#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3459#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3460#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3461#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
3462 GEN6_PM_RP_DOWN_THRESHOLD | \
3463 GEN6_PM_RP_DOWN_TIMEOUT)
3464
3465#define GEN6_PCODE_MAILBOX 0x138124
3466#define GEN6_PCODE_READY (1<<31)
3467#define GEN6_READ_OC_PARAMS 0xc
3468#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3469#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3470#define GEN6_PCODE_DATA 0x138128
3471#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
3472
3473#endif /* _I915_REG_H_ */
1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28/**
29 * DOC: The i915 register macro definition style guide
30 *
31 * Follow the style described here for new macros, and while changing existing
32 * macros. Do **not** mass change existing definitions just to update the style.
33 *
34 * Layout
35 * ''''''
36 *
37 * Keep helper macros near the top. For example, _PIPE() and friends.
38 *
39 * Prefix macros that generally should not be used outside of this file with
40 * underscore '_'. For example, _PIPE() and friends, single instances of
41 * registers that are defined solely for the use by function-like macros.
42 *
43 * Avoid using the underscore prefixed macros outside of this file. There are
44 * exceptions, but keep them to a minimum.
45 *
46 * There are two basic types of register definitions: Single registers and
47 * register groups. Register groups are registers which have two or more
48 * instances, for example one per pipe, port, transcoder, etc. Register groups
49 * should be defined using function-like macros.
50 *
51 * For single registers, define the register offset first, followed by register
52 * contents.
53 *
54 * For register groups, define the register instance offsets first, prefixed
55 * with underscore, followed by a function-like macro choosing the right
56 * instance based on the parameter, followed by register contents.
57 *
58 * Define the register contents (i.e. bit and bit field macros) from most
59 * significant to least significant bit. Indent the register content macros
60 * using two extra spaces between ``#define`` and the macro name.
61 *
62 * For bit fields, define a ``_MASK`` and a ``_SHIFT`` macro. Define bit field
63 * contents so that they are already shifted in place, and can be directly
64 * OR'd. For convenience, function-like macros may be used to define bit fields,
65 * but do note that the macros may be needed to read as well as write the
66 * register contents.
67 *
68 * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
69 * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
70 * to the name.
71 *
72 * Group the register and its contents together without blank lines, separate
73 * from other registers and their contents with one blank line.
74 *
75 * Indent macro values from macro names using TABs. Align values vertically. Use
76 * braces in macro values as needed to avoid unintended precedence after macro
77 * substitution. Use spaces in macro values according to kernel coding
78 * style. Use lower case in hexadecimal values.
79 *
80 * Naming
81 * ''''''
82 *
83 * Try to name registers according to the specs. If the register name changes in
84 * the specs from platform to another, stick to the original name.
85 *
86 * Try to re-use existing register macro definitions. Only add new macros for
87 * new register offsets, or when the register contents have changed enough to
88 * warrant a full redefinition.
89 *
90 * When a register macro changes for a new platform, prefix the new macro using
91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
92 * prefix signifies the start platform/generation using the register.
93 *
94 * When a bit (field) macro changes or gets added for a new platform, while
95 * retaining the existing register macro, add a platform acronym or generation
96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
97 *
98 * Examples
99 * ''''''''
100 *
101 * (Note that the values in the example are indented using spaces instead of
102 * TABs to avoid misalignment in generated documentation. Use TABs in the
103 * definitions.)::
104 *
105 * #define _FOO_A 0xf000
106 * #define _FOO_B 0xf001
107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
108 * #define FOO_ENABLE (1 << 31)
109 * #define FOO_MODE_MASK (0xf << 16)
110 * #define FOO_MODE_SHIFT 16
111 * #define FOO_MODE_BAR (0 << 16)
112 * #define FOO_MODE_BAZ (1 << 16)
113 * #define FOO_MODE_QUX_SNB (2 << 16)
114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
119typedef struct {
120 uint32_t reg;
121} i915_reg_t;
122
123#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
124
125#define INVALID_MMIO_REG _MMIO(0)
126
127static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
128{
129 return reg.reg;
130}
131
132static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
133{
134 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
135}
136
137static inline bool i915_mmio_reg_valid(i915_reg_t reg)
138{
139 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
140}
141
142#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
143
144#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
145#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
146#define _PLANE(plane, a, b) _PIPE(plane, a, b)
147#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
148#define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
149#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
150#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
151#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
152#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
153#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
154#define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
155#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
156#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
157#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \
158 _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
159#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
160#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
161
162#define _MASKED_FIELD(mask, value) ({ \
163 if (__builtin_constant_p(mask)) \
164 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
165 if (__builtin_constant_p(value)) \
166 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
167 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
168 BUILD_BUG_ON_MSG((value) & ~(mask), \
169 "Incorrect value for mask"); \
170 (mask) << 16 | (value); })
171#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
172#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
173
174/* Engine ID */
175
176#define RCS_HW 0
177#define VCS_HW 1
178#define BCS_HW 2
179#define VECS_HW 3
180#define VCS2_HW 4
181#define VCS3_HW 6
182#define VCS4_HW 7
183#define VECS2_HW 12
184
185/* Engine class */
186
187#define RENDER_CLASS 0
188#define VIDEO_DECODE_CLASS 1
189#define VIDEO_ENHANCEMENT_CLASS 2
190#define COPY_ENGINE_CLASS 3
191#define OTHER_CLASS 4
192#define MAX_ENGINE_CLASS 4
193
194#define MAX_ENGINE_INSTANCE 3
195
196/* PCI config space */
197
198#define MCHBAR_I915 0x44
199#define MCHBAR_I965 0x48
200#define MCHBAR_SIZE (4 * 4096)
201
202#define DEVEN 0x54
203#define DEVEN_MCHBAR_EN (1 << 28)
204
205/* BSM in include/drm/i915_drm.h */
206
207#define HPLLCC 0xc0 /* 85x only */
208#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
209#define GC_CLOCK_133_200 (0 << 0)
210#define GC_CLOCK_100_200 (1 << 0)
211#define GC_CLOCK_100_133 (2 << 0)
212#define GC_CLOCK_133_266 (3 << 0)
213#define GC_CLOCK_133_200_2 (4 << 0)
214#define GC_CLOCK_133_266_2 (5 << 0)
215#define GC_CLOCK_166_266 (6 << 0)
216#define GC_CLOCK_166_250 (7 << 0)
217
218#define I915_GDRST 0xc0 /* PCI config register */
219#define GRDOM_FULL (0 << 2)
220#define GRDOM_RENDER (1 << 2)
221#define GRDOM_MEDIA (3 << 2)
222#define GRDOM_MASK (3 << 2)
223#define GRDOM_RESET_STATUS (1 << 1)
224#define GRDOM_RESET_ENABLE (1 << 0)
225
226/* BSpec only has register offset, PCI device and bit found empirically */
227#define I830_CLOCK_GATE 0xc8 /* device 0 */
228#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2)
229
230#define GCDGMBUS 0xcc
231
232#define GCFGC2 0xda
233#define GCFGC 0xf0 /* 915+ only */
234#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
235#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
236#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
237#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
238#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
239#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
240#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
241#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
242#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
243#define GC_DISPLAY_CLOCK_MASK (7 << 4)
244#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
245#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
246#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
247#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
248#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
249#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
250#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
251#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
252#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
253#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
254#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
255#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
256#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
257#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
258#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
259#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
260#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
261#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
262#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
263
264#define ASLE 0xe4
265#define ASLS 0xfc
266
267#define SWSCI 0xe8
268#define SWSCI_SCISEL (1 << 15)
269#define SWSCI_GSSCIE (1 << 0)
270
271#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
272
273
274#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
275#define ILK_GRDOM_FULL (0<<1)
276#define ILK_GRDOM_RENDER (1<<1)
277#define ILK_GRDOM_MEDIA (3<<1)
278#define ILK_GRDOM_MASK (3<<1)
279#define ILK_GRDOM_RESET_ENABLE (1<<0)
280
281#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
282#define GEN6_MBC_SNPCR_SHIFT 21
283#define GEN6_MBC_SNPCR_MASK (3<<21)
284#define GEN6_MBC_SNPCR_MAX (0<<21)
285#define GEN6_MBC_SNPCR_MED (1<<21)
286#define GEN6_MBC_SNPCR_LOW (2<<21)
287#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
288
289#define VLV_G3DCTL _MMIO(0x9024)
290#define VLV_GSCKGCTL _MMIO(0x9028)
291
292#define GEN6_MBCTL _MMIO(0x0907c)
293#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
294#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
295#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
296#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
297#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
298
299#define GEN6_GDRST _MMIO(0x941c)
300#define GEN6_GRDOM_FULL (1 << 0)
301#define GEN6_GRDOM_RENDER (1 << 1)
302#define GEN6_GRDOM_MEDIA (1 << 2)
303#define GEN6_GRDOM_BLT (1 << 3)
304#define GEN6_GRDOM_VECS (1 << 4)
305#define GEN9_GRDOM_GUC (1 << 5)
306#define GEN8_GRDOM_MEDIA2 (1 << 7)
307
308#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base+0x228)
309#define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base+0x518)
310#define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base+0x220)
311#define PP_DIR_DCLV_2G 0xffffffff
312
313#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8 + 4)
314#define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base+0x270 + (n) * 8)
315
316#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
317#define GEN8_RPCS_ENABLE (1 << 31)
318#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
319#define GEN8_RPCS_S_CNT_SHIFT 15
320#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
321#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
322#define GEN8_RPCS_SS_CNT_SHIFT 8
323#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
324#define GEN8_RPCS_EU_MAX_SHIFT 4
325#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
326#define GEN8_RPCS_EU_MIN_SHIFT 0
327#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
328
329#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC)
330/* HSW only */
331#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2
332#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT)
333#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4
334#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT)
335/* HSW+ */
336#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0)
337#define HSW_RCS_CONTEXT_ENABLE (1 << 7)
338#define HSW_RCS_INHIBIT (1 << 8)
339/* Gen8 */
340#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
341#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
342#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4
343#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT)
344#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6)
345#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9
346#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT)
347#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11
348#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT)
349#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13)
350
351#define GAM_ECOCHK _MMIO(0x4090)
352#define BDW_DISABLE_HDC_INVALIDATION (1<<25)
353#define ECOCHK_SNB_BIT (1<<10)
354#define ECOCHK_DIS_TLB (1<<8)
355#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
356#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
357#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
358#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
359#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
360#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
361#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
362#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
363
364#define GAC_ECO_BITS _MMIO(0x14090)
365#define ECOBITS_SNB_BIT (1<<13)
366#define ECOBITS_PPGTT_CACHE64B (3<<8)
367#define ECOBITS_PPGTT_CACHE4B (0<<8)
368
369#define GAB_CTL _MMIO(0x24000)
370#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
371
372#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
373#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
374#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
375#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
376#define GEN6_STOLEN_RESERVED_1M (0 << 4)
377#define GEN6_STOLEN_RESERVED_512K (1 << 4)
378#define GEN6_STOLEN_RESERVED_256K (2 << 4)
379#define GEN6_STOLEN_RESERVED_128K (3 << 4)
380#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
381#define GEN7_STOLEN_RESERVED_1M (0 << 5)
382#define GEN7_STOLEN_RESERVED_256K (1 << 5)
383#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
384#define GEN8_STOLEN_RESERVED_1M (0 << 7)
385#define GEN8_STOLEN_RESERVED_2M (1 << 7)
386#define GEN8_STOLEN_RESERVED_4M (2 << 7)
387#define GEN8_STOLEN_RESERVED_8M (3 << 7)
388#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
389
390/* VGA stuff */
391
392#define VGA_ST01_MDA 0x3ba
393#define VGA_ST01_CGA 0x3da
394
395#define _VGA_MSR_WRITE _MMIO(0x3c2)
396#define VGA_MSR_WRITE 0x3c2
397#define VGA_MSR_READ 0x3cc
398#define VGA_MSR_MEM_EN (1<<1)
399#define VGA_MSR_CGA_MODE (1<<0)
400
401#define VGA_SR_INDEX 0x3c4
402#define SR01 1
403#define VGA_SR_DATA 0x3c5
404
405#define VGA_AR_INDEX 0x3c0
406#define VGA_AR_VID_EN (1<<5)
407#define VGA_AR_DATA_WRITE 0x3c0
408#define VGA_AR_DATA_READ 0x3c1
409
410#define VGA_GR_INDEX 0x3ce
411#define VGA_GR_DATA 0x3cf
412/* GR05 */
413#define VGA_GR_MEM_READ_MODE_SHIFT 3
414#define VGA_GR_MEM_READ_MODE_PLANE 1
415/* GR06 */
416#define VGA_GR_MEM_MODE_MASK 0xc
417#define VGA_GR_MEM_MODE_SHIFT 2
418#define VGA_GR_MEM_A0000_AFFFF 0
419#define VGA_GR_MEM_A0000_BFFFF 1
420#define VGA_GR_MEM_B0000_B7FFF 2
421#define VGA_GR_MEM_B0000_BFFFF 3
422
423#define VGA_DACMASK 0x3c6
424#define VGA_DACRX 0x3c7
425#define VGA_DACWX 0x3c8
426#define VGA_DACDATA 0x3c9
427
428#define VGA_CR_INDEX_MDA 0x3b4
429#define VGA_CR_DATA_MDA 0x3b5
430#define VGA_CR_INDEX_CGA 0x3d4
431#define VGA_CR_DATA_CGA 0x3d5
432
433/*
434 * Instruction field definitions used by the command parser
435 */
436#define INSTR_CLIENT_SHIFT 29
437#define INSTR_MI_CLIENT 0x0
438#define INSTR_BC_CLIENT 0x2
439#define INSTR_RC_CLIENT 0x3
440#define INSTR_SUBCLIENT_SHIFT 27
441#define INSTR_SUBCLIENT_MASK 0x18000000
442#define INSTR_MEDIA_SUBCLIENT 0x2
443#define INSTR_26_TO_24_MASK 0x7000000
444#define INSTR_26_TO_24_SHIFT 24
445
446/*
447 * Memory interface instructions used by the kernel
448 */
449#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
450/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
451#define MI_GLOBAL_GTT (1<<22)
452
453#define MI_NOOP MI_INSTR(0, 0)
454#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
455#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
456#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
457#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
458#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
459#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
460#define MI_FLUSH MI_INSTR(0x04, 0)
461#define MI_READ_FLUSH (1 << 0)
462#define MI_EXE_FLUSH (1 << 1)
463#define MI_NO_WRITE_FLUSH (1 << 2)
464#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
465#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
466#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
467#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
468#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
469#define MI_ARB_ENABLE (1<<0)
470#define MI_ARB_DISABLE (0<<0)
471#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
472#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
473#define MI_SUSPEND_FLUSH_EN (1<<0)
474#define MI_SET_APPID MI_INSTR(0x0e, 0)
475#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
476#define MI_OVERLAY_CONTINUE (0x0<<21)
477#define MI_OVERLAY_ON (0x1<<21)
478#define MI_OVERLAY_OFF (0x2<<21)
479#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
480#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
481#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
482#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
483/* IVB has funny definitions for which plane to flip. */
484#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
485#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
486#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
487#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
488#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
489#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
490/* SKL ones */
491#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
492#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
493#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
494#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
495#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
496#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
497#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
498#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
499#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
500#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
501#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
502#define MI_SEMAPHORE_UPDATE (1<<21)
503#define MI_SEMAPHORE_COMPARE (1<<20)
504#define MI_SEMAPHORE_REGISTER (1<<18)
505#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
506#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
507#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
508#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
509#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
510#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
511#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
512#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
513#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
514#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
515#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
516#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
517#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
518#define MI_SEMAPHORE_SYNC_MASK (3<<16)
519#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
520#define MI_MM_SPACE_GTT (1<<8)
521#define MI_MM_SPACE_PHYSICAL (0<<8)
522#define MI_SAVE_EXT_STATE_EN (1<<3)
523#define MI_RESTORE_EXT_STATE_EN (1<<2)
524#define MI_FORCE_RESTORE (1<<1)
525#define MI_RESTORE_INHIBIT (1<<0)
526#define HSW_MI_RS_SAVE_STATE_EN (1<<3)
527#define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
528#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
529#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
530#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
531#define MI_SEMAPHORE_POLL (1<<15)
532#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
533#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
534#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
535#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
536#define MI_USE_GGTT (1 << 22) /* g4x+ */
537#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
538#define MI_STORE_DWORD_INDEX_SHIFT 2
539/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
540 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
541 * simply ignores the register load under certain conditions.
542 * - One can actually load arbitrary many arbitrary registers: Simply issue x
543 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
544 */
545#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
546#define MI_LRI_FORCE_POSTED (1<<12)
547#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
548#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
549#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
550#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
551#define MI_FLUSH_DW_STORE_INDEX (1<<21)
552#define MI_INVALIDATE_TLB (1<<18)
553#define MI_FLUSH_DW_OP_STOREDW (1<<14)
554#define MI_FLUSH_DW_OP_MASK (3<<14)
555#define MI_FLUSH_DW_NOTIFY (1<<8)
556#define MI_INVALIDATE_BSD (1<<7)
557#define MI_FLUSH_DW_USE_GTT (1<<2)
558#define MI_FLUSH_DW_USE_PPGTT (0<<2)
559#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
560#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
561#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
562#define MI_BATCH_NON_SECURE (1)
563/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
564#define MI_BATCH_NON_SECURE_I965 (1<<8)
565#define MI_BATCH_PPGTT_HSW (1<<8)
566#define MI_BATCH_NON_SECURE_HSW (1<<13)
567#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
568#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
569#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
570#define MI_BATCH_RESOURCE_STREAMER (1<<10)
571
572#define MI_PREDICATE_SRC0 _MMIO(0x2400)
573#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
574#define MI_PREDICATE_SRC1 _MMIO(0x2408)
575#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
576
577#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
578#define LOWER_SLICE_ENABLED (1<<0)
579#define LOWER_SLICE_DISABLED (0<<0)
580
581/*
582 * 3D instructions used by the kernel
583 */
584#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
585
586#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
587#define GEN9_MEDIA_POOL_ENABLE (1 << 31)
588#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
589#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
590#define SC_UPDATE_SCISSOR (0x1<<1)
591#define SC_ENABLE_MASK (0x1<<0)
592#define SC_ENABLE (0x1<<0)
593#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
594#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
595#define SCI_YMIN_MASK (0xffff<<16)
596#define SCI_XMIN_MASK (0xffff<<0)
597#define SCI_YMAX_MASK (0xffff<<16)
598#define SCI_XMAX_MASK (0xffff<<0)
599#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
600#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
601#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
602#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
603#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
604#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
605#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
606#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
607#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
608
609#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
610#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
611#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
612#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
613#define BLT_WRITE_A (2<<20)
614#define BLT_WRITE_RGB (1<<20)
615#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
616#define BLT_DEPTH_8 (0<<24)
617#define BLT_DEPTH_16_565 (1<<24)
618#define BLT_DEPTH_16_1555 (2<<24)
619#define BLT_DEPTH_32 (3<<24)
620#define BLT_ROP_SRC_COPY (0xcc<<16)
621#define BLT_ROP_COLOR_COPY (0xf0<<16)
622#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
623#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
624#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
625#define ASYNC_FLIP (1<<22)
626#define DISPLAY_PLANE_A (0<<20)
627#define DISPLAY_PLANE_B (1<<20)
628#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
629#define PIPE_CONTROL_FLUSH_L3 (1<<27)
630#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
631#define PIPE_CONTROL_MMIO_WRITE (1<<23)
632#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
633#define PIPE_CONTROL_CS_STALL (1<<20)
634#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
635#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
636#define PIPE_CONTROL_QW_WRITE (1<<14)
637#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
638#define PIPE_CONTROL_DEPTH_STALL (1<<13)
639#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
640#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
641#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
642#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
643#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
644#define PIPE_CONTROL_NOTIFY (1<<8)
645#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
646#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
647#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
648#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
649#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
650#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
651#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
652#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
653
654/*
655 * Commands used only by the command parser
656 */
657#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
658#define MI_ARB_CHECK MI_INSTR(0x05, 0)
659#define MI_RS_CONTROL MI_INSTR(0x06, 0)
660#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
661#define MI_PREDICATE MI_INSTR(0x0C, 0)
662#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
663#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
664#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
665#define MI_URB_CLEAR MI_INSTR(0x19, 0)
666#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
667#define MI_CLFLUSH MI_INSTR(0x27, 0)
668#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
669#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
670#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
671#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
672#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
673#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
674#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
675
676#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
677#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
678#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
679#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
680#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
681#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
682#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
683 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
684#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
685 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
686#define GFX_OP_3DSTATE_SO_DECL_LIST \
687 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
688
689#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
690 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
691#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
692 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
693#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
694 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
695#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
696 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
697#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
698 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
699
700#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
701
702#define COLOR_BLT ((0x2<<29)|(0x40<<22))
703#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
704
705/*
706 * Registers used only by the command parser
707 */
708#define BCS_SWCTRL _MMIO(0x22200)
709
710#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
711#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
712#define HS_INVOCATION_COUNT _MMIO(0x2300)
713#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
714#define DS_INVOCATION_COUNT _MMIO(0x2308)
715#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
716#define IA_VERTICES_COUNT _MMIO(0x2310)
717#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
718#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
719#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
720#define VS_INVOCATION_COUNT _MMIO(0x2320)
721#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
722#define GS_INVOCATION_COUNT _MMIO(0x2328)
723#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
724#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
725#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
726#define CL_INVOCATION_COUNT _MMIO(0x2338)
727#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
728#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
729#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
730#define PS_INVOCATION_COUNT _MMIO(0x2348)
731#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
732#define PS_DEPTH_COUNT _MMIO(0x2350)
733#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
734
735/* There are the 4 64-bit counter registers, one for each stream output */
736#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
737#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
738
739#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
740#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
741
742#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
743#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
744#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
745#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
746#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
747#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
748
749#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
750#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
751#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
752
753/* There are the 16 64-bit CS General Purpose Registers */
754#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8)
755#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4)
756
757#define GEN7_OACONTROL _MMIO(0x2360)
758#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000
759#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F
760#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6
761#define GEN7_OACONTROL_TIMER_ENABLE (1<<5)
762#define GEN7_OACONTROL_FORMAT_A13 (0<<2)
763#define GEN7_OACONTROL_FORMAT_A29 (1<<2)
764#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2<<2)
765#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3<<2)
766#define GEN7_OACONTROL_FORMAT_B4_C8 (4<<2)
767#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5<<2)
768#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6<<2)
769#define GEN7_OACONTROL_FORMAT_C4_B8 (7<<2)
770#define GEN7_OACONTROL_FORMAT_SHIFT 2
771#define GEN7_OACONTROL_PER_CTX_ENABLE (1<<1)
772#define GEN7_OACONTROL_ENABLE (1<<0)
773
774#define GEN8_OACTXID _MMIO(0x2364)
775
776#define GEN8_OA_DEBUG _MMIO(0x2B04)
777#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1<<5)
778#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1<<6)
779#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1<<2)
780#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1<<1)
781
782#define GEN8_OACONTROL _MMIO(0x2B00)
783#define GEN8_OA_REPORT_FORMAT_A12 (0<<2)
784#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2<<2)
785#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5<<2)
786#define GEN8_OA_REPORT_FORMAT_C4_B8 (7<<2)
787#define GEN8_OA_REPORT_FORMAT_SHIFT 2
788#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1<<1)
789#define GEN8_OA_COUNTER_ENABLE (1<<0)
790
791#define GEN8_OACTXCONTROL _MMIO(0x2360)
792#define GEN8_OA_TIMER_PERIOD_MASK 0x3F
793#define GEN8_OA_TIMER_PERIOD_SHIFT 2
794#define GEN8_OA_TIMER_ENABLE (1<<1)
795#define GEN8_OA_COUNTER_RESUME (1<<0)
796
797#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
798#define GEN7_OABUFFER_OVERRUN_DISABLE (1<<3)
799#define GEN7_OABUFFER_EDGE_TRIGGER (1<<2)
800#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1<<1)
801#define GEN7_OABUFFER_RESUME (1<<0)
802
803#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
804#define GEN8_OABUFFER _MMIO(0x2b14)
805
806#define GEN7_OASTATUS1 _MMIO(0x2364)
807#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0
808#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1<<2)
809#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1<<1)
810#define GEN7_OASTATUS1_REPORT_LOST (1<<0)
811
812#define GEN7_OASTATUS2 _MMIO(0x2368)
813#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
814
815#define GEN8_OASTATUS _MMIO(0x2b08)
816#define GEN8_OASTATUS_OVERRUN_STATUS (1<<3)
817#define GEN8_OASTATUS_COUNTER_OVERFLOW (1<<2)
818#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1<<1)
819#define GEN8_OASTATUS_REPORT_LOST (1<<0)
820
821#define GEN8_OAHEADPTR _MMIO(0x2B0C)
822#define GEN8_OAHEADPTR_MASK 0xffffffc0
823#define GEN8_OATAILPTR _MMIO(0x2B10)
824#define GEN8_OATAILPTR_MASK 0xffffffc0
825
826#define OABUFFER_SIZE_128K (0<<3)
827#define OABUFFER_SIZE_256K (1<<3)
828#define OABUFFER_SIZE_512K (2<<3)
829#define OABUFFER_SIZE_1M (3<<3)
830#define OABUFFER_SIZE_2M (4<<3)
831#define OABUFFER_SIZE_4M (5<<3)
832#define OABUFFER_SIZE_8M (6<<3)
833#define OABUFFER_SIZE_16M (7<<3)
834
835#define OA_MEM_SELECT_GGTT (1<<0)
836
837/*
838 * Flexible, Aggregate EU Counter Registers.
839 * Note: these aren't contiguous
840 */
841#define EU_PERF_CNTL0 _MMIO(0xe458)
842#define EU_PERF_CNTL1 _MMIO(0xe558)
843#define EU_PERF_CNTL2 _MMIO(0xe658)
844#define EU_PERF_CNTL3 _MMIO(0xe758)
845#define EU_PERF_CNTL4 _MMIO(0xe45c)
846#define EU_PERF_CNTL5 _MMIO(0xe55c)
847#define EU_PERF_CNTL6 _MMIO(0xe65c)
848
849/*
850 * OA Boolean state
851 */
852
853#define OASTARTTRIG1 _MMIO(0x2710)
854#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
855#define OASTARTTRIG1_THRESHOLD_MASK 0xffff
856
857#define OASTARTTRIG2 _MMIO(0x2714)
858#define OASTARTTRIG2_INVERT_A_0 (1<<0)
859#define OASTARTTRIG2_INVERT_A_1 (1<<1)
860#define OASTARTTRIG2_INVERT_A_2 (1<<2)
861#define OASTARTTRIG2_INVERT_A_3 (1<<3)
862#define OASTARTTRIG2_INVERT_A_4 (1<<4)
863#define OASTARTTRIG2_INVERT_A_5 (1<<5)
864#define OASTARTTRIG2_INVERT_A_6 (1<<6)
865#define OASTARTTRIG2_INVERT_A_7 (1<<7)
866#define OASTARTTRIG2_INVERT_A_8 (1<<8)
867#define OASTARTTRIG2_INVERT_A_9 (1<<9)
868#define OASTARTTRIG2_INVERT_A_10 (1<<10)
869#define OASTARTTRIG2_INVERT_A_11 (1<<11)
870#define OASTARTTRIG2_INVERT_A_12 (1<<12)
871#define OASTARTTRIG2_INVERT_A_13 (1<<13)
872#define OASTARTTRIG2_INVERT_A_14 (1<<14)
873#define OASTARTTRIG2_INVERT_A_15 (1<<15)
874#define OASTARTTRIG2_INVERT_B_0 (1<<16)
875#define OASTARTTRIG2_INVERT_B_1 (1<<17)
876#define OASTARTTRIG2_INVERT_B_2 (1<<18)
877#define OASTARTTRIG2_INVERT_B_3 (1<<19)
878#define OASTARTTRIG2_INVERT_C_0 (1<<20)
879#define OASTARTTRIG2_INVERT_C_1 (1<<21)
880#define OASTARTTRIG2_INVERT_D_0 (1<<22)
881#define OASTARTTRIG2_THRESHOLD_ENABLE (1<<23)
882#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1<<24)
883#define OASTARTTRIG2_EVENT_SELECT_0 (1<<28)
884#define OASTARTTRIG2_EVENT_SELECT_1 (1<<29)
885#define OASTARTTRIG2_EVENT_SELECT_2 (1<<30)
886#define OASTARTTRIG2_EVENT_SELECT_3 (1<<31)
887
888#define OASTARTTRIG3 _MMIO(0x2718)
889#define OASTARTTRIG3_NOA_SELECT_MASK 0xf
890#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0
891#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4
892#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8
893#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12
894#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16
895#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20
896#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24
897#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28
898
899#define OASTARTTRIG4 _MMIO(0x271c)
900#define OASTARTTRIG4_NOA_SELECT_MASK 0xf
901#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0
902#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4
903#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8
904#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12
905#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16
906#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20
907#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24
908#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28
909
910#define OASTARTTRIG5 _MMIO(0x2720)
911#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000
912#define OASTARTTRIG5_THRESHOLD_MASK 0xffff
913
914#define OASTARTTRIG6 _MMIO(0x2724)
915#define OASTARTTRIG6_INVERT_A_0 (1<<0)
916#define OASTARTTRIG6_INVERT_A_1 (1<<1)
917#define OASTARTTRIG6_INVERT_A_2 (1<<2)
918#define OASTARTTRIG6_INVERT_A_3 (1<<3)
919#define OASTARTTRIG6_INVERT_A_4 (1<<4)
920#define OASTARTTRIG6_INVERT_A_5 (1<<5)
921#define OASTARTTRIG6_INVERT_A_6 (1<<6)
922#define OASTARTTRIG6_INVERT_A_7 (1<<7)
923#define OASTARTTRIG6_INVERT_A_8 (1<<8)
924#define OASTARTTRIG6_INVERT_A_9 (1<<9)
925#define OASTARTTRIG6_INVERT_A_10 (1<<10)
926#define OASTARTTRIG6_INVERT_A_11 (1<<11)
927#define OASTARTTRIG6_INVERT_A_12 (1<<12)
928#define OASTARTTRIG6_INVERT_A_13 (1<<13)
929#define OASTARTTRIG6_INVERT_A_14 (1<<14)
930#define OASTARTTRIG6_INVERT_A_15 (1<<15)
931#define OASTARTTRIG6_INVERT_B_0 (1<<16)
932#define OASTARTTRIG6_INVERT_B_1 (1<<17)
933#define OASTARTTRIG6_INVERT_B_2 (1<<18)
934#define OASTARTTRIG6_INVERT_B_3 (1<<19)
935#define OASTARTTRIG6_INVERT_C_0 (1<<20)
936#define OASTARTTRIG6_INVERT_C_1 (1<<21)
937#define OASTARTTRIG6_INVERT_D_0 (1<<22)
938#define OASTARTTRIG6_THRESHOLD_ENABLE (1<<23)
939#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1<<24)
940#define OASTARTTRIG6_EVENT_SELECT_4 (1<<28)
941#define OASTARTTRIG6_EVENT_SELECT_5 (1<<29)
942#define OASTARTTRIG6_EVENT_SELECT_6 (1<<30)
943#define OASTARTTRIG6_EVENT_SELECT_7 (1<<31)
944
945#define OASTARTTRIG7 _MMIO(0x2728)
946#define OASTARTTRIG7_NOA_SELECT_MASK 0xf
947#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0
948#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4
949#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8
950#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12
951#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16
952#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20
953#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24
954#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28
955
956#define OASTARTTRIG8 _MMIO(0x272c)
957#define OASTARTTRIG8_NOA_SELECT_MASK 0xf
958#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0
959#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4
960#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8
961#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12
962#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16
963#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20
964#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24
965#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28
966
967#define OAREPORTTRIG1 _MMIO(0x2740)
968#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff
969#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
970
971#define OAREPORTTRIG2 _MMIO(0x2744)
972#define OAREPORTTRIG2_INVERT_A_0 (1<<0)
973#define OAREPORTTRIG2_INVERT_A_1 (1<<1)
974#define OAREPORTTRIG2_INVERT_A_2 (1<<2)
975#define OAREPORTTRIG2_INVERT_A_3 (1<<3)
976#define OAREPORTTRIG2_INVERT_A_4 (1<<4)
977#define OAREPORTTRIG2_INVERT_A_5 (1<<5)
978#define OAREPORTTRIG2_INVERT_A_6 (1<<6)
979#define OAREPORTTRIG2_INVERT_A_7 (1<<7)
980#define OAREPORTTRIG2_INVERT_A_8 (1<<8)
981#define OAREPORTTRIG2_INVERT_A_9 (1<<9)
982#define OAREPORTTRIG2_INVERT_A_10 (1<<10)
983#define OAREPORTTRIG2_INVERT_A_11 (1<<11)
984#define OAREPORTTRIG2_INVERT_A_12 (1<<12)
985#define OAREPORTTRIG2_INVERT_A_13 (1<<13)
986#define OAREPORTTRIG2_INVERT_A_14 (1<<14)
987#define OAREPORTTRIG2_INVERT_A_15 (1<<15)
988#define OAREPORTTRIG2_INVERT_B_0 (1<<16)
989#define OAREPORTTRIG2_INVERT_B_1 (1<<17)
990#define OAREPORTTRIG2_INVERT_B_2 (1<<18)
991#define OAREPORTTRIG2_INVERT_B_3 (1<<19)
992#define OAREPORTTRIG2_INVERT_C_0 (1<<20)
993#define OAREPORTTRIG2_INVERT_C_1 (1<<21)
994#define OAREPORTTRIG2_INVERT_D_0 (1<<22)
995#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23)
996#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31)
997
998#define OAREPORTTRIG3 _MMIO(0x2748)
999#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf
1000#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0
1001#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4
1002#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8
1003#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12
1004#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16
1005#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20
1006#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24
1007#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28
1008
1009#define OAREPORTTRIG4 _MMIO(0x274c)
1010#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf
1011#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0
1012#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4
1013#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8
1014#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12
1015#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16
1016#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20
1017#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24
1018#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28
1019
1020#define OAREPORTTRIG5 _MMIO(0x2750)
1021#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff
1022#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */
1023
1024#define OAREPORTTRIG6 _MMIO(0x2754)
1025#define OAREPORTTRIG6_INVERT_A_0 (1<<0)
1026#define OAREPORTTRIG6_INVERT_A_1 (1<<1)
1027#define OAREPORTTRIG6_INVERT_A_2 (1<<2)
1028#define OAREPORTTRIG6_INVERT_A_3 (1<<3)
1029#define OAREPORTTRIG6_INVERT_A_4 (1<<4)
1030#define OAREPORTTRIG6_INVERT_A_5 (1<<5)
1031#define OAREPORTTRIG6_INVERT_A_6 (1<<6)
1032#define OAREPORTTRIG6_INVERT_A_7 (1<<7)
1033#define OAREPORTTRIG6_INVERT_A_8 (1<<8)
1034#define OAREPORTTRIG6_INVERT_A_9 (1<<9)
1035#define OAREPORTTRIG6_INVERT_A_10 (1<<10)
1036#define OAREPORTTRIG6_INVERT_A_11 (1<<11)
1037#define OAREPORTTRIG6_INVERT_A_12 (1<<12)
1038#define OAREPORTTRIG6_INVERT_A_13 (1<<13)
1039#define OAREPORTTRIG6_INVERT_A_14 (1<<14)
1040#define OAREPORTTRIG6_INVERT_A_15 (1<<15)
1041#define OAREPORTTRIG6_INVERT_B_0 (1<<16)
1042#define OAREPORTTRIG6_INVERT_B_1 (1<<17)
1043#define OAREPORTTRIG6_INVERT_B_2 (1<<18)
1044#define OAREPORTTRIG6_INVERT_B_3 (1<<19)
1045#define OAREPORTTRIG6_INVERT_C_0 (1<<20)
1046#define OAREPORTTRIG6_INVERT_C_1 (1<<21)
1047#define OAREPORTTRIG6_INVERT_D_0 (1<<22)
1048#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23)
1049#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31)
1050
1051#define OAREPORTTRIG7 _MMIO(0x2758)
1052#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf
1053#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0
1054#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4
1055#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8
1056#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12
1057#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16
1058#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20
1059#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24
1060#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28
1061
1062#define OAREPORTTRIG8 _MMIO(0x275c)
1063#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf
1064#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0
1065#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4
1066#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8
1067#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12
1068#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16
1069#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20
1070#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
1071#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
1072
1073/* CECX_0 */
1074#define OACEC_COMPARE_LESS_OR_EQUAL 6
1075#define OACEC_COMPARE_NOT_EQUAL 5
1076#define OACEC_COMPARE_LESS_THAN 4
1077#define OACEC_COMPARE_GREATER_OR_EQUAL 3
1078#define OACEC_COMPARE_EQUAL 2
1079#define OACEC_COMPARE_GREATER_THAN 1
1080#define OACEC_COMPARE_ANY_EQUAL 0
1081
1082#define OACEC_COMPARE_VALUE_MASK 0xffff
1083#define OACEC_COMPARE_VALUE_SHIFT 3
1084
1085#define OACEC_SELECT_NOA (0<<19)
1086#define OACEC_SELECT_PREV (1<<19)
1087#define OACEC_SELECT_BOOLEAN (2<<19)
1088
1089/* CECX_1 */
1090#define OACEC_MASK_MASK 0xffff
1091#define OACEC_CONSIDERATIONS_MASK 0xffff
1092#define OACEC_CONSIDERATIONS_SHIFT 16
1093
1094#define OACEC0_0 _MMIO(0x2770)
1095#define OACEC0_1 _MMIO(0x2774)
1096#define OACEC1_0 _MMIO(0x2778)
1097#define OACEC1_1 _MMIO(0x277c)
1098#define OACEC2_0 _MMIO(0x2780)
1099#define OACEC2_1 _MMIO(0x2784)
1100#define OACEC3_0 _MMIO(0x2788)
1101#define OACEC3_1 _MMIO(0x278c)
1102#define OACEC4_0 _MMIO(0x2790)
1103#define OACEC4_1 _MMIO(0x2794)
1104#define OACEC5_0 _MMIO(0x2798)
1105#define OACEC5_1 _MMIO(0x279c)
1106#define OACEC6_0 _MMIO(0x27a0)
1107#define OACEC6_1 _MMIO(0x27a4)
1108#define OACEC7_0 _MMIO(0x27a8)
1109#define OACEC7_1 _MMIO(0x27ac)
1110
1111/* OA perf counters */
1112#define OA_PERFCNT1_LO _MMIO(0x91B8)
1113#define OA_PERFCNT1_HI _MMIO(0x91BC)
1114#define OA_PERFCNT2_LO _MMIO(0x91C0)
1115#define OA_PERFCNT2_HI _MMIO(0x91C4)
1116#define OA_PERFCNT3_LO _MMIO(0x91C8)
1117#define OA_PERFCNT3_HI _MMIO(0x91CC)
1118#define OA_PERFCNT4_LO _MMIO(0x91D8)
1119#define OA_PERFCNT4_HI _MMIO(0x91DC)
1120
1121#define OA_PERFMATRIX_LO _MMIO(0x91C8)
1122#define OA_PERFMATRIX_HI _MMIO(0x91CC)
1123
1124/* RPM unit config (Gen8+) */
1125#define RPM_CONFIG0 _MMIO(0x0D00)
1126#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
1127#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
1128#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0
1129#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1
1130#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1
1131#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
1132
1133#define RPM_CONFIG1 _MMIO(0x0D04)
1134#define GEN10_GT_NOA_ENABLE (1 << 9)
1135
1136/* GPM unit config (Gen9+) */
1137#define CTC_MODE _MMIO(0xA26C)
1138#define CTC_SOURCE_PARAMETER_MASK 1
1139#define CTC_SOURCE_CRYSTAL_CLOCK 0
1140#define CTC_SOURCE_DIVIDE_LOGIC 1
1141#define CTC_SHIFT_PARAMETER_SHIFT 1
1142#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT)
1143
1144/* RCP unit config (Gen8+) */
1145#define RCP_CONFIG _MMIO(0x0D08)
1146
1147/* NOA (HSW) */
1148#define HSW_MBVID2_NOA0 _MMIO(0x9E80)
1149#define HSW_MBVID2_NOA1 _MMIO(0x9E84)
1150#define HSW_MBVID2_NOA2 _MMIO(0x9E88)
1151#define HSW_MBVID2_NOA3 _MMIO(0x9E8C)
1152#define HSW_MBVID2_NOA4 _MMIO(0x9E90)
1153#define HSW_MBVID2_NOA5 _MMIO(0x9E94)
1154#define HSW_MBVID2_NOA6 _MMIO(0x9E98)
1155#define HSW_MBVID2_NOA7 _MMIO(0x9E9C)
1156#define HSW_MBVID2_NOA8 _MMIO(0x9EA0)
1157#define HSW_MBVID2_NOA9 _MMIO(0x9EA4)
1158
1159#define HSW_MBVID2_MISR0 _MMIO(0x9EC0)
1160
1161/* NOA (Gen8+) */
1162#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)
1163
1164#define MICRO_BP0_0 _MMIO(0x9800)
1165#define MICRO_BP0_2 _MMIO(0x9804)
1166#define MICRO_BP0_1 _MMIO(0x9808)
1167
1168#define MICRO_BP1_0 _MMIO(0x980C)
1169#define MICRO_BP1_2 _MMIO(0x9810)
1170#define MICRO_BP1_1 _MMIO(0x9814)
1171
1172#define MICRO_BP2_0 _MMIO(0x9818)
1173#define MICRO_BP2_2 _MMIO(0x981C)
1174#define MICRO_BP2_1 _MMIO(0x9820)
1175
1176#define MICRO_BP3_0 _MMIO(0x9824)
1177#define MICRO_BP3_2 _MMIO(0x9828)
1178#define MICRO_BP3_1 _MMIO(0x982C)
1179
1180#define MICRO_BP_TRIGGER _MMIO(0x9830)
1181#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834)
1182#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838)
1183#define MICRO_BP_FIRED_ARMED _MMIO(0x983C)
1184
1185#define GDT_CHICKEN_BITS _MMIO(0x9840)
1186#define GT_NOA_ENABLE 0x00000080
1187
1188#define NOA_DATA _MMIO(0x986C)
1189#define NOA_WRITE _MMIO(0x9888)
1190
1191#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
1192#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
1193#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
1194
1195/*
1196 * Reset registers
1197 */
1198#define DEBUG_RESET_I830 _MMIO(0x6070)
1199#define DEBUG_RESET_FULL (1<<7)
1200#define DEBUG_RESET_RENDER (1<<8)
1201#define DEBUG_RESET_DISPLAY (1<<9)
1202
1203/*
1204 * IOSF sideband
1205 */
1206#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
1207#define IOSF_DEVFN_SHIFT 24
1208#define IOSF_OPCODE_SHIFT 16
1209#define IOSF_PORT_SHIFT 8
1210#define IOSF_BYTE_ENABLES_SHIFT 4
1211#define IOSF_BAR_SHIFT 1
1212#define IOSF_SB_BUSY (1<<0)
1213#define IOSF_PORT_BUNIT 0x03
1214#define IOSF_PORT_PUNIT 0x04
1215#define IOSF_PORT_NC 0x11
1216#define IOSF_PORT_DPIO 0x12
1217#define IOSF_PORT_GPIO_NC 0x13
1218#define IOSF_PORT_CCK 0x14
1219#define IOSF_PORT_DPIO_2 0x1a
1220#define IOSF_PORT_FLISDSI 0x1b
1221#define IOSF_PORT_GPIO_SC 0x48
1222#define IOSF_PORT_GPIO_SUS 0xa8
1223#define IOSF_PORT_CCU 0xa9
1224#define CHV_IOSF_PORT_GPIO_N 0x13
1225#define CHV_IOSF_PORT_GPIO_SE 0x48
1226#define CHV_IOSF_PORT_GPIO_E 0xa8
1227#define CHV_IOSF_PORT_GPIO_SW 0xb2
1228#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1229#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1230
1231/* See configdb bunit SB addr map */
1232#define BUNIT_REG_BISOC 0x11
1233
1234#define PUNIT_REG_DSPFREQ 0x36
1235#define DSPFREQSTAT_SHIFT_CHV 24
1236#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
1237#define DSPFREQGUAR_SHIFT_CHV 8
1238#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
1239#define DSPFREQSTAT_SHIFT 30
1240#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
1241#define DSPFREQGUAR_SHIFT 14
1242#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
1243#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
1244#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
1245#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
1246#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
1247#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
1248#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
1249#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
1250#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
1251#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
1252#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
1253#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
1254#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
1255#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
1256#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
1257#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
1258
1259/*
1260 * i915_power_well_id:
1261 *
1262 * Platform specific IDs used to look up power wells and - except for custom
1263 * power wells - to define request/status register flag bit positions. As such
1264 * the set of IDs on a given platform must be unique and except for custom
1265 * power wells their value must stay fixed.
1266 */
1267enum i915_power_well_id {
1268 /*
1269 * I830
1270 * - custom power well
1271 */
1272 I830_DISP_PW_PIPES = 0,
1273
1274 /*
1275 * VLV/CHV
1276 * - PUNIT_REG_PWRGT_CTRL (bit: id*2),
1277 * PUNIT_REG_PWRGT_STATUS (bit: id*2) (PUNIT HAS v0.8)
1278 */
1279 PUNIT_POWER_WELL_RENDER = 0,
1280 PUNIT_POWER_WELL_MEDIA = 1,
1281 PUNIT_POWER_WELL_DISP2D = 3,
1282 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
1283 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
1284 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
1285 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
1286 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
1287 PUNIT_POWER_WELL_DPIO_RX0 = 10,
1288 PUNIT_POWER_WELL_DPIO_RX1 = 11,
1289 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
1290 /* - custom power well */
1291 CHV_DISP_PW_PIPE_A, /* 13 */
1292
1293 /*
1294 * HSW/BDW
1295 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
1296 */
1297 HSW_DISP_PW_GLOBAL = 15,
1298
1299 /*
1300 * GEN9+
1301 * - HSW_PWR_WELL_CTL_DRIVER(0) (status bit: id*2, req bit: id*2+1)
1302 */
1303 SKL_DISP_PW_MISC_IO = 0,
1304 SKL_DISP_PW_DDI_A_E,
1305 GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1306 CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
1307 SKL_DISP_PW_DDI_B,
1308 SKL_DISP_PW_DDI_C,
1309 SKL_DISP_PW_DDI_D,
1310 CNL_DISP_PW_DDI_F = 6,
1311
1312 GLK_DISP_PW_AUX_A = 8,
1313 GLK_DISP_PW_AUX_B,
1314 GLK_DISP_PW_AUX_C,
1315 CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
1316 CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
1317 CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
1318 CNL_DISP_PW_AUX_D,
1319 CNL_DISP_PW_AUX_F,
1320
1321 SKL_DISP_PW_1 = 14,
1322 SKL_DISP_PW_2,
1323
1324 /* - custom power wells */
1325 SKL_DISP_PW_DC_OFF,
1326 BXT_DPIO_CMN_A,
1327 BXT_DPIO_CMN_BC,
1328 GLK_DPIO_CMN_C, /* 19 */
1329
1330 /*
1331 * Multiple platforms.
1332 * Must start following the highest ID of any platform.
1333 * - custom power wells
1334 */
1335 I915_DISP_PW_ALWAYS_ON = 20,
1336};
1337
1338#define PUNIT_REG_PWRGT_CTRL 0x60
1339#define PUNIT_REG_PWRGT_STATUS 0x61
1340#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
1341#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
1342#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
1343#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
1344#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
1345
1346#define PUNIT_REG_GPU_LFM 0xd3
1347#define PUNIT_REG_GPU_FREQ_REQ 0xd4
1348#define PUNIT_REG_GPU_FREQ_STS 0xd8
1349#define GPLLENABLE (1<<4)
1350#define GENFREQSTATUS (1<<0)
1351#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
1352#define PUNIT_REG_CZ_TIMESTAMP 0xce
1353
1354#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
1355#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
1356
1357#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
1358#define FB_GFX_FREQ_FUSE_MASK 0xff
1359#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
1360#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
1361#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
1362
1363#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
1364#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
1365
1366#define PUNIT_REG_DDR_SETUP2 0x139
1367#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
1368#define FORCE_DDR_LOW_FREQ (1 << 1)
1369#define FORCE_DDR_HIGH_FREQ (1 << 0)
1370
1371#define PUNIT_GPU_STATUS_REG 0xdb
1372#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
1373#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
1374#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
1375#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
1376
1377#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
1378#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
1379#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
1380
1381#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
1382#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
1383#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
1384#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
1385#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
1386#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
1387#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
1388#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
1389#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
1390#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
1391
1392#define VLV_TURBO_SOC_OVERRIDE 0x04
1393#define VLV_OVERRIDE_EN 1
1394#define VLV_SOC_TDP_EN (1 << 1)
1395#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
1396#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
1397
1398/* vlv2 north clock has */
1399#define CCK_FUSE_REG 0x8
1400#define CCK_FUSE_HPLL_FREQ_MASK 0x3
1401#define CCK_REG_DSI_PLL_FUSE 0x44
1402#define CCK_REG_DSI_PLL_CONTROL 0x48
1403#define DSI_PLL_VCO_EN (1 << 31)
1404#define DSI_PLL_LDO_GATE (1 << 30)
1405#define DSI_PLL_P1_POST_DIV_SHIFT 17
1406#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
1407#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
1408#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
1409#define DSI_PLL_MUX_MASK (3 << 9)
1410#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
1411#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
1412#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
1413#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
1414#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
1415#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
1416#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
1417#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
1418#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
1419#define DSI_PLL_LOCK (1 << 0)
1420#define CCK_REG_DSI_PLL_DIVIDER 0x4c
1421#define DSI_PLL_LFSR (1 << 31)
1422#define DSI_PLL_FRACTION_EN (1 << 30)
1423#define DSI_PLL_FRAC_COUNTER_SHIFT 27
1424#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
1425#define DSI_PLL_USYNC_CNT_SHIFT 18
1426#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
1427#define DSI_PLL_N1_DIV_SHIFT 16
1428#define DSI_PLL_N1_DIV_MASK (3 << 16)
1429#define DSI_PLL_M1_DIV_SHIFT 0
1430#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
1431#define CCK_CZ_CLOCK_CONTROL 0x62
1432#define CCK_GPLL_CLOCK_CONTROL 0x67
1433#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
1434#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c
1435#define CCK_TRUNK_FORCE_ON (1 << 17)
1436#define CCK_TRUNK_FORCE_OFF (1 << 16)
1437#define CCK_FREQUENCY_STATUS (0x1f << 8)
1438#define CCK_FREQUENCY_STATUS_SHIFT 8
1439#define CCK_FREQUENCY_VALUES (0x1f << 0)
1440
1441/* DPIO registers */
1442#define DPIO_DEVFN 0
1443
1444#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1445#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
1446#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
1447#define DPIO_SFR_BYPASS (1<<1)
1448#define DPIO_CMNRST (1<<0)
1449
1450#define DPIO_PHY(pipe) ((pipe) >> 1)
1451#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1452
1453/*
1454 * Per pipe/PLL DPIO regs
1455 */
1456#define _VLV_PLL_DW3_CH0 0x800c
1457#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
1458#define DPIO_POST_DIV_DAC 0
1459#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
1460#define DPIO_POST_DIV_LVDS1 2
1461#define DPIO_POST_DIV_LVDS2 3
1462#define DPIO_K_SHIFT (24) /* 4 bits */
1463#define DPIO_P1_SHIFT (21) /* 3 bits */
1464#define DPIO_P2_SHIFT (16) /* 5 bits */
1465#define DPIO_N_SHIFT (12) /* 4 bits */
1466#define DPIO_ENABLE_CALIBRATION (1<<11)
1467#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
1468#define DPIO_M2DIV_MASK 0xff
1469#define _VLV_PLL_DW3_CH1 0x802c
1470#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
1471
1472#define _VLV_PLL_DW5_CH0 0x8014
1473#define DPIO_REFSEL_OVERRIDE 27
1474#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
1475#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
1476#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
1477#define DPIO_PLL_REFCLK_SEL_MASK 3
1478#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
1479#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1480#define _VLV_PLL_DW5_CH1 0x8034
1481#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
1482
1483#define _VLV_PLL_DW7_CH0 0x801c
1484#define _VLV_PLL_DW7_CH1 0x803c
1485#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
1486
1487#define _VLV_PLL_DW8_CH0 0x8040
1488#define _VLV_PLL_DW8_CH1 0x8060
1489#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
1490
1491#define VLV_PLL_DW9_BCAST 0xc044
1492#define _VLV_PLL_DW9_CH0 0x8044
1493#define _VLV_PLL_DW9_CH1 0x8064
1494#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
1495
1496#define _VLV_PLL_DW10_CH0 0x8048
1497#define _VLV_PLL_DW10_CH1 0x8068
1498#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
1499
1500#define _VLV_PLL_DW11_CH0 0x804c
1501#define _VLV_PLL_DW11_CH1 0x806c
1502#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
1503
1504/* Spec for ref block start counts at DW10 */
1505#define VLV_REF_DW13 0x80ac
1506
1507#define VLV_CMN_DW0 0x8100
1508
1509/*
1510 * Per DDI channel DPIO regs
1511 */
1512
1513#define _VLV_PCS_DW0_CH0 0x8200
1514#define _VLV_PCS_DW0_CH1 0x8400
1515#define DPIO_PCS_TX_LANE2_RESET (1<<16)
1516#define DPIO_PCS_TX_LANE1_RESET (1<<7)
1517#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
1518#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
1519#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
1520
1521#define _VLV_PCS01_DW0_CH0 0x200
1522#define _VLV_PCS23_DW0_CH0 0x400
1523#define _VLV_PCS01_DW0_CH1 0x2600
1524#define _VLV_PCS23_DW0_CH1 0x2800
1525#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
1526#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
1527
1528#define _VLV_PCS_DW1_CH0 0x8204
1529#define _VLV_PCS_DW1_CH1 0x8404
1530#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
1531#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
1532#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
1533#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
1534#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
1535#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
1536
1537#define _VLV_PCS01_DW1_CH0 0x204
1538#define _VLV_PCS23_DW1_CH0 0x404
1539#define _VLV_PCS01_DW1_CH1 0x2604
1540#define _VLV_PCS23_DW1_CH1 0x2804
1541#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
1542#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
1543
1544#define _VLV_PCS_DW8_CH0 0x8220
1545#define _VLV_PCS_DW8_CH1 0x8420
1546#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
1547#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
1548#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
1549
1550#define _VLV_PCS01_DW8_CH0 0x0220
1551#define _VLV_PCS23_DW8_CH0 0x0420
1552#define _VLV_PCS01_DW8_CH1 0x2620
1553#define _VLV_PCS23_DW8_CH1 0x2820
1554#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
1555#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
1556
1557#define _VLV_PCS_DW9_CH0 0x8224
1558#define _VLV_PCS_DW9_CH1 0x8424
1559#define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
1560#define DPIO_PCS_TX2MARGIN_000 (0<<13)
1561#define DPIO_PCS_TX2MARGIN_101 (1<<13)
1562#define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
1563#define DPIO_PCS_TX1MARGIN_000 (0<<10)
1564#define DPIO_PCS_TX1MARGIN_101 (1<<10)
1565#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1566
1567#define _VLV_PCS01_DW9_CH0 0x224
1568#define _VLV_PCS23_DW9_CH0 0x424
1569#define _VLV_PCS01_DW9_CH1 0x2624
1570#define _VLV_PCS23_DW9_CH1 0x2824
1571#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1572#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1573
1574#define _CHV_PCS_DW10_CH0 0x8228
1575#define _CHV_PCS_DW10_CH1 0x8428
1576#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
1577#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
1578#define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
1579#define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
1580#define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
1581#define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
1582#define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
1583#define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
1584#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1585
1586#define _VLV_PCS01_DW10_CH0 0x0228
1587#define _VLV_PCS23_DW10_CH0 0x0428
1588#define _VLV_PCS01_DW10_CH1 0x2628
1589#define _VLV_PCS23_DW10_CH1 0x2828
1590#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1591#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1592
1593#define _VLV_PCS_DW11_CH0 0x822c
1594#define _VLV_PCS_DW11_CH1 0x842c
1595#define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
1596#define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
1597#define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
1598#define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
1599#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1600
1601#define _VLV_PCS01_DW11_CH0 0x022c
1602#define _VLV_PCS23_DW11_CH0 0x042c
1603#define _VLV_PCS01_DW11_CH1 0x262c
1604#define _VLV_PCS23_DW11_CH1 0x282c
1605#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1606#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1607
1608#define _VLV_PCS01_DW12_CH0 0x0230
1609#define _VLV_PCS23_DW12_CH0 0x0430
1610#define _VLV_PCS01_DW12_CH1 0x2630
1611#define _VLV_PCS23_DW12_CH1 0x2830
1612#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1613#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1614
1615#define _VLV_PCS_DW12_CH0 0x8230
1616#define _VLV_PCS_DW12_CH1 0x8430
1617#define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
1618#define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
1619#define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
1620#define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
1621#define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
1622#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1623
1624#define _VLV_PCS_DW14_CH0 0x8238
1625#define _VLV_PCS_DW14_CH1 0x8438
1626#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1627
1628#define _VLV_PCS_DW23_CH0 0x825c
1629#define _VLV_PCS_DW23_CH1 0x845c
1630#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1631
1632#define _VLV_TX_DW2_CH0 0x8288
1633#define _VLV_TX_DW2_CH1 0x8488
1634#define DPIO_SWING_MARGIN000_SHIFT 16
1635#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1636#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1637#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1638
1639#define _VLV_TX_DW3_CH0 0x828c
1640#define _VLV_TX_DW3_CH1 0x848c
1641/* The following bit for CHV phy */
1642#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
1643#define DPIO_SWING_MARGIN101_SHIFT 16
1644#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1645#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1646
1647#define _VLV_TX_DW4_CH0 0x8290
1648#define _VLV_TX_DW4_CH1 0x8490
1649#define DPIO_SWING_DEEMPH9P5_SHIFT 24
1650#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1651#define DPIO_SWING_DEEMPH6P0_SHIFT 16
1652#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1653#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1654
1655#define _VLV_TX3_DW4_CH0 0x690
1656#define _VLV_TX3_DW4_CH1 0x2a90
1657#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1658
1659#define _VLV_TX_DW5_CH0 0x8294
1660#define _VLV_TX_DW5_CH1 0x8494
1661#define DPIO_TX_OCALINIT_EN (1<<31)
1662#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1663
1664#define _VLV_TX_DW11_CH0 0x82ac
1665#define _VLV_TX_DW11_CH1 0x84ac
1666#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1667
1668#define _VLV_TX_DW14_CH0 0x82b8
1669#define _VLV_TX_DW14_CH1 0x84b8
1670#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1671
1672/* CHV dpPhy registers */
1673#define _CHV_PLL_DW0_CH0 0x8000
1674#define _CHV_PLL_DW0_CH1 0x8180
1675#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1676
1677#define _CHV_PLL_DW1_CH0 0x8004
1678#define _CHV_PLL_DW1_CH1 0x8184
1679#define DPIO_CHV_N_DIV_SHIFT 8
1680#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1681#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1682
1683#define _CHV_PLL_DW2_CH0 0x8008
1684#define _CHV_PLL_DW2_CH1 0x8188
1685#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1686
1687#define _CHV_PLL_DW3_CH0 0x800c
1688#define _CHV_PLL_DW3_CH1 0x818c
1689#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1690#define DPIO_CHV_FIRST_MOD (0 << 8)
1691#define DPIO_CHV_SECOND_MOD (1 << 8)
1692#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1693#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1694#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1695
1696#define _CHV_PLL_DW6_CH0 0x8018
1697#define _CHV_PLL_DW6_CH1 0x8198
1698#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1699#define DPIO_CHV_INT_COEFF_SHIFT 8
1700#define DPIO_CHV_PROP_COEFF_SHIFT 0
1701#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1702
1703#define _CHV_PLL_DW8_CH0 0x8020
1704#define _CHV_PLL_DW8_CH1 0x81A0
1705#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1706#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1707#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1708
1709#define _CHV_PLL_DW9_CH0 0x8024
1710#define _CHV_PLL_DW9_CH1 0x81A4
1711#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1712#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1713#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1714#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1715
1716#define _CHV_CMN_DW0_CH0 0x8100
1717#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1718#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1719#define DPIO_ALLDL_POWERDOWN (1 << 1)
1720#define DPIO_ANYDL_POWERDOWN (1 << 0)
1721
1722#define _CHV_CMN_DW5_CH0 0x8114
1723#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1724#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1725#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1726#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1727#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1728#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1729#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1730#define CHV_BUFLEFTENA1_MASK (3 << 22)
1731
1732#define _CHV_CMN_DW13_CH0 0x8134
1733#define _CHV_CMN_DW0_CH1 0x8080
1734#define DPIO_CHV_S1_DIV_SHIFT 21
1735#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1736#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1737#define DPIO_CHV_K_DIV_SHIFT 4
1738#define DPIO_PLL_FREQLOCK (1 << 1)
1739#define DPIO_PLL_LOCK (1 << 0)
1740#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1741
1742#define _CHV_CMN_DW14_CH0 0x8138
1743#define _CHV_CMN_DW1_CH1 0x8084
1744#define DPIO_AFC_RECAL (1 << 14)
1745#define DPIO_DCLKP_EN (1 << 13)
1746#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1747#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1748#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1749#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1750#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1751#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1752#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1753#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1754#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1755
1756#define _CHV_CMN_DW19_CH0 0x814c
1757#define _CHV_CMN_DW6_CH1 0x8098
1758#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1759#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1760#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1761#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1762
1763#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1764
1765#define CHV_CMN_DW28 0x8170
1766#define DPIO_CL1POWERDOWNEN (1 << 23)
1767#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1768#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1769#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1770#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1771#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1772
1773#define CHV_CMN_DW30 0x8178
1774#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1775#define DPIO_LRC_BYPASS (1 << 3)
1776
1777#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1778 (lane) * 0x200 + (offset))
1779
1780#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1781#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1782#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1783#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1784#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1785#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1786#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1787#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1788#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1789#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1790#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1791#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1792#define DPIO_FRC_LATENCY_SHFIT 8
1793#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1794#define DPIO_UPAR_SHIFT 30
1795
1796/* BXT PHY registers */
1797#define _BXT_PHY0_BASE 0x6C000
1798#define _BXT_PHY1_BASE 0x162000
1799#define _BXT_PHY2_BASE 0x163000
1800#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \
1801 _BXT_PHY1_BASE, \
1802 _BXT_PHY2_BASE)
1803
1804#define _BXT_PHY(phy, reg) \
1805 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
1806
1807#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1808 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
1809 (reg_ch1) - _BXT_PHY0_BASE))
1810#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
1811 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
1812
1813#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1814#define MIPIO_RST_CTRL (1 << 2)
1815
1816#define _BXT_PHY_CTL_DDI_A 0x64C00
1817#define _BXT_PHY_CTL_DDI_B 0x64C10
1818#define _BXT_PHY_CTL_DDI_C 0x64C20
1819#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
1820#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
1821#define BXT_PHY_LANE_ENABLED (1 << 8)
1822#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
1823 _BXT_PHY_CTL_DDI_B)
1824
1825#define _PHY_CTL_FAMILY_EDP 0x64C80
1826#define _PHY_CTL_FAMILY_DDI 0x64C90
1827#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
1828#define COMMON_RESET_DIS (1 << 31)
1829#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \
1830 _PHY_CTL_FAMILY_EDP, \
1831 _PHY_CTL_FAMILY_DDI_C)
1832
1833/* BXT PHY PLL registers */
1834#define _PORT_PLL_A 0x46074
1835#define _PORT_PLL_B 0x46078
1836#define _PORT_PLL_C 0x4607c
1837#define PORT_PLL_ENABLE (1 << 31)
1838#define PORT_PLL_LOCK (1 << 30)
1839#define PORT_PLL_REF_SEL (1 << 27)
1840#define PORT_PLL_POWER_ENABLE (1 << 26)
1841#define PORT_PLL_POWER_STATE (1 << 25)
1842#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1843
1844#define _PORT_PLL_EBB_0_A 0x162034
1845#define _PORT_PLL_EBB_0_B 0x6C034
1846#define _PORT_PLL_EBB_0_C 0x6C340
1847#define PORT_PLL_P1_SHIFT 13
1848#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1849#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1850#define PORT_PLL_P2_SHIFT 8
1851#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1852#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1853#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1854 _PORT_PLL_EBB_0_B, \
1855 _PORT_PLL_EBB_0_C)
1856
1857#define _PORT_PLL_EBB_4_A 0x162038
1858#define _PORT_PLL_EBB_4_B 0x6C038
1859#define _PORT_PLL_EBB_4_C 0x6C344
1860#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1861#define PORT_PLL_RECALIBRATE (1 << 14)
1862#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
1863 _PORT_PLL_EBB_4_B, \
1864 _PORT_PLL_EBB_4_C)
1865
1866#define _PORT_PLL_0_A 0x162100
1867#define _PORT_PLL_0_B 0x6C100
1868#define _PORT_PLL_0_C 0x6C380
1869/* PORT_PLL_0_A */
1870#define PORT_PLL_M2_MASK 0xFF
1871/* PORT_PLL_1_A */
1872#define PORT_PLL_N_SHIFT 8
1873#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1874#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1875/* PORT_PLL_2_A */
1876#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1877/* PORT_PLL_3_A */
1878#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1879/* PORT_PLL_6_A */
1880#define PORT_PLL_PROP_COEFF_MASK 0xF
1881#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1882#define PORT_PLL_INT_COEFF(x) ((x) << 8)
1883#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1884#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1885/* PORT_PLL_8_A */
1886#define PORT_PLL_TARGET_CNT_MASK 0x3FF
1887/* PORT_PLL_9_A */
1888#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1889#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1890/* PORT_PLL_10_A */
1891#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
1892#define PORT_PLL_DCO_AMP_DEFAULT 15
1893#define PORT_PLL_DCO_AMP_MASK 0x3c00
1894#define PORT_PLL_DCO_AMP(x) ((x)<<10)
1895#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
1896 _PORT_PLL_0_B, \
1897 _PORT_PLL_0_C)
1898#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
1899 (idx) * 4)
1900
1901/* BXT PHY common lane registers */
1902#define _PORT_CL1CM_DW0_A 0x162000
1903#define _PORT_CL1CM_DW0_BC 0x6C000
1904#define PHY_POWER_GOOD (1 << 16)
1905#define PHY_RESERVED (1 << 7)
1906#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
1907
1908#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1909#define CL_POWER_DOWN_ENABLE (1 << 4)
1910#define SUS_CLOCK_CONFIG (3 << 0)
1911
1912#define _ICL_PORT_CL_DW5_A 0x162014
1913#define _ICL_PORT_CL_DW5_B 0x6C014
1914#define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
1915 _ICL_PORT_CL_DW5_B)
1916
1917#define _PORT_CL1CM_DW9_A 0x162024
1918#define _PORT_CL1CM_DW9_BC 0x6C024
1919#define IREF0RC_OFFSET_SHIFT 8
1920#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1921#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1922
1923#define _PORT_CL1CM_DW10_A 0x162028
1924#define _PORT_CL1CM_DW10_BC 0x6C028
1925#define IREF1RC_OFFSET_SHIFT 8
1926#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1927#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1928
1929#define _PORT_CL1CM_DW28_A 0x162070
1930#define _PORT_CL1CM_DW28_BC 0x6C070
1931#define OCL1_POWER_DOWN_EN (1 << 23)
1932#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1933#define SUS_CLK_CONFIG 0x3
1934#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1935
1936#define _PORT_CL1CM_DW30_A 0x162078
1937#define _PORT_CL1CM_DW30_BC 0x6C078
1938#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1939#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1940
1941#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
1942#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
1943#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
1944#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84
1945#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04
1946#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404
1947#define _CNL_PORT_PCS_DW1_LN0_B 0x162604
1948#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
1949#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
1950#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
1951#define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \
1952 _CNL_PORT_PCS_DW1_GRP_AE, \
1953 _CNL_PORT_PCS_DW1_GRP_B, \
1954 _CNL_PORT_PCS_DW1_GRP_C, \
1955 _CNL_PORT_PCS_DW1_GRP_D, \
1956 _CNL_PORT_PCS_DW1_GRP_AE, \
1957 _CNL_PORT_PCS_DW1_GRP_F)
1958#define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \
1959 _CNL_PORT_PCS_DW1_LN0_AE, \
1960 _CNL_PORT_PCS_DW1_LN0_B, \
1961 _CNL_PORT_PCS_DW1_LN0_C, \
1962 _CNL_PORT_PCS_DW1_LN0_D, \
1963 _CNL_PORT_PCS_DW1_LN0_AE, \
1964 _CNL_PORT_PCS_DW1_LN0_F)
1965#define COMMON_KEEPER_EN (1 << 26)
1966
1967#define _CNL_PORT_TX_DW2_GRP_AE 0x162348
1968#define _CNL_PORT_TX_DW2_GRP_B 0x1623C8
1969#define _CNL_PORT_TX_DW2_GRP_C 0x162B48
1970#define _CNL_PORT_TX_DW2_GRP_D 0x162BC8
1971#define _CNL_PORT_TX_DW2_GRP_F 0x162A48
1972#define _CNL_PORT_TX_DW2_LN0_AE 0x162448
1973#define _CNL_PORT_TX_DW2_LN0_B 0x162648
1974#define _CNL_PORT_TX_DW2_LN0_C 0x162C48
1975#define _CNL_PORT_TX_DW2_LN0_D 0x162E48
1976#define _CNL_PORT_TX_DW2_LN0_F 0x162848
1977#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \
1978 _CNL_PORT_TX_DW2_GRP_AE, \
1979 _CNL_PORT_TX_DW2_GRP_B, \
1980 _CNL_PORT_TX_DW2_GRP_C, \
1981 _CNL_PORT_TX_DW2_GRP_D, \
1982 _CNL_PORT_TX_DW2_GRP_AE, \
1983 _CNL_PORT_TX_DW2_GRP_F)
1984#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \
1985 _CNL_PORT_TX_DW2_LN0_AE, \
1986 _CNL_PORT_TX_DW2_LN0_B, \
1987 _CNL_PORT_TX_DW2_LN0_C, \
1988 _CNL_PORT_TX_DW2_LN0_D, \
1989 _CNL_PORT_TX_DW2_LN0_AE, \
1990 _CNL_PORT_TX_DW2_LN0_F)
1991#define SWING_SEL_UPPER(x) ((x >> 3) << 15)
1992#define SWING_SEL_UPPER_MASK (1 << 15)
1993#define SWING_SEL_LOWER(x) ((x & 0x7) << 11)
1994#define SWING_SEL_LOWER_MASK (0x7 << 11)
1995#define RCOMP_SCALAR(x) ((x) << 0)
1996#define RCOMP_SCALAR_MASK (0xFF << 0)
1997
1998#define _CNL_PORT_TX_DW4_GRP_AE 0x162350
1999#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0
2000#define _CNL_PORT_TX_DW4_GRP_C 0x162B50
2001#define _CNL_PORT_TX_DW4_GRP_D 0x162BD0
2002#define _CNL_PORT_TX_DW4_GRP_F 0x162A50
2003#define _CNL_PORT_TX_DW4_LN0_AE 0x162450
2004#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
2005#define _CNL_PORT_TX_DW4_LN0_B 0x162650
2006#define _CNL_PORT_TX_DW4_LN0_C 0x162C50
2007#define _CNL_PORT_TX_DW4_LN0_D 0x162E50
2008#define _CNL_PORT_TX_DW4_LN0_F 0x162850
2009#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \
2010 _CNL_PORT_TX_DW4_GRP_AE, \
2011 _CNL_PORT_TX_DW4_GRP_B, \
2012 _CNL_PORT_TX_DW4_GRP_C, \
2013 _CNL_PORT_TX_DW4_GRP_D, \
2014 _CNL_PORT_TX_DW4_GRP_AE, \
2015 _CNL_PORT_TX_DW4_GRP_F)
2016#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \
2017 _CNL_PORT_TX_DW4_LN0_AE, \
2018 _CNL_PORT_TX_DW4_LN1_AE, \
2019 _CNL_PORT_TX_DW4_LN0_B, \
2020 _CNL_PORT_TX_DW4_LN0_C, \
2021 _CNL_PORT_TX_DW4_LN0_D, \
2022 _CNL_PORT_TX_DW4_LN0_AE, \
2023 _CNL_PORT_TX_DW4_LN0_F)
2024#define LOADGEN_SELECT (1 << 31)
2025#define POST_CURSOR_1(x) ((x) << 12)
2026#define POST_CURSOR_1_MASK (0x3F << 12)
2027#define POST_CURSOR_2(x) ((x) << 6)
2028#define POST_CURSOR_2_MASK (0x3F << 6)
2029#define CURSOR_COEFF(x) ((x) << 0)
2030#define CURSOR_COEFF_MASK (0x3F << 0)
2031
2032#define _CNL_PORT_TX_DW5_GRP_AE 0x162354
2033#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4
2034#define _CNL_PORT_TX_DW5_GRP_C 0x162B54
2035#define _CNL_PORT_TX_DW5_GRP_D 0x162BD4
2036#define _CNL_PORT_TX_DW5_GRP_F 0x162A54
2037#define _CNL_PORT_TX_DW5_LN0_AE 0x162454
2038#define _CNL_PORT_TX_DW5_LN0_B 0x162654
2039#define _CNL_PORT_TX_DW5_LN0_C 0x162C54
2040#define _CNL_PORT_TX_DW5_LN0_D 0x162E54
2041#define _CNL_PORT_TX_DW5_LN0_F 0x162854
2042#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
2043 _CNL_PORT_TX_DW5_GRP_AE, \
2044 _CNL_PORT_TX_DW5_GRP_B, \
2045 _CNL_PORT_TX_DW5_GRP_C, \
2046 _CNL_PORT_TX_DW5_GRP_D, \
2047 _CNL_PORT_TX_DW5_GRP_AE, \
2048 _CNL_PORT_TX_DW5_GRP_F)
2049#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \
2050 _CNL_PORT_TX_DW5_LN0_AE, \
2051 _CNL_PORT_TX_DW5_LN0_B, \
2052 _CNL_PORT_TX_DW5_LN0_C, \
2053 _CNL_PORT_TX_DW5_LN0_D, \
2054 _CNL_PORT_TX_DW5_LN0_AE, \
2055 _CNL_PORT_TX_DW5_LN0_F)
2056#define TX_TRAINING_EN (1 << 31)
2057#define TAP3_DISABLE (1 << 29)
2058#define SCALING_MODE_SEL(x) ((x) << 18)
2059#define SCALING_MODE_SEL_MASK (0x7 << 18)
2060#define RTERM_SELECT(x) ((x) << 3)
2061#define RTERM_SELECT_MASK (0x7 << 3)
2062
2063#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C
2064#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC
2065#define _CNL_PORT_TX_DW7_GRP_C 0x162B5C
2066#define _CNL_PORT_TX_DW7_GRP_D 0x162BDC
2067#define _CNL_PORT_TX_DW7_GRP_F 0x162A5C
2068#define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
2069#define _CNL_PORT_TX_DW7_LN0_B 0x16265C
2070#define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
2071#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C
2072#define _CNL_PORT_TX_DW7_LN0_F 0x16285C
2073#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
2074 _CNL_PORT_TX_DW7_GRP_AE, \
2075 _CNL_PORT_TX_DW7_GRP_B, \
2076 _CNL_PORT_TX_DW7_GRP_C, \
2077 _CNL_PORT_TX_DW7_GRP_D, \
2078 _CNL_PORT_TX_DW7_GRP_AE, \
2079 _CNL_PORT_TX_DW7_GRP_F)
2080#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \
2081 _CNL_PORT_TX_DW7_LN0_AE, \
2082 _CNL_PORT_TX_DW7_LN0_B, \
2083 _CNL_PORT_TX_DW7_LN0_C, \
2084 _CNL_PORT_TX_DW7_LN0_D, \
2085 _CNL_PORT_TX_DW7_LN0_AE, \
2086 _CNL_PORT_TX_DW7_LN0_F)
2087#define N_SCALAR(x) ((x) << 24)
2088#define N_SCALAR_MASK (0x7F << 24)
2089
2090/* The spec defines this only for BXT PHY0, but lets assume that this
2091 * would exist for PHY1 too if it had a second channel.
2092 */
2093#define _PORT_CL2CM_DW6_A 0x162358
2094#define _PORT_CL2CM_DW6_BC 0x6C358
2095#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
2096#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
2097
2098#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
2099#define COMP_INIT (1 << 31)
2100#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
2101#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
2102#define PROCESS_INFO_DOT_0 (0 << 26)
2103#define PROCESS_INFO_DOT_1 (1 << 26)
2104#define PROCESS_INFO_DOT_4 (2 << 26)
2105#define PROCESS_INFO_MASK (7 << 26)
2106#define PROCESS_INFO_SHIFT 26
2107#define VOLTAGE_INFO_0_85V (0 << 24)
2108#define VOLTAGE_INFO_0_95V (1 << 24)
2109#define VOLTAGE_INFO_1_05V (2 << 24)
2110#define VOLTAGE_INFO_MASK (3 << 24)
2111#define VOLTAGE_INFO_SHIFT 24
2112#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
2113#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
2114
2115#define _ICL_PORT_COMP_DW0_A 0x162100
2116#define _ICL_PORT_COMP_DW0_B 0x6C100
2117#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
2118 _ICL_PORT_COMP_DW0_B)
2119#define _ICL_PORT_COMP_DW1_A 0x162104
2120#define _ICL_PORT_COMP_DW1_B 0x6C104
2121#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
2122 _ICL_PORT_COMP_DW1_B)
2123#define _ICL_PORT_COMP_DW3_A 0x16210C
2124#define _ICL_PORT_COMP_DW3_B 0x6C10C
2125#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
2126 _ICL_PORT_COMP_DW3_B)
2127#define _ICL_PORT_COMP_DW9_A 0x162124
2128#define _ICL_PORT_COMP_DW9_B 0x6C124
2129#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
2130 _ICL_PORT_COMP_DW9_B)
2131#define _ICL_PORT_COMP_DW10_A 0x162128
2132#define _ICL_PORT_COMP_DW10_B 0x6C128
2133#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
2134 _ICL_PORT_COMP_DW10_A, \
2135 _ICL_PORT_COMP_DW10_B)
2136
2137/* BXT PHY Ref registers */
2138#define _PORT_REF_DW3_A 0x16218C
2139#define _PORT_REF_DW3_BC 0x6C18C
2140#define GRC_DONE (1 << 22)
2141#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
2142
2143#define _PORT_REF_DW6_A 0x162198
2144#define _PORT_REF_DW6_BC 0x6C198
2145#define GRC_CODE_SHIFT 24
2146#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
2147#define GRC_CODE_FAST_SHIFT 16
2148#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
2149#define GRC_CODE_SLOW_SHIFT 8
2150#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
2151#define GRC_CODE_NOM_MASK 0xFF
2152#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
2153
2154#define _PORT_REF_DW8_A 0x1621A0
2155#define _PORT_REF_DW8_BC 0x6C1A0
2156#define GRC_DIS (1 << 15)
2157#define GRC_RDY_OVRD (1 << 1)
2158#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
2159
2160/* BXT PHY PCS registers */
2161#define _PORT_PCS_DW10_LN01_A 0x162428
2162#define _PORT_PCS_DW10_LN01_B 0x6C428
2163#define _PORT_PCS_DW10_LN01_C 0x6C828
2164#define _PORT_PCS_DW10_GRP_A 0x162C28
2165#define _PORT_PCS_DW10_GRP_B 0x6CC28
2166#define _PORT_PCS_DW10_GRP_C 0x6CE28
2167#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2168 _PORT_PCS_DW10_LN01_B, \
2169 _PORT_PCS_DW10_LN01_C)
2170#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2171 _PORT_PCS_DW10_GRP_B, \
2172 _PORT_PCS_DW10_GRP_C)
2173
2174#define TX2_SWING_CALC_INIT (1 << 31)
2175#define TX1_SWING_CALC_INIT (1 << 30)
2176
2177#define _PORT_PCS_DW12_LN01_A 0x162430
2178#define _PORT_PCS_DW12_LN01_B 0x6C430
2179#define _PORT_PCS_DW12_LN01_C 0x6C830
2180#define _PORT_PCS_DW12_LN23_A 0x162630
2181#define _PORT_PCS_DW12_LN23_B 0x6C630
2182#define _PORT_PCS_DW12_LN23_C 0x6CA30
2183#define _PORT_PCS_DW12_GRP_A 0x162c30
2184#define _PORT_PCS_DW12_GRP_B 0x6CC30
2185#define _PORT_PCS_DW12_GRP_C 0x6CE30
2186#define LANESTAGGER_STRAP_OVRD (1 << 6)
2187#define LANE_STAGGER_MASK 0x1F
2188#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2189 _PORT_PCS_DW12_LN01_B, \
2190 _PORT_PCS_DW12_LN01_C)
2191#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2192 _PORT_PCS_DW12_LN23_B, \
2193 _PORT_PCS_DW12_LN23_C)
2194#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2195 _PORT_PCS_DW12_GRP_B, \
2196 _PORT_PCS_DW12_GRP_C)
2197
2198/* BXT PHY TX registers */
2199#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
2200 ((lane) & 1) * 0x80)
2201
2202#define _PORT_TX_DW2_LN0_A 0x162508
2203#define _PORT_TX_DW2_LN0_B 0x6C508
2204#define _PORT_TX_DW2_LN0_C 0x6C908
2205#define _PORT_TX_DW2_GRP_A 0x162D08
2206#define _PORT_TX_DW2_GRP_B 0x6CD08
2207#define _PORT_TX_DW2_GRP_C 0x6CF08
2208#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2209 _PORT_TX_DW2_LN0_B, \
2210 _PORT_TX_DW2_LN0_C)
2211#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2212 _PORT_TX_DW2_GRP_B, \
2213 _PORT_TX_DW2_GRP_C)
2214#define MARGIN_000_SHIFT 16
2215#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
2216#define UNIQ_TRANS_SCALE_SHIFT 8
2217#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
2218
2219#define _PORT_TX_DW3_LN0_A 0x16250C
2220#define _PORT_TX_DW3_LN0_B 0x6C50C
2221#define _PORT_TX_DW3_LN0_C 0x6C90C
2222#define _PORT_TX_DW3_GRP_A 0x162D0C
2223#define _PORT_TX_DW3_GRP_B 0x6CD0C
2224#define _PORT_TX_DW3_GRP_C 0x6CF0C
2225#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2226 _PORT_TX_DW3_LN0_B, \
2227 _PORT_TX_DW3_LN0_C)
2228#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2229 _PORT_TX_DW3_GRP_B, \
2230 _PORT_TX_DW3_GRP_C)
2231#define SCALE_DCOMP_METHOD (1 << 26)
2232#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
2233
2234#define _PORT_TX_DW4_LN0_A 0x162510
2235#define _PORT_TX_DW4_LN0_B 0x6C510
2236#define _PORT_TX_DW4_LN0_C 0x6C910
2237#define _PORT_TX_DW4_GRP_A 0x162D10
2238#define _PORT_TX_DW4_GRP_B 0x6CD10
2239#define _PORT_TX_DW4_GRP_C 0x6CF10
2240#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2241 _PORT_TX_DW4_LN0_B, \
2242 _PORT_TX_DW4_LN0_C)
2243#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2244 _PORT_TX_DW4_GRP_B, \
2245 _PORT_TX_DW4_GRP_C)
2246#define DEEMPH_SHIFT 24
2247#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
2248
2249#define _PORT_TX_DW5_LN0_A 0x162514
2250#define _PORT_TX_DW5_LN0_B 0x6C514
2251#define _PORT_TX_DW5_LN0_C 0x6C914
2252#define _PORT_TX_DW5_GRP_A 0x162D14
2253#define _PORT_TX_DW5_GRP_B 0x6CD14
2254#define _PORT_TX_DW5_GRP_C 0x6CF14
2255#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2256 _PORT_TX_DW5_LN0_B, \
2257 _PORT_TX_DW5_LN0_C)
2258#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
2259 _PORT_TX_DW5_GRP_B, \
2260 _PORT_TX_DW5_GRP_C)
2261#define DCC_DELAY_RANGE_1 (1 << 9)
2262#define DCC_DELAY_RANGE_2 (1 << 8)
2263
2264#define _PORT_TX_DW14_LN0_A 0x162538
2265#define _PORT_TX_DW14_LN0_B 0x6C538
2266#define _PORT_TX_DW14_LN0_C 0x6C938
2267#define LATENCY_OPTIM_SHIFT 30
2268#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
2269#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
2270 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
2271 _PORT_TX_DW14_LN0_C) + \
2272 _BXT_LANE_OFFSET(lane))
2273
2274/* UAIMI scratch pad register 1 */
2275#define UAIMI_SPR1 _MMIO(0x4F074)
2276/* SKL VccIO mask */
2277#define SKL_VCCIO_MASK 0x1
2278/* SKL balance leg register */
2279#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
2280/* I_boost values */
2281#define BALANCE_LEG_SHIFT(port) (8+3*(port))
2282#define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
2283/* Balance leg disable bits */
2284#define BALANCE_LEG_DISABLE_SHIFT 23
2285#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
2286
2287/*
2288 * Fence registers
2289 * [0-7] @ 0x2000 gen2,gen3
2290 * [8-15] @ 0x3000 945,g33,pnv
2291 *
2292 * [0-15] @ 0x3000 gen4,gen5
2293 *
2294 * [0-15] @ 0x100000 gen6,vlv,chv
2295 * [0-31] @ 0x100000 gen7+
2296 */
2297#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
2298#define I830_FENCE_START_MASK 0x07f80000
2299#define I830_FENCE_TILING_Y_SHIFT 12
2300#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
2301#define I830_FENCE_PITCH_SHIFT 4
2302#define I830_FENCE_REG_VALID (1<<0)
2303#define I915_FENCE_MAX_PITCH_VAL 4
2304#define I830_FENCE_MAX_PITCH_VAL 6
2305#define I830_FENCE_MAX_SIZE_VAL (1<<8)
2306
2307#define I915_FENCE_START_MASK 0x0ff00000
2308#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
2309
2310#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
2311#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
2312#define I965_FENCE_PITCH_SHIFT 2
2313#define I965_FENCE_TILING_Y_SHIFT 1
2314#define I965_FENCE_REG_VALID (1<<0)
2315#define I965_FENCE_MAX_PITCH_VAL 0x0400
2316
2317#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
2318#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
2319#define GEN6_FENCE_PITCH_SHIFT 32
2320#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
2321
2322
2323/* control register for cpu gtt access */
2324#define TILECTL _MMIO(0x101000)
2325#define TILECTL_SWZCTL (1 << 0)
2326#define TILECTL_TLBPF (1 << 1)
2327#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
2328#define TILECTL_BACKSNOOP_DIS (1 << 3)
2329
2330/*
2331 * Instruction and interrupt control regs
2332 */
2333#define PGTBL_CTL _MMIO(0x02020)
2334#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
2335#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
2336#define PGTBL_ER _MMIO(0x02024)
2337#define PRB0_BASE (0x2030-0x30)
2338#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
2339#define PRB2_BASE (0x2050-0x30) /* gen3 */
2340#define SRB0_BASE (0x2100-0x30) /* gen2 */
2341#define SRB1_BASE (0x2110-0x30) /* gen2 */
2342#define SRB2_BASE (0x2120-0x30) /* 830 */
2343#define SRB3_BASE (0x2130-0x30) /* 830 */
2344#define RENDER_RING_BASE 0x02000
2345#define BSD_RING_BASE 0x04000
2346#define GEN6_BSD_RING_BASE 0x12000
2347#define GEN8_BSD2_RING_BASE 0x1c000
2348#define GEN11_BSD_RING_BASE 0x1c0000
2349#define GEN11_BSD2_RING_BASE 0x1c4000
2350#define GEN11_BSD3_RING_BASE 0x1d0000
2351#define GEN11_BSD4_RING_BASE 0x1d4000
2352#define VEBOX_RING_BASE 0x1a000
2353#define GEN11_VEBOX_RING_BASE 0x1c8000
2354#define GEN11_VEBOX2_RING_BASE 0x1d8000
2355#define BLT_RING_BASE 0x22000
2356#define RING_TAIL(base) _MMIO((base)+0x30)
2357#define RING_HEAD(base) _MMIO((base)+0x34)
2358#define RING_START(base) _MMIO((base)+0x38)
2359#define RING_CTL(base) _MMIO((base)+0x3c)
2360#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */
2361#define RING_SYNC_0(base) _MMIO((base)+0x40)
2362#define RING_SYNC_1(base) _MMIO((base)+0x44)
2363#define RING_SYNC_2(base) _MMIO((base)+0x48)
2364#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2365#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2366#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
2367#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
2368#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
2369#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
2370#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
2371#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
2372#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
2373#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
2374#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
2375#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
2376#define GEN6_NOSYNC INVALID_MMIO_REG
2377#define RING_PSMI_CTL(base) _MMIO((base)+0x50)
2378#define RING_MAX_IDLE(base) _MMIO((base)+0x54)
2379#define RING_HWS_PGA(base) _MMIO((base)+0x80)
2380#define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080)
2381#define RING_RESET_CTL(base) _MMIO((base)+0xd0)
2382#define RESET_CTL_REQUEST_RESET (1 << 0)
2383#define RESET_CTL_READY_TO_RESET (1 << 1)
2384
2385#define HSW_GTT_CACHE_EN _MMIO(0x4024)
2386#define GTT_CACHE_EN_ALL 0xF0007FFF
2387#define GEN7_WR_WATERMARK _MMIO(0x4028)
2388#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
2389#define ARB_MODE _MMIO(0x4030)
2390#define ARB_MODE_SWIZZLE_SNB (1<<4)
2391#define ARB_MODE_SWIZZLE_IVB (1<<5)
2392#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
2393#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
2394/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
2395#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
2396#define GEN7_LRA_LIMITS_REG_NUM 13
2397#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
2398#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
2399
2400#define GAMTARBMODE _MMIO(0x04a08)
2401#define ARB_MODE_BWGTLB_DISABLE (1<<9)
2402#define ARB_MODE_SWIZZLE_BDW (1<<1)
2403#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
2404#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100*(engine)->hw_id)
2405#define GEN8_RING_FAULT_REG _MMIO(0x4094)
2406#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
2407#define RING_FAULT_GTTSEL_MASK (1<<11)
2408#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
2409#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
2410#define RING_FAULT_VALID (1<<0)
2411#define DONE_REG _MMIO(0x40b0)
2412#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
2413#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
2414#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index)*4)
2415#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
2416#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
2417#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
2418#define RING_ACTHD(base) _MMIO((base)+0x74)
2419#define RING_ACTHD_UDW(base) _MMIO((base)+0x5c)
2420#define RING_NOPID(base) _MMIO((base)+0x94)
2421#define RING_IMR(base) _MMIO((base)+0xa8)
2422#define RING_HWSTAM(base) _MMIO((base)+0x98)
2423#define RING_TIMESTAMP(base) _MMIO((base)+0x358)
2424#define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4)
2425#define TAIL_ADDR 0x001FFFF8
2426#define HEAD_WRAP_COUNT 0xFFE00000
2427#define HEAD_WRAP_ONE 0x00200000
2428#define HEAD_ADDR 0x001FFFFC
2429#define RING_NR_PAGES 0x001FF000
2430#define RING_REPORT_MASK 0x00000006
2431#define RING_REPORT_64K 0x00000002
2432#define RING_REPORT_128K 0x00000004
2433#define RING_NO_REPORT 0x00000000
2434#define RING_VALID_MASK 0x00000001
2435#define RING_VALID 0x00000001
2436#define RING_INVALID 0x00000000
2437#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
2438#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
2439#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
2440
2441#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4)
2442#define RING_MAX_NONPRIV_SLOTS 12
2443
2444#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
2445
2446#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0)
2447#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18)
2448
2449#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
2450#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
2451
2452#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
2453#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
2454#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1<<24)
2455
2456#if 0
2457#define PRB0_TAIL _MMIO(0x2030)
2458#define PRB0_HEAD _MMIO(0x2034)
2459#define PRB0_START _MMIO(0x2038)
2460#define PRB0_CTL _MMIO(0x203c)
2461#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
2462#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
2463#define PRB1_START _MMIO(0x2048) /* 915+ only */
2464#define PRB1_CTL _MMIO(0x204c) /* 915+ only */
2465#endif
2466#define IPEIR_I965 _MMIO(0x2064)
2467#define IPEHR_I965 _MMIO(0x2068)
2468#define GEN7_SC_INSTDONE _MMIO(0x7100)
2469#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
2470#define GEN7_ROW_INSTDONE _MMIO(0xe164)
2471#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
2472#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
2473#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3)
2474#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24)
2475#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3)
2476#define RING_IPEIR(base) _MMIO((base)+0x64)
2477#define RING_IPEHR(base) _MMIO((base)+0x68)
2478/*
2479 * On GEN4, only the render ring INSTDONE exists and has a different
2480 * layout than the GEN7+ version.
2481 * The GEN2 counterpart of this register is GEN2_INSTDONE.
2482 */
2483#define RING_INSTDONE(base) _MMIO((base)+0x6c)
2484#define RING_INSTPS(base) _MMIO((base)+0x70)
2485#define RING_DMA_FADD(base) _MMIO((base)+0x78)
2486#define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */
2487#define RING_INSTPM(base) _MMIO((base)+0xc0)
2488#define RING_MI_MODE(base) _MMIO((base)+0x9c)
2489#define INSTPS _MMIO(0x2070) /* 965+ only */
2490#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
2491#define ACTHD_I965 _MMIO(0x2074)
2492#define HWS_PGA _MMIO(0x2080)
2493#define HWS_ADDRESS_MASK 0xfffff000
2494#define HWS_START_ADDRESS_SHIFT 4
2495#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
2496#define PWRCTX_EN (1<<0)
2497#define IPEIR _MMIO(0x2088)
2498#define IPEHR _MMIO(0x208c)
2499#define GEN2_INSTDONE _MMIO(0x2090)
2500#define NOPID _MMIO(0x2094)
2501#define HWSTAM _MMIO(0x2098)
2502#define DMA_FADD_I8XX _MMIO(0x20d0)
2503#define RING_BBSTATE(base) _MMIO((base)+0x110)
2504#define RING_BB_PPGTT (1 << 5)
2505#define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */
2506#define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */
2507#define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */
2508#define RING_BBADDR(base) _MMIO((base)+0x140)
2509#define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */
2510#define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */
2511#define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */
2512#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */
2513#define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */
2514
2515#define ERROR_GEN6 _MMIO(0x40a0)
2516#define GEN7_ERR_INT _MMIO(0x44040)
2517#define ERR_INT_POISON (1<<31)
2518#define ERR_INT_MMIO_UNCLAIMED (1<<13)
2519#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
2520#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
2521#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
2522#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
2523#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
2524#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
2525#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
2526#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
2527
2528#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
2529#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
2530#define FAULT_VA_HIGH_BITS (0xf << 0)
2531#define FAULT_GTT_SEL (1 << 4)
2532
2533#define FPGA_DBG _MMIO(0x42300)
2534#define FPGA_DBG_RM_NOCLAIM (1<<31)
2535
2536#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2537#define CLAIM_ER_CLR (1 << 31)
2538#define CLAIM_ER_OVERFLOW (1 << 16)
2539#define CLAIM_ER_CTR_MASK 0xffff
2540
2541#define DERRMR _MMIO(0x44050)
2542/* Note that HBLANK events are reserved on bdw+ */
2543#define DERRMR_PIPEA_SCANLINE (1<<0)
2544#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
2545#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
2546#define DERRMR_PIPEA_VBLANK (1<<3)
2547#define DERRMR_PIPEA_HBLANK (1<<5)
2548#define DERRMR_PIPEB_SCANLINE (1<<8)
2549#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
2550#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
2551#define DERRMR_PIPEB_VBLANK (1<<11)
2552#define DERRMR_PIPEB_HBLANK (1<<13)
2553/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
2554#define DERRMR_PIPEC_SCANLINE (1<<14)
2555#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
2556#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
2557#define DERRMR_PIPEC_VBLANK (1<<21)
2558#define DERRMR_PIPEC_HBLANK (1<<22)
2559
2560
2561/* GM45+ chicken bits -- debug workaround bits that may be required
2562 * for various sorts of correct behavior. The top 16 bits of each are
2563 * the enables for writing to the corresponding low bit.
2564 */
2565#define _3D_CHICKEN _MMIO(0x2084)
2566#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
2567#define _3D_CHICKEN2 _MMIO(0x208c)
2568/* Disables pipelining of read flushes past the SF-WIZ interface.
2569 * Required on all Ironlake steppings according to the B-Spec, but the
2570 * particular danger of not doing so is not specified.
2571 */
2572# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
2573#define _3D_CHICKEN3 _MMIO(0x2090)
2574#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
2575#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5)
2576#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
2577#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
2578#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
2579
2580#define MI_MODE _MMIO(0x209c)
2581# define VS_TIMER_DISPATCH (1 << 6)
2582# define MI_FLUSH_ENABLE (1 << 12)
2583# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
2584# define MODE_IDLE (1 << 9)
2585# define STOP_RING (1 << 8)
2586
2587#define GEN6_GT_MODE _MMIO(0x20d0)
2588#define GEN7_GT_MODE _MMIO(0x7008)
2589#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
2590#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
2591#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
2592#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
2593#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
2594#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
2595#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
2596#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
2597
2598/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
2599#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
2600#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
2601
2602/* WaClearTdlStateAckDirtyBits */
2603#define GEN8_STATE_ACK _MMIO(0x20F0)
2604#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
2605#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100)
2606#define GEN9_STATE_ACK_TDL0 (1 << 12)
2607#define GEN9_STATE_ACK_TDL1 (1 << 13)
2608#define GEN9_STATE_ACK_TDL2 (1 << 14)
2609#define GEN9_STATE_ACK_TDL3 (1 << 15)
2610#define GEN9_SUBSLICE_TDL_ACK_BITS \
2611 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
2612 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
2613
2614#define GFX_MODE _MMIO(0x2520)
2615#define GFX_MODE_GEN7 _MMIO(0x229c)
2616#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base+0x29c)
2617#define GFX_RUN_LIST_ENABLE (1<<15)
2618#define GFX_INTERRUPT_STEERING (1<<14)
2619#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
2620#define GFX_SURFACE_FAULT_ENABLE (1<<12)
2621#define GFX_REPLAY_MODE (1<<11)
2622#define GFX_PSMI_GRANULARITY (1<<10)
2623#define GFX_PPGTT_ENABLE (1<<9)
2624#define GEN8_GFX_PPGTT_48B (1<<7)
2625
2626#define GFX_FORWARD_VBLANK_MASK (3<<5)
2627#define GFX_FORWARD_VBLANK_NEVER (0<<5)
2628#define GFX_FORWARD_VBLANK_ALWAYS (1<<5)
2629#define GFX_FORWARD_VBLANK_COND (2<<5)
2630
2631#define GEN11_GFX_DISABLE_LEGACY_MODE (1<<3)
2632
2633#define VLV_DISPLAY_BASE 0x180000
2634#define VLV_MIPI_BASE VLV_DISPLAY_BASE
2635#define BXT_MIPI_BASE 0x60000
2636
2637#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2638#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2639#define SCPD0 _MMIO(0x209c) /* 915+ only */
2640#define IER _MMIO(0x20a0)
2641#define IIR _MMIO(0x20a4)
2642#define IMR _MMIO(0x20a8)
2643#define ISR _MMIO(0x20ac)
2644#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2645#define GINT_DIS (1<<22)
2646#define GCFG_DIS (1<<8)
2647#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2648#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2649#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2650#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2651#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2652#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2653#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2654#define VLV_PCBR_ADDR_SHIFT 12
2655
2656#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
2657#define EIR _MMIO(0x20b0)
2658#define EMR _MMIO(0x20b4)
2659#define ESR _MMIO(0x20b8)
2660#define GM45_ERROR_PAGE_TABLE (1<<5)
2661#define GM45_ERROR_MEM_PRIV (1<<4)
2662#define I915_ERROR_PAGE_TABLE (1<<4)
2663#define GM45_ERROR_CP_PRIV (1<<3)
2664#define I915_ERROR_MEMORY_REFRESH (1<<1)
2665#define I915_ERROR_INSTRUCTION (1<<0)
2666#define INSTPM _MMIO(0x20c0)
2667#define INSTPM_SELF_EN (1<<12) /* 915GM only */
2668#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
2669 will not assert AGPBUSY# and will only
2670 be delivered when out of C3. */
2671#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
2672#define INSTPM_TLB_INVALIDATE (1<<9)
2673#define INSTPM_SYNC_FLUSH (1<<5)
2674#define ACTHD _MMIO(0x20c8)
2675#define MEM_MODE _MMIO(0x20cc)
2676#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
2677#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
2678#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
2679#define FW_BLC _MMIO(0x20d8)
2680#define FW_BLC2 _MMIO(0x20dc)
2681#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
2682#define FW_BLC_SELF_EN_MASK (1<<31)
2683#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
2684#define FW_BLC_SELF_EN (1<<15) /* 945 only */
2685#define MM_BURST_LENGTH 0x00700000
2686#define MM_FIFO_WATERMARK 0x0001F000
2687#define LM_BURST_LENGTH 0x00000700
2688#define LM_FIFO_WATERMARK 0x0000001F
2689#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
2690
2691#define MBUS_ABOX_CTL _MMIO(0x45038)
2692#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
2693#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
2694#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
2695#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
2696#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
2697#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
2698#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
2699#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
2700
2701#define _PIPEA_MBUS_DBOX_CTL 0x7003C
2702#define _PIPEB_MBUS_DBOX_CTL 0x7103C
2703#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
2704 _PIPEB_MBUS_DBOX_CTL)
2705#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
2706#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14)
2707#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8)
2708#define MBUS_DBOX_B_CREDIT(x) ((x) << 8)
2709#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0)
2710#define MBUS_DBOX_A_CREDIT(x) ((x) << 0)
2711
2712#define MBUS_UBOX_CTL _MMIO(0x4503C)
2713#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
2714#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
2715
2716/* Make render/texture TLB fetches lower priorty than associated data
2717 * fetches. This is not turned on by default
2718 */
2719#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
2720
2721/* Isoch request wait on GTT enable (Display A/B/C streams).
2722 * Make isoch requests stall on the TLB update. May cause
2723 * display underruns (test mode only)
2724 */
2725#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
2726
2727/* Block grant count for isoch requests when block count is
2728 * set to a finite value.
2729 */
2730#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
2731#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
2732#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
2733#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
2734#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
2735
2736/* Enable render writes to complete in C2/C3/C4 power states.
2737 * If this isn't enabled, render writes are prevented in low
2738 * power states. That seems bad to me.
2739 */
2740#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
2741
2742/* This acknowledges an async flip immediately instead
2743 * of waiting for 2TLB fetches.
2744 */
2745#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
2746
2747/* Enables non-sequential data reads through arbiter
2748 */
2749#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
2750
2751/* Disable FSB snooping of cacheable write cycles from binner/render
2752 * command stream
2753 */
2754#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
2755
2756/* Arbiter time slice for non-isoch streams */
2757#define MI_ARB_TIME_SLICE_MASK (7 << 5)
2758#define MI_ARB_TIME_SLICE_1 (0 << 5)
2759#define MI_ARB_TIME_SLICE_2 (1 << 5)
2760#define MI_ARB_TIME_SLICE_4 (2 << 5)
2761#define MI_ARB_TIME_SLICE_6 (3 << 5)
2762#define MI_ARB_TIME_SLICE_8 (4 << 5)
2763#define MI_ARB_TIME_SLICE_10 (5 << 5)
2764#define MI_ARB_TIME_SLICE_14 (6 << 5)
2765#define MI_ARB_TIME_SLICE_16 (7 << 5)
2766
2767/* Low priority grace period page size */
2768#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
2769#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
2770
2771/* Disable display A/B trickle feed */
2772#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
2773
2774/* Set display plane priority */
2775#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
2776#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
2777
2778#define MI_STATE _MMIO(0x20e4) /* gen2 only */
2779#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
2780#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
2781
2782#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
2783#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
2784#define CM0_IZ_OPT_DISABLE (1<<6)
2785#define CM0_ZR_OPT_DISABLE (1<<5)
2786#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
2787#define CM0_DEPTH_EVICT_DISABLE (1<<4)
2788#define CM0_COLOR_EVICT_DISABLE (1<<3)
2789#define CM0_DEPTH_WRITE_DISABLE (1<<1)
2790#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
2791#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
2792#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
2793#define GFX_FLSH_CNTL_EN (1<<0)
2794#define ECOSKPD _MMIO(0x21d0)
2795#define ECO_GATING_CX_ONLY (1<<3)
2796#define ECO_FLIP_DONE (1<<0)
2797
2798#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
2799#define RC_OP_FLUSH_ENABLE (1<<0)
2800#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
2801#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
2802#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
2803#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
2804#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
2805
2806#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
2807#define GEN6_BLITTER_LOCK_SHIFT 16
2808#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
2809
2810#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
2811#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
2812#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
2813#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
2814
2815#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
2816#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
2817
2818/* Fuse readout registers for GT */
2819#define HSW_PAVP_FUSE1 _MMIO(0x911C)
2820#define HSW_F1_EU_DIS_SHIFT 16
2821#define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT)
2822#define HSW_F1_EU_DIS_10EUS 0
2823#define HSW_F1_EU_DIS_8EUS 1
2824#define HSW_F1_EU_DIS_6EUS 2
2825
2826#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
2827#define CHV_FGT_DISABLE_SS0 (1 << 10)
2828#define CHV_FGT_DISABLE_SS1 (1 << 11)
2829#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
2830#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
2831#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
2832#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
2833#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
2834#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
2835#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
2836#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
2837
2838#define GEN8_FUSE2 _MMIO(0x9120)
2839#define GEN8_F2_SS_DIS_SHIFT 21
2840#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
2841#define GEN8_F2_S_ENA_SHIFT 25
2842#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
2843
2844#define GEN9_F2_SS_DIS_SHIFT 20
2845#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
2846
2847#define GEN10_F2_S_ENA_SHIFT 22
2848#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT)
2849#define GEN10_F2_SS_DIS_SHIFT 18
2850#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
2851
2852#define GEN8_EU_DISABLE0 _MMIO(0x9134)
2853#define GEN8_EU_DIS0_S0_MASK 0xffffff
2854#define GEN8_EU_DIS0_S1_SHIFT 24
2855#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
2856
2857#define GEN8_EU_DISABLE1 _MMIO(0x9138)
2858#define GEN8_EU_DIS1_S1_MASK 0xffff
2859#define GEN8_EU_DIS1_S2_SHIFT 16
2860#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
2861
2862#define GEN8_EU_DISABLE2 _MMIO(0x913c)
2863#define GEN8_EU_DIS2_S2_MASK 0xff
2864
2865#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
2866
2867#define GEN10_EU_DISABLE3 _MMIO(0x9140)
2868#define GEN10_EU_DIS_SS_MASK 0xff
2869
2870#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
2871#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
2872#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
2873#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
2874#define GEN6_BSD_GO_INDICATOR (1 << 4)
2875
2876/* On modern GEN architectures interrupt control consists of two sets
2877 * of registers. The first set pertains to the ring generating the
2878 * interrupt. The second control is for the functional block generating the
2879 * interrupt. These are PM, GT, DE, etc.
2880 *
2881 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2882 * GT interrupt bits, so we don't need to duplicate the defines.
2883 *
2884 * These defines should cover us well from SNB->HSW with minor exceptions
2885 * it can also work on ILK.
2886 */
2887#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2888#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2889#define GT_BLT_USER_INTERRUPT (1 << 22)
2890#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2891#define GT_BSD_USER_INTERRUPT (1 << 12)
2892#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2893#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2894#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2895#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2896#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2897#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2898#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2899#define GT_RENDER_USER_INTERRUPT (1 << 0)
2900
2901#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2902#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2903
2904#define GT_PARITY_ERROR(dev_priv) \
2905 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2906 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2907
2908/* These are all the "old" interrupts */
2909#define ILK_BSD_USER_INTERRUPT (1<<5)
2910
2911#define I915_PM_INTERRUPT (1<<31)
2912#define I915_ISP_INTERRUPT (1<<22)
2913#define I915_LPE_PIPE_B_INTERRUPT (1<<21)
2914#define I915_LPE_PIPE_A_INTERRUPT (1<<20)
2915#define I915_MIPIC_INTERRUPT (1<<19)
2916#define I915_MIPIA_INTERRUPT (1<<18)
2917#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
2918#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
2919#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
2920#define I915_MASTER_ERROR_INTERRUPT (1<<15)
2921#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
2922#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
2923#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
2924#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
2925#define I915_HWB_OOM_INTERRUPT (1<<13)
2926#define I915_LPE_PIPE_C_INTERRUPT (1<<12)
2927#define I915_SYNC_STATUS_INTERRUPT (1<<12)
2928#define I915_MISC_INTERRUPT (1<<11)
2929#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
2930#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
2931#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
2932#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
2933#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
2934#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
2935#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
2936#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
2937#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
2938#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
2939#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
2940#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
2941#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
2942#define I915_DEBUG_INTERRUPT (1<<2)
2943#define I915_WINVALID_INTERRUPT (1<<1)
2944#define I915_USER_INTERRUPT (1<<1)
2945#define I915_ASLE_INTERRUPT (1<<0)
2946#define I915_BSD_USER_INTERRUPT (1<<25)
2947
2948#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
2949#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
2950
2951/* DisplayPort Audio w/ LPE */
2952#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
2953#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
2954
2955#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
2956#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
2957#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
2958#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
2959 _VLV_AUD_PORT_EN_B_DBG, \
2960 _VLV_AUD_PORT_EN_C_DBG, \
2961 _VLV_AUD_PORT_EN_D_DBG)
2962#define VLV_AMP_MUTE (1 << 1)
2963
2964#define GEN6_BSD_RNCID _MMIO(0x12198)
2965
2966#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2967#define GEN7_FF_SCHED_MASK 0x0077070
2968#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2969#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
2970#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
2971#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
2972#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
2973#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
2974#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
2975#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
2976#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
2977#define GEN7_FF_VS_SCHED_HW (0x0<<12)
2978#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
2979#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
2980#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
2981#define GEN7_FF_DS_SCHED_HW (0x0<<4)
2982
2983/*
2984 * Framebuffer compression (915+ only)
2985 */
2986
2987#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2988#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2989#define FBC_CONTROL _MMIO(0x3208)
2990#define FBC_CTL_EN (1<<31)
2991#define FBC_CTL_PERIODIC (1<<30)
2992#define FBC_CTL_INTERVAL_SHIFT (16)
2993#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
2994#define FBC_CTL_C3_IDLE (1<<13)
2995#define FBC_CTL_STRIDE_SHIFT (5)
2996#define FBC_CTL_FENCENO_SHIFT (0)
2997#define FBC_COMMAND _MMIO(0x320c)
2998#define FBC_CMD_COMPRESS (1<<0)
2999#define FBC_STATUS _MMIO(0x3210)
3000#define FBC_STAT_COMPRESSING (1<<31)
3001#define FBC_STAT_COMPRESSED (1<<30)
3002#define FBC_STAT_MODIFIED (1<<29)
3003#define FBC_STAT_CURRENT_LINE_SHIFT (0)
3004#define FBC_CONTROL2 _MMIO(0x3214)
3005#define FBC_CTL_FENCE_DBL (0<<4)
3006#define FBC_CTL_IDLE_IMM (0<<2)
3007#define FBC_CTL_IDLE_FULL (1<<2)
3008#define FBC_CTL_IDLE_LINE (2<<2)
3009#define FBC_CTL_IDLE_DEBUG (3<<2)
3010#define FBC_CTL_CPU_FENCE (1<<1)
3011#define FBC_CTL_PLANE(plane) ((plane)<<0)
3012#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
3013#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
3014
3015#define FBC_LL_SIZE (1536)
3016
3017#define FBC_LLC_READ_CTRL _MMIO(0x9044)
3018#define FBC_LLC_FULLY_OPEN (1<<30)
3019
3020/* Framebuffer compression for GM45+ */
3021#define DPFC_CB_BASE _MMIO(0x3200)
3022#define DPFC_CONTROL _MMIO(0x3208)
3023#define DPFC_CTL_EN (1<<31)
3024#define DPFC_CTL_PLANE(plane) ((plane)<<30)
3025#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
3026#define DPFC_CTL_FENCE_EN (1<<29)
3027#define IVB_DPFC_CTL_FENCE_EN (1<<28)
3028#define DPFC_CTL_PERSISTENT_MODE (1<<25)
3029#define DPFC_SR_EN (1<<10)
3030#define DPFC_CTL_LIMIT_1X (0<<6)
3031#define DPFC_CTL_LIMIT_2X (1<<6)
3032#define DPFC_CTL_LIMIT_4X (2<<6)
3033#define DPFC_RECOMP_CTL _MMIO(0x320c)
3034#define DPFC_RECOMP_STALL_EN (1<<27)
3035#define DPFC_RECOMP_STALL_WM_SHIFT (16)
3036#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
3037#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
3038#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
3039#define DPFC_STATUS _MMIO(0x3210)
3040#define DPFC_INVAL_SEG_SHIFT (16)
3041#define DPFC_INVAL_SEG_MASK (0x07ff0000)
3042#define DPFC_COMP_SEG_SHIFT (0)
3043#define DPFC_COMP_SEG_MASK (0x000007ff)
3044#define DPFC_STATUS2 _MMIO(0x3214)
3045#define DPFC_FENCE_YOFF _MMIO(0x3218)
3046#define DPFC_CHICKEN _MMIO(0x3224)
3047#define DPFC_HT_MODIFY (1<<31)
3048
3049/* Framebuffer compression for Ironlake */
3050#define ILK_DPFC_CB_BASE _MMIO(0x43200)
3051#define ILK_DPFC_CONTROL _MMIO(0x43208)
3052#define FBC_CTL_FALSE_COLOR (1<<10)
3053/* The bit 28-8 is reserved */
3054#define DPFC_RESERVED (0x1FFFFF00)
3055#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
3056#define ILK_DPFC_STATUS _MMIO(0x43210)
3057#define ILK_DPFC_COMP_SEG_MASK 0x7ff
3058#define IVB_FBC_STATUS2 _MMIO(0x43214)
3059#define IVB_FBC_COMP_SEG_MASK 0x7ff
3060#define BDW_FBC_COMP_SEG_MASK 0xfff
3061#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
3062#define ILK_DPFC_CHICKEN _MMIO(0x43224)
3063#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
3064#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
3065#define ILK_FBC_RT_BASE _MMIO(0x2128)
3066#define ILK_FBC_RT_VALID (1<<0)
3067#define SNB_FBC_FRONT_BUFFER (1<<1)
3068
3069#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
3070#define ILK_FBCQ_DIS (1<<22)
3071#define ILK_PABSTRETCH_DIS (1<<21)
3072
3073
3074/*
3075 * Framebuffer compression for Sandybridge
3076 *
3077 * The following two registers are of type GTTMMADR
3078 */
3079#define SNB_DPFC_CTL_SA _MMIO(0x100100)
3080#define SNB_CPU_FENCE_ENABLE (1<<29)
3081#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
3082
3083/* Framebuffer compression for Ivybridge */
3084#define IVB_FBC_RT_BASE _MMIO(0x7020)
3085
3086#define IPS_CTL _MMIO(0x43408)
3087#define IPS_ENABLE (1 << 31)
3088
3089#define MSG_FBC_REND_STATE _MMIO(0x50380)
3090#define FBC_REND_NUKE (1<<2)
3091#define FBC_REND_CACHE_CLEAN (1<<1)
3092
3093/*
3094 * GPIO regs
3095 */
3096#define GPIOA _MMIO(0x5010)
3097#define GPIOB _MMIO(0x5014)
3098#define GPIOC _MMIO(0x5018)
3099#define GPIOD _MMIO(0x501c)
3100#define GPIOE _MMIO(0x5020)
3101#define GPIOF _MMIO(0x5024)
3102#define GPIOG _MMIO(0x5028)
3103#define GPIOH _MMIO(0x502c)
3104# define GPIO_CLOCK_DIR_MASK (1 << 0)
3105# define GPIO_CLOCK_DIR_IN (0 << 1)
3106# define GPIO_CLOCK_DIR_OUT (1 << 1)
3107# define GPIO_CLOCK_VAL_MASK (1 << 2)
3108# define GPIO_CLOCK_VAL_OUT (1 << 3)
3109# define GPIO_CLOCK_VAL_IN (1 << 4)
3110# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
3111# define GPIO_DATA_DIR_MASK (1 << 8)
3112# define GPIO_DATA_DIR_IN (0 << 9)
3113# define GPIO_DATA_DIR_OUT (1 << 9)
3114# define GPIO_DATA_VAL_MASK (1 << 10)
3115# define GPIO_DATA_VAL_OUT (1 << 11)
3116# define GPIO_DATA_VAL_IN (1 << 12)
3117# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
3118
3119#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
3120#define GMBUS_AKSV_SELECT (1<<11)
3121#define GMBUS_RATE_100KHZ (0<<8)
3122#define GMBUS_RATE_50KHZ (1<<8)
3123#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
3124#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
3125#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
3126#define GMBUS_PIN_DISABLED 0
3127#define GMBUS_PIN_SSC 1
3128#define GMBUS_PIN_VGADDC 2
3129#define GMBUS_PIN_PANEL 3
3130#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
3131#define GMBUS_PIN_DPC 4 /* HDMIC */
3132#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
3133#define GMBUS_PIN_DPD 6 /* HDMID */
3134#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
3135#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
3136#define GMBUS_PIN_2_BXT 2
3137#define GMBUS_PIN_3_BXT 3
3138#define GMBUS_PIN_4_CNP 4
3139#define GMBUS_PIN_9_TC1_ICP 9
3140#define GMBUS_PIN_10_TC2_ICP 10
3141#define GMBUS_PIN_11_TC3_ICP 11
3142#define GMBUS_PIN_12_TC4_ICP 12
3143
3144#define GMBUS_NUM_PINS 13 /* including 0 */
3145#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
3146#define GMBUS_SW_CLR_INT (1<<31)
3147#define GMBUS_SW_RDY (1<<30)
3148#define GMBUS_ENT (1<<29) /* enable timeout */
3149#define GMBUS_CYCLE_NONE (0<<25)
3150#define GMBUS_CYCLE_WAIT (1<<25)
3151#define GMBUS_CYCLE_INDEX (2<<25)
3152#define GMBUS_CYCLE_STOP (4<<25)
3153#define GMBUS_BYTE_COUNT_SHIFT 16
3154#define GMBUS_BYTE_COUNT_MAX 256U
3155#define GMBUS_SLAVE_INDEX_SHIFT 8
3156#define GMBUS_SLAVE_ADDR_SHIFT 1
3157#define GMBUS_SLAVE_READ (1<<0)
3158#define GMBUS_SLAVE_WRITE (0<<0)
3159#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
3160#define GMBUS_INUSE (1<<15)
3161#define GMBUS_HW_WAIT_PHASE (1<<14)
3162#define GMBUS_STALL_TIMEOUT (1<<13)
3163#define GMBUS_INT (1<<12)
3164#define GMBUS_HW_RDY (1<<11)
3165#define GMBUS_SATOER (1<<10)
3166#define GMBUS_ACTIVE (1<<9)
3167#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
3168#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
3169#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
3170#define GMBUS_NAK_EN (1<<3)
3171#define GMBUS_IDLE_EN (1<<2)
3172#define GMBUS_HW_WAIT_EN (1<<1)
3173#define GMBUS_HW_RDY_EN (1<<0)
3174#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
3175#define GMBUS_2BYTE_INDEX_EN (1<<31)
3176
3177/*
3178 * Clock control & power management
3179 */
3180#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
3181#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
3182#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
3183#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3184
3185#define VGA0 _MMIO(0x6000)
3186#define VGA1 _MMIO(0x6004)
3187#define VGA_PD _MMIO(0x6010)
3188#define VGA0_PD_P2_DIV_4 (1 << 7)
3189#define VGA0_PD_P1_DIV_2 (1 << 5)
3190#define VGA0_PD_P1_SHIFT 0
3191#define VGA0_PD_P1_MASK (0x1f << 0)
3192#define VGA1_PD_P2_DIV_4 (1 << 15)
3193#define VGA1_PD_P1_DIV_2 (1 << 13)
3194#define VGA1_PD_P1_SHIFT 8
3195#define VGA1_PD_P1_MASK (0x1f << 8)
3196#define DPLL_VCO_ENABLE (1 << 31)
3197#define DPLL_SDVO_HIGH_SPEED (1 << 30)
3198#define DPLL_DVO_2X_MODE (1 << 30)
3199#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
3200#define DPLL_SYNCLOCK_ENABLE (1 << 29)
3201#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
3202#define DPLL_VGA_MODE_DIS (1 << 28)
3203#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
3204#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
3205#define DPLL_MODE_MASK (3 << 26)
3206#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
3207#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
3208#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
3209#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
3210#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
3211#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
3212#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
3213#define DPLL_LOCK_VLV (1<<15)
3214#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
3215#define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
3216#define DPLL_SSC_REF_CLK_CHV (1<<13)
3217#define DPLL_PORTC_READY_MASK (0xf << 4)
3218#define DPLL_PORTB_READY_MASK (0xf)
3219
3220#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
3221
3222/* Additional CHV pll/phy registers */
3223#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3224#define DPLL_PORTD_READY_MASK (0xf)
3225#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3226#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))
3227#define PHY_LDO_DELAY_0NS 0x0
3228#define PHY_LDO_DELAY_200NS 0x1
3229#define PHY_LDO_DELAY_600NS 0x2
3230#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
3231#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11))
3232#define PHY_CH_SU_PSR 0x1
3233#define PHY_CH_DEEP_PSR 0x7
3234#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
3235#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
3236#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3237#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
3238#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch))))
3239#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline))))
3240
3241/*
3242 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
3243 * this field (only one bit may be set).
3244 */
3245#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
3246#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
3247#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
3248/* i830, required in DVO non-gang */
3249#define PLL_P2_DIVIDE_BY_4 (1 << 23)
3250#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
3251#define PLL_REF_INPUT_DREFCLK (0 << 13)
3252#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
3253#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
3254#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
3255#define PLL_REF_INPUT_MASK (3 << 13)
3256#define PLL_LOAD_PULSE_PHASE_SHIFT 9
3257/* Ironlake */
3258# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
3259# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
3260# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
3261# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
3262# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
3263
3264/*
3265 * Parallel to Serial Load Pulse phase selection.
3266 * Selects the phase for the 10X DPLL clock for the PCIe
3267 * digital display port. The range is 4 to 13; 10 or more
3268 * is just a flip delay. The default is 6
3269 */
3270#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
3271#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
3272/*
3273 * SDVO multiplier for 945G/GM. Not used on 965.
3274 */
3275#define SDVO_MULTIPLIER_MASK 0x000000ff
3276#define SDVO_MULTIPLIER_SHIFT_HIRES 4
3277#define SDVO_MULTIPLIER_SHIFT_VGA 0
3278
3279#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
3280#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
3281#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
3282#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
3283
3284/*
3285 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
3286 *
3287 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
3288 */
3289#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
3290#define DPLL_MD_UDI_DIVIDER_SHIFT 24
3291/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
3292#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
3293#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
3294/*
3295 * SDVO/UDI pixel multiplier.
3296 *
3297 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
3298 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3299 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
3300 * dummy bytes in the datastream at an increased clock rate, with both sides of
3301 * the link knowing how many bytes are fill.
3302 *
3303 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
3304 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
3305 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
3306 * through an SDVO command.
3307 *
3308 * This register field has values of multiplication factor minus 1, with
3309 * a maximum multiplier of 5 for SDVO.
3310 */
3311#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
3312#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
3313/*
3314 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
3315 * This best be set to the default value (3) or the CRT won't work. No,
3316 * I don't entirely understand what this does...
3317 */
3318#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
3319#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
3320
3321#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3322
3323#define _FPA0 0x6040
3324#define _FPA1 0x6044
3325#define _FPB0 0x6048
3326#define _FPB1 0x604c
3327#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
3328#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
3329#define FP_N_DIV_MASK 0x003f0000
3330#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
3331#define FP_N_DIV_SHIFT 16
3332#define FP_M1_DIV_MASK 0x00003f00
3333#define FP_M1_DIV_SHIFT 8
3334#define FP_M2_DIV_MASK 0x0000003f
3335#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
3336#define FP_M2_DIV_SHIFT 0
3337#define DPLL_TEST _MMIO(0x606c)
3338#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
3339#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
3340#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
3341#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
3342#define DPLLB_TEST_N_BYPASS (1 << 19)
3343#define DPLLB_TEST_M_BYPASS (1 << 18)
3344#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
3345#define DPLLA_TEST_N_BYPASS (1 << 3)
3346#define DPLLA_TEST_M_BYPASS (1 << 2)
3347#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
3348#define D_STATE _MMIO(0x6104)
3349#define DSTATE_GFX_RESET_I830 (1<<6)
3350#define DSTATE_PLL_D3_OFF (1<<3)
3351#define DSTATE_GFX_CLOCK_GATING (1<<1)
3352#define DSTATE_DOT_CLOCK_GATING (1<<0)
3353#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
3354# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
3355# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
3356# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
3357# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
3358# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
3359# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
3360# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
3361# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
3362# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
3363# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
3364# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
3365# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
3366# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
3367# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
3368# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
3369# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
3370# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
3371# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
3372# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
3373# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
3374# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
3375# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
3376# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
3377# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
3378# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
3379# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
3380# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
3381# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
3382# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
3383/*
3384 * This bit must be set on the 830 to prevent hangs when turning off the
3385 * overlay scaler.
3386 */
3387# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
3388# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
3389# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
3390# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
3391# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
3392
3393#define RENCLK_GATE_D1 _MMIO(0x6204)
3394# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
3395# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
3396# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
3397# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
3398# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
3399# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
3400# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
3401# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
3402# define MAG_CLOCK_GATE_DISABLE (1 << 5)
3403/* This bit must be unset on 855,865 */
3404# define MECI_CLOCK_GATE_DISABLE (1 << 4)
3405# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
3406# define MEC_CLOCK_GATE_DISABLE (1 << 2)
3407# define MECO_CLOCK_GATE_DISABLE (1 << 1)
3408/* This bit must be set on 855,865. */
3409# define SV_CLOCK_GATE_DISABLE (1 << 0)
3410# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
3411# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
3412# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
3413# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
3414# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
3415# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
3416# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
3417# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
3418# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
3419# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
3420# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
3421# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
3422# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
3423# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
3424# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
3425# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
3426# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
3427
3428# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
3429/* This bit must always be set on 965G/965GM */
3430# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
3431# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
3432# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
3433# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
3434# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
3435# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
3436/* This bit must always be set on 965G */
3437# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
3438# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
3439# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
3440# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
3441# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
3442# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
3443# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
3444# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
3445# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
3446# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
3447# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
3448# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
3449# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
3450# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
3451# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
3452# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
3453# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
3454# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
3455# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
3456
3457#define RENCLK_GATE_D2 _MMIO(0x6208)
3458#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
3459#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
3460#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
3461
3462#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
3463#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
3464
3465#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
3466#define DEUC _MMIO(0x6214) /* CRL only */
3467
3468#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3469#define FW_CSPWRDWNEN (1<<15)
3470
3471#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3472
3473#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3474#define CDCLK_FREQ_SHIFT 4
3475#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
3476#define CZCLK_FREQ_MASK 0xf
3477
3478#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3479#define PFI_CREDIT_63 (9 << 28) /* chv only */
3480#define PFI_CREDIT_31 (8 << 28) /* chv only */
3481#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
3482#define PFI_CREDIT_RESEND (1 << 27)
3483#define VGA_FAST_MODE_DISABLE (1 << 14)
3484
3485#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
3486
3487/*
3488 * Palette regs
3489 */
3490#define PALETTE_A_OFFSET 0xa000
3491#define PALETTE_B_OFFSET 0xa800
3492#define CHV_PALETTE_C_OFFSET 0xc000
3493#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
3494 dev_priv->info.display_mmio_offset + (i) * 4)
3495
3496/* MCH MMIO space */
3497
3498/*
3499 * MCHBAR mirror.
3500 *
3501 * This mirrors the MCHBAR MMIO space whose location is determined by
3502 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
3503 * every way. It is not accessible from the CP register read instructions.
3504 *
3505 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
3506 * just read.
3507 */
3508#define MCHBAR_MIRROR_BASE 0x10000
3509
3510#define MCHBAR_MIRROR_BASE_SNB 0x140000
3511
3512#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
3513#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
3514#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
3515#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
3516#define G4X_STOLEN_RESERVED_ENABLE (1 << 0)
3517
3518/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
3519#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
3520
3521/* 915-945 and GM965 MCH register controlling DRAM channel access */
3522#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
3523#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
3524#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
3525#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
3526#define DCC_ADDRESSING_MODE_MASK (3 << 0)
3527#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
3528#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
3529#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
3530#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
3531
3532/* Pineview MCH register contains DDR3 setting */
3533#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
3534#define CSHRDDR3CTL_DDR3 (1 << 2)
3535
3536/* 965 MCH register controlling DRAM channel configuration */
3537#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
3538#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
3539
3540/* snb MCH registers for reading the DRAM channel configuration */
3541#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
3542#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
3543#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
3544#define MAD_DIMM_ECC_MASK (0x3 << 24)
3545#define MAD_DIMM_ECC_OFF (0x0 << 24)
3546#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
3547#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
3548#define MAD_DIMM_ECC_ON (0x3 << 24)
3549#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
3550#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
3551#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
3552#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
3553#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
3554#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
3555#define MAD_DIMM_A_SELECT (0x1 << 16)
3556/* DIMM sizes are in multiples of 256mb. */
3557#define MAD_DIMM_B_SIZE_SHIFT 8
3558#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
3559#define MAD_DIMM_A_SIZE_SHIFT 0
3560#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
3561
3562/* snb MCH registers for priority tuning */
3563#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
3564#define MCH_SSKPD_WM0_MASK 0x3f
3565#define MCH_SSKPD_WM0_VAL 0xc
3566
3567#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
3568
3569/* Clocking configuration register */
3570#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
3571#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
3572#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
3573#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
3574#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
3575#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
3576#define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */
3577#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
3578/*
3579 * Note that on at least on ELK the below value is reported for both
3580 * 333 and 400 MHz BIOS FSB setting, but given that the gmch datasheet
3581 * lists only 200/266/333 MHz FSB as supported let's decode it as 333 MHz.
3582 */
3583#define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */
3584#define CLKCFG_FSB_MASK (7 << 0)
3585#define CLKCFG_MEM_533 (1 << 4)
3586#define CLKCFG_MEM_667 (2 << 4)
3587#define CLKCFG_MEM_800 (3 << 4)
3588#define CLKCFG_MEM_MASK (7 << 4)
3589
3590#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
3591#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
3592
3593#define TSC1 _MMIO(0x11001)
3594#define TSE (1<<0)
3595#define TR1 _MMIO(0x11006)
3596#define TSFS _MMIO(0x11020)
3597#define TSFS_SLOPE_MASK 0x0000ff00
3598#define TSFS_SLOPE_SHIFT 8
3599#define TSFS_INTR_MASK 0x000000ff
3600
3601#define CRSTANDVID _MMIO(0x11100)
3602#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
3603#define PXVFREQ_PX_MASK 0x7f000000
3604#define PXVFREQ_PX_SHIFT 24
3605#define VIDFREQ_BASE _MMIO(0x11110)
3606#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
3607#define VIDFREQ2 _MMIO(0x11114)
3608#define VIDFREQ3 _MMIO(0x11118)
3609#define VIDFREQ4 _MMIO(0x1111c)
3610#define VIDFREQ_P0_MASK 0x1f000000
3611#define VIDFREQ_P0_SHIFT 24
3612#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
3613#define VIDFREQ_P0_CSCLK_SHIFT 20
3614#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
3615#define VIDFREQ_P0_CRCLK_SHIFT 16
3616#define VIDFREQ_P1_MASK 0x00001f00
3617#define VIDFREQ_P1_SHIFT 8
3618#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
3619#define VIDFREQ_P1_CSCLK_SHIFT 4
3620#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
3621#define INTTOEXT_BASE_ILK _MMIO(0x11300)
3622#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
3623#define INTTOEXT_MAP3_SHIFT 24
3624#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
3625#define INTTOEXT_MAP2_SHIFT 16
3626#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
3627#define INTTOEXT_MAP1_SHIFT 8
3628#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
3629#define INTTOEXT_MAP0_SHIFT 0
3630#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
3631#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
3632#define MEMCTL_CMD_MASK 0xe000
3633#define MEMCTL_CMD_SHIFT 13
3634#define MEMCTL_CMD_RCLK_OFF 0
3635#define MEMCTL_CMD_RCLK_ON 1
3636#define MEMCTL_CMD_CHFREQ 2
3637#define MEMCTL_CMD_CHVID 3
3638#define MEMCTL_CMD_VMMOFF 4
3639#define MEMCTL_CMD_VMMON 5
3640#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
3641 when command complete */
3642#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
3643#define MEMCTL_FREQ_SHIFT 8
3644#define MEMCTL_SFCAVM (1<<7)
3645#define MEMCTL_TGT_VID_MASK 0x007f
3646#define MEMIHYST _MMIO(0x1117c)
3647#define MEMINTREN _MMIO(0x11180) /* 16 bits */
3648#define MEMINT_RSEXIT_EN (1<<8)
3649#define MEMINT_CX_SUPR_EN (1<<7)
3650#define MEMINT_CONT_BUSY_EN (1<<6)
3651#define MEMINT_AVG_BUSY_EN (1<<5)
3652#define MEMINT_EVAL_CHG_EN (1<<4)
3653#define MEMINT_MON_IDLE_EN (1<<3)
3654#define MEMINT_UP_EVAL_EN (1<<2)
3655#define MEMINT_DOWN_EVAL_EN (1<<1)
3656#define MEMINT_SW_CMD_EN (1<<0)
3657#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
3658#define MEM_RSEXIT_MASK 0xc000
3659#define MEM_RSEXIT_SHIFT 14
3660#define MEM_CONT_BUSY_MASK 0x3000
3661#define MEM_CONT_BUSY_SHIFT 12
3662#define MEM_AVG_BUSY_MASK 0x0c00
3663#define MEM_AVG_BUSY_SHIFT 10
3664#define MEM_EVAL_CHG_MASK 0x0300
3665#define MEM_EVAL_BUSY_SHIFT 8
3666#define MEM_MON_IDLE_MASK 0x00c0
3667#define MEM_MON_IDLE_SHIFT 6
3668#define MEM_UP_EVAL_MASK 0x0030
3669#define MEM_UP_EVAL_SHIFT 4
3670#define MEM_DOWN_EVAL_MASK 0x000c
3671#define MEM_DOWN_EVAL_SHIFT 2
3672#define MEM_SW_CMD_MASK 0x0003
3673#define MEM_INT_STEER_GFX 0
3674#define MEM_INT_STEER_CMR 1
3675#define MEM_INT_STEER_SMI 2
3676#define MEM_INT_STEER_SCI 3
3677#define MEMINTRSTS _MMIO(0x11184)
3678#define MEMINT_RSEXIT (1<<7)
3679#define MEMINT_CONT_BUSY (1<<6)
3680#define MEMINT_AVG_BUSY (1<<5)
3681#define MEMINT_EVAL_CHG (1<<4)
3682#define MEMINT_MON_IDLE (1<<3)
3683#define MEMINT_UP_EVAL (1<<2)
3684#define MEMINT_DOWN_EVAL (1<<1)
3685#define MEMINT_SW_CMD (1<<0)
3686#define MEMMODECTL _MMIO(0x11190)
3687#define MEMMODE_BOOST_EN (1<<31)
3688#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
3689#define MEMMODE_BOOST_FREQ_SHIFT 24
3690#define MEMMODE_IDLE_MODE_MASK 0x00030000
3691#define MEMMODE_IDLE_MODE_SHIFT 16
3692#define MEMMODE_IDLE_MODE_EVAL 0
3693#define MEMMODE_IDLE_MODE_CONT 1
3694#define MEMMODE_HWIDLE_EN (1<<15)
3695#define MEMMODE_SWMODE_EN (1<<14)
3696#define MEMMODE_RCLK_GATE (1<<13)
3697#define MEMMODE_HW_UPDATE (1<<12)
3698#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
3699#define MEMMODE_FSTART_SHIFT 8
3700#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
3701#define MEMMODE_FMAX_SHIFT 4
3702#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
3703#define RCBMAXAVG _MMIO(0x1119c)
3704#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
3705#define SWMEMCMD_RENDER_OFF (0 << 13)
3706#define SWMEMCMD_RENDER_ON (1 << 13)
3707#define SWMEMCMD_SWFREQ (2 << 13)
3708#define SWMEMCMD_TARVID (3 << 13)
3709#define SWMEMCMD_VRM_OFF (4 << 13)
3710#define SWMEMCMD_VRM_ON (5 << 13)
3711#define CMDSTS (1<<12)
3712#define SFCAVM (1<<11)
3713#define SWFREQ_MASK 0x0380 /* P0-7 */
3714#define SWFREQ_SHIFT 7
3715#define TARVID_MASK 0x001f
3716#define MEMSTAT_CTG _MMIO(0x111a0)
3717#define RCBMINAVG _MMIO(0x111a0)
3718#define RCUPEI _MMIO(0x111b0)
3719#define RCDNEI _MMIO(0x111b4)
3720#define RSTDBYCTL _MMIO(0x111b8)
3721#define RS1EN (1<<31)
3722#define RS2EN (1<<30)
3723#define RS3EN (1<<29)
3724#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
3725#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
3726#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
3727#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
3728#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
3729#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
3730#define RSX_STATUS_MASK (7<<20)
3731#define RSX_STATUS_ON (0<<20)
3732#define RSX_STATUS_RC1 (1<<20)
3733#define RSX_STATUS_RC1E (2<<20)
3734#define RSX_STATUS_RS1 (3<<20)
3735#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
3736#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
3737#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
3738#define RSX_STATUS_RSVD2 (7<<20)
3739#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
3740#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
3741#define JRSC (1<<17) /* rsx coupled to cpu c-state */
3742#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
3743#define RS1CONTSAV_MASK (3<<14)
3744#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
3745#define RS1CONTSAV_RSVD (1<<14)
3746#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
3747#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
3748#define NORMSLEXLAT_MASK (3<<12)
3749#define SLOW_RS123 (0<<12)
3750#define SLOW_RS23 (1<<12)
3751#define SLOW_RS3 (2<<12)
3752#define NORMAL_RS123 (3<<12)
3753#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
3754#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
3755#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
3756#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
3757#define RS_CSTATE_MASK (3<<4)
3758#define RS_CSTATE_C367_RS1 (0<<4)
3759#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
3760#define RS_CSTATE_RSVD (2<<4)
3761#define RS_CSTATE_C367_RS2 (3<<4)
3762#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
3763#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
3764#define VIDCTL _MMIO(0x111c0)
3765#define VIDSTS _MMIO(0x111c8)
3766#define VIDSTART _MMIO(0x111cc) /* 8 bits */
3767#define MEMSTAT_ILK _MMIO(0x111f8)
3768#define MEMSTAT_VID_MASK 0x7f00
3769#define MEMSTAT_VID_SHIFT 8
3770#define MEMSTAT_PSTATE_MASK 0x00f8
3771#define MEMSTAT_PSTATE_SHIFT 3
3772#define MEMSTAT_MON_ACTV (1<<2)
3773#define MEMSTAT_SRC_CTL_MASK 0x0003
3774#define MEMSTAT_SRC_CTL_CORE 0
3775#define MEMSTAT_SRC_CTL_TRB 1
3776#define MEMSTAT_SRC_CTL_THM 2
3777#define MEMSTAT_SRC_CTL_STDBY 3
3778#define RCPREVBSYTUPAVG _MMIO(0x113b8)
3779#define RCPREVBSYTDNAVG _MMIO(0x113bc)
3780#define PMMISC _MMIO(0x11214)
3781#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
3782#define SDEW _MMIO(0x1124c)
3783#define CSIEW0 _MMIO(0x11250)
3784#define CSIEW1 _MMIO(0x11254)
3785#define CSIEW2 _MMIO(0x11258)
3786#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
3787#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
3788#define MCHAFE _MMIO(0x112c0)
3789#define CSIEC _MMIO(0x112e0)
3790#define DMIEC _MMIO(0x112e4)
3791#define DDREC _MMIO(0x112e8)
3792#define PEG0EC _MMIO(0x112ec)
3793#define PEG1EC _MMIO(0x112f0)
3794#define GFXEC _MMIO(0x112f4)
3795#define RPPREVBSYTUPAVG _MMIO(0x113b8)
3796#define RPPREVBSYTDNAVG _MMIO(0x113bc)
3797#define ECR _MMIO(0x11600)
3798#define ECR_GPFE (1<<31)
3799#define ECR_IMONE (1<<30)
3800#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
3801#define OGW0 _MMIO(0x11608)
3802#define OGW1 _MMIO(0x1160c)
3803#define EG0 _MMIO(0x11610)
3804#define EG1 _MMIO(0x11614)
3805#define EG2 _MMIO(0x11618)
3806#define EG3 _MMIO(0x1161c)
3807#define EG4 _MMIO(0x11620)
3808#define EG5 _MMIO(0x11624)
3809#define EG6 _MMIO(0x11628)
3810#define EG7 _MMIO(0x1162c)
3811#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
3812#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
3813#define LCFUSE02 _MMIO(0x116c0)
3814#define LCFUSE_HIV_MASK 0x000000ff
3815#define CSIPLL0 _MMIO(0x12c10)
3816#define DDRMPLL1 _MMIO(0X12c20)
3817#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
3818
3819#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
3820#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
3821
3822#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
3823#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
3824#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
3825#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
3826#define BXT_RP_STATE_CAP _MMIO(0x138170)
3827
3828/*
3829 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
3830 * 8300) freezing up around GPU hangs. Looks as if even
3831 * scheduling/timer interrupts start misbehaving if the RPS
3832 * EI/thresholds are "bad", leading to a very sluggish or even
3833 * frozen machine.
3834 */
3835#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
3836#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
3837#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
3838#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
3839 (IS_GEN9_LP(dev_priv) ? \
3840 INTERVAL_0_833_US(us) : \
3841 INTERVAL_1_33_US(us)) : \
3842 INTERVAL_1_28_US(us))
3843
3844#define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
3845#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
3846#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
3847#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
3848 (IS_GEN9_LP(dev_priv) ? \
3849 INTERVAL_0_833_TO_US(interval) : \
3850 INTERVAL_1_33_TO_US(interval)) : \
3851 INTERVAL_1_28_TO_US(interval))
3852
3853/*
3854 * Logical Context regs
3855 */
3856#define CCID _MMIO(0x2180)
3857#define CCID_EN BIT(0)
3858#define CCID_EXTENDED_STATE_RESTORE BIT(2)
3859#define CCID_EXTENDED_STATE_SAVE BIT(3)
3860/*
3861 * Notes on SNB/IVB/VLV context size:
3862 * - Power context is saved elsewhere (LLC or stolen)
3863 * - Ring/execlist context is saved on SNB, not on IVB
3864 * - Extended context size already includes render context size
3865 * - We always need to follow the extended context size.
3866 * SNB BSpec has comments indicating that we should use the
3867 * render context size instead if execlists are disabled, but
3868 * based on empirical testing that's just nonsense.
3869 * - Pipelined/VF state is saved on SNB/IVB respectively
3870 * - GT1 size just indicates how much of render context
3871 * doesn't need saving on GT1
3872 */
3873#define CXT_SIZE _MMIO(0x21a0)
3874#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
3875#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
3876#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
3877#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
3878#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
3879#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
3880 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
3881 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
3882#define GEN7_CXT_SIZE _MMIO(0x21a8)
3883#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
3884#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
3885#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
3886#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
3887#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
3888#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
3889#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
3890 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
3891
3892enum {
3893 INTEL_ADVANCED_CONTEXT = 0,
3894 INTEL_LEGACY_32B_CONTEXT,
3895 INTEL_ADVANCED_AD_CONTEXT,
3896 INTEL_LEGACY_64B_CONTEXT
3897};
3898
3899enum {
3900 FAULT_AND_HANG = 0,
3901 FAULT_AND_HALT, /* Debug only */
3902 FAULT_AND_STREAM,
3903 FAULT_AND_CONTINUE /* Unsupported */
3904};
3905
3906#define GEN8_CTX_VALID (1<<0)
3907#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
3908#define GEN8_CTX_FORCE_RESTORE (1<<2)
3909#define GEN8_CTX_L3LLC_COHERENT (1<<5)
3910#define GEN8_CTX_PRIVILEGE (1<<8)
3911#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
3912
3913#define GEN8_CTX_ID_SHIFT 32
3914#define GEN8_CTX_ID_WIDTH 21
3915#define GEN11_SW_CTX_ID_SHIFT 37
3916#define GEN11_SW_CTX_ID_WIDTH 11
3917#define GEN11_ENGINE_CLASS_SHIFT 61
3918#define GEN11_ENGINE_CLASS_WIDTH 3
3919#define GEN11_ENGINE_INSTANCE_SHIFT 48
3920#define GEN11_ENGINE_INSTANCE_WIDTH 6
3921
3922#define CHV_CLK_CTL1 _MMIO(0x101100)
3923#define VLV_CLK_CTL2 _MMIO(0x101104)
3924#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
3925
3926/*
3927 * Overlay regs
3928 */
3929
3930#define OVADD _MMIO(0x30000)
3931#define DOVSTA _MMIO(0x30008)
3932#define OC_BUF (0x3<<20)
3933#define OGAMC5 _MMIO(0x30010)
3934#define OGAMC4 _MMIO(0x30014)
3935#define OGAMC3 _MMIO(0x30018)
3936#define OGAMC2 _MMIO(0x3001c)
3937#define OGAMC1 _MMIO(0x30020)
3938#define OGAMC0 _MMIO(0x30024)
3939
3940/*
3941 * GEN9 clock gating regs
3942 */
3943#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
3944#define DARBF_GATING_DIS (1 << 27)
3945#define PWM2_GATING_DIS (1 << 14)
3946#define PWM1_GATING_DIS (1 << 13)
3947
3948#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
3949#define BXT_GMBUS_GATING_DIS (1 << 14)
3950
3951#define _CLKGATE_DIS_PSL_A 0x46520
3952#define _CLKGATE_DIS_PSL_B 0x46524
3953#define _CLKGATE_DIS_PSL_C 0x46528
3954#define DPF_GATING_DIS (1 << 10)
3955#define DPF_RAM_GATING_DIS (1 << 9)
3956#define DPFR_GATING_DIS (1 << 8)
3957
3958#define CLKGATE_DIS_PSL(pipe) \
3959 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
3960
3961/*
3962 * GEN10 clock gating regs
3963 */
3964#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
3965#define SARBUNIT_CLKGATE_DIS (1 << 5)
3966#define RCCUNIT_CLKGATE_DIS (1 << 7)
3967
3968#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
3969#define GWUNIT_CLKGATE_DIS (1 << 16)
3970
3971#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434)
3972#define VFUNIT_CLKGATE_DIS (1 << 20)
3973
3974/*
3975 * Display engine regs
3976 */
3977
3978/* Pipe A CRC regs */
3979#define _PIPE_CRC_CTL_A 0x60050
3980#define PIPE_CRC_ENABLE (1 << 31)
3981/* ivb+ source selection */
3982#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3983#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3984#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
3985/* ilk+ source selection */
3986#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3987#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3988#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
3989/* embedded DP port on the north display block, reserved on ivb */
3990#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
3991#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
3992/* vlv source selection */
3993#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
3994#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
3995#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
3996/* with DP port the pipe source is invalid */
3997#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
3998#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
3999#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
4000/* gen3+ source selection */
4001#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
4002#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
4003#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
4004/* with DP/TV port the pipe source is invalid */
4005#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
4006#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
4007#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
4008#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
4009#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
4010/* gen2 doesn't have source selection bits */
4011#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
4012
4013#define _PIPE_CRC_RES_1_A_IVB 0x60064
4014#define _PIPE_CRC_RES_2_A_IVB 0x60068
4015#define _PIPE_CRC_RES_3_A_IVB 0x6006c
4016#define _PIPE_CRC_RES_4_A_IVB 0x60070
4017#define _PIPE_CRC_RES_5_A_IVB 0x60074
4018
4019#define _PIPE_CRC_RES_RED_A 0x60060
4020#define _PIPE_CRC_RES_GREEN_A 0x60064
4021#define _PIPE_CRC_RES_BLUE_A 0x60068
4022#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
4023#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
4024
4025/* Pipe B CRC regs */
4026#define _PIPE_CRC_RES_1_B_IVB 0x61064
4027#define _PIPE_CRC_RES_2_B_IVB 0x61068
4028#define _PIPE_CRC_RES_3_B_IVB 0x6106c
4029#define _PIPE_CRC_RES_4_B_IVB 0x61070
4030#define _PIPE_CRC_RES_5_B_IVB 0x61074
4031
4032#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
4033#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
4034#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
4035#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
4036#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
4037#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
4038
4039#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
4040#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
4041#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
4042#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
4043#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
4044
4045/* Pipe A timing regs */
4046#define _HTOTAL_A 0x60000
4047#define _HBLANK_A 0x60004
4048#define _HSYNC_A 0x60008
4049#define _VTOTAL_A 0x6000c
4050#define _VBLANK_A 0x60010
4051#define _VSYNC_A 0x60014
4052#define _PIPEASRC 0x6001c
4053#define _BCLRPAT_A 0x60020
4054#define _VSYNCSHIFT_A 0x60028
4055#define _PIPE_MULT_A 0x6002c
4056
4057/* Pipe B timing regs */
4058#define _HTOTAL_B 0x61000
4059#define _HBLANK_B 0x61004
4060#define _HSYNC_B 0x61008
4061#define _VTOTAL_B 0x6100c
4062#define _VBLANK_B 0x61010
4063#define _VSYNC_B 0x61014
4064#define _PIPEBSRC 0x6101c
4065#define _BCLRPAT_B 0x61020
4066#define _VSYNCSHIFT_B 0x61028
4067#define _PIPE_MULT_B 0x6102c
4068
4069#define TRANSCODER_A_OFFSET 0x60000
4070#define TRANSCODER_B_OFFSET 0x61000
4071#define TRANSCODER_C_OFFSET 0x62000
4072#define CHV_TRANSCODER_C_OFFSET 0x63000
4073#define TRANSCODER_EDP_OFFSET 0x6f000
4074
4075#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
4076 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
4077 dev_priv->info.display_mmio_offset)
4078
4079#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
4080#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
4081#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
4082#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
4083#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
4084#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
4085#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
4086#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
4087#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
4088#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
4089
4090/* VLV eDP PSR registers */
4091#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
4092#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
4093#define VLV_EDP_PSR_ENABLE (1<<0)
4094#define VLV_EDP_PSR_RESET (1<<1)
4095#define VLV_EDP_PSR_MODE_MASK (7<<2)
4096#define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
4097#define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
4098#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
4099#define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
4100#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
4101#define VLV_EDP_PSR_DBL_FRAME (1<<10)
4102#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
4103#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
4104#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
4105
4106#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
4107#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
4108#define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
4109#define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
4110#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
4111#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
4112
4113#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
4114#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
4115#define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
4116#define VLV_EDP_PSR_CURR_STATE_MASK 7
4117#define VLV_EDP_PSR_DISABLED (0<<0)
4118#define VLV_EDP_PSR_INACTIVE (1<<0)
4119#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
4120#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
4121#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
4122#define VLV_EDP_PSR_EXIT (5<<0)
4123#define VLV_EDP_PSR_IN_TRANS (1<<7)
4124#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
4125
4126/* HSW+ eDP PSR registers */
4127#define HSW_EDP_PSR_BASE 0x64800
4128#define BDW_EDP_PSR_BASE 0x6f800
4129#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
4130#define EDP_PSR_ENABLE (1<<31)
4131#define BDW_PSR_SINGLE_FRAME (1<<30)
4132#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */
4133#define EDP_PSR_LINK_STANDBY (1<<27)
4134#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
4135#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
4136#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
4137#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
4138#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
4139#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
4140#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
4141#define EDP_PSR_TP1_TP2_SEL (0<<11)
4142#define EDP_PSR_TP1_TP3_SEL (1<<11)
4143#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
4144#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
4145#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
4146#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
4147#define EDP_PSR_TP1_TIME_500us (0<<4)
4148#define EDP_PSR_TP1_TIME_100us (1<<4)
4149#define EDP_PSR_TP1_TIME_2500us (2<<4)
4150#define EDP_PSR_TP1_TIME_0us (3<<4)
4151#define EDP_PSR_IDLE_FRAME_SHIFT 0
4152
4153#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
4154#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
4155
4156#define EDP_PSR_STATUS _MMIO(dev_priv->psr_mmio_base + 0x40)
4157#define EDP_PSR_STATUS_STATE_MASK (7<<29)
4158#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
4159#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
4160#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
4161#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
4162#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
4163#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
4164#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
4165#define EDP_PSR_STATUS_LINK_MASK (3<<26)
4166#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
4167#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
4168#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
4169#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
4170#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
4171#define EDP_PSR_STATUS_COUNT_SHIFT 16
4172#define EDP_PSR_STATUS_COUNT_MASK 0xf
4173#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
4174#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
4175#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
4176#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
4177#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
4178#define EDP_PSR_STATUS_IDLE_MASK 0xf
4179
4180#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
4181#define EDP_PSR_PERF_CNT_MASK 0xffffff
4182
4183#define EDP_PSR_DEBUG _MMIO(dev_priv->psr_mmio_base + 0x60)
4184#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28)
4185#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
4186#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
4187#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
4188#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1<<16)
4189#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
4190
4191#define EDP_PSR2_CTL _MMIO(0x6f900)
4192#define EDP_PSR2_ENABLE (1<<31)
4193#define EDP_SU_TRACK_ENABLE (1<<30)
4194#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
4195#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
4196#define EDP_PSR2_TP2_TIME_500 (0<<8)
4197#define EDP_PSR2_TP2_TIME_100 (1<<8)
4198#define EDP_PSR2_TP2_TIME_2500 (2<<8)
4199#define EDP_PSR2_TP2_TIME_50 (3<<8)
4200#define EDP_PSR2_TP2_TIME_MASK (3<<8)
4201#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
4202#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
4203#define EDP_PSR2_IDLE_MASK 0xf
4204#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
4205
4206#define EDP_PSR2_STATUS _MMIO(0x6f940)
4207#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
4208#define EDP_PSR2_STATUS_STATE_SHIFT 28
4209
4210/* VGA port control */
4211#define ADPA _MMIO(0x61100)
4212#define PCH_ADPA _MMIO(0xe1100)
4213#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4214
4215#define ADPA_DAC_ENABLE (1<<31)
4216#define ADPA_DAC_DISABLE 0
4217#define ADPA_PIPE_SELECT_MASK (1<<30)
4218#define ADPA_PIPE_A_SELECT 0
4219#define ADPA_PIPE_B_SELECT (1<<30)
4220#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
4221/* CPT uses bits 29:30 for pch transcoder select */
4222#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
4223#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
4224#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
4225#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
4226#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
4227#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
4228#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
4229#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
4230#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
4231#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
4232#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
4233#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
4234#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
4235#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
4236#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
4237#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
4238#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
4239#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
4240#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
4241#define ADPA_USE_VGA_HVPOLARITY (1<<15)
4242#define ADPA_SETS_HVPOLARITY 0
4243#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
4244#define ADPA_VSYNC_CNTL_ENABLE 0
4245#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
4246#define ADPA_HSYNC_CNTL_ENABLE 0
4247#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
4248#define ADPA_VSYNC_ACTIVE_LOW 0
4249#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
4250#define ADPA_HSYNC_ACTIVE_LOW 0
4251#define ADPA_DPMS_MASK (~(3<<10))
4252#define ADPA_DPMS_ON (0<<10)
4253#define ADPA_DPMS_SUSPEND (1<<10)
4254#define ADPA_DPMS_STANDBY (2<<10)
4255#define ADPA_DPMS_OFF (3<<10)
4256
4257
4258/* Hotplug control (945+ only) */
4259#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
4260#define PORTB_HOTPLUG_INT_EN (1 << 29)
4261#define PORTC_HOTPLUG_INT_EN (1 << 28)
4262#define PORTD_HOTPLUG_INT_EN (1 << 27)
4263#define SDVOB_HOTPLUG_INT_EN (1 << 26)
4264#define SDVOC_HOTPLUG_INT_EN (1 << 25)
4265#define TV_HOTPLUG_INT_EN (1 << 18)
4266#define CRT_HOTPLUG_INT_EN (1 << 9)
4267#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
4268 PORTC_HOTPLUG_INT_EN | \
4269 PORTD_HOTPLUG_INT_EN | \
4270 SDVOC_HOTPLUG_INT_EN | \
4271 SDVOB_HOTPLUG_INT_EN | \
4272 CRT_HOTPLUG_INT_EN)
4273#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
4274#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
4275/* must use period 64 on GM45 according to docs */
4276#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
4277#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
4278#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
4279#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
4280#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
4281#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
4282#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
4283#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
4284#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
4285#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
4286#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
4287#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
4288
4289#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
4290/*
4291 * HDMI/DP bits are g4x+
4292 *
4293 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
4294 * Please check the detailed lore in the commit message for for experimental
4295 * evidence.
4296 */
4297/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
4298#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
4299#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
4300#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
4301/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
4302#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
4303#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
4304#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
4305#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
4306#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
4307#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
4308#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
4309#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
4310#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
4311#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
4312#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
4313#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
4314/* CRT/TV common between gen3+ */
4315#define CRT_HOTPLUG_INT_STATUS (1 << 11)
4316#define TV_HOTPLUG_INT_STATUS (1 << 10)
4317#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
4318#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
4319#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
4320#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
4321#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
4322#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
4323#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
4324#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
4325
4326/* SDVO is different across gen3/4 */
4327#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
4328#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
4329/*
4330 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
4331 * since reality corrobates that they're the same as on gen3. But keep these
4332 * bits here (and the comment!) to help any other lost wanderers back onto the
4333 * right tracks.
4334 */
4335#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
4336#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
4337#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
4338#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
4339#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
4340 SDVOB_HOTPLUG_INT_STATUS_G4X | \
4341 SDVOC_HOTPLUG_INT_STATUS_G4X | \
4342 PORTB_HOTPLUG_INT_STATUS | \
4343 PORTC_HOTPLUG_INT_STATUS | \
4344 PORTD_HOTPLUG_INT_STATUS)
4345
4346#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
4347 SDVOB_HOTPLUG_INT_STATUS_I915 | \
4348 SDVOC_HOTPLUG_INT_STATUS_I915 | \
4349 PORTB_HOTPLUG_INT_STATUS | \
4350 PORTC_HOTPLUG_INT_STATUS | \
4351 PORTD_HOTPLUG_INT_STATUS)
4352
4353/* SDVO and HDMI port control.
4354 * The same register may be used for SDVO or HDMI */
4355#define _GEN3_SDVOB 0x61140
4356#define _GEN3_SDVOC 0x61160
4357#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
4358#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
4359#define GEN4_HDMIB GEN3_SDVOB
4360#define GEN4_HDMIC GEN3_SDVOC
4361#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4362#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4363#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4364#define PCH_SDVOB _MMIO(0xe1140)
4365#define PCH_HDMIB PCH_SDVOB
4366#define PCH_HDMIC _MMIO(0xe1150)
4367#define PCH_HDMID _MMIO(0xe1160)
4368
4369#define PORT_DFT_I9XX _MMIO(0x61150)
4370#define DC_BALANCE_RESET (1 << 25)
4371#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
4372#define DC_BALANCE_RESET_VLV (1 << 31)
4373#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
4374#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
4375#define PIPE_B_SCRAMBLE_RESET (1 << 1)
4376#define PIPE_A_SCRAMBLE_RESET (1 << 0)
4377
4378/* Gen 3 SDVO bits: */
4379#define SDVO_ENABLE (1 << 31)
4380#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
4381#define SDVO_PIPE_SEL_MASK (1 << 30)
4382#define SDVO_PIPE_B_SELECT (1 << 30)
4383#define SDVO_STALL_SELECT (1 << 29)
4384#define SDVO_INTERRUPT_ENABLE (1 << 26)
4385/*
4386 * 915G/GM SDVO pixel multiplier.
4387 * Programmed value is multiplier - 1, up to 5x.
4388 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
4389 */
4390#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
4391#define SDVO_PORT_MULTIPLY_SHIFT 23
4392#define SDVO_PHASE_SELECT_MASK (15 << 19)
4393#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
4394#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
4395#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
4396#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
4397#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
4398#define SDVO_DETECTED (1 << 2)
4399/* Bits to be preserved when writing */
4400#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
4401 SDVO_INTERRUPT_ENABLE)
4402#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
4403
4404/* Gen 4 SDVO/HDMI bits: */
4405#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
4406#define SDVO_COLOR_FORMAT_MASK (7 << 26)
4407#define SDVO_ENCODING_SDVO (0 << 10)
4408#define SDVO_ENCODING_HDMI (2 << 10)
4409#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
4410#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
4411#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
4412#define SDVO_AUDIO_ENABLE (1 << 6)
4413/* VSYNC/HSYNC bits new with 965, default is to be set */
4414#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
4415#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
4416
4417/* Gen 5 (IBX) SDVO/HDMI bits: */
4418#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
4419#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
4420
4421/* Gen 6 (CPT) SDVO/HDMI bits: */
4422#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
4423#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
4424
4425/* CHV SDVO/HDMI bits: */
4426#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
4427#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
4428
4429
4430/* DVO port control */
4431#define _DVOA 0x61120
4432#define DVOA _MMIO(_DVOA)
4433#define _DVOB 0x61140
4434#define DVOB _MMIO(_DVOB)
4435#define _DVOC 0x61160
4436#define DVOC _MMIO(_DVOC)
4437#define DVO_ENABLE (1 << 31)
4438#define DVO_PIPE_B_SELECT (1 << 30)
4439#define DVO_PIPE_STALL_UNUSED (0 << 28)
4440#define DVO_PIPE_STALL (1 << 28)
4441#define DVO_PIPE_STALL_TV (2 << 28)
4442#define DVO_PIPE_STALL_MASK (3 << 28)
4443#define DVO_USE_VGA_SYNC (1 << 15)
4444#define DVO_DATA_ORDER_I740 (0 << 14)
4445#define DVO_DATA_ORDER_FP (1 << 14)
4446#define DVO_VSYNC_DISABLE (1 << 11)
4447#define DVO_HSYNC_DISABLE (1 << 10)
4448#define DVO_VSYNC_TRISTATE (1 << 9)
4449#define DVO_HSYNC_TRISTATE (1 << 8)
4450#define DVO_BORDER_ENABLE (1 << 7)
4451#define DVO_DATA_ORDER_GBRG (1 << 6)
4452#define DVO_DATA_ORDER_RGGB (0 << 6)
4453#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
4454#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
4455#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
4456#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
4457#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
4458#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
4459#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
4460#define DVO_PRESERVE_MASK (0x7<<24)
4461#define DVOA_SRCDIM _MMIO(0x61124)
4462#define DVOB_SRCDIM _MMIO(0x61144)
4463#define DVOC_SRCDIM _MMIO(0x61164)
4464#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
4465#define DVO_SRCDIM_VERTICAL_SHIFT 0
4466
4467/* LVDS port control */
4468#define LVDS _MMIO(0x61180)
4469/*
4470 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
4471 * the DPLL semantics change when the LVDS is assigned to that pipe.
4472 */
4473#define LVDS_PORT_EN (1 << 31)
4474/* Selects pipe B for LVDS data. Must be set on pre-965. */
4475#define LVDS_PIPEB_SELECT (1 << 30)
4476#define LVDS_PIPE_MASK (1 << 30)
4477#define LVDS_PIPE(pipe) ((pipe) << 30)
4478/* LVDS dithering flag on 965/g4x platform */
4479#define LVDS_ENABLE_DITHER (1 << 25)
4480/* LVDS sync polarity flags. Set to invert (i.e. negative) */
4481#define LVDS_VSYNC_POLARITY (1 << 21)
4482#define LVDS_HSYNC_POLARITY (1 << 20)
4483
4484/* Enable border for unscaled (or aspect-scaled) display */
4485#define LVDS_BORDER_ENABLE (1 << 15)
4486/*
4487 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
4488 * pixel.
4489 */
4490#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
4491#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
4492#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
4493/*
4494 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
4495 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
4496 * on.
4497 */
4498#define LVDS_A3_POWER_MASK (3 << 6)
4499#define LVDS_A3_POWER_DOWN (0 << 6)
4500#define LVDS_A3_POWER_UP (3 << 6)
4501/*
4502 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
4503 * is set.
4504 */
4505#define LVDS_CLKB_POWER_MASK (3 << 4)
4506#define LVDS_CLKB_POWER_DOWN (0 << 4)
4507#define LVDS_CLKB_POWER_UP (3 << 4)
4508/*
4509 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
4510 * setting for whether we are in dual-channel mode. The B3 pair will
4511 * additionally only be powered up when LVDS_A3_POWER_UP is set.
4512 */
4513#define LVDS_B0B3_POWER_MASK (3 << 2)
4514#define LVDS_B0B3_POWER_DOWN (0 << 2)
4515#define LVDS_B0B3_POWER_UP (3 << 2)
4516
4517/* Video Data Island Packet control */
4518#define VIDEO_DIP_DATA _MMIO(0x61178)
4519/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
4520 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
4521 * of the infoframe structure specified by CEA-861. */
4522#define VIDEO_DIP_DATA_SIZE 32
4523#define VIDEO_DIP_VSC_DATA_SIZE 36
4524#define VIDEO_DIP_CTL _MMIO(0x61170)
4525/* Pre HSW: */
4526#define VIDEO_DIP_ENABLE (1 << 31)
4527#define VIDEO_DIP_PORT(port) ((port) << 29)
4528#define VIDEO_DIP_PORT_MASK (3 << 29)
4529#define VIDEO_DIP_ENABLE_GCP (1 << 25)
4530#define VIDEO_DIP_ENABLE_AVI (1 << 21)
4531#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
4532#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
4533#define VIDEO_DIP_ENABLE_SPD (8 << 21)
4534#define VIDEO_DIP_SELECT_AVI (0 << 19)
4535#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
4536#define VIDEO_DIP_SELECT_SPD (3 << 19)
4537#define VIDEO_DIP_SELECT_MASK (3 << 19)
4538#define VIDEO_DIP_FREQ_ONCE (0 << 16)
4539#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
4540#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
4541#define VIDEO_DIP_FREQ_MASK (3 << 16)
4542/* HSW and later: */
4543#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
4544#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
4545#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
4546#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
4547#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
4548#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
4549
4550/* Panel power sequencing */
4551#define PPS_BASE 0x61200
4552#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
4553#define PCH_PPS_BASE 0xC7200
4554
4555#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
4556 PPS_BASE + (reg) + \
4557 (pps_idx) * 0x100)
4558
4559#define _PP_STATUS 0x61200
4560#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
4561#define PP_ON (1 << 31)
4562/*
4563 * Indicates that all dependencies of the panel are on:
4564 *
4565 * - PLL enabled
4566 * - pipe enabled
4567 * - LVDS/DVOB/DVOC on
4568 */
4569#define PP_READY (1 << 30)
4570#define PP_SEQUENCE_NONE (0 << 28)
4571#define PP_SEQUENCE_POWER_UP (1 << 28)
4572#define PP_SEQUENCE_POWER_DOWN (2 << 28)
4573#define PP_SEQUENCE_MASK (3 << 28)
4574#define PP_SEQUENCE_SHIFT 28
4575#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
4576#define PP_SEQUENCE_STATE_MASK 0x0000000f
4577#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
4578#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
4579#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
4580#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
4581#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
4582#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
4583#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
4584#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
4585#define PP_SEQUENCE_STATE_RESET (0xf << 0)
4586
4587#define _PP_CONTROL 0x61204
4588#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
4589#define PANEL_UNLOCK_REGS (0xabcd << 16)
4590#define PANEL_UNLOCK_MASK (0xffff << 16)
4591#define BXT_POWER_CYCLE_DELAY_MASK 0x1f0
4592#define BXT_POWER_CYCLE_DELAY_SHIFT 4
4593#define EDP_FORCE_VDD (1 << 3)
4594#define EDP_BLC_ENABLE (1 << 2)
4595#define PANEL_POWER_RESET (1 << 1)
4596#define PANEL_POWER_OFF (0 << 0)
4597#define PANEL_POWER_ON (1 << 0)
4598
4599#define _PP_ON_DELAYS 0x61208
4600#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS)
4601#define PANEL_PORT_SELECT_SHIFT 30
4602#define PANEL_PORT_SELECT_MASK (3 << 30)
4603#define PANEL_PORT_SELECT_LVDS (0 << 30)
4604#define PANEL_PORT_SELECT_DPA (1 << 30)
4605#define PANEL_PORT_SELECT_DPC (2 << 30)
4606#define PANEL_PORT_SELECT_DPD (3 << 30)
4607#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
4608#define PANEL_POWER_UP_DELAY_MASK 0x1fff0000
4609#define PANEL_POWER_UP_DELAY_SHIFT 16
4610#define PANEL_LIGHT_ON_DELAY_MASK 0x1fff
4611#define PANEL_LIGHT_ON_DELAY_SHIFT 0
4612
4613#define _PP_OFF_DELAYS 0x6120C
4614#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
4615#define PANEL_POWER_DOWN_DELAY_MASK 0x1fff0000
4616#define PANEL_POWER_DOWN_DELAY_SHIFT 16
4617#define PANEL_LIGHT_OFF_DELAY_MASK 0x1fff
4618#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4619
4620#define _PP_DIVISOR 0x61210
4621#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR)
4622#define PP_REFERENCE_DIVIDER_MASK 0xffffff00
4623#define PP_REFERENCE_DIVIDER_SHIFT 8
4624#define PANEL_POWER_CYCLE_DELAY_MASK 0x1f
4625#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4626
4627/* Panel fitting */
4628#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
4629#define PFIT_ENABLE (1 << 31)
4630#define PFIT_PIPE_MASK (3 << 29)
4631#define PFIT_PIPE_SHIFT 29
4632#define VERT_INTERP_DISABLE (0 << 10)
4633#define VERT_INTERP_BILINEAR (1 << 10)
4634#define VERT_INTERP_MASK (3 << 10)
4635#define VERT_AUTO_SCALE (1 << 9)
4636#define HORIZ_INTERP_DISABLE (0 << 6)
4637#define HORIZ_INTERP_BILINEAR (1 << 6)
4638#define HORIZ_INTERP_MASK (3 << 6)
4639#define HORIZ_AUTO_SCALE (1 << 5)
4640#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
4641#define PFIT_FILTER_FUZZY (0 << 24)
4642#define PFIT_SCALING_AUTO (0 << 26)
4643#define PFIT_SCALING_PROGRAMMED (1 << 26)
4644#define PFIT_SCALING_PILLAR (2 << 26)
4645#define PFIT_SCALING_LETTER (3 << 26)
4646#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
4647/* Pre-965 */
4648#define PFIT_VERT_SCALE_SHIFT 20
4649#define PFIT_VERT_SCALE_MASK 0xfff00000
4650#define PFIT_HORIZ_SCALE_SHIFT 4
4651#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
4652/* 965+ */
4653#define PFIT_VERT_SCALE_SHIFT_965 16
4654#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
4655#define PFIT_HORIZ_SCALE_SHIFT_965 0
4656#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
4657
4658#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
4659
4660#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
4661#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
4662#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
4663 _VLV_BLC_PWM_CTL2_B)
4664
4665#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
4666#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
4667#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
4668 _VLV_BLC_PWM_CTL_B)
4669
4670#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
4671#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
4672#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
4673 _VLV_BLC_HIST_CTL_B)
4674
4675/* Backlight control */
4676#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
4677#define BLM_PWM_ENABLE (1 << 31)
4678#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
4679#define BLM_PIPE_SELECT (1 << 29)
4680#define BLM_PIPE_SELECT_IVB (3 << 29)
4681#define BLM_PIPE_A (0 << 29)
4682#define BLM_PIPE_B (1 << 29)
4683#define BLM_PIPE_C (2 << 29) /* ivb + */
4684#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
4685#define BLM_TRANSCODER_B BLM_PIPE_B
4686#define BLM_TRANSCODER_C BLM_PIPE_C
4687#define BLM_TRANSCODER_EDP (3 << 29)
4688#define BLM_PIPE(pipe) ((pipe) << 29)
4689#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
4690#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
4691#define BLM_PHASE_IN_ENABLE (1 << 25)
4692#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
4693#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
4694#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
4695#define BLM_PHASE_IN_COUNT_SHIFT (8)
4696#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
4697#define BLM_PHASE_IN_INCR_SHIFT (0)
4698#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
4699#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
4700/*
4701 * This is the most significant 15 bits of the number of backlight cycles in a
4702 * complete cycle of the modulated backlight control.
4703 *
4704 * The actual value is this field multiplied by two.
4705 */
4706#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
4707#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
4708#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
4709/*
4710 * This is the number of cycles out of the backlight modulation cycle for which
4711 * the backlight is on.
4712 *
4713 * This field must be no greater than the number of cycles in the complete
4714 * backlight modulation cycle.
4715 */
4716#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
4717#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
4718#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
4719#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
4720
4721#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
4722#define BLM_HISTOGRAM_ENABLE (1 << 31)
4723
4724/* New registers for PCH-split platforms. Safe where new bits show up, the
4725 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
4726#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
4727#define BLC_PWM_CPU_CTL _MMIO(0x48254)
4728
4729#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
4730
4731/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
4732 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
4733#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
4734#define BLM_PCH_PWM_ENABLE (1 << 31)
4735#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
4736#define BLM_PCH_POLARITY (1 << 29)
4737#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
4738
4739#define UTIL_PIN_CTL _MMIO(0x48400)
4740#define UTIL_PIN_ENABLE (1 << 31)
4741
4742#define UTIL_PIN_PIPE(x) ((x) << 29)
4743#define UTIL_PIN_PIPE_MASK (3 << 29)
4744#define UTIL_PIN_MODE_PWM (1 << 24)
4745#define UTIL_PIN_MODE_MASK (0xf << 24)
4746#define UTIL_PIN_POLARITY (1 << 22)
4747
4748/* BXT backlight register definition. */
4749#define _BXT_BLC_PWM_CTL1 0xC8250
4750#define BXT_BLC_PWM_ENABLE (1 << 31)
4751#define BXT_BLC_PWM_POLARITY (1 << 29)
4752#define _BXT_BLC_PWM_FREQ1 0xC8254
4753#define _BXT_BLC_PWM_DUTY1 0xC8258
4754
4755#define _BXT_BLC_PWM_CTL2 0xC8350
4756#define _BXT_BLC_PWM_FREQ2 0xC8354
4757#define _BXT_BLC_PWM_DUTY2 0xC8358
4758
4759#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
4760 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
4761#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
4762 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
4763#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
4764 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
4765
4766#define PCH_GTC_CTL _MMIO(0xe7000)
4767#define PCH_GTC_ENABLE (1 << 31)
4768
4769/* TV port control */
4770#define TV_CTL _MMIO(0x68000)
4771/* Enables the TV encoder */
4772# define TV_ENC_ENABLE (1 << 31)
4773/* Sources the TV encoder input from pipe B instead of A. */
4774# define TV_ENC_PIPEB_SELECT (1 << 30)
4775/* Outputs composite video (DAC A only) */
4776# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
4777/* Outputs SVideo video (DAC B/C) */
4778# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
4779/* Outputs Component video (DAC A/B/C) */
4780# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
4781/* Outputs Composite and SVideo (DAC A/B/C) */
4782# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
4783# define TV_TRILEVEL_SYNC (1 << 21)
4784/* Enables slow sync generation (945GM only) */
4785# define TV_SLOW_SYNC (1 << 20)
4786/* Selects 4x oversampling for 480i and 576p */
4787# define TV_OVERSAMPLE_4X (0 << 18)
4788/* Selects 2x oversampling for 720p and 1080i */
4789# define TV_OVERSAMPLE_2X (1 << 18)
4790/* Selects no oversampling for 1080p */
4791# define TV_OVERSAMPLE_NONE (2 << 18)
4792/* Selects 8x oversampling */
4793# define TV_OVERSAMPLE_8X (3 << 18)
4794/* Selects progressive mode rather than interlaced */
4795# define TV_PROGRESSIVE (1 << 17)
4796/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
4797# define TV_PAL_BURST (1 << 16)
4798/* Field for setting delay of Y compared to C */
4799# define TV_YC_SKEW_MASK (7 << 12)
4800/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
4801# define TV_ENC_SDP_FIX (1 << 11)
4802/*
4803 * Enables a fix for the 915GM only.
4804 *
4805 * Not sure what it does.
4806 */
4807# define TV_ENC_C0_FIX (1 << 10)
4808/* Bits that must be preserved by software */
4809# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
4810# define TV_FUSE_STATE_MASK (3 << 4)
4811/* Read-only state that reports all features enabled */
4812# define TV_FUSE_STATE_ENABLED (0 << 4)
4813/* Read-only state that reports that Macrovision is disabled in hardware*/
4814# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
4815/* Read-only state that reports that TV-out is disabled in hardware. */
4816# define TV_FUSE_STATE_DISABLED (2 << 4)
4817/* Normal operation */
4818# define TV_TEST_MODE_NORMAL (0 << 0)
4819/* Encoder test pattern 1 - combo pattern */
4820# define TV_TEST_MODE_PATTERN_1 (1 << 0)
4821/* Encoder test pattern 2 - full screen vertical 75% color bars */
4822# define TV_TEST_MODE_PATTERN_2 (2 << 0)
4823/* Encoder test pattern 3 - full screen horizontal 75% color bars */
4824# define TV_TEST_MODE_PATTERN_3 (3 << 0)
4825/* Encoder test pattern 4 - random noise */
4826# define TV_TEST_MODE_PATTERN_4 (4 << 0)
4827/* Encoder test pattern 5 - linear color ramps */
4828# define TV_TEST_MODE_PATTERN_5 (5 << 0)
4829/*
4830 * This test mode forces the DACs to 50% of full output.
4831 *
4832 * This is used for load detection in combination with TVDAC_SENSE_MASK
4833 */
4834# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
4835# define TV_TEST_MODE_MASK (7 << 0)
4836
4837#define TV_DAC _MMIO(0x68004)
4838# define TV_DAC_SAVE 0x00ffff00
4839/*
4840 * Reports that DAC state change logic has reported change (RO).
4841 *
4842 * This gets cleared when TV_DAC_STATE_EN is cleared
4843*/
4844# define TVDAC_STATE_CHG (1 << 31)
4845# define TVDAC_SENSE_MASK (7 << 28)
4846/* Reports that DAC A voltage is above the detect threshold */
4847# define TVDAC_A_SENSE (1 << 30)
4848/* Reports that DAC B voltage is above the detect threshold */
4849# define TVDAC_B_SENSE (1 << 29)
4850/* Reports that DAC C voltage is above the detect threshold */
4851# define TVDAC_C_SENSE (1 << 28)
4852/*
4853 * Enables DAC state detection logic, for load-based TV detection.
4854 *
4855 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
4856 * to off, for load detection to work.
4857 */
4858# define TVDAC_STATE_CHG_EN (1 << 27)
4859/* Sets the DAC A sense value to high */
4860# define TVDAC_A_SENSE_CTL (1 << 26)
4861/* Sets the DAC B sense value to high */
4862# define TVDAC_B_SENSE_CTL (1 << 25)
4863/* Sets the DAC C sense value to high */
4864# define TVDAC_C_SENSE_CTL (1 << 24)
4865/* Overrides the ENC_ENABLE and DAC voltage levels */
4866# define DAC_CTL_OVERRIDE (1 << 7)
4867/* Sets the slew rate. Must be preserved in software */
4868# define ENC_TVDAC_SLEW_FAST (1 << 6)
4869# define DAC_A_1_3_V (0 << 4)
4870# define DAC_A_1_1_V (1 << 4)
4871# define DAC_A_0_7_V (2 << 4)
4872# define DAC_A_MASK (3 << 4)
4873# define DAC_B_1_3_V (0 << 2)
4874# define DAC_B_1_1_V (1 << 2)
4875# define DAC_B_0_7_V (2 << 2)
4876# define DAC_B_MASK (3 << 2)
4877# define DAC_C_1_3_V (0 << 0)
4878# define DAC_C_1_1_V (1 << 0)
4879# define DAC_C_0_7_V (2 << 0)
4880# define DAC_C_MASK (3 << 0)
4881
4882/*
4883 * CSC coefficients are stored in a floating point format with 9 bits of
4884 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
4885 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
4886 * -1 (0x3) being the only legal negative value.
4887 */
4888#define TV_CSC_Y _MMIO(0x68010)
4889# define TV_RY_MASK 0x07ff0000
4890# define TV_RY_SHIFT 16
4891# define TV_GY_MASK 0x00000fff
4892# define TV_GY_SHIFT 0
4893
4894#define TV_CSC_Y2 _MMIO(0x68014)
4895# define TV_BY_MASK 0x07ff0000
4896# define TV_BY_SHIFT 16
4897/*
4898 * Y attenuation for component video.
4899 *
4900 * Stored in 1.9 fixed point.
4901 */
4902# define TV_AY_MASK 0x000003ff
4903# define TV_AY_SHIFT 0
4904
4905#define TV_CSC_U _MMIO(0x68018)
4906# define TV_RU_MASK 0x07ff0000
4907# define TV_RU_SHIFT 16
4908# define TV_GU_MASK 0x000007ff
4909# define TV_GU_SHIFT 0
4910
4911#define TV_CSC_U2 _MMIO(0x6801c)
4912# define TV_BU_MASK 0x07ff0000
4913# define TV_BU_SHIFT 16
4914/*
4915 * U attenuation for component video.
4916 *
4917 * Stored in 1.9 fixed point.
4918 */
4919# define TV_AU_MASK 0x000003ff
4920# define TV_AU_SHIFT 0
4921
4922#define TV_CSC_V _MMIO(0x68020)
4923# define TV_RV_MASK 0x0fff0000
4924# define TV_RV_SHIFT 16
4925# define TV_GV_MASK 0x000007ff
4926# define TV_GV_SHIFT 0
4927
4928#define TV_CSC_V2 _MMIO(0x68024)
4929# define TV_BV_MASK 0x07ff0000
4930# define TV_BV_SHIFT 16
4931/*
4932 * V attenuation for component video.
4933 *
4934 * Stored in 1.9 fixed point.
4935 */
4936# define TV_AV_MASK 0x000007ff
4937# define TV_AV_SHIFT 0
4938
4939#define TV_CLR_KNOBS _MMIO(0x68028)
4940/* 2s-complement brightness adjustment */
4941# define TV_BRIGHTNESS_MASK 0xff000000
4942# define TV_BRIGHTNESS_SHIFT 24
4943/* Contrast adjustment, as a 2.6 unsigned floating point number */
4944# define TV_CONTRAST_MASK 0x00ff0000
4945# define TV_CONTRAST_SHIFT 16
4946/* Saturation adjustment, as a 2.6 unsigned floating point number */
4947# define TV_SATURATION_MASK 0x0000ff00
4948# define TV_SATURATION_SHIFT 8
4949/* Hue adjustment, as an integer phase angle in degrees */
4950# define TV_HUE_MASK 0x000000ff
4951# define TV_HUE_SHIFT 0
4952
4953#define TV_CLR_LEVEL _MMIO(0x6802c)
4954/* Controls the DAC level for black */
4955# define TV_BLACK_LEVEL_MASK 0x01ff0000
4956# define TV_BLACK_LEVEL_SHIFT 16
4957/* Controls the DAC level for blanking */
4958# define TV_BLANK_LEVEL_MASK 0x000001ff
4959# define TV_BLANK_LEVEL_SHIFT 0
4960
4961#define TV_H_CTL_1 _MMIO(0x68030)
4962/* Number of pixels in the hsync. */
4963# define TV_HSYNC_END_MASK 0x1fff0000
4964# define TV_HSYNC_END_SHIFT 16
4965/* Total number of pixels minus one in the line (display and blanking). */
4966# define TV_HTOTAL_MASK 0x00001fff
4967# define TV_HTOTAL_SHIFT 0
4968
4969#define TV_H_CTL_2 _MMIO(0x68034)
4970/* Enables the colorburst (needed for non-component color) */
4971# define TV_BURST_ENA (1 << 31)
4972/* Offset of the colorburst from the start of hsync, in pixels minus one. */
4973# define TV_HBURST_START_SHIFT 16
4974# define TV_HBURST_START_MASK 0x1fff0000
4975/* Length of the colorburst */
4976# define TV_HBURST_LEN_SHIFT 0
4977# define TV_HBURST_LEN_MASK 0x0001fff
4978
4979#define TV_H_CTL_3 _MMIO(0x68038)
4980/* End of hblank, measured in pixels minus one from start of hsync */
4981# define TV_HBLANK_END_SHIFT 16
4982# define TV_HBLANK_END_MASK 0x1fff0000
4983/* Start of hblank, measured in pixels minus one from start of hsync */
4984# define TV_HBLANK_START_SHIFT 0
4985# define TV_HBLANK_START_MASK 0x0001fff
4986
4987#define TV_V_CTL_1 _MMIO(0x6803c)
4988/* XXX */
4989# define TV_NBR_END_SHIFT 16
4990# define TV_NBR_END_MASK 0x07ff0000
4991/* XXX */
4992# define TV_VI_END_F1_SHIFT 8
4993# define TV_VI_END_F1_MASK 0x00003f00
4994/* XXX */
4995# define TV_VI_END_F2_SHIFT 0
4996# define TV_VI_END_F2_MASK 0x0000003f
4997
4998#define TV_V_CTL_2 _MMIO(0x68040)
4999/* Length of vsync, in half lines */
5000# define TV_VSYNC_LEN_MASK 0x07ff0000
5001# define TV_VSYNC_LEN_SHIFT 16
5002/* Offset of the start of vsync in field 1, measured in one less than the
5003 * number of half lines.
5004 */
5005# define TV_VSYNC_START_F1_MASK 0x00007f00
5006# define TV_VSYNC_START_F1_SHIFT 8
5007/*
5008 * Offset of the start of vsync in field 2, measured in one less than the
5009 * number of half lines.
5010 */
5011# define TV_VSYNC_START_F2_MASK 0x0000007f
5012# define TV_VSYNC_START_F2_SHIFT 0
5013
5014#define TV_V_CTL_3 _MMIO(0x68044)
5015/* Enables generation of the equalization signal */
5016# define TV_EQUAL_ENA (1 << 31)
5017/* Length of vsync, in half lines */
5018# define TV_VEQ_LEN_MASK 0x007f0000
5019# define TV_VEQ_LEN_SHIFT 16
5020/* Offset of the start of equalization in field 1, measured in one less than
5021 * the number of half lines.
5022 */
5023# define TV_VEQ_START_F1_MASK 0x0007f00
5024# define TV_VEQ_START_F1_SHIFT 8
5025/*
5026 * Offset of the start of equalization in field 2, measured in one less than
5027 * the number of half lines.
5028 */
5029# define TV_VEQ_START_F2_MASK 0x000007f
5030# define TV_VEQ_START_F2_SHIFT 0
5031
5032#define TV_V_CTL_4 _MMIO(0x68048)
5033/*
5034 * Offset to start of vertical colorburst, measured in one less than the
5035 * number of lines from vertical start.
5036 */
5037# define TV_VBURST_START_F1_MASK 0x003f0000
5038# define TV_VBURST_START_F1_SHIFT 16
5039/*
5040 * Offset to the end of vertical colorburst, measured in one less than the
5041 * number of lines from the start of NBR.
5042 */
5043# define TV_VBURST_END_F1_MASK 0x000000ff
5044# define TV_VBURST_END_F1_SHIFT 0
5045
5046#define TV_V_CTL_5 _MMIO(0x6804c)
5047/*
5048 * Offset to start of vertical colorburst, measured in one less than the
5049 * number of lines from vertical start.
5050 */
5051# define TV_VBURST_START_F2_MASK 0x003f0000
5052# define TV_VBURST_START_F2_SHIFT 16
5053/*
5054 * Offset to the end of vertical colorburst, measured in one less than the
5055 * number of lines from the start of NBR.
5056 */
5057# define TV_VBURST_END_F2_MASK 0x000000ff
5058# define TV_VBURST_END_F2_SHIFT 0
5059
5060#define TV_V_CTL_6 _MMIO(0x68050)
5061/*
5062 * Offset to start of vertical colorburst, measured in one less than the
5063 * number of lines from vertical start.
5064 */
5065# define TV_VBURST_START_F3_MASK 0x003f0000
5066# define TV_VBURST_START_F3_SHIFT 16
5067/*
5068 * Offset to the end of vertical colorburst, measured in one less than the
5069 * number of lines from the start of NBR.
5070 */
5071# define TV_VBURST_END_F3_MASK 0x000000ff
5072# define TV_VBURST_END_F3_SHIFT 0
5073
5074#define TV_V_CTL_7 _MMIO(0x68054)
5075/*
5076 * Offset to start of vertical colorburst, measured in one less than the
5077 * number of lines from vertical start.
5078 */
5079# define TV_VBURST_START_F4_MASK 0x003f0000
5080# define TV_VBURST_START_F4_SHIFT 16
5081/*
5082 * Offset to the end of vertical colorburst, measured in one less than the
5083 * number of lines from the start of NBR.
5084 */
5085# define TV_VBURST_END_F4_MASK 0x000000ff
5086# define TV_VBURST_END_F4_SHIFT 0
5087
5088#define TV_SC_CTL_1 _MMIO(0x68060)
5089/* Turns on the first subcarrier phase generation DDA */
5090# define TV_SC_DDA1_EN (1 << 31)
5091/* Turns on the first subcarrier phase generation DDA */
5092# define TV_SC_DDA2_EN (1 << 30)
5093/* Turns on the first subcarrier phase generation DDA */
5094# define TV_SC_DDA3_EN (1 << 29)
5095/* Sets the subcarrier DDA to reset frequency every other field */
5096# define TV_SC_RESET_EVERY_2 (0 << 24)
5097/* Sets the subcarrier DDA to reset frequency every fourth field */
5098# define TV_SC_RESET_EVERY_4 (1 << 24)
5099/* Sets the subcarrier DDA to reset frequency every eighth field */
5100# define TV_SC_RESET_EVERY_8 (2 << 24)
5101/* Sets the subcarrier DDA to never reset the frequency */
5102# define TV_SC_RESET_NEVER (3 << 24)
5103/* Sets the peak amplitude of the colorburst.*/
5104# define TV_BURST_LEVEL_MASK 0x00ff0000
5105# define TV_BURST_LEVEL_SHIFT 16
5106/* Sets the increment of the first subcarrier phase generation DDA */
5107# define TV_SCDDA1_INC_MASK 0x00000fff
5108# define TV_SCDDA1_INC_SHIFT 0
5109
5110#define TV_SC_CTL_2 _MMIO(0x68064)
5111/* Sets the rollover for the second subcarrier phase generation DDA */
5112# define TV_SCDDA2_SIZE_MASK 0x7fff0000
5113# define TV_SCDDA2_SIZE_SHIFT 16
5114/* Sets the increent of the second subcarrier phase generation DDA */
5115# define TV_SCDDA2_INC_MASK 0x00007fff
5116# define TV_SCDDA2_INC_SHIFT 0
5117
5118#define TV_SC_CTL_3 _MMIO(0x68068)
5119/* Sets the rollover for the third subcarrier phase generation DDA */
5120# define TV_SCDDA3_SIZE_MASK 0x7fff0000
5121# define TV_SCDDA3_SIZE_SHIFT 16
5122/* Sets the increent of the third subcarrier phase generation DDA */
5123# define TV_SCDDA3_INC_MASK 0x00007fff
5124# define TV_SCDDA3_INC_SHIFT 0
5125
5126#define TV_WIN_POS _MMIO(0x68070)
5127/* X coordinate of the display from the start of horizontal active */
5128# define TV_XPOS_MASK 0x1fff0000
5129# define TV_XPOS_SHIFT 16
5130/* Y coordinate of the display from the start of vertical active (NBR) */
5131# define TV_YPOS_MASK 0x00000fff
5132# define TV_YPOS_SHIFT 0
5133
5134#define TV_WIN_SIZE _MMIO(0x68074)
5135/* Horizontal size of the display window, measured in pixels*/
5136# define TV_XSIZE_MASK 0x1fff0000
5137# define TV_XSIZE_SHIFT 16
5138/*
5139 * Vertical size of the display window, measured in pixels.
5140 *
5141 * Must be even for interlaced modes.
5142 */
5143# define TV_YSIZE_MASK 0x00000fff
5144# define TV_YSIZE_SHIFT 0
5145
5146#define TV_FILTER_CTL_1 _MMIO(0x68080)
5147/*
5148 * Enables automatic scaling calculation.
5149 *
5150 * If set, the rest of the registers are ignored, and the calculated values can
5151 * be read back from the register.
5152 */
5153# define TV_AUTO_SCALE (1 << 31)
5154/*
5155 * Disables the vertical filter.
5156 *
5157 * This is required on modes more than 1024 pixels wide */
5158# define TV_V_FILTER_BYPASS (1 << 29)
5159/* Enables adaptive vertical filtering */
5160# define TV_VADAPT (1 << 28)
5161# define TV_VADAPT_MODE_MASK (3 << 26)
5162/* Selects the least adaptive vertical filtering mode */
5163# define TV_VADAPT_MODE_LEAST (0 << 26)
5164/* Selects the moderately adaptive vertical filtering mode */
5165# define TV_VADAPT_MODE_MODERATE (1 << 26)
5166/* Selects the most adaptive vertical filtering mode */
5167# define TV_VADAPT_MODE_MOST (3 << 26)
5168/*
5169 * Sets the horizontal scaling factor.
5170 *
5171 * This should be the fractional part of the horizontal scaling factor divided
5172 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
5173 *
5174 * (src width - 1) / ((oversample * dest width) - 1)
5175 */
5176# define TV_HSCALE_FRAC_MASK 0x00003fff
5177# define TV_HSCALE_FRAC_SHIFT 0
5178
5179#define TV_FILTER_CTL_2 _MMIO(0x68084)
5180/*
5181 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5182 *
5183 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
5184 */
5185# define TV_VSCALE_INT_MASK 0x00038000
5186# define TV_VSCALE_INT_SHIFT 15
5187/*
5188 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5189 *
5190 * \sa TV_VSCALE_INT_MASK
5191 */
5192# define TV_VSCALE_FRAC_MASK 0x00007fff
5193# define TV_VSCALE_FRAC_SHIFT 0
5194
5195#define TV_FILTER_CTL_3 _MMIO(0x68088)
5196/*
5197 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
5198 *
5199 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
5200 *
5201 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5202 */
5203# define TV_VSCALE_IP_INT_MASK 0x00038000
5204# define TV_VSCALE_IP_INT_SHIFT 15
5205/*
5206 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
5207 *
5208 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
5209 *
5210 * \sa TV_VSCALE_IP_INT_MASK
5211 */
5212# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
5213# define TV_VSCALE_IP_FRAC_SHIFT 0
5214
5215#define TV_CC_CONTROL _MMIO(0x68090)
5216# define TV_CC_ENABLE (1 << 31)
5217/*
5218 * Specifies which field to send the CC data in.
5219 *
5220 * CC data is usually sent in field 0.
5221 */
5222# define TV_CC_FID_MASK (1 << 27)
5223# define TV_CC_FID_SHIFT 27
5224/* Sets the horizontal position of the CC data. Usually 135. */
5225# define TV_CC_HOFF_MASK 0x03ff0000
5226# define TV_CC_HOFF_SHIFT 16
5227/* Sets the vertical position of the CC data. Usually 21 */
5228# define TV_CC_LINE_MASK 0x0000003f
5229# define TV_CC_LINE_SHIFT 0
5230
5231#define TV_CC_DATA _MMIO(0x68094)
5232# define TV_CC_RDY (1 << 31)
5233/* Second word of CC data to be transmitted. */
5234# define TV_CC_DATA_2_MASK 0x007f0000
5235# define TV_CC_DATA_2_SHIFT 16
5236/* First word of CC data to be transmitted. */
5237# define TV_CC_DATA_1_MASK 0x0000007f
5238# define TV_CC_DATA_1_SHIFT 0
5239
5240#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
5241#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
5242#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
5243#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
5244
5245/* Display Port */
5246#define DP_A _MMIO(0x64000) /* eDP */
5247#define DP_B _MMIO(0x64100)
5248#define DP_C _MMIO(0x64200)
5249#define DP_D _MMIO(0x64300)
5250
5251#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5252#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5253#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5254
5255#define DP_PORT_EN (1 << 31)
5256#define DP_PIPEB_SELECT (1 << 30)
5257#define DP_PIPE_MASK (1 << 30)
5258#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
5259#define DP_PIPE_MASK_CHV (3 << 16)
5260
5261/* Link training mode - select a suitable mode for each stage */
5262#define DP_LINK_TRAIN_PAT_1 (0 << 28)
5263#define DP_LINK_TRAIN_PAT_2 (1 << 28)
5264#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
5265#define DP_LINK_TRAIN_OFF (3 << 28)
5266#define DP_LINK_TRAIN_MASK (3 << 28)
5267#define DP_LINK_TRAIN_SHIFT 28
5268#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
5269#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
5270
5271/* CPT Link training mode */
5272#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
5273#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
5274#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
5275#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
5276#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
5277#define DP_LINK_TRAIN_SHIFT_CPT 8
5278
5279/* Signal voltages. These are mostly controlled by the other end */
5280#define DP_VOLTAGE_0_4 (0 << 25)
5281#define DP_VOLTAGE_0_6 (1 << 25)
5282#define DP_VOLTAGE_0_8 (2 << 25)
5283#define DP_VOLTAGE_1_2 (3 << 25)
5284#define DP_VOLTAGE_MASK (7 << 25)
5285#define DP_VOLTAGE_SHIFT 25
5286
5287/* Signal pre-emphasis levels, like voltages, the other end tells us what
5288 * they want
5289 */
5290#define DP_PRE_EMPHASIS_0 (0 << 22)
5291#define DP_PRE_EMPHASIS_3_5 (1 << 22)
5292#define DP_PRE_EMPHASIS_6 (2 << 22)
5293#define DP_PRE_EMPHASIS_9_5 (3 << 22)
5294#define DP_PRE_EMPHASIS_MASK (7 << 22)
5295#define DP_PRE_EMPHASIS_SHIFT 22
5296
5297/* How many wires to use. I guess 3 was too hard */
5298#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
5299#define DP_PORT_WIDTH_MASK (7 << 19)
5300#define DP_PORT_WIDTH_SHIFT 19
5301
5302/* Mystic DPCD version 1.1 special mode */
5303#define DP_ENHANCED_FRAMING (1 << 18)
5304
5305/* eDP */
5306#define DP_PLL_FREQ_270MHZ (0 << 16)
5307#define DP_PLL_FREQ_162MHZ (1 << 16)
5308#define DP_PLL_FREQ_MASK (3 << 16)
5309
5310/* locked once port is enabled */
5311#define DP_PORT_REVERSAL (1 << 15)
5312
5313/* eDP */
5314#define DP_PLL_ENABLE (1 << 14)
5315
5316/* sends the clock on lane 15 of the PEG for debug */
5317#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
5318
5319#define DP_SCRAMBLING_DISABLE (1 << 12)
5320#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
5321
5322/* limit RGB values to avoid confusing TVs */
5323#define DP_COLOR_RANGE_16_235 (1 << 8)
5324
5325/* Turn on the audio link */
5326#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
5327
5328/* vs and hs sync polarity */
5329#define DP_SYNC_VS_HIGH (1 << 4)
5330#define DP_SYNC_HS_HIGH (1 << 3)
5331
5332/* A fantasy */
5333#define DP_DETECTED (1 << 2)
5334
5335/* The aux channel provides a way to talk to the
5336 * signal sink for DDC etc. Max packet size supported
5337 * is 20 bytes in each direction, hence the 5 fixed
5338 * data registers
5339 */
5340#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
5341#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
5342#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
5343#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
5344#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
5345#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
5346
5347#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
5348#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
5349#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
5350#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
5351#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
5352#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
5353
5354#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
5355#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
5356#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
5357#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
5358#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
5359#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
5360
5361#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
5362#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
5363#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
5364#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
5365#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
5366#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
5367
5368#define _DPF_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64510)
5369#define _DPF_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64514)
5370#define _DPF_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64518)
5371#define _DPF_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6451c)
5372#define _DPF_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64520)
5373#define _DPF_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64524)
5374
5375#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
5376#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5377
5378#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
5379#define DP_AUX_CH_CTL_DONE (1 << 30)
5380#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
5381#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
5382#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
5383#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
5384#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
5385#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */
5386#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
5387#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
5388#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
5389#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
5390#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
5391#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
5392#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
5393#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
5394#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
5395#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
5396#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
5397#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
5398#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
5399#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
5400#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
5401#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
5402#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
5403#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
5404#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
5405
5406/*
5407 * Computing GMCH M and N values for the Display Port link
5408 *
5409 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
5410 *
5411 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
5412 *
5413 * The GMCH value is used internally
5414 *
5415 * bytes_per_pixel is the number of bytes coming out of the plane,
5416 * which is after the LUTs, so we want the bytes for our color format.
5417 * For our current usage, this is always 3, one byte for R, G and B.
5418 */
5419#define _PIPEA_DATA_M_G4X 0x70050
5420#define _PIPEB_DATA_M_G4X 0x71050
5421
5422/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
5423#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
5424#define TU_SIZE_SHIFT 25
5425#define TU_SIZE_MASK (0x3f << 25)
5426
5427#define DATA_LINK_M_N_MASK (0xffffff)
5428#define DATA_LINK_N_MAX (0x800000)
5429
5430#define _PIPEA_DATA_N_G4X 0x70054
5431#define _PIPEB_DATA_N_G4X 0x71054
5432#define PIPE_GMCH_DATA_N_MASK (0xffffff)
5433
5434/*
5435 * Computing Link M and N values for the Display Port link
5436 *
5437 * Link M / N = pixel_clock / ls_clk
5438 *
5439 * (the DP spec calls pixel_clock the 'strm_clk')
5440 *
5441 * The Link value is transmitted in the Main Stream
5442 * Attributes and VB-ID.
5443 */
5444
5445#define _PIPEA_LINK_M_G4X 0x70060
5446#define _PIPEB_LINK_M_G4X 0x71060
5447#define PIPEA_DP_LINK_M_MASK (0xffffff)
5448
5449#define _PIPEA_LINK_N_G4X 0x70064
5450#define _PIPEB_LINK_N_G4X 0x71064
5451#define PIPEA_DP_LINK_N_MASK (0xffffff)
5452
5453#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
5454#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
5455#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
5456#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
5457
5458/* Display & cursor control */
5459
5460/* Pipe A */
5461#define _PIPEADSL 0x70000
5462#define DSL_LINEMASK_GEN2 0x00000fff
5463#define DSL_LINEMASK_GEN3 0x00001fff
5464#define _PIPEACONF 0x70008
5465#define PIPECONF_ENABLE (1<<31)
5466#define PIPECONF_DISABLE 0
5467#define PIPECONF_DOUBLE_WIDE (1<<30)
5468#define I965_PIPECONF_ACTIVE (1<<30)
5469#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
5470#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
5471#define PIPECONF_SINGLE_WIDE 0
5472#define PIPECONF_PIPE_UNLOCKED 0
5473#define PIPECONF_PIPE_LOCKED (1<<25)
5474#define PIPECONF_PALETTE 0
5475#define PIPECONF_GAMMA (1<<24)
5476#define PIPECONF_FORCE_BORDER (1<<25)
5477#define PIPECONF_INTERLACE_MASK (7 << 21)
5478#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
5479/* Note that pre-gen3 does not support interlaced display directly. Panel
5480 * fitting must be disabled on pre-ilk for interlaced. */
5481#define PIPECONF_PROGRESSIVE (0 << 21)
5482#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
5483#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
5484#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
5485#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
5486/* Ironlake and later have a complete new set of values for interlaced. PFIT
5487 * means panel fitter required, PF means progressive fetch, DBL means power
5488 * saving pixel doubling. */
5489#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
5490#define PIPECONF_INTERLACED_ILK (3 << 21)
5491#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
5492#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
5493#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
5494#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
5495#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
5496#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
5497#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
5498#define PIPECONF_BPC_MASK (0x7 << 5)
5499#define PIPECONF_8BPC (0<<5)
5500#define PIPECONF_10BPC (1<<5)
5501#define PIPECONF_6BPC (2<<5)
5502#define PIPECONF_12BPC (3<<5)
5503#define PIPECONF_DITHER_EN (1<<4)
5504#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
5505#define PIPECONF_DITHER_TYPE_SP (0<<2)
5506#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
5507#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
5508#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
5509#define _PIPEASTAT 0x70024
5510#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
5511#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
5512#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
5513#define PIPE_CRC_DONE_ENABLE (1UL<<28)
5514#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
5515#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
5516#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
5517#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
5518#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
5519#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
5520#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
5521#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
5522#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
5523#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
5524#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
5525#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
5526#define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
5527#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
5528#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
5529#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
5530#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
5531#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
5532#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
5533#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
5534#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
5535#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
5536#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
5537#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
5538#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
5539#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
5540#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
5541#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
5542#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
5543#define PIPE_DPST_EVENT_STATUS (1UL<<7)
5544#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
5545#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
5546#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
5547#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
5548#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
5549#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
5550#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
5551#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
5552#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
5553#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
5554#define PIPE_HBLANK_INT_STATUS (1UL<<0)
5555#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
5556
5557#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
5558#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
5559
5560#define PIPE_A_OFFSET 0x70000
5561#define PIPE_B_OFFSET 0x71000
5562#define PIPE_C_OFFSET 0x72000
5563#define CHV_PIPE_C_OFFSET 0x74000
5564/*
5565 * There's actually no pipe EDP. Some pipe registers have
5566 * simply shifted from the pipe to the transcoder, while
5567 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
5568 * to access such registers in transcoder EDP.
5569 */
5570#define PIPE_EDP_OFFSET 0x7f000
5571
5572#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
5573 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
5574 dev_priv->info.display_mmio_offset)
5575
5576#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
5577#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
5578#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
5579#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
5580#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
5581
5582#define _PIPE_MISC_A 0x70030
5583#define _PIPE_MISC_B 0x71030
5584#define PIPEMISC_YUV420_ENABLE (1<<27)
5585#define PIPEMISC_YUV420_MODE_FULL_BLEND (1<<26)
5586#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1<<11)
5587#define PIPEMISC_DITHER_BPC_MASK (7<<5)
5588#define PIPEMISC_DITHER_8_BPC (0<<5)
5589#define PIPEMISC_DITHER_10_BPC (1<<5)
5590#define PIPEMISC_DITHER_6_BPC (2<<5)
5591#define PIPEMISC_DITHER_12_BPC (3<<5)
5592#define PIPEMISC_DITHER_ENABLE (1<<4)
5593#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
5594#define PIPEMISC_DITHER_TYPE_SP (0<<2)
5595#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
5596
5597#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5598#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
5599#define PIPEB_HLINE_INT_EN (1<<28)
5600#define PIPEB_VBLANK_INT_EN (1<<27)
5601#define SPRITED_FLIP_DONE_INT_EN (1<<26)
5602#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
5603#define PLANEB_FLIP_DONE_INT_EN (1<<24)
5604#define PIPE_PSR_INT_EN (1<<22)
5605#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
5606#define PIPEA_HLINE_INT_EN (1<<20)
5607#define PIPEA_VBLANK_INT_EN (1<<19)
5608#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
5609#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
5610#define PLANEA_FLIPDONE_INT_EN (1<<16)
5611#define PIPEC_LINE_COMPARE_INT_EN (1<<13)
5612#define PIPEC_HLINE_INT_EN (1<<12)
5613#define PIPEC_VBLANK_INT_EN (1<<11)
5614#define SPRITEF_FLIPDONE_INT_EN (1<<10)
5615#define SPRITEE_FLIPDONE_INT_EN (1<<9)
5616#define PLANEC_FLIPDONE_INT_EN (1<<8)
5617
5618#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5619#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
5620#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
5621#define PLANEC_INVALID_GTT_INT_EN (1<<25)
5622#define CURSORC_INVALID_GTT_INT_EN (1<<24)
5623#define CURSORB_INVALID_GTT_INT_EN (1<<23)
5624#define CURSORA_INVALID_GTT_INT_EN (1<<22)
5625#define SPRITED_INVALID_GTT_INT_EN (1<<21)
5626#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
5627#define PLANEB_INVALID_GTT_INT_EN (1<<19)
5628#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
5629#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
5630#define PLANEA_INVALID_GTT_INT_EN (1<<16)
5631#define DPINVGTT_EN_MASK 0xff0000
5632#define DPINVGTT_EN_MASK_CHV 0xfff0000
5633#define SPRITEF_INVALID_GTT_STATUS (1<<11)
5634#define SPRITEE_INVALID_GTT_STATUS (1<<10)
5635#define PLANEC_INVALID_GTT_STATUS (1<<9)
5636#define CURSORC_INVALID_GTT_STATUS (1<<8)
5637#define CURSORB_INVALID_GTT_STATUS (1<<7)
5638#define CURSORA_INVALID_GTT_STATUS (1<<6)
5639#define SPRITED_INVALID_GTT_STATUS (1<<5)
5640#define SPRITEC_INVALID_GTT_STATUS (1<<4)
5641#define PLANEB_INVALID_GTT_STATUS (1<<3)
5642#define SPRITEB_INVALID_GTT_STATUS (1<<2)
5643#define SPRITEA_INVALID_GTT_STATUS (1<<1)
5644#define PLANEA_INVALID_GTT_STATUS (1<<0)
5645#define DPINVGTT_STATUS_MASK 0xff
5646#define DPINVGTT_STATUS_MASK_CHV 0xfff
5647
5648#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
5649#define DSPARB_CSTART_MASK (0x7f << 7)
5650#define DSPARB_CSTART_SHIFT 7
5651#define DSPARB_BSTART_MASK (0x7f)
5652#define DSPARB_BSTART_SHIFT 0
5653#define DSPARB_BEND_SHIFT 9 /* on 855 */
5654#define DSPARB_AEND_SHIFT 0
5655#define DSPARB_SPRITEA_SHIFT_VLV 0
5656#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
5657#define DSPARB_SPRITEB_SHIFT_VLV 8
5658#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
5659#define DSPARB_SPRITEC_SHIFT_VLV 16
5660#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
5661#define DSPARB_SPRITED_SHIFT_VLV 24
5662#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
5663#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5664#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
5665#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
5666#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
5667#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
5668#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
5669#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
5670#define DSPARB_SPRITED_HI_SHIFT_VLV 12
5671#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
5672#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
5673#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
5674#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
5675#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
5676#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5677#define DSPARB_SPRITEE_SHIFT_VLV 0
5678#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
5679#define DSPARB_SPRITEF_SHIFT_VLV 8
5680#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
5681
5682/* pnv/gen4/g4x/vlv/chv */
5683#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
5684#define DSPFW_SR_SHIFT 23
5685#define DSPFW_SR_MASK (0x1ff<<23)
5686#define DSPFW_CURSORB_SHIFT 16
5687#define DSPFW_CURSORB_MASK (0x3f<<16)
5688#define DSPFW_PLANEB_SHIFT 8
5689#define DSPFW_PLANEB_MASK (0x7f<<8)
5690#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
5691#define DSPFW_PLANEA_SHIFT 0
5692#define DSPFW_PLANEA_MASK (0x7f<<0)
5693#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
5694#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
5695#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
5696#define DSPFW_FBC_SR_SHIFT 28
5697#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
5698#define DSPFW_FBC_HPLL_SR_SHIFT 24
5699#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
5700#define DSPFW_SPRITEB_SHIFT (16)
5701#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
5702#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
5703#define DSPFW_CURSORA_SHIFT 8
5704#define DSPFW_CURSORA_MASK (0x3f<<8)
5705#define DSPFW_PLANEC_OLD_SHIFT 0
5706#define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
5707#define DSPFW_SPRITEA_SHIFT 0
5708#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
5709#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
5710#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
5711#define DSPFW_HPLL_SR_EN (1<<31)
5712#define PINEVIEW_SELF_REFRESH_EN (1<<30)
5713#define DSPFW_CURSOR_SR_SHIFT 24
5714#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
5715#define DSPFW_HPLL_CURSOR_SHIFT 16
5716#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
5717#define DSPFW_HPLL_SR_SHIFT 0
5718#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
5719
5720/* vlv/chv */
5721#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5722#define DSPFW_SPRITEB_WM1_SHIFT 16
5723#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
5724#define DSPFW_CURSORA_WM1_SHIFT 8
5725#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
5726#define DSPFW_SPRITEA_WM1_SHIFT 0
5727#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
5728#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5729#define DSPFW_PLANEB_WM1_SHIFT 24
5730#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
5731#define DSPFW_PLANEA_WM1_SHIFT 16
5732#define DSPFW_PLANEA_WM1_MASK (0xff<<16)
5733#define DSPFW_CURSORB_WM1_SHIFT 8
5734#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
5735#define DSPFW_CURSOR_SR_WM1_SHIFT 0
5736#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
5737#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5738#define DSPFW_SR_WM1_SHIFT 0
5739#define DSPFW_SR_WM1_MASK (0x1ff<<0)
5740#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5741#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5742#define DSPFW_SPRITED_WM1_SHIFT 24
5743#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
5744#define DSPFW_SPRITED_SHIFT 16
5745#define DSPFW_SPRITED_MASK_VLV (0xff<<16)
5746#define DSPFW_SPRITEC_WM1_SHIFT 8
5747#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
5748#define DSPFW_SPRITEC_SHIFT 0
5749#define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
5750#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5751#define DSPFW_SPRITEF_WM1_SHIFT 24
5752#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
5753#define DSPFW_SPRITEF_SHIFT 16
5754#define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
5755#define DSPFW_SPRITEE_WM1_SHIFT 8
5756#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
5757#define DSPFW_SPRITEE_SHIFT 0
5758#define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
5759#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5760#define DSPFW_PLANEC_WM1_SHIFT 24
5761#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
5762#define DSPFW_PLANEC_SHIFT 16
5763#define DSPFW_PLANEC_MASK_VLV (0xff<<16)
5764#define DSPFW_CURSORC_WM1_SHIFT 8
5765#define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
5766#define DSPFW_CURSORC_SHIFT 0
5767#define DSPFW_CURSORC_MASK (0x3f<<0)
5768
5769/* vlv/chv high order bits */
5770#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
5771#define DSPFW_SR_HI_SHIFT 24
5772#define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
5773#define DSPFW_SPRITEF_HI_SHIFT 23
5774#define DSPFW_SPRITEF_HI_MASK (1<<23)
5775#define DSPFW_SPRITEE_HI_SHIFT 22
5776#define DSPFW_SPRITEE_HI_MASK (1<<22)
5777#define DSPFW_PLANEC_HI_SHIFT 21
5778#define DSPFW_PLANEC_HI_MASK (1<<21)
5779#define DSPFW_SPRITED_HI_SHIFT 20
5780#define DSPFW_SPRITED_HI_MASK (1<<20)
5781#define DSPFW_SPRITEC_HI_SHIFT 16
5782#define DSPFW_SPRITEC_HI_MASK (1<<16)
5783#define DSPFW_PLANEB_HI_SHIFT 12
5784#define DSPFW_PLANEB_HI_MASK (1<<12)
5785#define DSPFW_SPRITEB_HI_SHIFT 8
5786#define DSPFW_SPRITEB_HI_MASK (1<<8)
5787#define DSPFW_SPRITEA_HI_SHIFT 4
5788#define DSPFW_SPRITEA_HI_MASK (1<<4)
5789#define DSPFW_PLANEA_HI_SHIFT 0
5790#define DSPFW_PLANEA_HI_MASK (1<<0)
5791#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
5792#define DSPFW_SR_WM1_HI_SHIFT 24
5793#define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
5794#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
5795#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
5796#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
5797#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
5798#define DSPFW_PLANEC_WM1_HI_SHIFT 21
5799#define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
5800#define DSPFW_SPRITED_WM1_HI_SHIFT 20
5801#define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
5802#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
5803#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
5804#define DSPFW_PLANEB_WM1_HI_SHIFT 12
5805#define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
5806#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
5807#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
5808#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
5809#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
5810#define DSPFW_PLANEA_WM1_HI_SHIFT 0
5811#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
5812
5813/* drain latency register values*/
5814#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5815#define DDL_CURSOR_SHIFT 24
5816#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
5817#define DDL_PLANE_SHIFT 0
5818#define DDL_PRECISION_HIGH (1<<7)
5819#define DDL_PRECISION_LOW (0<<7)
5820#define DRAIN_LATENCY_MASK 0x7f
5821
5822#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
5823#define CBR_PND_DEADLINE_DISABLE (1<<31)
5824#define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
5825
5826#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
5827#define CBR_DPLLBMD_PIPE(pipe) (1<<(7+(pipe)*11)) /* pipes B and C */
5828
5829/* FIFO watermark sizes etc */
5830#define G4X_FIFO_LINE_SIZE 64
5831#define I915_FIFO_LINE_SIZE 64
5832#define I830_FIFO_LINE_SIZE 32
5833
5834#define VALLEYVIEW_FIFO_SIZE 255
5835#define G4X_FIFO_SIZE 127
5836#define I965_FIFO_SIZE 512
5837#define I945_FIFO_SIZE 127
5838#define I915_FIFO_SIZE 95
5839#define I855GM_FIFO_SIZE 127 /* In cachelines */
5840#define I830_FIFO_SIZE 95
5841
5842#define VALLEYVIEW_MAX_WM 0xff
5843#define G4X_MAX_WM 0x3f
5844#define I915_MAX_WM 0x3f
5845
5846#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
5847#define PINEVIEW_FIFO_LINE_SIZE 64
5848#define PINEVIEW_MAX_WM 0x1ff
5849#define PINEVIEW_DFT_WM 0x3f
5850#define PINEVIEW_DFT_HPLLOFF_WM 0
5851#define PINEVIEW_GUARD_WM 10
5852#define PINEVIEW_CURSOR_FIFO 64
5853#define PINEVIEW_CURSOR_MAX_WM 0x3f
5854#define PINEVIEW_CURSOR_DFT_WM 0
5855#define PINEVIEW_CURSOR_GUARD_WM 5
5856
5857#define VALLEYVIEW_CURSOR_MAX_WM 64
5858#define I965_CURSOR_FIFO 64
5859#define I965_CURSOR_MAX_WM 32
5860#define I965_CURSOR_DFT_WM 8
5861
5862/* Watermark register definitions for SKL */
5863#define _CUR_WM_A_0 0x70140
5864#define _CUR_WM_B_0 0x71140
5865#define _PLANE_WM_1_A_0 0x70240
5866#define _PLANE_WM_1_B_0 0x71240
5867#define _PLANE_WM_2_A_0 0x70340
5868#define _PLANE_WM_2_B_0 0x71340
5869#define _PLANE_WM_TRANS_1_A_0 0x70268
5870#define _PLANE_WM_TRANS_1_B_0 0x71268
5871#define _PLANE_WM_TRANS_2_A_0 0x70368
5872#define _PLANE_WM_TRANS_2_B_0 0x71368
5873#define _CUR_WM_TRANS_A_0 0x70168
5874#define _CUR_WM_TRANS_B_0 0x71168
5875#define PLANE_WM_EN (1 << 31)
5876#define PLANE_WM_LINES_SHIFT 14
5877#define PLANE_WM_LINES_MASK 0x1f
5878#define PLANE_WM_BLOCKS_MASK 0x3ff
5879
5880#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
5881#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
5882#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
5883
5884#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
5885#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
5886#define _PLANE_WM_BASE(pipe, plane) \
5887 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
5888#define PLANE_WM(pipe, plane, level) \
5889 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
5890#define _PLANE_WM_TRANS_1(pipe) \
5891 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
5892#define _PLANE_WM_TRANS_2(pipe) \
5893 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
5894#define PLANE_WM_TRANS(pipe, plane) \
5895 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
5896
5897/* define the Watermark register on Ironlake */
5898#define WM0_PIPEA_ILK _MMIO(0x45100)
5899#define WM0_PIPE_PLANE_MASK (0xffff<<16)
5900#define WM0_PIPE_PLANE_SHIFT 16
5901#define WM0_PIPE_SPRITE_MASK (0xff<<8)
5902#define WM0_PIPE_SPRITE_SHIFT 8
5903#define WM0_PIPE_CURSOR_MASK (0xff)
5904
5905#define WM0_PIPEB_ILK _MMIO(0x45104)
5906#define WM0_PIPEC_IVB _MMIO(0x45200)
5907#define WM1_LP_ILK _MMIO(0x45108)
5908#define WM1_LP_SR_EN (1<<31)
5909#define WM1_LP_LATENCY_SHIFT 24
5910#define WM1_LP_LATENCY_MASK (0x7f<<24)
5911#define WM1_LP_FBC_MASK (0xf<<20)
5912#define WM1_LP_FBC_SHIFT 20
5913#define WM1_LP_FBC_SHIFT_BDW 19
5914#define WM1_LP_SR_MASK (0x7ff<<8)
5915#define WM1_LP_SR_SHIFT 8
5916#define WM1_LP_CURSOR_MASK (0xff)
5917#define WM2_LP_ILK _MMIO(0x4510c)
5918#define WM2_LP_EN (1<<31)
5919#define WM3_LP_ILK _MMIO(0x45110)
5920#define WM3_LP_EN (1<<31)
5921#define WM1S_LP_ILK _MMIO(0x45120)
5922#define WM2S_LP_IVB _MMIO(0x45124)
5923#define WM3S_LP_IVB _MMIO(0x45128)
5924#define WM1S_LP_EN (1<<31)
5925
5926#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
5927 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
5928 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
5929
5930/* Memory latency timer register */
5931#define MLTR_ILK _MMIO(0x11222)
5932#define MLTR_WM1_SHIFT 0
5933#define MLTR_WM2_SHIFT 8
5934/* the unit of memory self-refresh latency time is 0.5us */
5935#define ILK_SRLT_MASK 0x3f
5936
5937
5938/* the address where we get all kinds of latency value */
5939#define SSKPD _MMIO(0x5d10)
5940#define SSKPD_WM_MASK 0x3f
5941#define SSKPD_WM0_SHIFT 0
5942#define SSKPD_WM1_SHIFT 8
5943#define SSKPD_WM2_SHIFT 16
5944#define SSKPD_WM3_SHIFT 24
5945
5946/*
5947 * The two pipe frame counter registers are not synchronized, so
5948 * reading a stable value is somewhat tricky. The following code
5949 * should work:
5950 *
5951 * do {
5952 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5953 * PIPE_FRAME_HIGH_SHIFT;
5954 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
5955 * PIPE_FRAME_LOW_SHIFT);
5956 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
5957 * PIPE_FRAME_HIGH_SHIFT);
5958 * } while (high1 != high2);
5959 * frame = (high1 << 8) | low1;
5960 */
5961#define _PIPEAFRAMEHIGH 0x70040
5962#define PIPE_FRAME_HIGH_MASK 0x0000ffff
5963#define PIPE_FRAME_HIGH_SHIFT 0
5964#define _PIPEAFRAMEPIXEL 0x70044
5965#define PIPE_FRAME_LOW_MASK 0xff000000
5966#define PIPE_FRAME_LOW_SHIFT 24
5967#define PIPE_PIXEL_MASK 0x00ffffff
5968#define PIPE_PIXEL_SHIFT 0
5969/* GM45+ just has to be different */
5970#define _PIPEA_FRMCOUNT_G4X 0x70040
5971#define _PIPEA_FLIPCOUNT_G4X 0x70044
5972#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
5973#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
5974
5975/* Cursor A & B regs */
5976#define _CURACNTR 0x70080
5977/* Old style CUR*CNTR flags (desktop 8xx) */
5978#define CURSOR_ENABLE 0x80000000
5979#define CURSOR_GAMMA_ENABLE 0x40000000
5980#define CURSOR_STRIDE_SHIFT 28
5981#define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
5982#define CURSOR_PIPE_CSC_ENABLE (1<<24)
5983#define CURSOR_FORMAT_SHIFT 24
5984#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
5985#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
5986#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
5987#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
5988#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
5989#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
5990/* New style CUR*CNTR flags */
5991#define CURSOR_MODE 0x27
5992#define CURSOR_MODE_DISABLE 0x00
5993#define CURSOR_MODE_128_32B_AX 0x02
5994#define CURSOR_MODE_256_32B_AX 0x03
5995#define CURSOR_MODE_64_32B_AX 0x07
5996#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
5997#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
5998#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
5999#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
6000#define MCURSOR_GAMMA_ENABLE (1 << 26)
6001#define CURSOR_ROTATE_180 (1<<15)
6002#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
6003#define _CURABASE 0x70084
6004#define _CURAPOS 0x70088
6005#define CURSOR_POS_MASK 0x007FF
6006#define CURSOR_POS_SIGN 0x8000
6007#define CURSOR_X_SHIFT 0
6008#define CURSOR_Y_SHIFT 16
6009#define CURSIZE _MMIO(0x700a0) /* 845/865 */
6010#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
6011#define CUR_FBC_CTL_EN (1 << 31)
6012#define _CURBCNTR 0x700c0
6013#define _CURBBASE 0x700c4
6014#define _CURBPOS 0x700c8
6015
6016#define _CURBCNTR_IVB 0x71080
6017#define _CURBBASE_IVB 0x71084
6018#define _CURBPOS_IVB 0x71088
6019
6020#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
6021 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
6022 dev_priv->info.display_mmio_offset)
6023
6024#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
6025#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
6026#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
6027#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
6028
6029#define CURSOR_A_OFFSET 0x70080
6030#define CURSOR_B_OFFSET 0x700c0
6031#define CHV_CURSOR_C_OFFSET 0x700e0
6032#define IVB_CURSOR_B_OFFSET 0x71080
6033#define IVB_CURSOR_C_OFFSET 0x72080
6034
6035/* Display A control */
6036#define _DSPACNTR 0x70180
6037#define DISPLAY_PLANE_ENABLE (1<<31)
6038#define DISPLAY_PLANE_DISABLE 0
6039#define DISPPLANE_GAMMA_ENABLE (1<<30)
6040#define DISPPLANE_GAMMA_DISABLE 0
6041#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
6042#define DISPPLANE_YUV422 (0x0<<26)
6043#define DISPPLANE_8BPP (0x2<<26)
6044#define DISPPLANE_BGRA555 (0x3<<26)
6045#define DISPPLANE_BGRX555 (0x4<<26)
6046#define DISPPLANE_BGRX565 (0x5<<26)
6047#define DISPPLANE_BGRX888 (0x6<<26)
6048#define DISPPLANE_BGRA888 (0x7<<26)
6049#define DISPPLANE_RGBX101010 (0x8<<26)
6050#define DISPPLANE_RGBA101010 (0x9<<26)
6051#define DISPPLANE_BGRX101010 (0xa<<26)
6052#define DISPPLANE_RGBX161616 (0xc<<26)
6053#define DISPPLANE_RGBX888 (0xe<<26)
6054#define DISPPLANE_RGBA888 (0xf<<26)
6055#define DISPPLANE_STEREO_ENABLE (1<<25)
6056#define DISPPLANE_STEREO_DISABLE 0
6057#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
6058#define DISPPLANE_SEL_PIPE_SHIFT 24
6059#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
6060#define DISPPLANE_SEL_PIPE(pipe) ((pipe)<<DISPPLANE_SEL_PIPE_SHIFT)
6061#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
6062#define DISPPLANE_SRC_KEY_DISABLE 0
6063#define DISPPLANE_LINE_DOUBLE (1<<20)
6064#define DISPPLANE_NO_LINE_DOUBLE 0
6065#define DISPPLANE_STEREO_POLARITY_FIRST 0
6066#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
6067#define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
6068#define DISPPLANE_ROTATE_180 (1<<15)
6069#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
6070#define DISPPLANE_TILED (1<<10)
6071#define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
6072#define _DSPAADDR 0x70184
6073#define _DSPASTRIDE 0x70188
6074#define _DSPAPOS 0x7018C /* reserved */
6075#define _DSPASIZE 0x70190
6076#define _DSPASURF 0x7019C /* 965+ only */
6077#define _DSPATILEOFF 0x701A4 /* 965+ only */
6078#define _DSPAOFFSET 0x701A4 /* HSW */
6079#define _DSPASURFLIVE 0x701AC
6080
6081#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
6082#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
6083#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
6084#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
6085#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
6086#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
6087#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
6088#define DSPLINOFF(plane) DSPADDR(plane)
6089#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
6090#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
6091
6092/* CHV pipe B blender and primary plane */
6093#define _CHV_BLEND_A 0x60a00
6094#define CHV_BLEND_LEGACY (0<<30)
6095#define CHV_BLEND_ANDROID (1<<30)
6096#define CHV_BLEND_MPO (2<<30)
6097#define CHV_BLEND_MASK (3<<30)
6098#define _CHV_CANVAS_A 0x60a04
6099#define _PRIMPOS_A 0x60a08
6100#define _PRIMSIZE_A 0x60a0c
6101#define _PRIMCNSTALPHA_A 0x60a10
6102#define PRIM_CONST_ALPHA_ENABLE (1<<31)
6103
6104#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
6105#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
6106#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
6107#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
6108#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
6109
6110/* Display/Sprite base address macros */
6111#define DISP_BASEADDR_MASK (0xfffff000)
6112#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
6113#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
6114
6115/*
6116 * VBIOS flags
6117 * gen2:
6118 * [00:06] alm,mgm
6119 * [10:16] all
6120 * [30:32] alm,mgm
6121 * gen3+:
6122 * [00:0f] all
6123 * [10:1f] all
6124 * [30:32] all
6125 */
6126#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
6127#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
6128#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
6129#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
6130
6131/* Pipe B */
6132#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
6133#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
6134#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
6135#define _PIPEBFRAMEHIGH 0x71040
6136#define _PIPEBFRAMEPIXEL 0x71044
6137#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
6138#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
6139
6140
6141/* Display B control */
6142#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
6143#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
6144#define DISPPLANE_ALPHA_TRANS_DISABLE 0
6145#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
6146#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
6147#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
6148#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
6149#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
6150#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
6151#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
6152#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
6153#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
6154#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
6155
6156/* Sprite A control */
6157#define _DVSACNTR 0x72180
6158#define DVS_ENABLE (1<<31)
6159#define DVS_GAMMA_ENABLE (1<<30)
6160#define DVS_YUV_RANGE_CORRECTION_DISABLE (1<<27)
6161#define DVS_PIXFORMAT_MASK (3<<25)
6162#define DVS_FORMAT_YUV422 (0<<25)
6163#define DVS_FORMAT_RGBX101010 (1<<25)
6164#define DVS_FORMAT_RGBX888 (2<<25)
6165#define DVS_FORMAT_RGBX161616 (3<<25)
6166#define DVS_PIPE_CSC_ENABLE (1<<24)
6167#define DVS_SOURCE_KEY (1<<22)
6168#define DVS_RGB_ORDER_XBGR (1<<20)
6169#define DVS_YUV_FORMAT_BT709 (1<<18)
6170#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
6171#define DVS_YUV_ORDER_YUYV (0<<16)
6172#define DVS_YUV_ORDER_UYVY (1<<16)
6173#define DVS_YUV_ORDER_YVYU (2<<16)
6174#define DVS_YUV_ORDER_VYUY (3<<16)
6175#define DVS_ROTATE_180 (1<<15)
6176#define DVS_DEST_KEY (1<<2)
6177#define DVS_TRICKLE_FEED_DISABLE (1<<14)
6178#define DVS_TILED (1<<10)
6179#define _DVSALINOFF 0x72184
6180#define _DVSASTRIDE 0x72188
6181#define _DVSAPOS 0x7218c
6182#define _DVSASIZE 0x72190
6183#define _DVSAKEYVAL 0x72194
6184#define _DVSAKEYMSK 0x72198
6185#define _DVSASURF 0x7219c
6186#define _DVSAKEYMAXVAL 0x721a0
6187#define _DVSATILEOFF 0x721a4
6188#define _DVSASURFLIVE 0x721ac
6189#define _DVSASCALE 0x72204
6190#define DVS_SCALE_ENABLE (1<<31)
6191#define DVS_FILTER_MASK (3<<29)
6192#define DVS_FILTER_MEDIUM (0<<29)
6193#define DVS_FILTER_ENHANCING (1<<29)
6194#define DVS_FILTER_SOFTENING (2<<29)
6195#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
6196#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
6197#define _DVSAGAMC 0x72300
6198
6199#define _DVSBCNTR 0x73180
6200#define _DVSBLINOFF 0x73184
6201#define _DVSBSTRIDE 0x73188
6202#define _DVSBPOS 0x7318c
6203#define _DVSBSIZE 0x73190
6204#define _DVSBKEYVAL 0x73194
6205#define _DVSBKEYMSK 0x73198
6206#define _DVSBSURF 0x7319c
6207#define _DVSBKEYMAXVAL 0x731a0
6208#define _DVSBTILEOFF 0x731a4
6209#define _DVSBSURFLIVE 0x731ac
6210#define _DVSBSCALE 0x73204
6211#define _DVSBGAMC 0x73300
6212
6213#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
6214#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
6215#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
6216#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
6217#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
6218#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
6219#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
6220#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
6221#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
6222#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
6223#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
6224#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
6225
6226#define _SPRA_CTL 0x70280
6227#define SPRITE_ENABLE (1<<31)
6228#define SPRITE_GAMMA_ENABLE (1<<30)
6229#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1<<28)
6230#define SPRITE_PIXFORMAT_MASK (7<<25)
6231#define SPRITE_FORMAT_YUV422 (0<<25)
6232#define SPRITE_FORMAT_RGBX101010 (1<<25)
6233#define SPRITE_FORMAT_RGBX888 (2<<25)
6234#define SPRITE_FORMAT_RGBX161616 (3<<25)
6235#define SPRITE_FORMAT_YUV444 (4<<25)
6236#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
6237#define SPRITE_PIPE_CSC_ENABLE (1<<24)
6238#define SPRITE_SOURCE_KEY (1<<22)
6239#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
6240#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
6241#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
6242#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
6243#define SPRITE_YUV_ORDER_YUYV (0<<16)
6244#define SPRITE_YUV_ORDER_UYVY (1<<16)
6245#define SPRITE_YUV_ORDER_YVYU (2<<16)
6246#define SPRITE_YUV_ORDER_VYUY (3<<16)
6247#define SPRITE_ROTATE_180 (1<<15)
6248#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
6249#define SPRITE_INT_GAMMA_ENABLE (1<<13)
6250#define SPRITE_TILED (1<<10)
6251#define SPRITE_DEST_KEY (1<<2)
6252#define _SPRA_LINOFF 0x70284
6253#define _SPRA_STRIDE 0x70288
6254#define _SPRA_POS 0x7028c
6255#define _SPRA_SIZE 0x70290
6256#define _SPRA_KEYVAL 0x70294
6257#define _SPRA_KEYMSK 0x70298
6258#define _SPRA_SURF 0x7029c
6259#define _SPRA_KEYMAX 0x702a0
6260#define _SPRA_TILEOFF 0x702a4
6261#define _SPRA_OFFSET 0x702a4
6262#define _SPRA_SURFLIVE 0x702ac
6263#define _SPRA_SCALE 0x70304
6264#define SPRITE_SCALE_ENABLE (1<<31)
6265#define SPRITE_FILTER_MASK (3<<29)
6266#define SPRITE_FILTER_MEDIUM (0<<29)
6267#define SPRITE_FILTER_ENHANCING (1<<29)
6268#define SPRITE_FILTER_SOFTENING (2<<29)
6269#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
6270#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
6271#define _SPRA_GAMC 0x70400
6272
6273#define _SPRB_CTL 0x71280
6274#define _SPRB_LINOFF 0x71284
6275#define _SPRB_STRIDE 0x71288
6276#define _SPRB_POS 0x7128c
6277#define _SPRB_SIZE 0x71290
6278#define _SPRB_KEYVAL 0x71294
6279#define _SPRB_KEYMSK 0x71298
6280#define _SPRB_SURF 0x7129c
6281#define _SPRB_KEYMAX 0x712a0
6282#define _SPRB_TILEOFF 0x712a4
6283#define _SPRB_OFFSET 0x712a4
6284#define _SPRB_SURFLIVE 0x712ac
6285#define _SPRB_SCALE 0x71304
6286#define _SPRB_GAMC 0x71400
6287
6288#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
6289#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
6290#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
6291#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
6292#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
6293#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
6294#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
6295#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
6296#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
6297#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
6298#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
6299#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
6300#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
6301#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
6302
6303#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6304#define SP_ENABLE (1<<31)
6305#define SP_GAMMA_ENABLE (1<<30)
6306#define SP_PIXFORMAT_MASK (0xf<<26)
6307#define SP_FORMAT_YUV422 (0<<26)
6308#define SP_FORMAT_BGR565 (5<<26)
6309#define SP_FORMAT_BGRX8888 (6<<26)
6310#define SP_FORMAT_BGRA8888 (7<<26)
6311#define SP_FORMAT_RGBX1010102 (8<<26)
6312#define SP_FORMAT_RGBA1010102 (9<<26)
6313#define SP_FORMAT_RGBX8888 (0xe<<26)
6314#define SP_FORMAT_RGBA8888 (0xf<<26)
6315#define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
6316#define SP_SOURCE_KEY (1<<22)
6317#define SP_YUV_FORMAT_BT709 (1<<18)
6318#define SP_YUV_BYTE_ORDER_MASK (3<<16)
6319#define SP_YUV_ORDER_YUYV (0<<16)
6320#define SP_YUV_ORDER_UYVY (1<<16)
6321#define SP_YUV_ORDER_YVYU (2<<16)
6322#define SP_YUV_ORDER_VYUY (3<<16)
6323#define SP_ROTATE_180 (1<<15)
6324#define SP_TILED (1<<10)
6325#define SP_MIRROR (1<<8) /* CHV pipe B */
6326#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6327#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6328#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6329#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6330#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6331#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6332#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6333#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6334#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6335#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6336#define SP_CONST_ALPHA_ENABLE (1<<31)
6337#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
6338#define SP_CONTRAST(x) ((x) << 18) /* u3.6 */
6339#define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */
6340#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6341#define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */
6342#define SP_SH_COS(x) (x) /* u3.7 */
6343#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
6344
6345#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6346#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6347#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6348#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6349#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6350#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6351#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6352#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6353#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6354#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6355#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6356#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6357#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6358#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
6359
6360#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
6361 _MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
6362
6363#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
6364#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
6365#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
6366#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
6367#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
6368#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
6369#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
6370#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
6371#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
6372#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
6373#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
6374#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
6375#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
6376#define SPGAMC(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
6377
6378/*
6379 * CHV pipe B sprite CSC
6380 *
6381 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
6382 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
6383 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
6384 */
6385#define _MMIO_CHV_SPCSC(plane_id, reg) \
6386 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6387
6388#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
6389#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
6390#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
6391#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
6392#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
6393
6394#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
6395#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
6396#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
6397#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
6398#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
6399#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
6400#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
6401
6402#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
6403#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
6404#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
6405#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
6406#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
6407
6408#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
6409#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
6410#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
6411#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
6412#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
6413
6414/* Skylake plane registers */
6415
6416#define _PLANE_CTL_1_A 0x70180
6417#define _PLANE_CTL_2_A 0x70280
6418#define _PLANE_CTL_3_A 0x70380
6419#define PLANE_CTL_ENABLE (1 << 31)
6420#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */
6421#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6422/*
6423 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
6424 * expanded to include bit 23 as well. However, the shift-24 based values
6425 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
6426 */
6427#define PLANE_CTL_FORMAT_MASK (0xf << 24)
6428#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
6429#define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
6430#define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
6431#define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
6432#define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
6433#define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
6434#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
6435#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
6436#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23)
6437#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */
6438#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
6439#define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
6440#define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
6441#define PLANE_CTL_ORDER_BGRX (0 << 20)
6442#define PLANE_CTL_ORDER_RGBX (1 << 20)
6443#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
6444#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
6445#define PLANE_CTL_YUV422_YUYV ( 0 << 16)
6446#define PLANE_CTL_YUV422_UYVY ( 1 << 16)
6447#define PLANE_CTL_YUV422_YVYU ( 2 << 16)
6448#define PLANE_CTL_YUV422_VYUY ( 3 << 16)
6449#define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
6450#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
6451#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */
6452#define PLANE_CTL_TILED_MASK (0x7 << 10)
6453#define PLANE_CTL_TILED_LINEAR ( 0 << 10)
6454#define PLANE_CTL_TILED_X ( 1 << 10)
6455#define PLANE_CTL_TILED_Y ( 4 << 10)
6456#define PLANE_CTL_TILED_YF ( 5 << 10)
6457#define PLANE_CTL_FLIP_HORIZONTAL ( 1 << 8)
6458#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
6459#define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
6460#define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
6461#define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
6462#define PLANE_CTL_ROTATE_MASK 0x3
6463#define PLANE_CTL_ROTATE_0 0x0
6464#define PLANE_CTL_ROTATE_90 0x1
6465#define PLANE_CTL_ROTATE_180 0x2
6466#define PLANE_CTL_ROTATE_270 0x3
6467#define _PLANE_STRIDE_1_A 0x70188
6468#define _PLANE_STRIDE_2_A 0x70288
6469#define _PLANE_STRIDE_3_A 0x70388
6470#define _PLANE_POS_1_A 0x7018c
6471#define _PLANE_POS_2_A 0x7028c
6472#define _PLANE_POS_3_A 0x7038c
6473#define _PLANE_SIZE_1_A 0x70190
6474#define _PLANE_SIZE_2_A 0x70290
6475#define _PLANE_SIZE_3_A 0x70390
6476#define _PLANE_SURF_1_A 0x7019c
6477#define _PLANE_SURF_2_A 0x7029c
6478#define _PLANE_SURF_3_A 0x7039c
6479#define _PLANE_OFFSET_1_A 0x701a4
6480#define _PLANE_OFFSET_2_A 0x702a4
6481#define _PLANE_OFFSET_3_A 0x703a4
6482#define _PLANE_KEYVAL_1_A 0x70194
6483#define _PLANE_KEYVAL_2_A 0x70294
6484#define _PLANE_KEYMSK_1_A 0x70198
6485#define _PLANE_KEYMSK_2_A 0x70298
6486#define _PLANE_KEYMAX_1_A 0x701a0
6487#define _PLANE_KEYMAX_2_A 0x702a0
6488#define _PLANE_AUX_DIST_1_A 0x701c0
6489#define _PLANE_AUX_DIST_2_A 0x702c0
6490#define _PLANE_AUX_OFFSET_1_A 0x701c4
6491#define _PLANE_AUX_OFFSET_2_A 0x702c4
6492#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
6493#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
6494#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
6495#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
6496#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
6497#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
6498#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
6499#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
6500#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
6501#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
6502#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
6503#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
6504#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
6505#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
6506#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
6507#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
6508#define _PLANE_BUF_CFG_1_A 0x7027c
6509#define _PLANE_BUF_CFG_2_A 0x7037c
6510#define _PLANE_NV12_BUF_CFG_1_A 0x70278
6511#define _PLANE_NV12_BUF_CFG_2_A 0x70378
6512
6513
6514#define _PLANE_CTL_1_B 0x71180
6515#define _PLANE_CTL_2_B 0x71280
6516#define _PLANE_CTL_3_B 0x71380
6517#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
6518#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
6519#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
6520#define PLANE_CTL(pipe, plane) \
6521 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
6522
6523#define _PLANE_STRIDE_1_B 0x71188
6524#define _PLANE_STRIDE_2_B 0x71288
6525#define _PLANE_STRIDE_3_B 0x71388
6526#define _PLANE_STRIDE_1(pipe) \
6527 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
6528#define _PLANE_STRIDE_2(pipe) \
6529 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
6530#define _PLANE_STRIDE_3(pipe) \
6531 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
6532#define PLANE_STRIDE(pipe, plane) \
6533 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
6534
6535#define _PLANE_POS_1_B 0x7118c
6536#define _PLANE_POS_2_B 0x7128c
6537#define _PLANE_POS_3_B 0x7138c
6538#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
6539#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
6540#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
6541#define PLANE_POS(pipe, plane) \
6542 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
6543
6544#define _PLANE_SIZE_1_B 0x71190
6545#define _PLANE_SIZE_2_B 0x71290
6546#define _PLANE_SIZE_3_B 0x71390
6547#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
6548#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
6549#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
6550#define PLANE_SIZE(pipe, plane) \
6551 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
6552
6553#define _PLANE_SURF_1_B 0x7119c
6554#define _PLANE_SURF_2_B 0x7129c
6555#define _PLANE_SURF_3_B 0x7139c
6556#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
6557#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
6558#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
6559#define PLANE_SURF(pipe, plane) \
6560 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
6561
6562#define _PLANE_OFFSET_1_B 0x711a4
6563#define _PLANE_OFFSET_2_B 0x712a4
6564#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
6565#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
6566#define PLANE_OFFSET(pipe, plane) \
6567 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
6568
6569#define _PLANE_KEYVAL_1_B 0x71194
6570#define _PLANE_KEYVAL_2_B 0x71294
6571#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
6572#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
6573#define PLANE_KEYVAL(pipe, plane) \
6574 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
6575
6576#define _PLANE_KEYMSK_1_B 0x71198
6577#define _PLANE_KEYMSK_2_B 0x71298
6578#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
6579#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
6580#define PLANE_KEYMSK(pipe, plane) \
6581 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
6582
6583#define _PLANE_KEYMAX_1_B 0x711a0
6584#define _PLANE_KEYMAX_2_B 0x712a0
6585#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
6586#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
6587#define PLANE_KEYMAX(pipe, plane) \
6588 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
6589
6590#define _PLANE_BUF_CFG_1_B 0x7127c
6591#define _PLANE_BUF_CFG_2_B 0x7137c
6592#define _PLANE_BUF_CFG_1(pipe) \
6593 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
6594#define _PLANE_BUF_CFG_2(pipe) \
6595 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
6596#define PLANE_BUF_CFG(pipe, plane) \
6597 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
6598
6599#define _PLANE_NV12_BUF_CFG_1_B 0x71278
6600#define _PLANE_NV12_BUF_CFG_2_B 0x71378
6601#define _PLANE_NV12_BUF_CFG_1(pipe) \
6602 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
6603#define _PLANE_NV12_BUF_CFG_2(pipe) \
6604 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
6605#define PLANE_NV12_BUF_CFG(pipe, plane) \
6606 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
6607
6608#define _PLANE_AUX_DIST_1_B 0x711c0
6609#define _PLANE_AUX_DIST_2_B 0x712c0
6610#define _PLANE_AUX_DIST_1(pipe) \
6611 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
6612#define _PLANE_AUX_DIST_2(pipe) \
6613 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
6614#define PLANE_AUX_DIST(pipe, plane) \
6615 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
6616
6617#define _PLANE_AUX_OFFSET_1_B 0x711c4
6618#define _PLANE_AUX_OFFSET_2_B 0x712c4
6619#define _PLANE_AUX_OFFSET_1(pipe) \
6620 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
6621#define _PLANE_AUX_OFFSET_2(pipe) \
6622 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
6623#define PLANE_AUX_OFFSET(pipe, plane) \
6624 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
6625
6626#define _PLANE_COLOR_CTL_1_B 0x711CC
6627#define _PLANE_COLOR_CTL_2_B 0x712CC
6628#define _PLANE_COLOR_CTL_3_B 0x713CC
6629#define _PLANE_COLOR_CTL_1(pipe) \
6630 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
6631#define _PLANE_COLOR_CTL_2(pipe) \
6632 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
6633#define PLANE_COLOR_CTL(pipe, plane) \
6634 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
6635
6636#/* SKL new cursor registers */
6637#define _CUR_BUF_CFG_A 0x7017c
6638#define _CUR_BUF_CFG_B 0x7117c
6639#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
6640
6641/* VBIOS regs */
6642#define VGACNTRL _MMIO(0x71400)
6643# define VGA_DISP_DISABLE (1 << 31)
6644# define VGA_2X_MODE (1 << 30)
6645# define VGA_PIPE_B_SELECT (1 << 29)
6646
6647#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
6648
6649/* Ironlake */
6650
6651#define CPU_VGACNTRL _MMIO(0x41000)
6652
6653#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
6654#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
6655#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
6656#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
6657#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
6658#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
6659#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
6660#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
6661#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
6662#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
6663#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
6664
6665/* refresh rate hardware control */
6666#define RR_HW_CTL _MMIO(0x45300)
6667#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
6668#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
6669
6670#define FDI_PLL_BIOS_0 _MMIO(0x46000)
6671#define FDI_PLL_FB_CLOCK_MASK 0xff
6672#define FDI_PLL_BIOS_1 _MMIO(0x46004)
6673#define FDI_PLL_BIOS_2 _MMIO(0x46008)
6674#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
6675#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
6676#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
6677
6678#define PCH_3DCGDIS0 _MMIO(0x46020)
6679# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
6680# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
6681
6682#define PCH_3DCGDIS1 _MMIO(0x46024)
6683# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
6684
6685#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
6686#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
6687#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
6688#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
6689
6690
6691#define _PIPEA_DATA_M1 0x60030
6692#define PIPE_DATA_M1_OFFSET 0
6693#define _PIPEA_DATA_N1 0x60034
6694#define PIPE_DATA_N1_OFFSET 0
6695
6696#define _PIPEA_DATA_M2 0x60038
6697#define PIPE_DATA_M2_OFFSET 0
6698#define _PIPEA_DATA_N2 0x6003c
6699#define PIPE_DATA_N2_OFFSET 0
6700
6701#define _PIPEA_LINK_M1 0x60040
6702#define PIPE_LINK_M1_OFFSET 0
6703#define _PIPEA_LINK_N1 0x60044
6704#define PIPE_LINK_N1_OFFSET 0
6705
6706#define _PIPEA_LINK_M2 0x60048
6707#define PIPE_LINK_M2_OFFSET 0
6708#define _PIPEA_LINK_N2 0x6004c
6709#define PIPE_LINK_N2_OFFSET 0
6710
6711/* PIPEB timing regs are same start from 0x61000 */
6712
6713#define _PIPEB_DATA_M1 0x61030
6714#define _PIPEB_DATA_N1 0x61034
6715#define _PIPEB_DATA_M2 0x61038
6716#define _PIPEB_DATA_N2 0x6103c
6717#define _PIPEB_LINK_M1 0x61040
6718#define _PIPEB_LINK_N1 0x61044
6719#define _PIPEB_LINK_M2 0x61048
6720#define _PIPEB_LINK_N2 0x6104c
6721
6722#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
6723#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
6724#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
6725#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
6726#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
6727#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
6728#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
6729#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
6730
6731/* CPU panel fitter */
6732/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
6733#define _PFA_CTL_1 0x68080
6734#define _PFB_CTL_1 0x68880
6735#define PF_ENABLE (1<<31)
6736#define PF_PIPE_SEL_MASK_IVB (3<<29)
6737#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
6738#define PF_FILTER_MASK (3<<23)
6739#define PF_FILTER_PROGRAMMED (0<<23)
6740#define PF_FILTER_MED_3x3 (1<<23)
6741#define PF_FILTER_EDGE_ENHANCE (2<<23)
6742#define PF_FILTER_EDGE_SOFTEN (3<<23)
6743#define _PFA_WIN_SZ 0x68074
6744#define _PFB_WIN_SZ 0x68874
6745#define _PFA_WIN_POS 0x68070
6746#define _PFB_WIN_POS 0x68870
6747#define _PFA_VSCALE 0x68084
6748#define _PFB_VSCALE 0x68884
6749#define _PFA_HSCALE 0x68090
6750#define _PFB_HSCALE 0x68890
6751
6752#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
6753#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
6754#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
6755#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
6756#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
6757
6758#define _PSA_CTL 0x68180
6759#define _PSB_CTL 0x68980
6760#define PS_ENABLE (1<<31)
6761#define _PSA_WIN_SZ 0x68174
6762#define _PSB_WIN_SZ 0x68974
6763#define _PSA_WIN_POS 0x68170
6764#define _PSB_WIN_POS 0x68970
6765
6766#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
6767#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
6768#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
6769
6770/*
6771 * Skylake scalers
6772 */
6773#define _PS_1A_CTRL 0x68180
6774#define _PS_2A_CTRL 0x68280
6775#define _PS_1B_CTRL 0x68980
6776#define _PS_2B_CTRL 0x68A80
6777#define _PS_1C_CTRL 0x69180
6778#define PS_SCALER_EN (1 << 31)
6779#define PS_SCALER_MODE_MASK (3 << 28)
6780#define PS_SCALER_MODE_DYN (0 << 28)
6781#define PS_SCALER_MODE_HQ (1 << 28)
6782#define PS_PLANE_SEL_MASK (7 << 25)
6783#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
6784#define PS_FILTER_MASK (3 << 23)
6785#define PS_FILTER_MEDIUM (0 << 23)
6786#define PS_FILTER_EDGE_ENHANCE (2 << 23)
6787#define PS_FILTER_BILINEAR (3 << 23)
6788#define PS_VERT3TAP (1 << 21)
6789#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
6790#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
6791#define PS_PWRUP_PROGRESS (1 << 17)
6792#define PS_V_FILTER_BYPASS (1 << 8)
6793#define PS_VADAPT_EN (1 << 7)
6794#define PS_VADAPT_MODE_MASK (3 << 5)
6795#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
6796#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
6797#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
6798
6799#define _PS_PWR_GATE_1A 0x68160
6800#define _PS_PWR_GATE_2A 0x68260
6801#define _PS_PWR_GATE_1B 0x68960
6802#define _PS_PWR_GATE_2B 0x68A60
6803#define _PS_PWR_GATE_1C 0x69160
6804#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
6805#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
6806#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
6807#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
6808#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
6809#define PS_PWR_GATE_SLPEN_8 0
6810#define PS_PWR_GATE_SLPEN_16 1
6811#define PS_PWR_GATE_SLPEN_24 2
6812#define PS_PWR_GATE_SLPEN_32 3
6813
6814#define _PS_WIN_POS_1A 0x68170
6815#define _PS_WIN_POS_2A 0x68270
6816#define _PS_WIN_POS_1B 0x68970
6817#define _PS_WIN_POS_2B 0x68A70
6818#define _PS_WIN_POS_1C 0x69170
6819
6820#define _PS_WIN_SZ_1A 0x68174
6821#define _PS_WIN_SZ_2A 0x68274
6822#define _PS_WIN_SZ_1B 0x68974
6823#define _PS_WIN_SZ_2B 0x68A74
6824#define _PS_WIN_SZ_1C 0x69174
6825
6826#define _PS_VSCALE_1A 0x68184
6827#define _PS_VSCALE_2A 0x68284
6828#define _PS_VSCALE_1B 0x68984
6829#define _PS_VSCALE_2B 0x68A84
6830#define _PS_VSCALE_1C 0x69184
6831
6832#define _PS_HSCALE_1A 0x68190
6833#define _PS_HSCALE_2A 0x68290
6834#define _PS_HSCALE_1B 0x68990
6835#define _PS_HSCALE_2B 0x68A90
6836#define _PS_HSCALE_1C 0x69190
6837
6838#define _PS_VPHASE_1A 0x68188
6839#define _PS_VPHASE_2A 0x68288
6840#define _PS_VPHASE_1B 0x68988
6841#define _PS_VPHASE_2B 0x68A88
6842#define _PS_VPHASE_1C 0x69188
6843
6844#define _PS_HPHASE_1A 0x68194
6845#define _PS_HPHASE_2A 0x68294
6846#define _PS_HPHASE_1B 0x68994
6847#define _PS_HPHASE_2B 0x68A94
6848#define _PS_HPHASE_1C 0x69194
6849
6850#define _PS_ECC_STAT_1A 0x681D0
6851#define _PS_ECC_STAT_2A 0x682D0
6852#define _PS_ECC_STAT_1B 0x689D0
6853#define _PS_ECC_STAT_2B 0x68AD0
6854#define _PS_ECC_STAT_1C 0x691D0
6855
6856#define _ID(id, a, b) ((a) + (id)*((b)-(a)))
6857#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
6858 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
6859 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
6860#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
6861 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
6862 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
6863#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
6864 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
6865 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
6866#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
6867 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
6868 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
6869#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
6870 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
6871 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
6872#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
6873 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
6874 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
6875#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
6876 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
6877 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
6878#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
6879 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
6880 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
6881#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
6882 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
6883 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
6884
6885/* legacy palette */
6886#define _LGC_PALETTE_A 0x4a000
6887#define _LGC_PALETTE_B 0x4a800
6888#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
6889
6890#define _GAMMA_MODE_A 0x4a480
6891#define _GAMMA_MODE_B 0x4ac80
6892#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
6893#define GAMMA_MODE_MODE_MASK (3 << 0)
6894#define GAMMA_MODE_MODE_8BIT (0 << 0)
6895#define GAMMA_MODE_MODE_10BIT (1 << 0)
6896#define GAMMA_MODE_MODE_12BIT (2 << 0)
6897#define GAMMA_MODE_MODE_SPLIT (3 << 0)
6898
6899/* DMC/CSR */
6900#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
6901#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
6902#define CSR_HTP_ADDR_SKL 0x00500034
6903#define CSR_SSP_BASE _MMIO(0x8F074)
6904#define CSR_HTP_SKL _MMIO(0x8F004)
6905#define CSR_LAST_WRITE _MMIO(0x8F034)
6906#define CSR_LAST_WRITE_VALUE 0xc003b400
6907/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
6908#define CSR_MMIO_START_RANGE 0x80000
6909#define CSR_MMIO_END_RANGE 0x8FFFF
6910#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
6911#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
6912#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
6913
6914/* interrupts */
6915#define DE_MASTER_IRQ_CONTROL (1 << 31)
6916#define DE_SPRITEB_FLIP_DONE (1 << 29)
6917#define DE_SPRITEA_FLIP_DONE (1 << 28)
6918#define DE_PLANEB_FLIP_DONE (1 << 27)
6919#define DE_PLANEA_FLIP_DONE (1 << 26)
6920#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
6921#define DE_PCU_EVENT (1 << 25)
6922#define DE_GTT_FAULT (1 << 24)
6923#define DE_POISON (1 << 23)
6924#define DE_PERFORM_COUNTER (1 << 22)
6925#define DE_PCH_EVENT (1 << 21)
6926#define DE_AUX_CHANNEL_A (1 << 20)
6927#define DE_DP_A_HOTPLUG (1 << 19)
6928#define DE_GSE (1 << 18)
6929#define DE_PIPEB_VBLANK (1 << 15)
6930#define DE_PIPEB_EVEN_FIELD (1 << 14)
6931#define DE_PIPEB_ODD_FIELD (1 << 13)
6932#define DE_PIPEB_LINE_COMPARE (1 << 12)
6933#define DE_PIPEB_VSYNC (1 << 11)
6934#define DE_PIPEB_CRC_DONE (1 << 10)
6935#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
6936#define DE_PIPEA_VBLANK (1 << 7)
6937#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
6938#define DE_PIPEA_EVEN_FIELD (1 << 6)
6939#define DE_PIPEA_ODD_FIELD (1 << 5)
6940#define DE_PIPEA_LINE_COMPARE (1 << 4)
6941#define DE_PIPEA_VSYNC (1 << 3)
6942#define DE_PIPEA_CRC_DONE (1 << 2)
6943#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
6944#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
6945#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
6946
6947/* More Ivybridge lolz */
6948#define DE_ERR_INT_IVB (1<<30)
6949#define DE_GSE_IVB (1<<29)
6950#define DE_PCH_EVENT_IVB (1<<28)
6951#define DE_DP_A_HOTPLUG_IVB (1<<27)
6952#define DE_AUX_CHANNEL_A_IVB (1<<26)
6953#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
6954#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
6955#define DE_PIPEC_VBLANK_IVB (1<<10)
6956#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
6957#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
6958#define DE_PIPEB_VBLANK_IVB (1<<5)
6959#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
6960#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
6961#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
6962#define DE_PIPEA_VBLANK_IVB (1<<0)
6963#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
6964
6965#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
6966#define MASTER_INTERRUPT_ENABLE (1<<31)
6967
6968#define DEISR _MMIO(0x44000)
6969#define DEIMR _MMIO(0x44004)
6970#define DEIIR _MMIO(0x44008)
6971#define DEIER _MMIO(0x4400c)
6972
6973#define GTISR _MMIO(0x44010)
6974#define GTIMR _MMIO(0x44014)
6975#define GTIIR _MMIO(0x44018)
6976#define GTIER _MMIO(0x4401c)
6977
6978#define GEN8_MASTER_IRQ _MMIO(0x44200)
6979#define GEN8_MASTER_IRQ_CONTROL (1<<31)
6980#define GEN8_PCU_IRQ (1<<30)
6981#define GEN8_DE_PCH_IRQ (1<<23)
6982#define GEN8_DE_MISC_IRQ (1<<22)
6983#define GEN8_DE_PORT_IRQ (1<<20)
6984#define GEN8_DE_PIPE_C_IRQ (1<<18)
6985#define GEN8_DE_PIPE_B_IRQ (1<<17)
6986#define GEN8_DE_PIPE_A_IRQ (1<<16)
6987#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
6988#define GEN8_GT_VECS_IRQ (1<<6)
6989#define GEN8_GT_GUC_IRQ (1<<5)
6990#define GEN8_GT_PM_IRQ (1<<4)
6991#define GEN8_GT_VCS2_IRQ (1<<3)
6992#define GEN8_GT_VCS1_IRQ (1<<2)
6993#define GEN8_GT_BCS_IRQ (1<<1)
6994#define GEN8_GT_RCS_IRQ (1<<0)
6995
6996#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
6997#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
6998#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
6999#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
7000
7001#define GEN9_GUC_TO_HOST_INT_EVENT (1<<31)
7002#define GEN9_GUC_EXEC_ERROR_EVENT (1<<30)
7003#define GEN9_GUC_DISPLAY_EVENT (1<<29)
7004#define GEN9_GUC_SEMA_SIGNAL_EVENT (1<<28)
7005#define GEN9_GUC_IOMMU_MSG_EVENT (1<<27)
7006#define GEN9_GUC_DB_RING_EVENT (1<<26)
7007#define GEN9_GUC_DMA_DONE_EVENT (1<<25)
7008#define GEN9_GUC_FATAL_ERROR_EVENT (1<<24)
7009#define GEN9_GUC_NOTIFICATION_EVENT (1<<23)
7010
7011#define GEN8_RCS_IRQ_SHIFT 0
7012#define GEN8_BCS_IRQ_SHIFT 16
7013#define GEN8_VCS1_IRQ_SHIFT 0
7014#define GEN8_VCS2_IRQ_SHIFT 16
7015#define GEN8_VECS_IRQ_SHIFT 0
7016#define GEN8_WD_IRQ_SHIFT 16
7017
7018#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
7019#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
7020#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
7021#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
7022#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
7023#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
7024#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
7025#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
7026#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
7027#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
7028#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
7029#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
7030#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
7031#define GEN8_PIPE_VSYNC (1 << 1)
7032#define GEN8_PIPE_VBLANK (1 << 0)
7033#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
7034#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
7035#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
7036#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
7037#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
7038#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
7039#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
7040#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
7041#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
7042#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
7043#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
7044 (GEN8_PIPE_CURSOR_FAULT | \
7045 GEN8_PIPE_SPRITE_FAULT | \
7046 GEN8_PIPE_PRIMARY_FAULT)
7047#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
7048 (GEN9_PIPE_CURSOR_FAULT | \
7049 GEN9_PIPE_PLANE4_FAULT | \
7050 GEN9_PIPE_PLANE3_FAULT | \
7051 GEN9_PIPE_PLANE2_FAULT | \
7052 GEN9_PIPE_PLANE1_FAULT)
7053
7054#define GEN8_DE_PORT_ISR _MMIO(0x44440)
7055#define GEN8_DE_PORT_IMR _MMIO(0x44444)
7056#define GEN8_DE_PORT_IIR _MMIO(0x44448)
7057#define GEN8_DE_PORT_IER _MMIO(0x4444c)
7058#define CNL_AUX_CHANNEL_F (1 << 28)
7059#define GEN9_AUX_CHANNEL_D (1 << 27)
7060#define GEN9_AUX_CHANNEL_C (1 << 26)
7061#define GEN9_AUX_CHANNEL_B (1 << 25)
7062#define BXT_DE_PORT_HP_DDIC (1 << 5)
7063#define BXT_DE_PORT_HP_DDIB (1 << 4)
7064#define BXT_DE_PORT_HP_DDIA (1 << 3)
7065#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
7066 BXT_DE_PORT_HP_DDIB | \
7067 BXT_DE_PORT_HP_DDIC)
7068#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
7069#define BXT_DE_PORT_GMBUS (1 << 1)
7070#define GEN8_AUX_CHANNEL_A (1 << 0)
7071
7072#define GEN8_DE_MISC_ISR _MMIO(0x44460)
7073#define GEN8_DE_MISC_IMR _MMIO(0x44464)
7074#define GEN8_DE_MISC_IIR _MMIO(0x44468)
7075#define GEN8_DE_MISC_IER _MMIO(0x4446c)
7076#define GEN8_DE_MISC_GSE (1 << 27)
7077
7078#define GEN8_PCU_ISR _MMIO(0x444e0)
7079#define GEN8_PCU_IMR _MMIO(0x444e4)
7080#define GEN8_PCU_IIR _MMIO(0x444e8)
7081#define GEN8_PCU_IER _MMIO(0x444ec)
7082
7083#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
7084#define GEN11_MASTER_IRQ (1 << 31)
7085#define GEN11_PCU_IRQ (1 << 30)
7086#define GEN11_DISPLAY_IRQ (1 << 16)
7087#define GEN11_GT_DW_IRQ(x) (1 << (x))
7088#define GEN11_GT_DW1_IRQ (1 << 1)
7089#define GEN11_GT_DW0_IRQ (1 << 0)
7090
7091#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
7092#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
7093#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
7094#define GEN11_DE_PCH_IRQ (1 << 23)
7095#define GEN11_DE_MISC_IRQ (1 << 22)
7096#define GEN11_DE_PORT_IRQ (1 << 20)
7097#define GEN11_DE_PIPE_C (1 << 18)
7098#define GEN11_DE_PIPE_B (1 << 17)
7099#define GEN11_DE_PIPE_A (1 << 16)
7100
7101#define GEN11_GT_INTR_DW0 _MMIO(0x190018)
7102#define GEN11_CSME (31)
7103#define GEN11_GUNIT (28)
7104#define GEN11_GUC (25)
7105#define GEN11_WDPERF (20)
7106#define GEN11_KCR (19)
7107#define GEN11_GTPM (16)
7108#define GEN11_BCS (15)
7109#define GEN11_RCS0 (0)
7110
7111#define GEN11_GT_INTR_DW1 _MMIO(0x19001c)
7112#define GEN11_VECS(x) (31 - (x))
7113#define GEN11_VCS(x) (x)
7114
7115#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + (x * 4))
7116
7117#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060)
7118#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064)
7119#define GEN11_INTR_DATA_VALID (1 << 31)
7120#define GEN11_INTR_ENGINE_MASK (0xffff)
7121
7122#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + (x * 4))
7123
7124#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070)
7125#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074)
7126
7127#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + (x * 4))
7128
7129#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030)
7130#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034)
7131#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038)
7132#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c)
7133#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040)
7134#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044)
7135
7136#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090)
7137#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0)
7138#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8)
7139#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac)
7140#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0)
7141#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8)
7142#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec)
7143#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0)
7144#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4)
7145
7146#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
7147/* Required on all Ironlake and Sandybridge according to the B-Spec. */
7148#define ILK_ELPIN_409_SELECT (1 << 25)
7149#define ILK_DPARB_GATE (1<<22)
7150#define ILK_VSDPFD_FULL (1<<21)
7151#define FUSE_STRAP _MMIO(0x42014)
7152#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
7153#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
7154#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
7155#define IVB_PIPE_C_DISABLE (1 << 28)
7156#define ILK_HDCP_DISABLE (1 << 25)
7157#define ILK_eDP_A_DISABLE (1 << 24)
7158#define HSW_CDCLK_LIMIT (1 << 24)
7159#define ILK_DESKTOP (1 << 23)
7160
7161#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
7162#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
7163#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
7164#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
7165#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
7166#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
7167
7168#define IVB_CHICKEN3 _MMIO(0x4200c)
7169# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
7170# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
7171
7172#define CHICKEN_PAR1_1 _MMIO(0x42080)
7173#define SKL_DE_COMPRESSED_HASH_MODE (1 << 15)
7174#define DPA_MASK_VBLANK_SRD (1 << 15)
7175#define FORCE_ARB_IDLE_PLANES (1 << 14)
7176#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
7177
7178#define CHICKEN_PAR2_1 _MMIO(0x42090)
7179#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14)
7180
7181#define CHICKEN_MISC_2 _MMIO(0x42084)
7182#define CNL_COMP_PWR_DOWN (1 << 23)
7183#define GLK_CL2_PWR_DOWN (1 << 12)
7184#define GLK_CL1_PWR_DOWN (1 << 11)
7185#define GLK_CL0_PWR_DOWN (1 << 10)
7186
7187#define CHICKEN_MISC_4 _MMIO(0x4208c)
7188#define FBC_STRIDE_OVERRIDE (1 << 13)
7189#define FBC_STRIDE_MASK 0x1FFF
7190
7191#define _CHICKEN_PIPESL_1_A 0x420b0
7192#define _CHICKEN_PIPESL_1_B 0x420b4
7193#define HSW_FBCQ_DIS (1 << 22)
7194#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
7195#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
7196
7197#define CHICKEN_TRANS_A 0x420c0
7198#define CHICKEN_TRANS_B 0x420c4
7199#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
7200#define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
7201#define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
7202#define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
7203#define DDIE_TRAINING_OVERRIDE_VALUE (1<<16) /* CHICKEN_TRANS_A only */
7204#define PSR2_ADD_VERTICAL_LINE_COUNT (1<<15)
7205#define PSR2_VSC_ENABLE_PROG_HEADER (1<<12)
7206
7207#define DISP_ARB_CTL _MMIO(0x45000)
7208#define DISP_FBC_MEMORY_WAKE (1<<31)
7209#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
7210#define DISP_FBC_WM_DIS (1<<15)
7211#define DISP_ARB_CTL2 _MMIO(0x45004)
7212#define DISP_DATA_PARTITION_5_6 (1<<6)
7213#define DISP_IPC_ENABLE (1<<3)
7214#define DBUF_CTL _MMIO(0x45008)
7215#define DBUF_CTL_S1 _MMIO(0x45008)
7216#define DBUF_CTL_S2 _MMIO(0x44FE8)
7217#define DBUF_POWER_REQUEST (1<<31)
7218#define DBUF_POWER_STATE (1<<30)
7219#define GEN7_MSG_CTL _MMIO(0x45010)
7220#define WAIT_FOR_PCH_RESET_ACK (1<<1)
7221#define WAIT_FOR_PCH_FLR_ACK (1<<0)
7222#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
7223#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
7224
7225#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
7226#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30)
7227#define MASK_WAKEMEM (1 << 13)
7228#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
7229
7230#define SKL_DFSM _MMIO(0x51000)
7231#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
7232#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
7233#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
7234#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
7235#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
7236#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
7237#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
7238#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
7239
7240#define SKL_DSSM _MMIO(0x51004)
7241#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
7242#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
7243#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
7244#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
7245#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
7246
7247#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
7248#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
7249
7250#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
7251#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
7252#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1<<10)
7253
7254#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
7255#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
7256#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
7257#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1<<0)
7258#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
7259#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
7260#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
7261#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
7262#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
7263
7264/* GEN7 chicken */
7265#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
7266# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
7267# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
7268#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
7269# define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
7270# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
7271# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
7272# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
7273
7274#define HIZ_CHICKEN _MMIO(0x7018)
7275# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
7276# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
7277
7278#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
7279#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
7280
7281#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
7282
7283#define GEN7_L3SQCREG1 _MMIO(0xB010)
7284#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
7285
7286#define GEN8_L3SQCREG1 _MMIO(0xB100)
7287/*
7288 * Note that on CHV the following has an off-by-one error wrt. to BSpec.
7289 * Using the formula in BSpec leads to a hang, while the formula here works
7290 * fine and matches the formulas for all other platforms. A BSpec change
7291 * request has been filed to clarify this.
7292 */
7293#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19)
7294#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
7295#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
7296
7297#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
7298#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
7299#define GEN7_L3AGDIS (1<<19)
7300#define GEN7_L3CNTLREG2 _MMIO(0xB020)
7301#define GEN7_L3CNTLREG3 _MMIO(0xB024)
7302
7303#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
7304#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
7305
7306#define GEN7_L3SQCREG4 _MMIO(0xb034)
7307#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
7308
7309#define GEN8_L3SQCREG4 _MMIO(0xb118)
7310#define GEN8_LQSC_RO_PERF_DIS (1<<27)
7311#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
7312
7313/* GEN8 chicken */
7314#define HDC_CHICKEN0 _MMIO(0x7300)
7315#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0)
7316#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
7317#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
7318#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
7319#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
7320#define HDC_FORCE_NON_COHERENT (1<<4)
7321#define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
7322
7323#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
7324
7325/* GEN9 chicken */
7326#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
7327#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
7328
7329#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
7330#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
7331
7332/* WaCatErrorRejectionIssue */
7333#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
7334#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
7335
7336#define HSW_SCRATCH1 _MMIO(0xb038)
7337#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
7338
7339#define BDW_SCRATCH1 _MMIO(0xb11c)
7340#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
7341
7342/* PCH */
7343
7344/* south display engine interrupt: IBX */
7345#define SDE_AUDIO_POWER_D (1 << 27)
7346#define SDE_AUDIO_POWER_C (1 << 26)
7347#define SDE_AUDIO_POWER_B (1 << 25)
7348#define SDE_AUDIO_POWER_SHIFT (25)
7349#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
7350#define SDE_GMBUS (1 << 24)
7351#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
7352#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
7353#define SDE_AUDIO_HDCP_MASK (3 << 22)
7354#define SDE_AUDIO_TRANSB (1 << 21)
7355#define SDE_AUDIO_TRANSA (1 << 20)
7356#define SDE_AUDIO_TRANS_MASK (3 << 20)
7357#define SDE_POISON (1 << 19)
7358/* 18 reserved */
7359#define SDE_FDI_RXB (1 << 17)
7360#define SDE_FDI_RXA (1 << 16)
7361#define SDE_FDI_MASK (3 << 16)
7362#define SDE_AUXD (1 << 15)
7363#define SDE_AUXC (1 << 14)
7364#define SDE_AUXB (1 << 13)
7365#define SDE_AUX_MASK (7 << 13)
7366/* 12 reserved */
7367#define SDE_CRT_HOTPLUG (1 << 11)
7368#define SDE_PORTD_HOTPLUG (1 << 10)
7369#define SDE_PORTC_HOTPLUG (1 << 9)
7370#define SDE_PORTB_HOTPLUG (1 << 8)
7371#define SDE_SDVOB_HOTPLUG (1 << 6)
7372#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
7373 SDE_SDVOB_HOTPLUG | \
7374 SDE_PORTB_HOTPLUG | \
7375 SDE_PORTC_HOTPLUG | \
7376 SDE_PORTD_HOTPLUG)
7377#define SDE_TRANSB_CRC_DONE (1 << 5)
7378#define SDE_TRANSB_CRC_ERR (1 << 4)
7379#define SDE_TRANSB_FIFO_UNDER (1 << 3)
7380#define SDE_TRANSA_CRC_DONE (1 << 2)
7381#define SDE_TRANSA_CRC_ERR (1 << 1)
7382#define SDE_TRANSA_FIFO_UNDER (1 << 0)
7383#define SDE_TRANS_MASK (0x3f)
7384
7385/* south display engine interrupt: CPT/PPT */
7386#define SDE_AUDIO_POWER_D_CPT (1 << 31)
7387#define SDE_AUDIO_POWER_C_CPT (1 << 30)
7388#define SDE_AUDIO_POWER_B_CPT (1 << 29)
7389#define SDE_AUDIO_POWER_SHIFT_CPT 29
7390#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
7391#define SDE_AUXD_CPT (1 << 27)
7392#define SDE_AUXC_CPT (1 << 26)
7393#define SDE_AUXB_CPT (1 << 25)
7394#define SDE_AUX_MASK_CPT (7 << 25)
7395#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
7396#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
7397#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
7398#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
7399#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
7400#define SDE_CRT_HOTPLUG_CPT (1 << 19)
7401#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
7402#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
7403 SDE_SDVOB_HOTPLUG_CPT | \
7404 SDE_PORTD_HOTPLUG_CPT | \
7405 SDE_PORTC_HOTPLUG_CPT | \
7406 SDE_PORTB_HOTPLUG_CPT)
7407#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
7408 SDE_PORTD_HOTPLUG_CPT | \
7409 SDE_PORTC_HOTPLUG_CPT | \
7410 SDE_PORTB_HOTPLUG_CPT | \
7411 SDE_PORTA_HOTPLUG_SPT)
7412#define SDE_GMBUS_CPT (1 << 17)
7413#define SDE_ERROR_CPT (1 << 16)
7414#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
7415#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
7416#define SDE_FDI_RXC_CPT (1 << 8)
7417#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
7418#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
7419#define SDE_FDI_RXB_CPT (1 << 4)
7420#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
7421#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
7422#define SDE_FDI_RXA_CPT (1 << 0)
7423#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
7424 SDE_AUDIO_CP_REQ_B_CPT | \
7425 SDE_AUDIO_CP_REQ_A_CPT)
7426#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
7427 SDE_AUDIO_CP_CHG_B_CPT | \
7428 SDE_AUDIO_CP_CHG_A_CPT)
7429#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
7430 SDE_FDI_RXB_CPT | \
7431 SDE_FDI_RXA_CPT)
7432
7433#define SDEISR _MMIO(0xc4000)
7434#define SDEIMR _MMIO(0xc4004)
7435#define SDEIIR _MMIO(0xc4008)
7436#define SDEIER _MMIO(0xc400c)
7437
7438#define SERR_INT _MMIO(0xc4040)
7439#define SERR_INT_POISON (1<<31)
7440#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
7441
7442/* digital port hotplug */
7443#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
7444#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
7445#define BXT_DDIA_HPD_INVERT (1 << 27)
7446#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
7447#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
7448#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
7449#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
7450#define PORTD_HOTPLUG_ENABLE (1 << 20)
7451#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
7452#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
7453#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
7454#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
7455#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
7456#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
7457#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
7458#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
7459#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
7460#define PORTC_HOTPLUG_ENABLE (1 << 12)
7461#define BXT_DDIC_HPD_INVERT (1 << 11)
7462#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
7463#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
7464#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
7465#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
7466#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
7467#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
7468#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
7469#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
7470#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
7471#define PORTB_HOTPLUG_ENABLE (1 << 4)
7472#define BXT_DDIB_HPD_INVERT (1 << 3)
7473#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
7474#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
7475#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
7476#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
7477#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
7478#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
7479#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
7480#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
7481#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
7482#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
7483 BXT_DDIB_HPD_INVERT | \
7484 BXT_DDIC_HPD_INVERT)
7485
7486#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
7487#define PORTE_HOTPLUG_ENABLE (1 << 4)
7488#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
7489#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
7490#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
7491#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
7492
7493#define PCH_GPIOA _MMIO(0xc5010)
7494#define PCH_GPIOB _MMIO(0xc5014)
7495#define PCH_GPIOC _MMIO(0xc5018)
7496#define PCH_GPIOD _MMIO(0xc501c)
7497#define PCH_GPIOE _MMIO(0xc5020)
7498#define PCH_GPIOF _MMIO(0xc5024)
7499
7500#define PCH_GMBUS0 _MMIO(0xc5100)
7501#define PCH_GMBUS1 _MMIO(0xc5104)
7502#define PCH_GMBUS2 _MMIO(0xc5108)
7503#define PCH_GMBUS3 _MMIO(0xc510c)
7504#define PCH_GMBUS4 _MMIO(0xc5110)
7505#define PCH_GMBUS5 _MMIO(0xc5120)
7506
7507#define _PCH_DPLL_A 0xc6014
7508#define _PCH_DPLL_B 0xc6018
7509#define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
7510
7511#define _PCH_FPA0 0xc6040
7512#define FP_CB_TUNE (0x3<<22)
7513#define _PCH_FPA1 0xc6044
7514#define _PCH_FPB0 0xc6048
7515#define _PCH_FPB1 0xc604c
7516#define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
7517#define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
7518
7519#define PCH_DPLL_TEST _MMIO(0xc606c)
7520
7521#define PCH_DREF_CONTROL _MMIO(0xC6200)
7522#define DREF_CONTROL_MASK 0x7fc3
7523#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
7524#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
7525#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
7526#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
7527#define DREF_SSC_SOURCE_DISABLE (0<<11)
7528#define DREF_SSC_SOURCE_ENABLE (2<<11)
7529#define DREF_SSC_SOURCE_MASK (3<<11)
7530#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
7531#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
7532#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
7533#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
7534#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
7535#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
7536#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
7537#define DREF_SSC4_DOWNSPREAD (0<<6)
7538#define DREF_SSC4_CENTERSPREAD (1<<6)
7539#define DREF_SSC1_DISABLE (0<<1)
7540#define DREF_SSC1_ENABLE (1<<1)
7541#define DREF_SSC4_DISABLE (0)
7542#define DREF_SSC4_ENABLE (1)
7543
7544#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
7545#define FDL_TP1_TIMER_SHIFT 12
7546#define FDL_TP1_TIMER_MASK (3<<12)
7547#define FDL_TP2_TIMER_SHIFT 10
7548#define FDL_TP2_TIMER_MASK (3<<10)
7549#define RAWCLK_FREQ_MASK 0x3ff
7550#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
7551#define CNP_RAWCLK_DIV(div) ((div) << 16)
7552#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
7553#define CNP_RAWCLK_FRAC(frac) ((frac) << 26)
7554#define ICP_RAWCLK_DEN(den) ((den) << 26)
7555#define ICP_RAWCLK_NUM(num) ((num) << 11)
7556
7557#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
7558
7559#define PCH_SSC4_PARMS _MMIO(0xc6210)
7560#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
7561
7562#define PCH_DPLL_SEL _MMIO(0xc7000)
7563#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
7564#define TRANS_DPLLA_SEL(pipe) 0
7565#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
7566
7567/* transcoder */
7568
7569#define _PCH_TRANS_HTOTAL_A 0xe0000
7570#define TRANS_HTOTAL_SHIFT 16
7571#define TRANS_HACTIVE_SHIFT 0
7572#define _PCH_TRANS_HBLANK_A 0xe0004
7573#define TRANS_HBLANK_END_SHIFT 16
7574#define TRANS_HBLANK_START_SHIFT 0
7575#define _PCH_TRANS_HSYNC_A 0xe0008
7576#define TRANS_HSYNC_END_SHIFT 16
7577#define TRANS_HSYNC_START_SHIFT 0
7578#define _PCH_TRANS_VTOTAL_A 0xe000c
7579#define TRANS_VTOTAL_SHIFT 16
7580#define TRANS_VACTIVE_SHIFT 0
7581#define _PCH_TRANS_VBLANK_A 0xe0010
7582#define TRANS_VBLANK_END_SHIFT 16
7583#define TRANS_VBLANK_START_SHIFT 0
7584#define _PCH_TRANS_VSYNC_A 0xe0014
7585#define TRANS_VSYNC_END_SHIFT 16
7586#define TRANS_VSYNC_START_SHIFT 0
7587#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
7588
7589#define _PCH_TRANSA_DATA_M1 0xe0030
7590#define _PCH_TRANSA_DATA_N1 0xe0034
7591#define _PCH_TRANSA_DATA_M2 0xe0038
7592#define _PCH_TRANSA_DATA_N2 0xe003c
7593#define _PCH_TRANSA_LINK_M1 0xe0040
7594#define _PCH_TRANSA_LINK_N1 0xe0044
7595#define _PCH_TRANSA_LINK_M2 0xe0048
7596#define _PCH_TRANSA_LINK_N2 0xe004c
7597
7598/* Per-transcoder DIP controls (PCH) */
7599#define _VIDEO_DIP_CTL_A 0xe0200
7600#define _VIDEO_DIP_DATA_A 0xe0208
7601#define _VIDEO_DIP_GCP_A 0xe0210
7602#define GCP_COLOR_INDICATION (1 << 2)
7603#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
7604#define GCP_AV_MUTE (1 << 0)
7605
7606#define _VIDEO_DIP_CTL_B 0xe1200
7607#define _VIDEO_DIP_DATA_B 0xe1208
7608#define _VIDEO_DIP_GCP_B 0xe1210
7609
7610#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
7611#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
7612#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
7613
7614/* Per-transcoder DIP controls (VLV) */
7615#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
7616#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
7617#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
7618
7619#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
7620#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
7621#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
7622
7623#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
7624#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
7625#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
7626
7627#define VLV_TVIDEO_DIP_CTL(pipe) \
7628 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
7629 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
7630#define VLV_TVIDEO_DIP_DATA(pipe) \
7631 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
7632 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
7633#define VLV_TVIDEO_DIP_GCP(pipe) \
7634 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
7635 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
7636
7637/* Haswell DIP controls */
7638
7639#define _HSW_VIDEO_DIP_CTL_A 0x60200
7640#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
7641#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
7642#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
7643#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
7644#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
7645#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
7646#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
7647#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
7648#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
7649#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
7650#define _HSW_VIDEO_DIP_GCP_A 0x60210
7651
7652#define _HSW_VIDEO_DIP_CTL_B 0x61200
7653#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
7654#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
7655#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
7656#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
7657#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
7658#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
7659#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
7660#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
7661#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
7662#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
7663#define _HSW_VIDEO_DIP_GCP_B 0x61210
7664
7665#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
7666#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
7667#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
7668#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
7669#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
7670#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
7671
7672#define _HSW_STEREO_3D_CTL_A 0x70020
7673#define S3D_ENABLE (1<<31)
7674#define _HSW_STEREO_3D_CTL_B 0x71020
7675
7676#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
7677
7678#define _PCH_TRANS_HTOTAL_B 0xe1000
7679#define _PCH_TRANS_HBLANK_B 0xe1004
7680#define _PCH_TRANS_HSYNC_B 0xe1008
7681#define _PCH_TRANS_VTOTAL_B 0xe100c
7682#define _PCH_TRANS_VBLANK_B 0xe1010
7683#define _PCH_TRANS_VSYNC_B 0xe1014
7684#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
7685
7686#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
7687#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
7688#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
7689#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
7690#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
7691#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
7692#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
7693
7694#define _PCH_TRANSB_DATA_M1 0xe1030
7695#define _PCH_TRANSB_DATA_N1 0xe1034
7696#define _PCH_TRANSB_DATA_M2 0xe1038
7697#define _PCH_TRANSB_DATA_N2 0xe103c
7698#define _PCH_TRANSB_LINK_M1 0xe1040
7699#define _PCH_TRANSB_LINK_N1 0xe1044
7700#define _PCH_TRANSB_LINK_M2 0xe1048
7701#define _PCH_TRANSB_LINK_N2 0xe104c
7702
7703#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
7704#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
7705#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
7706#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
7707#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
7708#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
7709#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
7710#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
7711
7712#define _PCH_TRANSACONF 0xf0008
7713#define _PCH_TRANSBCONF 0xf1008
7714#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
7715#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
7716#define TRANS_DISABLE (0<<31)
7717#define TRANS_ENABLE (1<<31)
7718#define TRANS_STATE_MASK (1<<30)
7719#define TRANS_STATE_DISABLE (0<<30)
7720#define TRANS_STATE_ENABLE (1<<30)
7721#define TRANS_FSYNC_DELAY_HB1 (0<<27)
7722#define TRANS_FSYNC_DELAY_HB2 (1<<27)
7723#define TRANS_FSYNC_DELAY_HB3 (2<<27)
7724#define TRANS_FSYNC_DELAY_HB4 (3<<27)
7725#define TRANS_INTERLACE_MASK (7<<21)
7726#define TRANS_PROGRESSIVE (0<<21)
7727#define TRANS_INTERLACED (3<<21)
7728#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
7729#define TRANS_8BPC (0<<5)
7730#define TRANS_10BPC (1<<5)
7731#define TRANS_6BPC (2<<5)
7732#define TRANS_12BPC (3<<5)
7733
7734#define _TRANSA_CHICKEN1 0xf0060
7735#define _TRANSB_CHICKEN1 0xf1060
7736#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
7737#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
7738#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
7739#define _TRANSA_CHICKEN2 0xf0064
7740#define _TRANSB_CHICKEN2 0xf1064
7741#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
7742#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
7743#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
7744#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
7745#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
7746#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
7747
7748#define SOUTH_CHICKEN1 _MMIO(0xc2000)
7749#define FDIA_PHASE_SYNC_SHIFT_OVR 19
7750#define FDIA_PHASE_SYNC_SHIFT_EN 18
7751#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
7752#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
7753#define FDI_BC_BIFURCATION_SELECT (1 << 12)
7754#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
7755#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
7756#define SPT_PWM_GRANULARITY (1<<0)
7757#define SOUTH_CHICKEN2 _MMIO(0xc2004)
7758#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
7759#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
7760#define LPT_PWM_GRANULARITY (1<<5)
7761#define DPLS_EDP_PPS_FIX_DIS (1<<0)
7762
7763#define _FDI_RXA_CHICKEN 0xc200c
7764#define _FDI_RXB_CHICKEN 0xc2010
7765#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
7766#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
7767#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
7768
7769#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
7770#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1<<31)
7771#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
7772#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
7773#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
7774#define CNP_PWM_CGE_GATING_DISABLE (1<<13)
7775#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
7776
7777/* CPU: FDI_TX */
7778#define _FDI_TXA_CTL 0x60100
7779#define _FDI_TXB_CTL 0x61100
7780#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
7781#define FDI_TX_DISABLE (0<<31)
7782#define FDI_TX_ENABLE (1<<31)
7783#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
7784#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
7785#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
7786#define FDI_LINK_TRAIN_NONE (3<<28)
7787#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
7788#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
7789#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
7790#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
7791#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
7792#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
7793#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
7794#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
7795/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
7796 SNB has different settings. */
7797/* SNB A-stepping */
7798#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
7799#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
7800#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
7801#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
7802/* SNB B-stepping */
7803#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
7804#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
7805#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
7806#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
7807#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
7808#define FDI_DP_PORT_WIDTH_SHIFT 19
7809#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
7810#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
7811#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
7812/* Ironlake: hardwired to 1 */
7813#define FDI_TX_PLL_ENABLE (1<<14)
7814
7815/* Ivybridge has different bits for lolz */
7816#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
7817#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
7818#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
7819#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
7820
7821/* both Tx and Rx */
7822#define FDI_COMPOSITE_SYNC (1<<11)
7823#define FDI_LINK_TRAIN_AUTO (1<<10)
7824#define FDI_SCRAMBLING_ENABLE (0<<7)
7825#define FDI_SCRAMBLING_DISABLE (1<<7)
7826
7827/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
7828#define _FDI_RXA_CTL 0xf000c
7829#define _FDI_RXB_CTL 0xf100c
7830#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
7831#define FDI_RX_ENABLE (1<<31)
7832/* train, dp width same as FDI_TX */
7833#define FDI_FS_ERRC_ENABLE (1<<27)
7834#define FDI_FE_ERRC_ENABLE (1<<26)
7835#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
7836#define FDI_8BPC (0<<16)
7837#define FDI_10BPC (1<<16)
7838#define FDI_6BPC (2<<16)
7839#define FDI_12BPC (3<<16)
7840#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
7841#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
7842#define FDI_RX_PLL_ENABLE (1<<13)
7843#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
7844#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
7845#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
7846#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
7847#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
7848#define FDI_PCDCLK (1<<4)
7849/* CPT */
7850#define FDI_AUTO_TRAINING (1<<10)
7851#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
7852#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
7853#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
7854#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
7855#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
7856
7857#define _FDI_RXA_MISC 0xf0010
7858#define _FDI_RXB_MISC 0xf1010
7859#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
7860#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
7861#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
7862#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
7863#define FDI_RX_TP1_TO_TP2_48 (2<<20)
7864#define FDI_RX_TP1_TO_TP2_64 (3<<20)
7865#define FDI_RX_FDI_DELAY_90 (0x90<<0)
7866#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
7867
7868#define _FDI_RXA_TUSIZE1 0xf0030
7869#define _FDI_RXA_TUSIZE2 0xf0038
7870#define _FDI_RXB_TUSIZE1 0xf1030
7871#define _FDI_RXB_TUSIZE2 0xf1038
7872#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
7873#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
7874
7875/* FDI_RX interrupt register format */
7876#define FDI_RX_INTER_LANE_ALIGN (1<<10)
7877#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
7878#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
7879#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
7880#define FDI_RX_FS_CODE_ERR (1<<6)
7881#define FDI_RX_FE_CODE_ERR (1<<5)
7882#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
7883#define FDI_RX_HDCP_LINK_FAIL (1<<3)
7884#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
7885#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
7886#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
7887
7888#define _FDI_RXA_IIR 0xf0014
7889#define _FDI_RXA_IMR 0xf0018
7890#define _FDI_RXB_IIR 0xf1014
7891#define _FDI_RXB_IMR 0xf1018
7892#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
7893#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
7894
7895#define FDI_PLL_CTL_1 _MMIO(0xfe000)
7896#define FDI_PLL_CTL_2 _MMIO(0xfe004)
7897
7898#define PCH_LVDS _MMIO(0xe1180)
7899#define LVDS_DETECTED (1 << 1)
7900
7901#define _PCH_DP_B 0xe4100
7902#define PCH_DP_B _MMIO(_PCH_DP_B)
7903#define _PCH_DPB_AUX_CH_CTL 0xe4110
7904#define _PCH_DPB_AUX_CH_DATA1 0xe4114
7905#define _PCH_DPB_AUX_CH_DATA2 0xe4118
7906#define _PCH_DPB_AUX_CH_DATA3 0xe411c
7907#define _PCH_DPB_AUX_CH_DATA4 0xe4120
7908#define _PCH_DPB_AUX_CH_DATA5 0xe4124
7909
7910#define _PCH_DP_C 0xe4200
7911#define PCH_DP_C _MMIO(_PCH_DP_C)
7912#define _PCH_DPC_AUX_CH_CTL 0xe4210
7913#define _PCH_DPC_AUX_CH_DATA1 0xe4214
7914#define _PCH_DPC_AUX_CH_DATA2 0xe4218
7915#define _PCH_DPC_AUX_CH_DATA3 0xe421c
7916#define _PCH_DPC_AUX_CH_DATA4 0xe4220
7917#define _PCH_DPC_AUX_CH_DATA5 0xe4224
7918
7919#define _PCH_DP_D 0xe4300
7920#define PCH_DP_D _MMIO(_PCH_DP_D)
7921#define _PCH_DPD_AUX_CH_CTL 0xe4310
7922#define _PCH_DPD_AUX_CH_DATA1 0xe4314
7923#define _PCH_DPD_AUX_CH_DATA2 0xe4318
7924#define _PCH_DPD_AUX_CH_DATA3 0xe431c
7925#define _PCH_DPD_AUX_CH_DATA4 0xe4320
7926#define _PCH_DPD_AUX_CH_DATA5 0xe4324
7927
7928#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
7929#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
7930
7931/* CPT */
7932#define PORT_TRANS_A_SEL_CPT 0
7933#define PORT_TRANS_B_SEL_CPT (1<<29)
7934#define PORT_TRANS_C_SEL_CPT (2<<29)
7935#define PORT_TRANS_SEL_MASK (3<<29)
7936#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
7937#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
7938#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
7939#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
7940#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
7941
7942#define _TRANS_DP_CTL_A 0xe0300
7943#define _TRANS_DP_CTL_B 0xe1300
7944#define _TRANS_DP_CTL_C 0xe2300
7945#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
7946#define TRANS_DP_OUTPUT_ENABLE (1<<31)
7947#define TRANS_DP_PORT_SEL_B (0<<29)
7948#define TRANS_DP_PORT_SEL_C (1<<29)
7949#define TRANS_DP_PORT_SEL_D (2<<29)
7950#define TRANS_DP_PORT_SEL_NONE (3<<29)
7951#define TRANS_DP_PORT_SEL_MASK (3<<29)
7952#define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
7953#define TRANS_DP_AUDIO_ONLY (1<<26)
7954#define TRANS_DP_ENH_FRAMING (1<<18)
7955#define TRANS_DP_8BPC (0<<9)
7956#define TRANS_DP_10BPC (1<<9)
7957#define TRANS_DP_6BPC (2<<9)
7958#define TRANS_DP_12BPC (3<<9)
7959#define TRANS_DP_BPC_MASK (3<<9)
7960#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
7961#define TRANS_DP_VSYNC_ACTIVE_LOW 0
7962#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
7963#define TRANS_DP_HSYNC_ACTIVE_LOW 0
7964#define TRANS_DP_SYNC_MASK (3<<3)
7965
7966/* SNB eDP training params */
7967/* SNB A-stepping */
7968#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
7969#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
7970#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
7971#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
7972/* SNB B-stepping */
7973#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
7974#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
7975#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
7976#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
7977#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
7978#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
7979
7980/* IVB */
7981#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
7982#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
7983#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
7984#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
7985#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
7986#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
7987#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
7988
7989/* legacy values */
7990#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
7991#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
7992#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
7993#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
7994#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
7995
7996#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
7997
7998#define VLV_PMWGICZ _MMIO(0x1300a4)
7999
8000#define RC6_LOCATION _MMIO(0xD40)
8001#define RC6_CTX_IN_DRAM (1 << 0)
8002#define RC6_CTX_BASE _MMIO(0xD48)
8003#define RC6_CTX_BASE_MASK 0xFFFFFFF0
8004#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
8005#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
8006#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
8007#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
8008#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
8009#define IDLE_TIME_MASK 0xFFFFF
8010#define FORCEWAKE _MMIO(0xA18C)
8011#define FORCEWAKE_VLV _MMIO(0x1300b0)
8012#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
8013#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
8014#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
8015#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
8016#define FORCEWAKE_ACK _MMIO(0x130090)
8017#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
8018#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
8019#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
8020#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
8021
8022#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
8023#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
8024#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
8025#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
8026#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
8027#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
8028#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
8029#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4)
8030#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4)
8031#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
8032#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
8033#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
8034#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4)
8035#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4)
8036#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
8037#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
8038#define FORCEWAKE_KERNEL BIT(0)
8039#define FORCEWAKE_USER BIT(1)
8040#define FORCEWAKE_KERNEL_FALLBACK BIT(15)
8041#define FORCEWAKE_MT_ACK _MMIO(0x130040)
8042#define ECOBUS _MMIO(0xa180)
8043#define FORCEWAKE_MT_ENABLE (1<<5)
8044#define VLV_SPAREG2H _MMIO(0xA194)
8045#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0)
8046#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
8047#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
8048
8049#define GTFIFODBG _MMIO(0x120000)
8050#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
8051#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
8052#define GT_FIFO_SBDROPERR (1<<6)
8053#define GT_FIFO_BLOBDROPERR (1<<5)
8054#define GT_FIFO_SB_READ_ABORTERR (1<<4)
8055#define GT_FIFO_DROPERR (1<<3)
8056#define GT_FIFO_OVFERR (1<<2)
8057#define GT_FIFO_IAWRERR (1<<1)
8058#define GT_FIFO_IARDERR (1<<0)
8059
8060#define GTFIFOCTL _MMIO(0x120008)
8061#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
8062#define GT_FIFO_NUM_RESERVED_ENTRIES 20
8063#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
8064#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
8065
8066#define HSW_IDICR _MMIO(0x9008)
8067#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
8068#define HSW_EDRAM_CAP _MMIO(0x120010)
8069#define EDRAM_ENABLED 0x1
8070#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
8071#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
8072#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
8073
8074#define GEN6_UCGCTL1 _MMIO(0x9400)
8075# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
8076# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
8077# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
8078# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
8079
8080#define GEN6_UCGCTL2 _MMIO(0x9404)
8081# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
8082# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
8083# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
8084# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
8085# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
8086# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
8087
8088#define GEN6_UCGCTL3 _MMIO(0x9408)
8089# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20)
8090
8091#define GEN7_UCGCTL4 _MMIO(0x940c)
8092#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
8093#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
8094
8095#define GEN6_RCGCTL1 _MMIO(0x9410)
8096#define GEN6_RCGCTL2 _MMIO(0x9414)
8097#define GEN6_RSTCTL _MMIO(0x9420)
8098
8099#define GEN8_UCGCTL6 _MMIO(0x9430)
8100#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
8101#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
8102#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
8103
8104#define GEN6_GFXPAUSE _MMIO(0xA000)
8105#define GEN6_RPNSWREQ _MMIO(0xA008)
8106#define GEN6_TURBO_DISABLE (1<<31)
8107#define GEN6_FREQUENCY(x) ((x)<<25)
8108#define HSW_FREQUENCY(x) ((x)<<24)
8109#define GEN9_FREQUENCY(x) ((x)<<23)
8110#define GEN6_OFFSET(x) ((x)<<19)
8111#define GEN6_AGGRESSIVE_TURBO (0<<15)
8112#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
8113#define GEN6_RC_CONTROL _MMIO(0xA090)
8114#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
8115#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
8116#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
8117#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
8118#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
8119#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
8120#define GEN7_RC_CTL_TO_MODE (1<<28)
8121#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
8122#define GEN6_RC_CTL_HW_ENABLE (1<<31)
8123#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
8124#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
8125#define GEN6_RPSTAT1 _MMIO(0xA01C)
8126#define GEN6_CAGF_SHIFT 8
8127#define HSW_CAGF_SHIFT 7
8128#define GEN9_CAGF_SHIFT 23
8129#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
8130#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
8131#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
8132#define GEN6_RP_CONTROL _MMIO(0xA024)
8133#define GEN6_RP_MEDIA_TURBO (1<<11)
8134#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
8135#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
8136#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
8137#define GEN6_RP_MEDIA_HW_MODE (1<<9)
8138#define GEN6_RP_MEDIA_SW_MODE (0<<9)
8139#define GEN6_RP_MEDIA_IS_GFX (1<<8)
8140#define GEN6_RP_ENABLE (1<<7)
8141#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
8142#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
8143#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
8144#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
8145#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
8146#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
8147#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
8148#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
8149#define GEN6_RP_EI_MASK 0xffffff
8150#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK
8151#define GEN6_RP_CUR_UP _MMIO(0xA054)
8152#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK
8153#define GEN6_RP_PREV_UP _MMIO(0xA058)
8154#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
8155#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK
8156#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
8157#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
8158#define GEN6_RP_UP_EI _MMIO(0xA068)
8159#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
8160#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
8161#define GEN6_RPDEUHWTC _MMIO(0xA080)
8162#define GEN6_RPDEUC _MMIO(0xA084)
8163#define GEN6_RPDEUCSW _MMIO(0xA088)
8164#define GEN6_RC_STATE _MMIO(0xA094)
8165#define RC_SW_TARGET_STATE_SHIFT 16
8166#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT)
8167#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
8168#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
8169#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8170#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0)
8171#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
8172#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
8173#define GEN6_RC_SLEEP _MMIO(0xA0B0)
8174#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
8175#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
8176#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
8177#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
8178#define VLV_RCEDATA _MMIO(0xA0BC)
8179#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
8180#define GEN6_PMINTRMSK _MMIO(0xA168)
8181#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1<<31)
8182#define ARAT_EXPIRED_INTRMSK (1<<9)
8183#define GEN8_MISC_CTRL0 _MMIO(0xA180)
8184#define VLV_PWRDWNUPCTL _MMIO(0xA294)
8185#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
8186#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
8187#define GEN9_PG_ENABLE _MMIO(0xA210)
8188#define GEN9_RENDER_PG_ENABLE (1<<0)
8189#define GEN9_MEDIA_PG_ENABLE (1<<1)
8190#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
8191#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
8192#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
8193
8194#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
8195#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
8196#define PIXEL_OVERLAP_CNT_SHIFT 30
8197
8198#define GEN6_PMISR _MMIO(0x44020)
8199#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
8200#define GEN6_PMIIR _MMIO(0x44028)
8201#define GEN6_PMIER _MMIO(0x4402C)
8202#define GEN6_PM_MBOX_EVENT (1<<25)
8203#define GEN6_PM_THERMAL_EVENT (1<<24)
8204#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
8205#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
8206#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
8207#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
8208#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
8209#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
8210 GEN6_PM_RP_DOWN_THRESHOLD | \
8211 GEN6_PM_RP_DOWN_TIMEOUT)
8212
8213#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
8214#define GEN7_GT_SCRATCH_REG_NUM 8
8215
8216#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
8217#define VLV_GFX_CLK_STATUS_BIT (1<<3)
8218#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
8219
8220#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
8221#define VLV_COUNTER_CONTROL _MMIO(0x138104)
8222#define VLV_COUNT_RANGE_HIGH (1<<15)
8223#define VLV_MEDIA_RC0_COUNT_EN (1<<5)
8224#define VLV_RENDER_RC0_COUNT_EN (1<<4)
8225#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
8226#define VLV_RENDER_RC6_COUNT_EN (1<<0)
8227#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
8228#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
8229#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
8230
8231#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
8232#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
8233#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
8234#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
8235
8236#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8237#define GEN6_PCODE_READY (1<<31)
8238#define GEN6_PCODE_ERROR_MASK 0xFF
8239#define GEN6_PCODE_SUCCESS 0x0
8240#define GEN6_PCODE_ILLEGAL_CMD 0x1
8241#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
8242#define GEN6_PCODE_TIMEOUT 0x3
8243#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
8244#define GEN7_PCODE_TIMEOUT 0x2
8245#define GEN7_PCODE_ILLEGAL_DATA 0x3
8246#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
8247#define GEN6_PCODE_WRITE_RC6VIDS 0x4
8248#define GEN6_PCODE_READ_RC6VIDS 0x5
8249#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
8250#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
8251#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
8252#define GEN9_PCODE_READ_MEM_LATENCY 0x6
8253#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
8254#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
8255#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
8256#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
8257#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
8258#define SKL_PCODE_CDCLK_CONTROL 0x7
8259#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
8260#define SKL_CDCLK_READY_FOR_CHANGE 0x1
8261#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
8262#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
8263#define GEN6_READ_OC_PARAMS 0xc
8264#define GEN6_PCODE_READ_D_COMP 0x10
8265#define GEN6_PCODE_WRITE_D_COMP 0x11
8266#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
8267#define DISPLAY_IPS_CONTROL 0x19
8268 /* See also IPS_CTL */
8269#define IPS_PCODE_CONTROL (1 << 30)
8270#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
8271#define GEN9_PCODE_SAGV_CONTROL 0x21
8272#define GEN9_SAGV_DISABLE 0x0
8273#define GEN9_SAGV_IS_DISABLED 0x1
8274#define GEN9_SAGV_ENABLE 0x3
8275#define GEN6_PCODE_DATA _MMIO(0x138128)
8276#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
8277#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
8278#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
8279
8280#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
8281#define GEN6_CORE_CPD_STATE_MASK (7<<4)
8282#define GEN6_RCn_MASK 7
8283#define GEN6_RC0 0
8284#define GEN6_RC3 2
8285#define GEN6_RC6 3
8286#define GEN6_RC7 4
8287
8288#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
8289#define GEN8_LSLICESTAT_MASK 0x7
8290
8291#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
8292#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
8293#define CHV_SS_PG_ENABLE (1<<1)
8294#define CHV_EU08_PG_ENABLE (1<<9)
8295#define CHV_EU19_PG_ENABLE (1<<17)
8296#define CHV_EU210_PG_ENABLE (1<<25)
8297
8298#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
8299#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
8300#define CHV_EU311_PG_ENABLE (1<<1)
8301
8302#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
8303#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
8304 ((slice) % 3) * 0x4)
8305#define GEN9_PGCTL_SLICE_ACK (1 << 0)
8306#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
8307#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
8308
8309#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
8310#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \
8311 ((slice) % 3) * 0x8)
8312#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
8313#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \
8314 ((slice) % 3) * 0x8)
8315#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
8316#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
8317#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
8318#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
8319#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
8320#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
8321#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
8322#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
8323
8324#define GEN7_MISCCPCTL _MMIO(0x9424)
8325#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
8326#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
8327#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
8328#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
8329
8330#define GEN8_GARBCNTL _MMIO(0xB004)
8331#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
8332
8333/* IVYBRIDGE DPF */
8334#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
8335#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
8336#define GEN7_PARITY_ERROR_VALID (1<<13)
8337#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
8338#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
8339#define GEN7_PARITY_ERROR_ROW(reg) \
8340 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
8341#define GEN7_PARITY_ERROR_BANK(reg) \
8342 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
8343#define GEN7_PARITY_ERROR_SUBBANK(reg) \
8344 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
8345#define GEN7_L3CDERRST1_ENABLE (1<<7)
8346
8347#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
8348#define GEN7_L3LOG_SIZE 0x80
8349
8350#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
8351#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
8352#define GEN7_MAX_PS_THREAD_DEP (8<<12)
8353#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
8354#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
8355#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
8356
8357#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
8358#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
8359#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
8360
8361#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
8362#define FLOW_CONTROL_ENABLE (1<<15)
8363#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
8364#define STALL_DOP_GATING_DISABLE (1<<5)
8365#define THROTTLE_12_5 (7<<2)
8366#define DISABLE_EARLY_EOT (1<<1)
8367
8368#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
8369#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
8370#define DOP_CLOCK_GATING_DISABLE (1<<0)
8371#define PUSH_CONSTANT_DEREF_DISABLE (1<<8)
8372
8373#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
8374#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
8375
8376#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
8377#define GEN8_ST_PO_DISABLE (1<<13)
8378
8379#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
8380#define HSW_SAMPLE_C_PERFORMANCE (1<<9)
8381#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
8382#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
8383#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4)
8384#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
8385
8386#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
8387#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1<<8)
8388#define GEN9_ENABLE_YV12_BUGFIX (1<<4)
8389#define GEN9_ENABLE_GPGPU_PREEMPTION (1<<2)
8390
8391/* Audio */
8392#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
8393#define INTEL_AUDIO_DEVCL 0x808629FB
8394#define INTEL_AUDIO_DEVBLC 0x80862801
8395#define INTEL_AUDIO_DEVCTG 0x80862802
8396
8397#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
8398#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
8399#define G4X_ELDV_DEVCTG (1 << 14)
8400#define G4X_ELD_ADDR_MASK (0xf << 5)
8401#define G4X_ELD_ACK (1 << 4)
8402#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
8403
8404#define _IBX_HDMIW_HDMIEDID_A 0xE2050
8405#define _IBX_HDMIW_HDMIEDID_B 0xE2150
8406#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
8407 _IBX_HDMIW_HDMIEDID_B)
8408#define _IBX_AUD_CNTL_ST_A 0xE20B4
8409#define _IBX_AUD_CNTL_ST_B 0xE21B4
8410#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
8411 _IBX_AUD_CNTL_ST_B)
8412#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
8413#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
8414#define IBX_ELD_ACK (1 << 4)
8415#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
8416#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
8417#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
8418
8419#define _CPT_HDMIW_HDMIEDID_A 0xE5050
8420#define _CPT_HDMIW_HDMIEDID_B 0xE5150
8421#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
8422#define _CPT_AUD_CNTL_ST_A 0xE50B4
8423#define _CPT_AUD_CNTL_ST_B 0xE51B4
8424#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
8425#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
8426
8427#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
8428#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
8429#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
8430#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
8431#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
8432#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
8433#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
8434
8435/* These are the 4 32-bit write offset registers for each stream
8436 * output buffer. It determines the offset from the
8437 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
8438 */
8439#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
8440
8441#define _IBX_AUD_CONFIG_A 0xe2000
8442#define _IBX_AUD_CONFIG_B 0xe2100
8443#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
8444#define _CPT_AUD_CONFIG_A 0xe5000
8445#define _CPT_AUD_CONFIG_B 0xe5100
8446#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
8447#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
8448#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
8449#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
8450
8451#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
8452#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
8453#define AUD_CONFIG_UPPER_N_SHIFT 20
8454#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
8455#define AUD_CONFIG_LOWER_N_SHIFT 4
8456#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
8457#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)
8458#define AUD_CONFIG_N(n) \
8459 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \
8460 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))
8461#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
8462#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
8463#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
8464#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
8465#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
8466#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
8467#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
8468#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
8469#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
8470#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
8471#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
8472#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
8473#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
8474
8475/* HSW Audio */
8476#define _HSW_AUD_CONFIG_A 0x65000
8477#define _HSW_AUD_CONFIG_B 0x65100
8478#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
8479
8480#define _HSW_AUD_MISC_CTRL_A 0x65010
8481#define _HSW_AUD_MISC_CTRL_B 0x65110
8482#define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
8483
8484#define _HSW_AUD_M_CTS_ENABLE_A 0x65028
8485#define _HSW_AUD_M_CTS_ENABLE_B 0x65128
8486#define HSW_AUD_M_CTS_ENABLE(pipe) _MMIO_PIPE(pipe, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)
8487#define AUD_M_CTS_M_VALUE_INDEX (1 << 21)
8488#define AUD_M_CTS_M_PROG_ENABLE (1 << 20)
8489#define AUD_CONFIG_M_MASK 0xfffff
8490
8491#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
8492#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
8493#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
8494
8495/* Audio Digital Converter */
8496#define _HSW_AUD_DIG_CNVT_1 0x65080
8497#define _HSW_AUD_DIG_CNVT_2 0x65180
8498#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
8499#define DIP_PORT_SEL_MASK 0x3
8500
8501#define _HSW_AUD_EDID_DATA_A 0x65050
8502#define _HSW_AUD_EDID_DATA_B 0x65150
8503#define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
8504
8505#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
8506#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
8507#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
8508#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
8509#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
8510#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
8511
8512#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
8513#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
8514
8515/* HSW Power Wells */
8516#define _HSW_PWR_WELL_CTL1 0x45400
8517#define _HSW_PWR_WELL_CTL2 0x45404
8518#define _HSW_PWR_WELL_CTL3 0x45408
8519#define _HSW_PWR_WELL_CTL4 0x4540C
8520
8521/*
8522 * Each power well control register contains up to 16 (request, status) HW
8523 * flag tuples. The register index and HW flag shift is determined by the
8524 * power well ID (see i915_power_well_id). There are 4 possible sources of
8525 * power well requests each source having its own set of control registers:
8526 * BIOS, DRIVER, KVMR, DEBUG.
8527 */
8528#define _HSW_PW_REG_IDX(pw) ((pw) >> 4)
8529#define _HSW_PW_SHIFT(pw) (((pw) & 0xf) * 2)
8530/* TODO: Add all PWR_WELL_CTL registers below for new platforms */
8531#define HSW_PWR_WELL_CTL_BIOS(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8532 _HSW_PWR_WELL_CTL1))
8533#define HSW_PWR_WELL_CTL_DRIVER(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8534 _HSW_PWR_WELL_CTL2))
8535#define HSW_PWR_WELL_CTL_KVMR _MMIO(_HSW_PWR_WELL_CTL3)
8536#define HSW_PWR_WELL_CTL_DEBUG(pw) _MMIO(_PICK(_HSW_PW_REG_IDX(pw), \
8537 _HSW_PWR_WELL_CTL4))
8538
8539#define HSW_PWR_WELL_CTL_REQ(pw) (1 << (_HSW_PW_SHIFT(pw) + 1))
8540#define HSW_PWR_WELL_CTL_STATE(pw) (1 << _HSW_PW_SHIFT(pw))
8541#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
8542#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
8543#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
8544#define HSW_PWR_WELL_FORCE_ON (1<<19)
8545#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
8546
8547/* SKL Fuse Status */
8548enum skl_power_gate {
8549 SKL_PG0,
8550 SKL_PG1,
8551 SKL_PG2,
8552};
8553
8554#define SKL_FUSE_STATUS _MMIO(0x42000)
8555#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
8556/* PG0 (HW control->no power well ID), PG1..PG2 (SKL_DISP_PW1..SKL_DISP_PW2) */
8557#define SKL_PW_TO_PG(pw) ((pw) - SKL_DISP_PW_1 + SKL_PG1)
8558#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
8559
8560#define _CNL_AUX_REG_IDX(pw) ((pw) - 9)
8561#define _CNL_AUX_ANAOVRD1_B 0x162250
8562#define _CNL_AUX_ANAOVRD1_C 0x162210
8563#define _CNL_AUX_ANAOVRD1_D 0x1622D0
8564#define _CNL_AUX_ANAOVRD1_F 0x162A90
8565#define CNL_AUX_ANAOVRD1(pw) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
8566 _CNL_AUX_ANAOVRD1_B, \
8567 _CNL_AUX_ANAOVRD1_C, \
8568 _CNL_AUX_ANAOVRD1_D, \
8569 _CNL_AUX_ANAOVRD1_F))
8570#define CNL_AUX_ANAOVRD1_ENABLE (1<<16)
8571#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1<<23)
8572
8573/* HDCP Key Registers */
8574#define HDCP_KEY_CONF _MMIO(0x66c00)
8575#define HDCP_AKSV_SEND_TRIGGER BIT(31)
8576#define HDCP_CLEAR_KEYS_TRIGGER BIT(30)
8577#define HDCP_KEY_LOAD_TRIGGER BIT(8)
8578#define HDCP_KEY_STATUS _MMIO(0x66c04)
8579#define HDCP_FUSE_IN_PROGRESS BIT(7)
8580#define HDCP_FUSE_ERROR BIT(6)
8581#define HDCP_FUSE_DONE BIT(5)
8582#define HDCP_KEY_LOAD_STATUS BIT(1)
8583#define HDCP_KEY_LOAD_DONE BIT(0)
8584#define HDCP_AKSV_LO _MMIO(0x66c10)
8585#define HDCP_AKSV_HI _MMIO(0x66c14)
8586
8587/* HDCP Repeater Registers */
8588#define HDCP_REP_CTL _MMIO(0x66d00)
8589#define HDCP_DDIB_REP_PRESENT BIT(30)
8590#define HDCP_DDIA_REP_PRESENT BIT(29)
8591#define HDCP_DDIC_REP_PRESENT BIT(28)
8592#define HDCP_DDID_REP_PRESENT BIT(27)
8593#define HDCP_DDIF_REP_PRESENT BIT(26)
8594#define HDCP_DDIE_REP_PRESENT BIT(25)
8595#define HDCP_DDIB_SHA1_M0 (1 << 20)
8596#define HDCP_DDIA_SHA1_M0 (2 << 20)
8597#define HDCP_DDIC_SHA1_M0 (3 << 20)
8598#define HDCP_DDID_SHA1_M0 (4 << 20)
8599#define HDCP_DDIF_SHA1_M0 (5 << 20)
8600#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */
8601#define HDCP_SHA1_BUSY BIT(16)
8602#define HDCP_SHA1_READY BIT(17)
8603#define HDCP_SHA1_COMPLETE BIT(18)
8604#define HDCP_SHA1_V_MATCH BIT(19)
8605#define HDCP_SHA1_TEXT_32 (1 << 1)
8606#define HDCP_SHA1_COMPLETE_HASH (2 << 1)
8607#define HDCP_SHA1_TEXT_24 (4 << 1)
8608#define HDCP_SHA1_TEXT_16 (5 << 1)
8609#define HDCP_SHA1_TEXT_8 (6 << 1)
8610#define HDCP_SHA1_TEXT_0 (7 << 1)
8611#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
8612#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
8613#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
8614#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
8615#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
8616#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + h * 4))
8617#define HDCP_SHA_TEXT _MMIO(0x66d18)
8618
8619/* HDCP Auth Registers */
8620#define _PORTA_HDCP_AUTHENC 0x66800
8621#define _PORTB_HDCP_AUTHENC 0x66500
8622#define _PORTC_HDCP_AUTHENC 0x66600
8623#define _PORTD_HDCP_AUTHENC 0x66700
8624#define _PORTE_HDCP_AUTHENC 0x66A00
8625#define _PORTF_HDCP_AUTHENC 0x66900
8626#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \
8627 _PORTA_HDCP_AUTHENC, \
8628 _PORTB_HDCP_AUTHENC, \
8629 _PORTC_HDCP_AUTHENC, \
8630 _PORTD_HDCP_AUTHENC, \
8631 _PORTE_HDCP_AUTHENC, \
8632 _PORTF_HDCP_AUTHENC) + x)
8633#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0)
8634#define HDCP_CONF_CAPTURE_AN BIT(0)
8635#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0))
8636#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4)
8637#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8)
8638#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC)
8639#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10)
8640#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14)
8641#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18)
8642#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C)
8643#define HDCP_STATUS_STREAM_A_ENC BIT(31)
8644#define HDCP_STATUS_STREAM_B_ENC BIT(30)
8645#define HDCP_STATUS_STREAM_C_ENC BIT(29)
8646#define HDCP_STATUS_STREAM_D_ENC BIT(28)
8647#define HDCP_STATUS_AUTH BIT(21)
8648#define HDCP_STATUS_ENC BIT(20)
8649#define HDCP_STATUS_RI_MATCH BIT(19)
8650#define HDCP_STATUS_R0_READY BIT(18)
8651#define HDCP_STATUS_AN_READY BIT(17)
8652#define HDCP_STATUS_CIPHER BIT(16)
8653#define HDCP_STATUS_FRAME_CNT(x) ((x >> 8) & 0xff)
8654
8655/* Per-pipe DDI Function Control */
8656#define _TRANS_DDI_FUNC_CTL_A 0x60400
8657#define _TRANS_DDI_FUNC_CTL_B 0x61400
8658#define _TRANS_DDI_FUNC_CTL_C 0x62400
8659#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
8660#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
8661
8662#define TRANS_DDI_FUNC_ENABLE (1<<31)
8663/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
8664#define TRANS_DDI_PORT_MASK (7<<28)
8665#define TRANS_DDI_PORT_SHIFT 28
8666#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
8667#define TRANS_DDI_PORT_NONE (0<<28)
8668#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
8669#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
8670#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
8671#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
8672#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
8673#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
8674#define TRANS_DDI_BPC_MASK (7<<20)
8675#define TRANS_DDI_BPC_8 (0<<20)
8676#define TRANS_DDI_BPC_10 (1<<20)
8677#define TRANS_DDI_BPC_6 (2<<20)
8678#define TRANS_DDI_BPC_12 (3<<20)
8679#define TRANS_DDI_PVSYNC (1<<17)
8680#define TRANS_DDI_PHSYNC (1<<16)
8681#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
8682#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
8683#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
8684#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
8685#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
8686#define TRANS_DDI_HDCP_SIGNALLING (1<<9)
8687#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
8688#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7)
8689#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6)
8690#define TRANS_DDI_BFI_ENABLE (1<<4)
8691#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1<<4)
8692#define TRANS_DDI_HDMI_SCRAMBLING (1<<0)
8693#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
8694 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
8695 | TRANS_DDI_HDMI_SCRAMBLING)
8696
8697/* DisplayPort Transport Control */
8698#define _DP_TP_CTL_A 0x64040
8699#define _DP_TP_CTL_B 0x64140
8700#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
8701#define DP_TP_CTL_ENABLE (1<<31)
8702#define DP_TP_CTL_MODE_SST (0<<27)
8703#define DP_TP_CTL_MODE_MST (1<<27)
8704#define DP_TP_CTL_FORCE_ACT (1<<25)
8705#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
8706#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
8707#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
8708#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
8709#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
8710#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
8711#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
8712#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
8713#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
8714
8715/* DisplayPort Transport Status */
8716#define _DP_TP_STATUS_A 0x64044
8717#define _DP_TP_STATUS_B 0x64144
8718#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
8719#define DP_TP_STATUS_IDLE_DONE (1<<25)
8720#define DP_TP_STATUS_ACT_SENT (1<<24)
8721#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
8722#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
8723#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
8724#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
8725#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
8726
8727/* DDI Buffer Control */
8728#define _DDI_BUF_CTL_A 0x64000
8729#define _DDI_BUF_CTL_B 0x64100
8730#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
8731#define DDI_BUF_CTL_ENABLE (1<<31)
8732#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
8733#define DDI_BUF_EMP_MASK (0xf<<24)
8734#define DDI_BUF_PORT_REVERSAL (1<<16)
8735#define DDI_BUF_IS_IDLE (1<<7)
8736#define DDI_A_4_LANES (1<<4)
8737#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
8738#define DDI_PORT_WIDTH_MASK (7 << 1)
8739#define DDI_PORT_WIDTH_SHIFT 1
8740#define DDI_INIT_DISPLAY_DETECTED (1<<0)
8741
8742/* DDI Buffer Translations */
8743#define _DDI_BUF_TRANS_A 0x64E00
8744#define _DDI_BUF_TRANS_B 0x64E60
8745#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
8746#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
8747#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
8748
8749/* Sideband Interface (SBI) is programmed indirectly, via
8750 * SBI_ADDR, which contains the register offset; and SBI_DATA,
8751 * which contains the payload */
8752#define SBI_ADDR _MMIO(0xC6000)
8753#define SBI_DATA _MMIO(0xC6004)
8754#define SBI_CTL_STAT _MMIO(0xC6008)
8755#define SBI_CTL_DEST_ICLK (0x0<<16)
8756#define SBI_CTL_DEST_MPHY (0x1<<16)
8757#define SBI_CTL_OP_IORD (0x2<<8)
8758#define SBI_CTL_OP_IOWR (0x3<<8)
8759#define SBI_CTL_OP_CRRD (0x6<<8)
8760#define SBI_CTL_OP_CRWR (0x7<<8)
8761#define SBI_RESPONSE_FAIL (0x1<<1)
8762#define SBI_RESPONSE_SUCCESS (0x0<<1)
8763#define SBI_BUSY (0x1<<0)
8764#define SBI_READY (0x0<<0)
8765
8766/* SBI offsets */
8767#define SBI_SSCDIVINTPHASE 0x0200
8768#define SBI_SSCDIVINTPHASE6 0x0600
8769#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
8770#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1)
8771#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
8772#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
8773#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8)
8774#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
8775#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
8776#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
8777#define SBI_SSCDITHPHASE 0x0204
8778#define SBI_SSCCTL 0x020c
8779#define SBI_SSCCTL6 0x060C
8780#define SBI_SSCCTL_PATHALT (1<<3)
8781#define SBI_SSCCTL_DISABLE (1<<0)
8782#define SBI_SSCAUXDIV6 0x0610
8783#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
8784#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4)
8785#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
8786#define SBI_DBUFF0 0x2a00
8787#define SBI_GEN0 0x1f00
8788#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
8789
8790/* LPT PIXCLK_GATE */
8791#define PIXCLK_GATE _MMIO(0xC6020)
8792#define PIXCLK_GATE_UNGATE (1<<0)
8793#define PIXCLK_GATE_GATE (0<<0)
8794
8795/* SPLL */
8796#define SPLL_CTL _MMIO(0x46020)
8797#define SPLL_PLL_ENABLE (1<<31)
8798#define SPLL_PLL_SSC (1<<28)
8799#define SPLL_PLL_NON_SSC (2<<28)
8800#define SPLL_PLL_LCPLL (3<<28)
8801#define SPLL_PLL_REF_MASK (3<<28)
8802#define SPLL_PLL_FREQ_810MHz (0<<26)
8803#define SPLL_PLL_FREQ_1350MHz (1<<26)
8804#define SPLL_PLL_FREQ_2700MHz (2<<26)
8805#define SPLL_PLL_FREQ_MASK (3<<26)
8806
8807/* WRPLL */
8808#define _WRPLL_CTL1 0x46040
8809#define _WRPLL_CTL2 0x46060
8810#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
8811#define WRPLL_PLL_ENABLE (1<<31)
8812#define WRPLL_PLL_SSC (1<<28)
8813#define WRPLL_PLL_NON_SSC (2<<28)
8814#define WRPLL_PLL_LCPLL (3<<28)
8815#define WRPLL_PLL_REF_MASK (3<<28)
8816/* WRPLL divider programming */
8817#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
8818#define WRPLL_DIVIDER_REF_MASK (0xff)
8819#define WRPLL_DIVIDER_POST(x) ((x)<<8)
8820#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
8821#define WRPLL_DIVIDER_POST_SHIFT 8
8822#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
8823#define WRPLL_DIVIDER_FB_SHIFT 16
8824#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
8825
8826/* Port clock selection */
8827#define _PORT_CLK_SEL_A 0x46100
8828#define _PORT_CLK_SEL_B 0x46104
8829#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
8830#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
8831#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
8832#define PORT_CLK_SEL_LCPLL_810 (2<<29)
8833#define PORT_CLK_SEL_SPLL (3<<29)
8834#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
8835#define PORT_CLK_SEL_WRPLL1 (4<<29)
8836#define PORT_CLK_SEL_WRPLL2 (5<<29)
8837#define PORT_CLK_SEL_NONE (7<<29)
8838#define PORT_CLK_SEL_MASK (7<<29)
8839
8840/* Transcoder clock selection */
8841#define _TRANS_CLK_SEL_A 0x46140
8842#define _TRANS_CLK_SEL_B 0x46144
8843#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
8844/* For each transcoder, we need to select the corresponding port clock */
8845#define TRANS_CLK_SEL_DISABLED (0x0<<29)
8846#define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
8847
8848#define CDCLK_FREQ _MMIO(0x46200)
8849
8850#define _TRANSA_MSA_MISC 0x60410
8851#define _TRANSB_MSA_MISC 0x61410
8852#define _TRANSC_MSA_MISC 0x62410
8853#define _TRANS_EDP_MSA_MISC 0x6f410
8854#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
8855
8856#define TRANS_MSA_SYNC_CLK (1<<0)
8857#define TRANS_MSA_6_BPC (0<<5)
8858#define TRANS_MSA_8_BPC (1<<5)
8859#define TRANS_MSA_10_BPC (2<<5)
8860#define TRANS_MSA_12_BPC (3<<5)
8861#define TRANS_MSA_16_BPC (4<<5)
8862
8863/* LCPLL Control */
8864#define LCPLL_CTL _MMIO(0x130040)
8865#define LCPLL_PLL_DISABLE (1<<31)
8866#define LCPLL_PLL_LOCK (1<<30)
8867#define LCPLL_CLK_FREQ_MASK (3<<26)
8868#define LCPLL_CLK_FREQ_450 (0<<26)
8869#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
8870#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
8871#define LCPLL_CLK_FREQ_675_BDW (3<<26)
8872#define LCPLL_CD_CLOCK_DISABLE (1<<25)
8873#define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
8874#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
8875#define LCPLL_POWER_DOWN_ALLOW (1<<22)
8876#define LCPLL_CD_SOURCE_FCLK (1<<21)
8877#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
8878
8879/*
8880 * SKL Clocks
8881 */
8882
8883/* CDCLK_CTL */
8884#define CDCLK_CTL _MMIO(0x46000)
8885#define CDCLK_FREQ_SEL_MASK (3 << 26)
8886#define CDCLK_FREQ_450_432 (0 << 26)
8887#define CDCLK_FREQ_540 (1 << 26)
8888#define CDCLK_FREQ_337_308 (2 << 26)
8889#define CDCLK_FREQ_675_617 (3 << 26)
8890#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
8891#define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22)
8892#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22)
8893#define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22)
8894#define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22)
8895#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
8896#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
8897#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
8898#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
8899#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
8900#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
8901
8902/* LCPLL_CTL */
8903#define LCPLL1_CTL _MMIO(0x46010)
8904#define LCPLL2_CTL _MMIO(0x46014)
8905#define LCPLL_PLL_ENABLE (1<<31)
8906
8907/* DPLL control1 */
8908#define DPLL_CTRL1 _MMIO(0x6C058)
8909#define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
8910#define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
8911#define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
8912#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
8913#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
8914#define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
8915#define DPLL_CTRL1_LINK_RATE_2700 0
8916#define DPLL_CTRL1_LINK_RATE_1350 1
8917#define DPLL_CTRL1_LINK_RATE_810 2
8918#define DPLL_CTRL1_LINK_RATE_1620 3
8919#define DPLL_CTRL1_LINK_RATE_1080 4
8920#define DPLL_CTRL1_LINK_RATE_2160 5
8921
8922/* DPLL control2 */
8923#define DPLL_CTRL2 _MMIO(0x6C05C)
8924#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
8925#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
8926#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
8927#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
8928#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
8929
8930/* DPLL Status */
8931#define DPLL_STATUS _MMIO(0x6C060)
8932#define DPLL_LOCK(id) (1<<((id)*8))
8933
8934/* DPLL cfg */
8935#define _DPLL1_CFGCR1 0x6C040
8936#define _DPLL2_CFGCR1 0x6C048
8937#define _DPLL3_CFGCR1 0x6C050
8938#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
8939#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
8940#define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
8941#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
8942
8943#define _DPLL1_CFGCR2 0x6C044
8944#define _DPLL2_CFGCR2 0x6C04C
8945#define _DPLL3_CFGCR2 0x6C054
8946#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
8947#define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
8948#define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
8949#define DPLL_CFGCR2_KDIV_MASK (3<<5)
8950#define DPLL_CFGCR2_KDIV(x) ((x)<<5)
8951#define DPLL_CFGCR2_KDIV_5 (0<<5)
8952#define DPLL_CFGCR2_KDIV_2 (1<<5)
8953#define DPLL_CFGCR2_KDIV_3 (2<<5)
8954#define DPLL_CFGCR2_KDIV_1 (3<<5)
8955#define DPLL_CFGCR2_PDIV_MASK (7<<2)
8956#define DPLL_CFGCR2_PDIV(x) ((x)<<2)
8957#define DPLL_CFGCR2_PDIV_1 (0<<2)
8958#define DPLL_CFGCR2_PDIV_2 (1<<2)
8959#define DPLL_CFGCR2_PDIV_3 (2<<2)
8960#define DPLL_CFGCR2_PDIV_7 (4<<2)
8961#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
8962
8963#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
8964#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
8965
8966/*
8967 * CNL Clocks
8968 */
8969#define DPCLKA_CFGCR0 _MMIO(0x6C200)
8970#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
8971 (port)+10))
8972#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
8973 (port)*2)
8974#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
8975#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
8976
8977/* CNL PLL */
8978#define DPLL0_ENABLE 0x46010
8979#define DPLL1_ENABLE 0x46014
8980#define PLL_ENABLE (1 << 31)
8981#define PLL_LOCK (1 << 30)
8982#define PLL_POWER_ENABLE (1 << 27)
8983#define PLL_POWER_STATE (1 << 26)
8984#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
8985
8986#define _CNL_DPLL0_CFGCR0 0x6C000
8987#define _CNL_DPLL1_CFGCR0 0x6C080
8988#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
8989#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
8990#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
8991#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
8992#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
8993#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
8994#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
8995#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
8996#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
8997#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
8998#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
8999#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
9000#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
9001#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
9002#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
9003#define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0)
9004
9005#define _CNL_DPLL0_CFGCR1 0x6C004
9006#define _CNL_DPLL1_CFGCR1 0x6C084
9007#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
9008#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
9009#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
9010#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
9011#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
9012#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
9013#define DPLL_CFGCR1_KDIV_1 (1 << 6)
9014#define DPLL_CFGCR1_KDIV_2 (2 << 6)
9015#define DPLL_CFGCR1_KDIV_4 (4 << 6)
9016#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
9017#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
9018#define DPLL_CFGCR1_PDIV_2 (1 << 2)
9019#define DPLL_CFGCR1_PDIV_3 (2 << 2)
9020#define DPLL_CFGCR1_PDIV_5 (4 << 2)
9021#define DPLL_CFGCR1_PDIV_7 (8 << 2)
9022#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
9023#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
9024
9025/* BXT display engine PLL */
9026#define BXT_DE_PLL_CTL _MMIO(0x6d000)
9027#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
9028#define BXT_DE_PLL_RATIO_MASK 0xff
9029
9030#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
9031#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
9032#define BXT_DE_PLL_LOCK (1 << 30)
9033#define CNL_CDCLK_PLL_RATIO(x) (x)
9034#define CNL_CDCLK_PLL_RATIO_MASK 0xff
9035
9036/* GEN9 DC */
9037#define DC_STATE_EN _MMIO(0x45504)
9038#define DC_STATE_DISABLE 0
9039#define DC_STATE_EN_UPTO_DC5 (1<<0)
9040#define DC_STATE_EN_DC9 (1<<3)
9041#define DC_STATE_EN_UPTO_DC6 (2<<0)
9042#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
9043
9044#define DC_STATE_DEBUG _MMIO(0x45520)
9045#define DC_STATE_DEBUG_MASK_CORES (1<<0)
9046#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
9047
9048/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
9049 * since on HSW we can't write to it using I915_WRITE. */
9050#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
9051#define D_COMP_BDW _MMIO(0x138144)
9052#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
9053#define D_COMP_COMP_FORCE (1<<8)
9054#define D_COMP_COMP_DISABLE (1<<0)
9055
9056/* Pipe WM_LINETIME - watermark line time */
9057#define _PIPE_WM_LINETIME_A 0x45270
9058#define _PIPE_WM_LINETIME_B 0x45274
9059#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
9060#define PIPE_WM_LINETIME_MASK (0x1ff)
9061#define PIPE_WM_LINETIME_TIME(x) ((x))
9062#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
9063#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
9064
9065/* SFUSE_STRAP */
9066#define SFUSE_STRAP _MMIO(0xc2014)
9067#define SFUSE_STRAP_FUSE_LOCK (1<<13)
9068#define SFUSE_STRAP_RAW_FREQUENCY (1<<8)
9069#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
9070#define SFUSE_STRAP_CRT_DISABLED (1<<6)
9071#define SFUSE_STRAP_DDIF_DETECTED (1<<3)
9072#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
9073#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
9074#define SFUSE_STRAP_DDID_DETECTED (1<<0)
9075
9076#define WM_MISC _MMIO(0x45260)
9077#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
9078
9079#define WM_DBG _MMIO(0x45280)
9080#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
9081#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
9082#define WM_DBG_DISALLOW_SPRITE (1<<2)
9083
9084/* pipe CSC */
9085#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
9086#define _PIPE_A_CSC_COEFF_BY 0x49014
9087#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
9088#define _PIPE_A_CSC_COEFF_BU 0x4901c
9089#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
9090#define _PIPE_A_CSC_COEFF_BV 0x49024
9091#define _PIPE_A_CSC_MODE 0x49028
9092#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
9093#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
9094#define CSC_MODE_YUV_TO_RGB (1 << 0)
9095#define _PIPE_A_CSC_PREOFF_HI 0x49030
9096#define _PIPE_A_CSC_PREOFF_ME 0x49034
9097#define _PIPE_A_CSC_PREOFF_LO 0x49038
9098#define _PIPE_A_CSC_POSTOFF_HI 0x49040
9099#define _PIPE_A_CSC_POSTOFF_ME 0x49044
9100#define _PIPE_A_CSC_POSTOFF_LO 0x49048
9101
9102#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
9103#define _PIPE_B_CSC_COEFF_BY 0x49114
9104#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
9105#define _PIPE_B_CSC_COEFF_BU 0x4911c
9106#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
9107#define _PIPE_B_CSC_COEFF_BV 0x49124
9108#define _PIPE_B_CSC_MODE 0x49128
9109#define _PIPE_B_CSC_PREOFF_HI 0x49130
9110#define _PIPE_B_CSC_PREOFF_ME 0x49134
9111#define _PIPE_B_CSC_PREOFF_LO 0x49138
9112#define _PIPE_B_CSC_POSTOFF_HI 0x49140
9113#define _PIPE_B_CSC_POSTOFF_ME 0x49144
9114#define _PIPE_B_CSC_POSTOFF_LO 0x49148
9115
9116#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
9117#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
9118#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
9119#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
9120#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
9121#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
9122#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
9123#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
9124#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
9125#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
9126#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
9127#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
9128#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
9129
9130/* pipe degamma/gamma LUTs on IVB+ */
9131#define _PAL_PREC_INDEX_A 0x4A400
9132#define _PAL_PREC_INDEX_B 0x4AC00
9133#define _PAL_PREC_INDEX_C 0x4B400
9134#define PAL_PREC_10_12_BIT (0 << 31)
9135#define PAL_PREC_SPLIT_MODE (1 << 31)
9136#define PAL_PREC_AUTO_INCREMENT (1 << 15)
9137#define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
9138#define _PAL_PREC_DATA_A 0x4A404
9139#define _PAL_PREC_DATA_B 0x4AC04
9140#define _PAL_PREC_DATA_C 0x4B404
9141#define _PAL_PREC_GC_MAX_A 0x4A410
9142#define _PAL_PREC_GC_MAX_B 0x4AC10
9143#define _PAL_PREC_GC_MAX_C 0x4B410
9144#define _PAL_PREC_EXT_GC_MAX_A 0x4A420
9145#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20
9146#define _PAL_PREC_EXT_GC_MAX_C 0x4B420
9147#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430
9148#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30
9149#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430
9150
9151#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
9152#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
9153#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
9154#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
9155
9156#define _PRE_CSC_GAMC_INDEX_A 0x4A484
9157#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
9158#define _PRE_CSC_GAMC_INDEX_C 0x4B484
9159#define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10)
9160#define _PRE_CSC_GAMC_DATA_A 0x4A488
9161#define _PRE_CSC_GAMC_DATA_B 0x4AC88
9162#define _PRE_CSC_GAMC_DATA_C 0x4B488
9163
9164#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B)
9165#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
9166
9167/* pipe CSC & degamma/gamma LUTs on CHV */
9168#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
9169#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
9170#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
9171#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
9172#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
9173#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
9174#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
9175#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
9176#define CGM_PIPE_MODE_GAMMA (1 << 2)
9177#define CGM_PIPE_MODE_CSC (1 << 1)
9178#define CGM_PIPE_MODE_DEGAMMA (1 << 0)
9179
9180#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
9181#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
9182#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
9183#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
9184#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
9185#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
9186#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
9187#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
9188
9189#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
9190#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
9191#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
9192#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
9193#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
9194#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
9195#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
9196#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE)
9197
9198/* MIPI DSI registers */
9199
9200#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
9201#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
9202
9203#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
9204#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
9205#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
9206#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
9207
9208/* Gen4+ Timestamp and Pipe Frame time stamp registers */
9209#define GEN4_TIMESTAMP _MMIO(0x2358)
9210#define ILK_TIMESTAMP_HI _MMIO(0x70070)
9211#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
9212
9213#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
9214#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
9215#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
9216#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
9217#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
9218
9219#define _PIPE_FRMTMSTMP_A 0x70048
9220#define PIPE_FRMTMSTMP(pipe) \
9221 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
9222
9223/* BXT MIPI clock controls */
9224#define BXT_MAX_VAR_OUTPUT_KHZ 39500
9225
9226#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
9227#define BXT_MIPI1_DIV_SHIFT 26
9228#define BXT_MIPI2_DIV_SHIFT 10
9229#define BXT_MIPI_DIV_SHIFT(port) \
9230 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
9231 BXT_MIPI2_DIV_SHIFT)
9232
9233/* TX control divider to select actual TX clock output from (8x/var) */
9234#define BXT_MIPI1_TX_ESCLK_SHIFT 26
9235#define BXT_MIPI2_TX_ESCLK_SHIFT 10
9236#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
9237 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
9238 BXT_MIPI2_TX_ESCLK_SHIFT)
9239#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26)
9240#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10)
9241#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
9242 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
9243 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
9244#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
9245 ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
9246/* RX upper control divider to select actual RX clock output from 8x */
9247#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21
9248#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5
9249#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
9250 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
9251 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
9252#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21)
9253#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5)
9254#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
9255 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
9256 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK)
9257#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
9258 ((val & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
9259/* 8/3X divider to select the actual 8/3X clock output from 8x */
9260#define BXT_MIPI1_8X_BY3_SHIFT 19
9261#define BXT_MIPI2_8X_BY3_SHIFT 3
9262#define BXT_MIPI_8X_BY3_SHIFT(port) \
9263 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
9264 BXT_MIPI2_8X_BY3_SHIFT)
9265#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19)
9266#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3)
9267#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
9268 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
9269 BXT_MIPI2_8X_BY3_DIVIDER_MASK)
9270#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
9271 ((val & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
9272/* RX lower control divider to select actual RX clock output from 8x */
9273#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16
9274#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0
9275#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
9276 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
9277 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT)
9278#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16)
9279#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0)
9280#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
9281 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
9282 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK)
9283#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
9284 ((val & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))
9285
9286#define RX_DIVIDER_BIT_1_2 0x3
9287#define RX_DIVIDER_BIT_3_4 0xC
9288
9289/* BXT MIPI mode configure */
9290#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
9291#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
9292#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
9293 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
9294
9295#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
9296#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
9297#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
9298 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
9299
9300#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
9301#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
9302#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
9303 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
9304
9305#define BXT_DSI_PLL_CTL _MMIO(0x161000)
9306#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
9307#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9308#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
9309#define BXT_DSIC_16X_BY1 (0 << 10)
9310#define BXT_DSIC_16X_BY2 (1 << 10)
9311#define BXT_DSIC_16X_BY3 (2 << 10)
9312#define BXT_DSIC_16X_BY4 (3 << 10)
9313#define BXT_DSIC_16X_MASK (3 << 10)
9314#define BXT_DSIA_16X_BY1 (0 << 8)
9315#define BXT_DSIA_16X_BY2 (1 << 8)
9316#define BXT_DSIA_16X_BY3 (2 << 8)
9317#define BXT_DSIA_16X_BY4 (3 << 8)
9318#define BXT_DSIA_16X_MASK (3 << 8)
9319#define BXT_DSI_FREQ_SEL_SHIFT 8
9320#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
9321
9322#define BXT_DSI_PLL_RATIO_MAX 0x7D
9323#define BXT_DSI_PLL_RATIO_MIN 0x22
9324#define GLK_DSI_PLL_RATIO_MAX 0x6F
9325#define GLK_DSI_PLL_RATIO_MIN 0x22
9326#define BXT_DSI_PLL_RATIO_MASK 0xFF
9327#define BXT_REF_CLOCK_KHZ 19200
9328
9329#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
9330#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
9331#define BXT_DSI_PLL_LOCKED (1 << 30)
9332
9333#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
9334#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
9335#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
9336
9337 /* BXT port control */
9338#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
9339#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
9340#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
9341
9342#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
9343#define STAP_SELECT (1 << 0)
9344
9345#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
9346#define HS_IO_CTRL_SELECT (1 << 0)
9347
9348#define DPI_ENABLE (1 << 31) /* A + C */
9349#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
9350#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
9351#define DUAL_LINK_MODE_SHIFT 26
9352#define DUAL_LINK_MODE_MASK (1 << 26)
9353#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
9354#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
9355#define DITHERING_ENABLE (1 << 25) /* A + C */
9356#define FLOPPED_HSTX (1 << 23)
9357#define DE_INVERT (1 << 19) /* XXX */
9358#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
9359#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
9360#define AFE_LATCHOUT (1 << 17)
9361#define LP_OUTPUT_HOLD (1 << 16)
9362#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
9363#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
9364#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
9365#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
9366#define CSB_SHIFT 9
9367#define CSB_MASK (3 << 9)
9368#define CSB_20MHZ (0 << 9)
9369#define CSB_10MHZ (1 << 9)
9370#define CSB_40MHZ (2 << 9)
9371#define BANDGAP_MASK (1 << 8)
9372#define BANDGAP_PNW_CIRCUIT (0 << 8)
9373#define BANDGAP_LNC_CIRCUIT (1 << 8)
9374#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
9375#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
9376#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
9377#define TEARING_EFFECT_SHIFT 2 /* A + C */
9378#define TEARING_EFFECT_MASK (3 << 2)
9379#define TEARING_EFFECT_OFF (0 << 2)
9380#define TEARING_EFFECT_DSI (1 << 2)
9381#define TEARING_EFFECT_GPIO (2 << 2)
9382#define LANE_CONFIGURATION_SHIFT 0
9383#define LANE_CONFIGURATION_MASK (3 << 0)
9384#define LANE_CONFIGURATION_4LANE (0 << 0)
9385#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
9386#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
9387
9388#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
9389#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
9390#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
9391#define TEARING_EFFECT_DELAY_SHIFT 0
9392#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
9393
9394/* XXX: all bits reserved */
9395#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
9396
9397/* MIPI DSI Controller and D-PHY registers */
9398
9399#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
9400#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
9401#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
9402#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
9403#define ULPS_STATE_MASK (3 << 1)
9404#define ULPS_STATE_ENTER (2 << 1)
9405#define ULPS_STATE_EXIT (1 << 1)
9406#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
9407#define DEVICE_READY (1 << 0)
9408
9409#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
9410#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
9411#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
9412#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
9413#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
9414#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
9415#define TEARING_EFFECT (1 << 31)
9416#define SPL_PKT_SENT_INTERRUPT (1 << 30)
9417#define GEN_READ_DATA_AVAIL (1 << 29)
9418#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
9419#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
9420#define RX_PROT_VIOLATION (1 << 26)
9421#define RX_INVALID_TX_LENGTH (1 << 25)
9422#define ACK_WITH_NO_ERROR (1 << 24)
9423#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
9424#define LP_RX_TIMEOUT (1 << 22)
9425#define HS_TX_TIMEOUT (1 << 21)
9426#define DPI_FIFO_UNDERRUN (1 << 20)
9427#define LOW_CONTENTION (1 << 19)
9428#define HIGH_CONTENTION (1 << 18)
9429#define TXDSI_VC_ID_INVALID (1 << 17)
9430#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
9431#define TXCHECKSUM_ERROR (1 << 15)
9432#define TXECC_MULTIBIT_ERROR (1 << 14)
9433#define TXECC_SINGLE_BIT_ERROR (1 << 13)
9434#define TXFALSE_CONTROL_ERROR (1 << 12)
9435#define RXDSI_VC_ID_INVALID (1 << 11)
9436#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
9437#define RXCHECKSUM_ERROR (1 << 9)
9438#define RXECC_MULTIBIT_ERROR (1 << 8)
9439#define RXECC_SINGLE_BIT_ERROR (1 << 7)
9440#define RXFALSE_CONTROL_ERROR (1 << 6)
9441#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
9442#define RX_LP_TX_SYNC_ERROR (1 << 4)
9443#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
9444#define RXEOT_SYNC_ERROR (1 << 2)
9445#define RXSOT_SYNC_ERROR (1 << 1)
9446#define RXSOT_ERROR (1 << 0)
9447
9448#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
9449#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
9450#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
9451#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
9452#define CMD_MODE_NOT_SUPPORTED (0 << 13)
9453#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
9454#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
9455#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
9456#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
9457#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
9458#define VID_MODE_FORMAT_MASK (0xf << 7)
9459#define VID_MODE_NOT_SUPPORTED (0 << 7)
9460#define VID_MODE_FORMAT_RGB565 (1 << 7)
9461#define VID_MODE_FORMAT_RGB666_PACKED (2 << 7)
9462#define VID_MODE_FORMAT_RGB666 (3 << 7)
9463#define VID_MODE_FORMAT_RGB888 (4 << 7)
9464#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
9465#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
9466#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
9467#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
9468#define DATA_LANES_PRG_REG_SHIFT 0
9469#define DATA_LANES_PRG_REG_MASK (7 << 0)
9470
9471#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
9472#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
9473#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
9474#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
9475
9476#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
9477#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
9478#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
9479#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
9480
9481#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
9482#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
9483#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
9484#define TURN_AROUND_TIMEOUT_MASK 0x3f
9485
9486#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
9487#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
9488#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
9489#define DEVICE_RESET_TIMER_MASK 0xffff
9490
9491#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
9492#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
9493#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
9494#define VERTICAL_ADDRESS_SHIFT 16
9495#define VERTICAL_ADDRESS_MASK (0xffff << 16)
9496#define HORIZONTAL_ADDRESS_SHIFT 0
9497#define HORIZONTAL_ADDRESS_MASK 0xffff
9498
9499#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
9500#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
9501#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
9502#define DBI_FIFO_EMPTY_HALF (0 << 0)
9503#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
9504#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
9505
9506/* regs below are bits 15:0 */
9507#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
9508#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
9509#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
9510
9511#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
9512#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
9513#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
9514
9515#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
9516#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
9517#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
9518
9519#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
9520#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
9521#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
9522
9523#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
9524#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
9525#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
9526
9527#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
9528#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
9529#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
9530
9531#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
9532#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
9533#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
9534
9535#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
9536#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
9537#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
9538
9539/* regs above are bits 15:0 */
9540
9541#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
9542#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
9543#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
9544#define DPI_LP_MODE (1 << 6)
9545#define BACKLIGHT_OFF (1 << 5)
9546#define BACKLIGHT_ON (1 << 4)
9547#define COLOR_MODE_OFF (1 << 3)
9548#define COLOR_MODE_ON (1 << 2)
9549#define TURN_ON (1 << 1)
9550#define SHUTDOWN (1 << 0)
9551
9552#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
9553#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
9554#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
9555#define COMMAND_BYTE_SHIFT 0
9556#define COMMAND_BYTE_MASK (0x3f << 0)
9557
9558#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
9559#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
9560#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
9561#define MASTER_INIT_TIMER_SHIFT 0
9562#define MASTER_INIT_TIMER_MASK (0xffff << 0)
9563
9564#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
9565#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
9566#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
9567 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
9568#define MAX_RETURN_PKT_SIZE_SHIFT 0
9569#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
9570
9571#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
9572#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
9573#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
9574#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
9575#define DISABLE_VIDEO_BTA (1 << 3)
9576#define IP_TG_CONFIG (1 << 2)
9577#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
9578#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
9579#define VIDEO_MODE_BURST (3 << 0)
9580
9581#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
9582#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
9583#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
9584#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
9585#define BXT_DPHY_DEFEATURE_EN (1 << 8)
9586#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
9587#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
9588#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
9589#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
9590#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
9591#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
9592#define CLOCKSTOP (1 << 1)
9593#define EOT_DISABLE (1 << 0)
9594
9595#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
9596#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
9597#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
9598#define LP_BYTECLK_SHIFT 0
9599#define LP_BYTECLK_MASK (0xffff << 0)
9600
9601#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
9602#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
9603#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
9604
9605#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
9606#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
9607#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
9608
9609/* bits 31:0 */
9610#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
9611#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
9612#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
9613
9614/* bits 31:0 */
9615#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
9616#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
9617#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
9618
9619#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
9620#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
9621#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
9622#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
9623#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
9624#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
9625#define LONG_PACKET_WORD_COUNT_SHIFT 8
9626#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
9627#define SHORT_PACKET_PARAM_SHIFT 8
9628#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
9629#define VIRTUAL_CHANNEL_SHIFT 6
9630#define VIRTUAL_CHANNEL_MASK (3 << 6)
9631#define DATA_TYPE_SHIFT 0
9632#define DATA_TYPE_MASK (0x3f << 0)
9633/* data type values, see include/video/mipi_display.h */
9634
9635#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
9636#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
9637#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
9638#define DPI_FIFO_EMPTY (1 << 28)
9639#define DBI_FIFO_EMPTY (1 << 27)
9640#define LP_CTRL_FIFO_EMPTY (1 << 26)
9641#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
9642#define LP_CTRL_FIFO_FULL (1 << 24)
9643#define HS_CTRL_FIFO_EMPTY (1 << 18)
9644#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
9645#define HS_CTRL_FIFO_FULL (1 << 16)
9646#define LP_DATA_FIFO_EMPTY (1 << 10)
9647#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
9648#define LP_DATA_FIFO_FULL (1 << 8)
9649#define HS_DATA_FIFO_EMPTY (1 << 2)
9650#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
9651#define HS_DATA_FIFO_FULL (1 << 0)
9652
9653#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
9654#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
9655#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
9656#define DBI_HS_LP_MODE_MASK (1 << 0)
9657#define DBI_LP_MODE (1 << 0)
9658#define DBI_HS_MODE (0 << 0)
9659
9660#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
9661#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
9662#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
9663#define EXIT_ZERO_COUNT_SHIFT 24
9664#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
9665#define TRAIL_COUNT_SHIFT 16
9666#define TRAIL_COUNT_MASK (0x1f << 16)
9667#define CLK_ZERO_COUNT_SHIFT 8
9668#define CLK_ZERO_COUNT_MASK (0xff << 8)
9669#define PREPARE_COUNT_SHIFT 0
9670#define PREPARE_COUNT_MASK (0x3f << 0)
9671
9672/* bits 31:0 */
9673#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
9674#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
9675#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
9676
9677#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
9678#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
9679#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
9680#define LP_HS_SSW_CNT_SHIFT 16
9681#define LP_HS_SSW_CNT_MASK (0xffff << 16)
9682#define HS_LP_PWR_SW_CNT_SHIFT 0
9683#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
9684
9685#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
9686#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
9687#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
9688#define STOP_STATE_STALL_COUNTER_SHIFT 0
9689#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
9690
9691#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
9692#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
9693#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
9694#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
9695#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
9696#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
9697#define RX_CONTENTION_DETECTED (1 << 0)
9698
9699/* XXX: only pipe A ?!? */
9700#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
9701#define DBI_TYPEC_ENABLE (1 << 31)
9702#define DBI_TYPEC_WIP (1 << 30)
9703#define DBI_TYPEC_OPTION_SHIFT 28
9704#define DBI_TYPEC_OPTION_MASK (3 << 28)
9705#define DBI_TYPEC_FREQ_SHIFT 24
9706#define DBI_TYPEC_FREQ_MASK (0xf << 24)
9707#define DBI_TYPEC_OVERRIDE (1 << 8)
9708#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
9709#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
9710
9711
9712/* MIPI adapter registers */
9713
9714#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
9715#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
9716#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
9717#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
9718#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
9719#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
9720#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
9721#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
9722#define READ_REQUEST_PRIORITY_SHIFT 3
9723#define READ_REQUEST_PRIORITY_MASK (3 << 3)
9724#define READ_REQUEST_PRIORITY_LOW (0 << 3)
9725#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
9726#define RGB_FLIP_TO_BGR (1 << 2)
9727
9728#define BXT_PIPE_SELECT_SHIFT 7
9729#define BXT_PIPE_SELECT_MASK (7 << 7)
9730#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
9731#define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */
9732#define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */
9733#define GLK_MIPIIO_RESET_RELEASED (1 << 28)
9734#define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */
9735#define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */
9736#define GLK_LP_WAKE (1 << 22)
9737#define GLK_LP11_LOW_PWR_MODE (1 << 21)
9738#define GLK_LP00_LOW_PWR_MODE (1 << 20)
9739#define GLK_FIREWALL_ENABLE (1 << 16)
9740#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10)
9741#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10
9742#define BXT_DSC_ENABLE (1 << 3)
9743#define BXT_RGB_FLIP (1 << 2)
9744#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
9745#define GLK_MIPIIO_ENABLE (1 << 0)
9746
9747#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
9748#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
9749#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
9750#define DATA_MEM_ADDRESS_SHIFT 5
9751#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
9752#define DATA_VALID (1 << 0)
9753
9754#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
9755#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
9756#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
9757#define DATA_LENGTH_SHIFT 0
9758#define DATA_LENGTH_MASK (0xfffff << 0)
9759
9760#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
9761#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
9762#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
9763#define COMMAND_MEM_ADDRESS_SHIFT 5
9764#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
9765#define AUTO_PWG_ENABLE (1 << 2)
9766#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
9767#define COMMAND_VALID (1 << 0)
9768
9769#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
9770#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
9771#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
9772#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
9773#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
9774
9775#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
9776#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
9777#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
9778
9779#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
9780#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
9781#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
9782#define READ_DATA_VALID(n) (1 << (n))
9783
9784/* For UMS only (deprecated): */
9785#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
9786#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
9787
9788/* MOCS (Memory Object Control State) registers */
9789#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
9790
9791#define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
9792#define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
9793#define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
9794#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
9795#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
9796
9797/* gamt regs */
9798#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
9799#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
9800#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
9801#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
9802#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
9803
9804#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */
9805#define MMCD_PCLA (1 << 31)
9806#define MMCD_HOTSPOT_EN (1 << 27)
9807
9808#define _ICL_PHY_MISC_A 0x64C00
9809#define _ICL_PHY_MISC_B 0x64C04
9810#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
9811 _ICL_PHY_MISC_B)
9812#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
9813
9814#endif /* _I915_REG_H_ */