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1/*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/errno.h>
28#include <linux/sched.h>
29#include <linux/i2c.h>
30#include <linux/seq_file.h>
31#include <drm/drm_dp_helper.h>
32#include <drm/drmP.h>
33
34#include "drm_crtc_helper_internal.h"
35
36/**
37 * DOC: dp helpers
38 *
39 * These functions contain some common logic and helpers at various abstraction
40 * levels to deal with Display Port sink devices and related things like DP aux
41 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
42 * blocks, ...
43 */
44
45/* Helpers for DP link training */
46static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
47{
48 return link_status[r - DP_LANE0_1_STATUS];
49}
50
51static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
52 int lane)
53{
54 int i = DP_LANE0_1_STATUS + (lane >> 1);
55 int s = (lane & 1) * 4;
56 u8 l = dp_link_status(link_status, i);
57 return (l >> s) & 0xf;
58}
59
60bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
61 int lane_count)
62{
63 u8 lane_align;
64 u8 lane_status;
65 int lane;
66
67 lane_align = dp_link_status(link_status,
68 DP_LANE_ALIGN_STATUS_UPDATED);
69 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
70 return false;
71 for (lane = 0; lane < lane_count; lane++) {
72 lane_status = dp_get_lane_status(link_status, lane);
73 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
74 return false;
75 }
76 return true;
77}
78EXPORT_SYMBOL(drm_dp_channel_eq_ok);
79
80bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
81 int lane_count)
82{
83 int lane;
84 u8 lane_status;
85
86 for (lane = 0; lane < lane_count; lane++) {
87 lane_status = dp_get_lane_status(link_status, lane);
88 if ((lane_status & DP_LANE_CR_DONE) == 0)
89 return false;
90 }
91 return true;
92}
93EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
94
95u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
96 int lane)
97{
98 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
99 int s = ((lane & 1) ?
100 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
101 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
102 u8 l = dp_link_status(link_status, i);
103
104 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
105}
106EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
107
108u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
109 int lane)
110{
111 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
112 int s = ((lane & 1) ?
113 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
114 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
115 u8 l = dp_link_status(link_status, i);
116
117 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
118}
119EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
120
121void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
122 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
123 udelay(100);
124 else
125 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
126}
127EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
128
129void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
130 if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
131 udelay(400);
132 else
133 mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
134}
135EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
136
137u8 drm_dp_link_rate_to_bw_code(int link_rate)
138{
139 switch (link_rate) {
140 default:
141 WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
142 DP_LINK_BW_1_62);
143 case 162000:
144 return DP_LINK_BW_1_62;
145 case 270000:
146 return DP_LINK_BW_2_7;
147 case 540000:
148 return DP_LINK_BW_5_4;
149 case 810000:
150 return DP_LINK_BW_8_1;
151 }
152}
153EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
154
155int drm_dp_bw_code_to_link_rate(u8 link_bw)
156{
157 switch (link_bw) {
158 default:
159 WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw);
160 case DP_LINK_BW_1_62:
161 return 162000;
162 case DP_LINK_BW_2_7:
163 return 270000;
164 case DP_LINK_BW_5_4:
165 return 540000;
166 case DP_LINK_BW_8_1:
167 return 810000;
168 }
169}
170EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
171
172#define AUX_RETRY_INTERVAL 500 /* us */
173
174/**
175 * DOC: dp helpers
176 *
177 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
178 * independent access to AUX functionality. Drivers can take advantage of
179 * this by filling in the fields of the drm_dp_aux structure.
180 *
181 * Transactions are described using a hardware-independent drm_dp_aux_msg
182 * structure, which is passed into a driver's .transfer() implementation.
183 * Both native and I2C-over-AUX transactions are supported.
184 */
185
186static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
187 unsigned int offset, void *buffer, size_t size)
188{
189 struct drm_dp_aux_msg msg;
190 unsigned int retry, native_reply;
191 int err = 0, ret = 0;
192
193 memset(&msg, 0, sizeof(msg));
194 msg.address = offset;
195 msg.request = request;
196 msg.buffer = buffer;
197 msg.size = size;
198
199 mutex_lock(&aux->hw_mutex);
200
201 /*
202 * The specification doesn't give any recommendation on how often to
203 * retry native transactions. We used to retry 7 times like for
204 * aux i2c transactions but real world devices this wasn't
205 * sufficient, bump to 32 which makes Dell 4k monitors happier.
206 */
207 for (retry = 0; retry < 32; retry++) {
208 if (ret != 0 && ret != -ETIMEDOUT) {
209 usleep_range(AUX_RETRY_INTERVAL,
210 AUX_RETRY_INTERVAL + 100);
211 }
212
213 ret = aux->transfer(aux, &msg);
214
215 if (ret >= 0) {
216 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
217 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
218 if (ret == size)
219 goto unlock;
220
221 ret = -EPROTO;
222 } else
223 ret = -EIO;
224 }
225
226 /*
227 * We want the error we return to be the error we received on
228 * the first transaction, since we may get a different error the
229 * next time we retry
230 */
231 if (!err)
232 err = ret;
233 }
234
235 DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err);
236 ret = err;
237
238unlock:
239 mutex_unlock(&aux->hw_mutex);
240 return ret;
241}
242
243/**
244 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
245 * @aux: DisplayPort AUX channel
246 * @offset: address of the (first) register to read
247 * @buffer: buffer to store the register values
248 * @size: number of bytes in @buffer
249 *
250 * Returns the number of bytes transferred on success, or a negative error
251 * code on failure. -EIO is returned if the request was NAKed by the sink or
252 * if the retry count was exceeded. If not all bytes were transferred, this
253 * function returns -EPROTO. Errors from the underlying AUX channel transfer
254 * function, with the exception of -EBUSY (which causes the transaction to
255 * be retried), are propagated to the caller.
256 */
257ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
258 void *buffer, size_t size)
259{
260 int ret;
261
262 /*
263 * HP ZR24w corrupts the first DPCD access after entering power save
264 * mode. Eg. on a read, the entire buffer will be filled with the same
265 * byte. Do a throw away read to avoid corrupting anything we care
266 * about. Afterwards things will work correctly until the monitor
267 * gets woken up and subsequently re-enters power save mode.
268 *
269 * The user pressing any button on the monitor is enough to wake it
270 * up, so there is no particularly good place to do the workaround.
271 * We just have to do it before any DPCD access and hope that the
272 * monitor doesn't power down exactly after the throw away read.
273 */
274 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
275 1);
276 if (ret != 1)
277 return ret;
278
279 return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
280 size);
281}
282EXPORT_SYMBOL(drm_dp_dpcd_read);
283
284/**
285 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
286 * @aux: DisplayPort AUX channel
287 * @offset: address of the (first) register to write
288 * @buffer: buffer containing the values to write
289 * @size: number of bytes in @buffer
290 *
291 * Returns the number of bytes transferred on success, or a negative error
292 * code on failure. -EIO is returned if the request was NAKed by the sink or
293 * if the retry count was exceeded. If not all bytes were transferred, this
294 * function returns -EPROTO. Errors from the underlying AUX channel transfer
295 * function, with the exception of -EBUSY (which causes the transaction to
296 * be retried), are propagated to the caller.
297 */
298ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
299 void *buffer, size_t size)
300{
301 return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
302 size);
303}
304EXPORT_SYMBOL(drm_dp_dpcd_write);
305
306/**
307 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
308 * @aux: DisplayPort AUX channel
309 * @status: buffer to store the link status in (must be at least 6 bytes)
310 *
311 * Returns the number of bytes transferred on success or a negative error
312 * code on failure.
313 */
314int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
315 u8 status[DP_LINK_STATUS_SIZE])
316{
317 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
318 DP_LINK_STATUS_SIZE);
319}
320EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
321
322/**
323 * drm_dp_link_probe() - probe a DisplayPort link for capabilities
324 * @aux: DisplayPort AUX channel
325 * @link: pointer to structure in which to return link capabilities
326 *
327 * The structure filled in by this function can usually be passed directly
328 * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
329 * configure the link based on the link's capabilities.
330 *
331 * Returns 0 on success or a negative error code on failure.
332 */
333int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
334{
335 u8 values[3];
336 int err;
337
338 memset(link, 0, sizeof(*link));
339
340 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
341 if (err < 0)
342 return err;
343
344 link->revision = values[0];
345 link->rate = drm_dp_bw_code_to_link_rate(values[1]);
346 link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
347
348 if (values[2] & DP_ENHANCED_FRAME_CAP)
349 link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
350
351 return 0;
352}
353EXPORT_SYMBOL(drm_dp_link_probe);
354
355/**
356 * drm_dp_link_power_up() - power up a DisplayPort link
357 * @aux: DisplayPort AUX channel
358 * @link: pointer to a structure containing the link configuration
359 *
360 * Returns 0 on success or a negative error code on failure.
361 */
362int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
363{
364 u8 value;
365 int err;
366
367 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
368 if (link->revision < 0x11)
369 return 0;
370
371 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
372 if (err < 0)
373 return err;
374
375 value &= ~DP_SET_POWER_MASK;
376 value |= DP_SET_POWER_D0;
377
378 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
379 if (err < 0)
380 return err;
381
382 /*
383 * According to the DP 1.1 specification, a "Sink Device must exit the
384 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
385 * Control Field" (register 0x600).
386 */
387 usleep_range(1000, 2000);
388
389 return 0;
390}
391EXPORT_SYMBOL(drm_dp_link_power_up);
392
393/**
394 * drm_dp_link_power_down() - power down a DisplayPort link
395 * @aux: DisplayPort AUX channel
396 * @link: pointer to a structure containing the link configuration
397 *
398 * Returns 0 on success or a negative error code on failure.
399 */
400int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
401{
402 u8 value;
403 int err;
404
405 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
406 if (link->revision < 0x11)
407 return 0;
408
409 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
410 if (err < 0)
411 return err;
412
413 value &= ~DP_SET_POWER_MASK;
414 value |= DP_SET_POWER_D3;
415
416 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
417 if (err < 0)
418 return err;
419
420 return 0;
421}
422EXPORT_SYMBOL(drm_dp_link_power_down);
423
424/**
425 * drm_dp_link_configure() - configure a DisplayPort link
426 * @aux: DisplayPort AUX channel
427 * @link: pointer to a structure containing the link configuration
428 *
429 * Returns 0 on success or a negative error code on failure.
430 */
431int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
432{
433 u8 values[2];
434 int err;
435
436 values[0] = drm_dp_link_rate_to_bw_code(link->rate);
437 values[1] = link->num_lanes;
438
439 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
440 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
441
442 err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
443 if (err < 0)
444 return err;
445
446 return 0;
447}
448EXPORT_SYMBOL(drm_dp_link_configure);
449
450/**
451 * drm_dp_downstream_max_clock() - extract branch device max
452 * pixel rate for legacy VGA
453 * converter or max TMDS clock
454 * rate for others
455 * @dpcd: DisplayPort configuration data
456 * @port_cap: port capabilities
457 *
458 * Returns max clock in kHz on success or 0 if max clock not defined
459 */
460int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
461 const u8 port_cap[4])
462{
463 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
464 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
465 DP_DETAILED_CAP_INFO_AVAILABLE;
466
467 if (!detailed_cap_info)
468 return 0;
469
470 switch (type) {
471 case DP_DS_PORT_TYPE_VGA:
472 return port_cap[1] * 8 * 1000;
473 case DP_DS_PORT_TYPE_DVI:
474 case DP_DS_PORT_TYPE_HDMI:
475 case DP_DS_PORT_TYPE_DP_DUALMODE:
476 return port_cap[1] * 2500;
477 default:
478 return 0;
479 }
480}
481EXPORT_SYMBOL(drm_dp_downstream_max_clock);
482
483/**
484 * drm_dp_downstream_max_bpc() - extract branch device max
485 * bits per component
486 * @dpcd: DisplayPort configuration data
487 * @port_cap: port capabilities
488 *
489 * Returns max bpc on success or 0 if max bpc not defined
490 */
491int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
492 const u8 port_cap[4])
493{
494 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
495 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
496 DP_DETAILED_CAP_INFO_AVAILABLE;
497 int bpc;
498
499 if (!detailed_cap_info)
500 return 0;
501
502 switch (type) {
503 case DP_DS_PORT_TYPE_VGA:
504 case DP_DS_PORT_TYPE_DVI:
505 case DP_DS_PORT_TYPE_HDMI:
506 case DP_DS_PORT_TYPE_DP_DUALMODE:
507 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
508
509 switch (bpc) {
510 case DP_DS_8BPC:
511 return 8;
512 case DP_DS_10BPC:
513 return 10;
514 case DP_DS_12BPC:
515 return 12;
516 case DP_DS_16BPC:
517 return 16;
518 }
519 default:
520 return 0;
521 }
522}
523EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
524
525/**
526 * drm_dp_downstream_id() - identify branch device
527 * @aux: DisplayPort AUX channel
528 * @id: DisplayPort branch device id
529 *
530 * Returns branch device id on success or NULL on failure
531 */
532int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
533{
534 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
535}
536EXPORT_SYMBOL(drm_dp_downstream_id);
537
538/**
539 * drm_dp_downstream_debug() - debug DP branch devices
540 * @m: pointer for debugfs file
541 * @dpcd: DisplayPort configuration data
542 * @port_cap: port capabilities
543 * @aux: DisplayPort AUX channel
544 *
545 */
546void drm_dp_downstream_debug(struct seq_file *m,
547 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
548 const u8 port_cap[4], struct drm_dp_aux *aux)
549{
550 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
551 DP_DETAILED_CAP_INFO_AVAILABLE;
552 int clk;
553 int bpc;
554 char id[7];
555 int len;
556 uint8_t rev[2];
557 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
558 bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
559 DP_DWN_STRM_PORT_PRESENT;
560
561 seq_printf(m, "\tDP branch device present: %s\n",
562 branch_device ? "yes" : "no");
563
564 if (!branch_device)
565 return;
566
567 switch (type) {
568 case DP_DS_PORT_TYPE_DP:
569 seq_puts(m, "\t\tType: DisplayPort\n");
570 break;
571 case DP_DS_PORT_TYPE_VGA:
572 seq_puts(m, "\t\tType: VGA\n");
573 break;
574 case DP_DS_PORT_TYPE_DVI:
575 seq_puts(m, "\t\tType: DVI\n");
576 break;
577 case DP_DS_PORT_TYPE_HDMI:
578 seq_puts(m, "\t\tType: HDMI\n");
579 break;
580 case DP_DS_PORT_TYPE_NON_EDID:
581 seq_puts(m, "\t\tType: others without EDID support\n");
582 break;
583 case DP_DS_PORT_TYPE_DP_DUALMODE:
584 seq_puts(m, "\t\tType: DP++\n");
585 break;
586 case DP_DS_PORT_TYPE_WIRELESS:
587 seq_puts(m, "\t\tType: Wireless\n");
588 break;
589 default:
590 seq_puts(m, "\t\tType: N/A\n");
591 }
592
593 memset(id, 0, sizeof(id));
594 drm_dp_downstream_id(aux, id);
595 seq_printf(m, "\t\tID: %s\n", id);
596
597 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
598 if (len > 0)
599 seq_printf(m, "\t\tHW: %d.%d\n",
600 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
601
602 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
603 if (len > 0)
604 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
605
606 if (detailed_cap_info) {
607 clk = drm_dp_downstream_max_clock(dpcd, port_cap);
608
609 if (clk > 0) {
610 if (type == DP_DS_PORT_TYPE_VGA)
611 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
612 else
613 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
614 }
615
616 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
617
618 if (bpc > 0)
619 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
620 }
621}
622EXPORT_SYMBOL(drm_dp_downstream_debug);
623
624/*
625 * I2C-over-AUX implementation
626 */
627
628static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
629{
630 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
631 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
632 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
633 I2C_FUNC_10BIT_ADDR;
634}
635
636static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
637{
638 /*
639 * In case of i2c defer or short i2c ack reply to a write,
640 * we need to switch to WRITE_STATUS_UPDATE to drain the
641 * rest of the message
642 */
643 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
644 msg->request &= DP_AUX_I2C_MOT;
645 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
646 }
647}
648
649#define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
650#define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
651#define AUX_STOP_LEN 4
652#define AUX_CMD_LEN 4
653#define AUX_ADDRESS_LEN 20
654#define AUX_REPLY_PAD_LEN 4
655#define AUX_LENGTH_LEN 8
656
657/*
658 * Calculate the duration of the AUX request/reply in usec. Gives the
659 * "best" case estimate, ie. successful while as short as possible.
660 */
661static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
662{
663 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
664 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
665
666 if ((msg->request & DP_AUX_I2C_READ) == 0)
667 len += msg->size * 8;
668
669 return len;
670}
671
672static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
673{
674 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
675 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
676
677 /*
678 * For read we expect what was asked. For writes there will
679 * be 0 or 1 data bytes. Assume 0 for the "best" case.
680 */
681 if (msg->request & DP_AUX_I2C_READ)
682 len += msg->size * 8;
683
684 return len;
685}
686
687#define I2C_START_LEN 1
688#define I2C_STOP_LEN 1
689#define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
690#define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
691
692/*
693 * Calculate the length of the i2c transfer in usec, assuming
694 * the i2c bus speed is as specified. Gives the the "worst"
695 * case estimate, ie. successful while as long as possible.
696 * Doesn't account the the "MOT" bit, and instead assumes each
697 * message includes a START, ADDRESS and STOP. Neither does it
698 * account for additional random variables such as clock stretching.
699 */
700static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
701 int i2c_speed_khz)
702{
703 /* AUX bitrate is 1MHz, i2c bitrate as specified */
704 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
705 msg->size * I2C_DATA_LEN +
706 I2C_STOP_LEN) * 1000, i2c_speed_khz);
707}
708
709/*
710 * Deterine how many retries should be attempted to successfully transfer
711 * the specified message, based on the estimated durations of the
712 * i2c and AUX transfers.
713 */
714static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
715 int i2c_speed_khz)
716{
717 int aux_time_us = drm_dp_aux_req_duration(msg) +
718 drm_dp_aux_reply_duration(msg);
719 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
720
721 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
722}
723
724/*
725 * FIXME currently assumes 10 kHz as some real world devices seem
726 * to require it. We should query/set the speed via DPCD if supported.
727 */
728static int dp_aux_i2c_speed_khz __read_mostly = 10;
729module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
730MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
731 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
732
733/*
734 * Transfer a single I2C-over-AUX message and handle various error conditions,
735 * retrying the transaction as appropriate. It is assumed that the
736 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
737 * reply field.
738 *
739 * Returns bytes transferred on success, or a negative error code on failure.
740 */
741static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
742{
743 unsigned int retry, defer_i2c;
744 int ret;
745 /*
746 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
747 * is required to retry at least seven times upon receiving AUX_DEFER
748 * before giving up the AUX transaction.
749 *
750 * We also try to account for the i2c bus speed.
751 */
752 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
753
754 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
755 ret = aux->transfer(aux, msg);
756 if (ret < 0) {
757 if (ret == -EBUSY)
758 continue;
759
760 /*
761 * While timeouts can be errors, they're usually normal
762 * behavior (for instance, when a driver tries to
763 * communicate with a non-existant DisplayPort device).
764 * Avoid spamming the kernel log with timeout errors.
765 */
766 if (ret == -ETIMEDOUT)
767 DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n");
768 else
769 DRM_DEBUG_KMS("transaction failed: %d\n", ret);
770
771 return ret;
772 }
773
774
775 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
776 case DP_AUX_NATIVE_REPLY_ACK:
777 /*
778 * For I2C-over-AUX transactions this isn't enough, we
779 * need to check for the I2C ACK reply.
780 */
781 break;
782
783 case DP_AUX_NATIVE_REPLY_NACK:
784 DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size);
785 return -EREMOTEIO;
786
787 case DP_AUX_NATIVE_REPLY_DEFER:
788 DRM_DEBUG_KMS("native defer\n");
789 /*
790 * We could check for I2C bit rate capabilities and if
791 * available adjust this interval. We could also be
792 * more careful with DP-to-legacy adapters where a
793 * long legacy cable may force very low I2C bit rates.
794 *
795 * For now just defer for long enough to hopefully be
796 * safe for all use-cases.
797 */
798 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
799 continue;
800
801 default:
802 DRM_ERROR("invalid native reply %#04x\n", msg->reply);
803 return -EREMOTEIO;
804 }
805
806 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
807 case DP_AUX_I2C_REPLY_ACK:
808 /*
809 * Both native ACK and I2C ACK replies received. We
810 * can assume the transfer was successful.
811 */
812 if (ret != msg->size)
813 drm_dp_i2c_msg_write_status_update(msg);
814 return ret;
815
816 case DP_AUX_I2C_REPLY_NACK:
817 DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu\n", ret, msg->size);
818 aux->i2c_nack_count++;
819 return -EREMOTEIO;
820
821 case DP_AUX_I2C_REPLY_DEFER:
822 DRM_DEBUG_KMS("I2C defer\n");
823 /* DP Compliance Test 4.2.2.5 Requirement:
824 * Must have at least 7 retries for I2C defers on the
825 * transaction to pass this test
826 */
827 aux->i2c_defer_count++;
828 if (defer_i2c < 7)
829 defer_i2c++;
830 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
831 drm_dp_i2c_msg_write_status_update(msg);
832
833 continue;
834
835 default:
836 DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
837 return -EREMOTEIO;
838 }
839 }
840
841 DRM_DEBUG_KMS("too many retries, giving up\n");
842 return -EREMOTEIO;
843}
844
845static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
846 const struct i2c_msg *i2c_msg)
847{
848 msg->request = (i2c_msg->flags & I2C_M_RD) ?
849 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
850 msg->request |= DP_AUX_I2C_MOT;
851}
852
853/*
854 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
855 *
856 * Returns an error code on failure, or a recommended transfer size on success.
857 */
858static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
859{
860 int err, ret = orig_msg->size;
861 struct drm_dp_aux_msg msg = *orig_msg;
862
863 while (msg.size > 0) {
864 err = drm_dp_i2c_do_msg(aux, &msg);
865 if (err <= 0)
866 return err == 0 ? -EPROTO : err;
867
868 if (err < msg.size && err < ret) {
869 DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n",
870 msg.size, err);
871 ret = err;
872 }
873
874 msg.size -= err;
875 msg.buffer += err;
876 }
877
878 return ret;
879}
880
881/*
882 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
883 * packets to be as large as possible. If not, the I2C transactions never
884 * succeed. Hence the default is maximum.
885 */
886static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
887module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
888MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
889 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
890
891static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
892 int num)
893{
894 struct drm_dp_aux *aux = adapter->algo_data;
895 unsigned int i, j;
896 unsigned transfer_size;
897 struct drm_dp_aux_msg msg;
898 int err = 0;
899
900 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
901
902 memset(&msg, 0, sizeof(msg));
903
904 for (i = 0; i < num; i++) {
905 msg.address = msgs[i].addr;
906 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
907 /* Send a bare address packet to start the transaction.
908 * Zero sized messages specify an address only (bare
909 * address) transaction.
910 */
911 msg.buffer = NULL;
912 msg.size = 0;
913 err = drm_dp_i2c_do_msg(aux, &msg);
914
915 /*
916 * Reset msg.request in case in case it got
917 * changed into a WRITE_STATUS_UPDATE.
918 */
919 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
920
921 if (err < 0)
922 break;
923 /* We want each transaction to be as large as possible, but
924 * we'll go to smaller sizes if the hardware gives us a
925 * short reply.
926 */
927 transfer_size = dp_aux_i2c_transfer_size;
928 for (j = 0; j < msgs[i].len; j += msg.size) {
929 msg.buffer = msgs[i].buf + j;
930 msg.size = min(transfer_size, msgs[i].len - j);
931
932 err = drm_dp_i2c_drain_msg(aux, &msg);
933
934 /*
935 * Reset msg.request in case in case it got
936 * changed into a WRITE_STATUS_UPDATE.
937 */
938 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
939
940 if (err < 0)
941 break;
942 transfer_size = err;
943 }
944 if (err < 0)
945 break;
946 }
947 if (err >= 0)
948 err = num;
949 /* Send a bare address packet to close out the transaction.
950 * Zero sized messages specify an address only (bare
951 * address) transaction.
952 */
953 msg.request &= ~DP_AUX_I2C_MOT;
954 msg.buffer = NULL;
955 msg.size = 0;
956 (void)drm_dp_i2c_do_msg(aux, &msg);
957
958 return err;
959}
960
961static const struct i2c_algorithm drm_dp_i2c_algo = {
962 .functionality = drm_dp_i2c_functionality,
963 .master_xfer = drm_dp_i2c_xfer,
964};
965
966static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
967{
968 return container_of(i2c, struct drm_dp_aux, ddc);
969}
970
971static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
972{
973 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
974}
975
976static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
977{
978 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
979}
980
981static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
982{
983 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
984}
985
986static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
987 .lock_bus = lock_bus,
988 .trylock_bus = trylock_bus,
989 .unlock_bus = unlock_bus,
990};
991
992static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
993{
994 u8 buf, count;
995 int ret;
996
997 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
998 if (ret < 0)
999 return ret;
1000
1001 WARN_ON(!(buf & DP_TEST_SINK_START));
1002
1003 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1004 if (ret < 0)
1005 return ret;
1006
1007 count = buf & DP_TEST_COUNT_MASK;
1008 if (count == aux->crc_count)
1009 return -EAGAIN; /* No CRC yet */
1010
1011 aux->crc_count = count;
1012
1013 /*
1014 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
1015 * per component (RGB or CrYCb).
1016 */
1017 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1018 if (ret < 0)
1019 return ret;
1020
1021 return 0;
1022}
1023
1024static void drm_dp_aux_crc_work(struct work_struct *work)
1025{
1026 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1027 crc_work);
1028 struct drm_crtc *crtc;
1029 u8 crc_bytes[6];
1030 uint32_t crcs[3];
1031 int ret;
1032
1033 if (WARN_ON(!aux->crtc))
1034 return;
1035
1036 crtc = aux->crtc;
1037 while (crtc->crc.opened) {
1038 drm_crtc_wait_one_vblank(crtc);
1039 if (!crtc->crc.opened)
1040 break;
1041
1042 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1043 if (ret == -EAGAIN) {
1044 usleep_range(1000, 2000);
1045 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1046 }
1047
1048 if (ret == -EAGAIN) {
1049 DRM_DEBUG_KMS("Get CRC failed after retrying: %d\n",
1050 ret);
1051 continue;
1052 } else if (ret) {
1053 DRM_DEBUG_KMS("Failed to get a CRC: %d\n", ret);
1054 continue;
1055 }
1056
1057 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1058 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1059 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1060 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1061 }
1062}
1063
1064/**
1065 * drm_dp_aux_init() - minimally initialise an aux channel
1066 * @aux: DisplayPort AUX channel
1067 *
1068 * If you need to use the drm_dp_aux's i2c adapter prior to registering it
1069 * with the outside world, call drm_dp_aux_init() first. You must still
1070 * call drm_dp_aux_register() once the connector has been registered to
1071 * allow userspace access to the auxiliary DP channel.
1072 */
1073void drm_dp_aux_init(struct drm_dp_aux *aux)
1074{
1075 mutex_init(&aux->hw_mutex);
1076 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1077
1078 aux->ddc.algo = &drm_dp_i2c_algo;
1079 aux->ddc.algo_data = aux;
1080 aux->ddc.retries = 3;
1081
1082 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1083}
1084EXPORT_SYMBOL(drm_dp_aux_init);
1085
1086/**
1087 * drm_dp_aux_register() - initialise and register aux channel
1088 * @aux: DisplayPort AUX channel
1089 *
1090 * Automatically calls drm_dp_aux_init() if this hasn't been done yet.
1091 *
1092 * Returns 0 on success or a negative error code on failure.
1093 */
1094int drm_dp_aux_register(struct drm_dp_aux *aux)
1095{
1096 int ret;
1097
1098 if (!aux->ddc.algo)
1099 drm_dp_aux_init(aux);
1100
1101 aux->ddc.class = I2C_CLASS_DDC;
1102 aux->ddc.owner = THIS_MODULE;
1103 aux->ddc.dev.parent = aux->dev;
1104
1105 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1106 sizeof(aux->ddc.name));
1107
1108 ret = drm_dp_aux_register_devnode(aux);
1109 if (ret)
1110 return ret;
1111
1112 ret = i2c_add_adapter(&aux->ddc);
1113 if (ret) {
1114 drm_dp_aux_unregister_devnode(aux);
1115 return ret;
1116 }
1117
1118 return 0;
1119}
1120EXPORT_SYMBOL(drm_dp_aux_register);
1121
1122/**
1123 * drm_dp_aux_unregister() - unregister an AUX adapter
1124 * @aux: DisplayPort AUX channel
1125 */
1126void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1127{
1128 drm_dp_aux_unregister_devnode(aux);
1129 i2c_del_adapter(&aux->ddc);
1130}
1131EXPORT_SYMBOL(drm_dp_aux_unregister);
1132
1133#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1134
1135/**
1136 * drm_dp_psr_setup_time() - PSR setup in time usec
1137 * @psr_cap: PSR capabilities from DPCD
1138 *
1139 * Returns:
1140 * PSR setup time for the panel in microseconds, negative
1141 * error code on failure.
1142 */
1143int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1144{
1145 static const u16 psr_setup_time_us[] = {
1146 PSR_SETUP_TIME(330),
1147 PSR_SETUP_TIME(275),
1148 PSR_SETUP_TIME(220),
1149 PSR_SETUP_TIME(165),
1150 PSR_SETUP_TIME(110),
1151 PSR_SETUP_TIME(55),
1152 PSR_SETUP_TIME(0),
1153 };
1154 int i;
1155
1156 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1157 if (i >= ARRAY_SIZE(psr_setup_time_us))
1158 return -EINVAL;
1159
1160 return psr_setup_time_us[i];
1161}
1162EXPORT_SYMBOL(drm_dp_psr_setup_time);
1163
1164#undef PSR_SETUP_TIME
1165
1166/**
1167 * drm_dp_start_crc() - start capture of frame CRCs
1168 * @aux: DisplayPort AUX channel
1169 * @crtc: CRTC displaying the frames whose CRCs are to be captured
1170 *
1171 * Returns 0 on success or a negative error code on failure.
1172 */
1173int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1174{
1175 u8 buf;
1176 int ret;
1177
1178 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1179 if (ret < 0)
1180 return ret;
1181
1182 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1183 if (ret < 0)
1184 return ret;
1185
1186 aux->crc_count = 0;
1187 aux->crtc = crtc;
1188 schedule_work(&aux->crc_work);
1189
1190 return 0;
1191}
1192EXPORT_SYMBOL(drm_dp_start_crc);
1193
1194/**
1195 * drm_dp_stop_crc() - stop capture of frame CRCs
1196 * @aux: DisplayPort AUX channel
1197 *
1198 * Returns 0 on success or a negative error code on failure.
1199 */
1200int drm_dp_stop_crc(struct drm_dp_aux *aux)
1201{
1202 u8 buf;
1203 int ret;
1204
1205 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1206 if (ret < 0)
1207 return ret;
1208
1209 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1210 if (ret < 0)
1211 return ret;
1212
1213 flush_work(&aux->crc_work);
1214 aux->crtc = NULL;
1215
1216 return 0;
1217}
1218EXPORT_SYMBOL(drm_dp_stop_crc);
1219
1220struct dpcd_quirk {
1221 u8 oui[3];
1222 bool is_branch;
1223 u32 quirks;
1224};
1225
1226#define OUI(first, second, third) { (first), (second), (third) }
1227
1228static const struct dpcd_quirk dpcd_quirk_list[] = {
1229 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
1230 { OUI(0x00, 0x22, 0xb9), true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
1231};
1232
1233#undef OUI
1234
1235/*
1236 * Get a bit mask of DPCD quirks for the sink/branch device identified by
1237 * ident. The quirk data is shared but it's up to the drivers to act on the
1238 * data.
1239 *
1240 * For now, only the OUI (first three bytes) is used, but this may be extended
1241 * to device identification string and hardware/firmware revisions later.
1242 */
1243static u32
1244drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1245{
1246 const struct dpcd_quirk *quirk;
1247 u32 quirks = 0;
1248 int i;
1249
1250 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1251 quirk = &dpcd_quirk_list[i];
1252
1253 if (quirk->is_branch != is_branch)
1254 continue;
1255
1256 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1257 continue;
1258
1259 quirks |= quirk->quirks;
1260 }
1261
1262 return quirks;
1263}
1264
1265/**
1266 * drm_dp_read_desc - read sink/branch descriptor from DPCD
1267 * @aux: DisplayPort AUX channel
1268 * @desc: Device decriptor to fill from DPCD
1269 * @is_branch: true for branch devices, false for sink devices
1270 *
1271 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1272 * identification.
1273 *
1274 * Returns 0 on success or a negative error code on failure.
1275 */
1276int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1277 bool is_branch)
1278{
1279 struct drm_dp_dpcd_ident *ident = &desc->ident;
1280 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
1281 int ret, dev_id_len;
1282
1283 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
1284 if (ret < 0)
1285 return ret;
1286
1287 desc->quirks = drm_dp_get_quirks(ident, is_branch);
1288
1289 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
1290
1291 DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
1292 is_branch ? "branch" : "sink",
1293 (int)sizeof(ident->oui), ident->oui,
1294 dev_id_len, ident->device_id,
1295 ident->hw_rev >> 4, ident->hw_rev & 0xf,
1296 ident->sw_major_rev, ident->sw_minor_rev,
1297 desc->quirks);
1298
1299 return 0;
1300}
1301EXPORT_SYMBOL(drm_dp_read_desc);