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1/****************************************************************************\
2*
3* File Name atomfirmware.h
4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
5*
6* Description header file of general definitions for OS nd pre-OS video drivers
7*
8* Copyright 2014 Advanced Micro Devices, Inc.
9*
10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11* and associated documentation files (the "Software"), to deal in the Software without restriction,
12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14* subject to the following conditions:
15*
16* The above copyright notice and this permission notice shall be included in all copies or substantial
17* portions of the Software.
18*
19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25* OTHER DEALINGS IN THE SOFTWARE.
26*
27\****************************************************************************/
28
29/*IMPORTANT NOTES
30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33*/
34
35#ifndef _ATOMFIRMWARE_H_
36#define _ATOMFIRMWARE_H_
37
38enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
41};
42
43#ifdef _H2INC
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
46 #endif
47
48 #ifndef uint16_t
49 typedef unsigned short uint16_t;
50 #endif
51
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
54 #endif
55#endif
56
57enum atom_crtc_def{
58 ATOM_CRTC1 =0,
59 ATOM_CRTC2 =1,
60 ATOM_CRTC3 =2,
61 ATOM_CRTC4 =3,
62 ATOM_CRTC5 =4,
63 ATOM_CRTC6 =5,
64 ATOM_CRTC_INVALID =0xff,
65};
66
67enum atom_ppll_def{
68 ATOM_PPLL0 =2,
69 ATOM_GCK_DFS =8,
70 ATOM_FCH_CLK =9,
71 ATOM_DP_DTO =11,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
79};
80
81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82enum atom_dig_def{
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
90};
91
92//ucEncoderMode
93enum atom_encode_mode_def
94{
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
104};
105
106enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
112};
113
114enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
118};
119
120enum atom_operation_def{
121 ATOM_DISABLE = 0,
122 ATOM_ENABLE = 1,
123 ATOM_INIT = 7,
124 ATOM_GET_STATUS = 8,
125};
126
127enum atom_embedded_display_op_def{
128 ATOM_LCD_BL_OFF = 2,
129 ATOM_LCD_BL_OM = 3,
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
133};
134
135enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
142};
143
144/* define panel bit per color */
145enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
152};
153
154//ucVoltageType
155enum atom_voltage_type
156{
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178};
179
180enum atom_dgpu_vram_type{
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM = 0x60,
183};
184
185enum atom_dp_vs_preemph_def{
186 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
187 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
188 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
189 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
190 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
191 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
192 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
193 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
194 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
195 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
196};
197
198
199/*
200enum atom_string_def{
201asic_bus_type_pcie_string = "PCI_EXPRESS",
202atom_fire_gl_string = "FGL",
203atom_bios_string = "ATOM"
204};
205*/
206
207#pragma pack(1) /* BIOS data must use byte aligment*/
208
209enum atombios_image_offset{
210OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048,
211OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002,
212OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94,
213MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/
214OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f,
215OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e,
216};
217
218/****************************************************************************
219* Common header for all tables (Data table, Command function).
220* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
221* And the pointer actually points to this header.
222****************************************************************************/
223
224struct atom_common_table_header
225{
226 uint16_t structuresize;
227 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
228 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
229};
230
231/****************************************************************************
232* Structure stores the ROM header.
233****************************************************************************/
234struct atom_rom_header_v2_2
235{
236 struct atom_common_table_header table_header;
237 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
238 uint16_t bios_segment_address;
239 uint16_t protectedmodeoffset;
240 uint16_t configfilenameoffset;
241 uint16_t crc_block_offset;
242 uint16_t vbios_bootupmessageoffset;
243 uint16_t int10_offset;
244 uint16_t pcibusdevinitcode;
245 uint16_t iobaseaddress;
246 uint16_t subsystem_vendor_id;
247 uint16_t subsystem_id;
248 uint16_t pci_info_offset;
249 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position
250 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position
251 uint16_t reserved;
252 uint32_t pspdirtableoffset;
253};
254
255/*==============================hw function portion======================================================================*/
256
257
258/****************************************************************************
259* Structures used in Command.mtb, each function name is not given here since those function could change from time to time
260* The real functionality of each function is associated with the parameter structure version when defined
261* For all internal cmd function definitions, please reference to atomstruct.h
262****************************************************************************/
263struct atom_master_list_of_command_functions_v2_1{
264 uint16_t asic_init; //Function
265 uint16_t cmd_function1; //used as an internal one
266 uint16_t cmd_function2; //used as an internal one
267 uint16_t cmd_function3; //used as an internal one
268 uint16_t digxencodercontrol; //Function
269 uint16_t cmd_function5; //used as an internal one
270 uint16_t cmd_function6; //used as an internal one
271 uint16_t cmd_function7; //used as an internal one
272 uint16_t cmd_function8; //used as an internal one
273 uint16_t cmd_function9; //used as an internal one
274 uint16_t setengineclock; //Function
275 uint16_t setmemoryclock; //Function
276 uint16_t setpixelclock; //Function
277 uint16_t enabledisppowergating; //Function
278 uint16_t cmd_function14; //used as an internal one
279 uint16_t cmd_function15; //used as an internal one
280 uint16_t cmd_function16; //used as an internal one
281 uint16_t cmd_function17; //used as an internal one
282 uint16_t cmd_function18; //used as an internal one
283 uint16_t cmd_function19; //used as an internal one
284 uint16_t cmd_function20; //used as an internal one
285 uint16_t cmd_function21; //used as an internal one
286 uint16_t cmd_function22; //used as an internal one
287 uint16_t cmd_function23; //used as an internal one
288 uint16_t cmd_function24; //used as an internal one
289 uint16_t cmd_function25; //used as an internal one
290 uint16_t cmd_function26; //used as an internal one
291 uint16_t cmd_function27; //used as an internal one
292 uint16_t cmd_function28; //used as an internal one
293 uint16_t cmd_function29; //used as an internal one
294 uint16_t cmd_function30; //used as an internal one
295 uint16_t cmd_function31; //used as an internal one
296 uint16_t cmd_function32; //used as an internal one
297 uint16_t cmd_function33; //used as an internal one
298 uint16_t blankcrtc; //Function
299 uint16_t enablecrtc; //Function
300 uint16_t cmd_function36; //used as an internal one
301 uint16_t cmd_function37; //used as an internal one
302 uint16_t cmd_function38; //used as an internal one
303 uint16_t cmd_function39; //used as an internal one
304 uint16_t cmd_function40; //used as an internal one
305 uint16_t getsmuclockinfo; //Function
306 uint16_t selectcrtc_source; //Function
307 uint16_t cmd_function43; //used as an internal one
308 uint16_t cmd_function44; //used as an internal one
309 uint16_t cmd_function45; //used as an internal one
310 uint16_t setdceclock; //Function
311 uint16_t getmemoryclock; //Function
312 uint16_t getengineclock; //Function
313 uint16_t setcrtc_usingdtdtiming; //Function
314 uint16_t externalencodercontrol; //Function
315 uint16_t cmd_function51; //used as an internal one
316 uint16_t cmd_function52; //used as an internal one
317 uint16_t cmd_function53; //used as an internal one
318 uint16_t processi2cchanneltransaction;//Function
319 uint16_t cmd_function55; //used as an internal one
320 uint16_t cmd_function56; //used as an internal one
321 uint16_t cmd_function57; //used as an internal one
322 uint16_t cmd_function58; //used as an internal one
323 uint16_t cmd_function59; //used as an internal one
324 uint16_t computegpuclockparam; //Function
325 uint16_t cmd_function61; //used as an internal one
326 uint16_t cmd_function62; //used as an internal one
327 uint16_t dynamicmemorysettings; //Function function
328 uint16_t memorytraining; //Function function
329 uint16_t cmd_function65; //used as an internal one
330 uint16_t cmd_function66; //used as an internal one
331 uint16_t setvoltage; //Function
332 uint16_t cmd_function68; //used as an internal one
333 uint16_t readefusevalue; //Function
334 uint16_t cmd_function70; //used as an internal one
335 uint16_t cmd_function71; //used as an internal one
336 uint16_t cmd_function72; //used as an internal one
337 uint16_t cmd_function73; //used as an internal one
338 uint16_t cmd_function74; //used as an internal one
339 uint16_t cmd_function75; //used as an internal one
340 uint16_t dig1transmittercontrol; //Function
341 uint16_t cmd_function77; //used as an internal one
342 uint16_t processauxchanneltransaction;//Function
343 uint16_t cmd_function79; //used as an internal one
344 uint16_t getvoltageinfo; //Function
345};
346
347struct atom_master_command_function_v2_1
348{
349 struct atom_common_table_header table_header;
350 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
351};
352
353/****************************************************************************
354* Structures used in every command function
355****************************************************************************/
356struct atom_function_attribute
357{
358 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
359 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
360 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util
361};
362
363
364/****************************************************************************
365* Common header for all hw functions.
366* Every function pointed by _master_list_of_hw_function has this common header.
367* And the pointer actually points to this header.
368****************************************************************************/
369struct atom_rom_hw_function_header
370{
371 struct atom_common_table_header func_header;
372 struct atom_function_attribute func_attrib;
373};
374
375
376/*==============================sw data table portion======================================================================*/
377/****************************************************************************
378* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
379* The real name of each table is given when its data structure version is defined
380****************************************************************************/
381struct atom_master_list_of_data_tables_v2_1{
382 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/
383 uint16_t multimedia_info;
384 uint16_t smc_dpm_info;
385 uint16_t sw_datatable3;
386 uint16_t firmwareinfo; /* Shared by various SW components */
387 uint16_t sw_datatable5;
388 uint16_t lcd_info; /* Shared by various SW components */
389 uint16_t sw_datatable7;
390 uint16_t smu_info;
391 uint16_t sw_datatable9;
392 uint16_t sw_datatable10;
393 uint16_t vram_usagebyfirmware; /* Shared by various SW components */
394 uint16_t gpio_pin_lut; /* Shared by various SW components */
395 uint16_t sw_datatable13;
396 uint16_t gfx_info;
397 uint16_t powerplayinfo; /* Shared by various SW components */
398 uint16_t sw_datatable16;
399 uint16_t sw_datatable17;
400 uint16_t sw_datatable18;
401 uint16_t sw_datatable19;
402 uint16_t sw_datatable20;
403 uint16_t sw_datatable21;
404 uint16_t displayobjectinfo; /* Shared by various SW components */
405 uint16_t indirectioaccess; /* used as an internal one */
406 uint16_t umc_info; /* Shared by various SW components */
407 uint16_t sw_datatable25;
408 uint16_t sw_datatable26;
409 uint16_t dce_info; /* Shared by various SW components */
410 uint16_t vram_info; /* Shared by various SW components */
411 uint16_t sw_datatable29;
412 uint16_t integratedsysteminfo; /* Shared by various SW components */
413 uint16_t asic_profiling_info; /* Shared by various SW components */
414 uint16_t voltageobject_info; /* shared by various SW components */
415 uint16_t sw_datatable33;
416 uint16_t sw_datatable34;
417};
418
419
420struct atom_master_data_table_v2_1
421{
422 struct atom_common_table_header table_header;
423 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
424};
425
426
427struct atom_dtd_format
428{
429 uint16_t pixclk;
430 uint16_t h_active;
431 uint16_t h_blanking_time;
432 uint16_t v_active;
433 uint16_t v_blanking_time;
434 uint16_t h_sync_offset;
435 uint16_t h_sync_width;
436 uint16_t v_sync_offset;
437 uint16_t v_syncwidth;
438 uint16_t reserved;
439 uint16_t reserved0;
440 uint8_t h_border;
441 uint8_t v_border;
442 uint16_t miscinfo;
443 uint8_t atom_mode_id;
444 uint8_t refreshrate;
445};
446
447/* atom_dtd_format.modemiscinfo defintion */
448enum atom_dtd_format_modemiscinfo{
449 ATOM_HSYNC_POLARITY = 0x0002,
450 ATOM_VSYNC_POLARITY = 0x0004,
451 ATOM_H_REPLICATIONBY2 = 0x0010,
452 ATOM_V_REPLICATIONBY2 = 0x0020,
453 ATOM_INTERLACE = 0x0080,
454 ATOM_COMPOSITESYNC = 0x0040,
455};
456
457
458/* utilitypipeline
459 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
460 * the location of it can't change
461*/
462
463
464/*
465 ***************************************************************************
466 Data Table firmwareinfo structure
467 ***************************************************************************
468*/
469
470struct atom_firmware_info_v3_1
471{
472 struct atom_common_table_header table_header;
473 uint32_t firmware_revision;
474 uint32_t bootup_sclk_in10khz;
475 uint32_t bootup_mclk_in10khz;
476 uint32_t firmware_capability; // enum atombios_firmware_capability
477 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
478 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
479 uint16_t bootup_vddc_mv;
480 uint16_t bootup_vddci_mv;
481 uint16_t bootup_mvddc_mv;
482 uint16_t bootup_vddgfx_mv;
483 uint8_t mem_module_id;
484 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
485 uint8_t reserved1[2];
486 uint32_t mc_baseaddr_high;
487 uint32_t mc_baseaddr_low;
488 uint32_t reserved2[6];
489};
490
491/* Total 32bit cap indication */
492enum atombios_firmware_capability
493{
494 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
495 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
496 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
497};
498
499enum atom_cooling_solution_id{
500 AIR_COOLING = 0x00,
501 LIQUID_COOLING = 0x01
502};
503
504struct atom_firmware_info_v3_2 {
505 struct atom_common_table_header table_header;
506 uint32_t firmware_revision;
507 uint32_t bootup_sclk_in10khz;
508 uint32_t bootup_mclk_in10khz;
509 uint32_t firmware_capability; // enum atombios_firmware_capability
510 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
511 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
512 uint16_t bootup_vddc_mv;
513 uint16_t bootup_vddci_mv;
514 uint16_t bootup_mvddc_mv;
515 uint16_t bootup_vddgfx_mv;
516 uint8_t mem_module_id;
517 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
518 uint8_t reserved1[2];
519 uint32_t mc_baseaddr_high;
520 uint32_t mc_baseaddr_low;
521 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
522 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
523 uint8_t board_i2c_feature_slave_addr;
524 uint8_t reserved3;
525 uint16_t bootup_mvddq_mv;
526 uint16_t bootup_mvpp_mv;
527 uint32_t zfbstartaddrin16mb;
528 uint32_t reserved2[3];
529};
530
531/*
532 ***************************************************************************
533 Data Table lcd_info structure
534 ***************************************************************************
535*/
536
537struct lcd_info_v2_1
538{
539 struct atom_common_table_header table_header;
540 struct atom_dtd_format lcd_timing;
541 uint16_t backlight_pwm;
542 uint16_t special_handle_cap;
543 uint16_t panel_misc;
544 uint16_t lvds_max_slink_pclk;
545 uint16_t lvds_ss_percentage;
546 uint16_t lvds_ss_rate_10hz;
547 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
548 uint8_t pwr_on_de_to_vary_bl;
549 uint8_t pwr_down_vary_bloff_to_de;
550 uint8_t pwr_down_de_to_digoff;
551 uint8_t pwr_off_delay;
552 uint8_t pwr_on_vary_bl_to_blon;
553 uint8_t pwr_down_bloff_to_vary_bloff;
554 uint8_t panel_bpc;
555 uint8_t dpcd_edp_config_cap;
556 uint8_t dpcd_max_link_rate;
557 uint8_t dpcd_max_lane_count;
558 uint8_t dpcd_max_downspread;
559 uint8_t min_allowed_bl_level;
560 uint8_t max_allowed_bl_level;
561 uint8_t bootup_bl_level;
562 uint8_t dplvdsrxid;
563 uint32_t reserved1[8];
564};
565
566/* lcd_info_v2_1.panel_misc defintion */
567enum atom_lcd_info_panel_misc{
568 ATOM_PANEL_MISC_FPDI =0x0002,
569};
570
571//uceDPToLVDSRxId
572enum atom_lcd_info_dptolvds_rx_id
573{
574 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
575 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init
576 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
577};
578
579
580/*
581 ***************************************************************************
582 Data Table gpio_pin_lut structure
583 ***************************************************************************
584*/
585
586struct atom_gpio_pin_assignment
587{
588 uint32_t data_a_reg_index;
589 uint8_t gpio_bitshift;
590 uint8_t gpio_mask_bitshift;
591 uint8_t gpio_id;
592 uint8_t reserved;
593};
594
595/* atom_gpio_pin_assignment.gpio_id definition */
596enum atom_gpio_pin_assignment_gpio_id {
597 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
598 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
599 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
600
601 /* gpio_id pre-define id for multiple usage */
602 /* GPIO use to control PCIE_VDDC in certain SLT board */
603 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
604 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
605 PP_AC_DC_SWITCH_GPIO_PINID = 60,
606 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
607 VDDC_VRHOT_GPIO_PINID = 61,
608 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
609 VDDC_PCC_GPIO_PINID = 62,
610 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
611 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
612 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
613 DRAM_SELF_REFRESH_GPIO_PINID = 64,
614 /* Thermal interrupt output->system thermal chip GPIO pin */
615 THERMAL_INT_OUTPUT_GPIO_PINID =65,
616};
617
618
619struct atom_gpio_pin_lut_v2_1
620{
621 struct atom_common_table_header table_header;
622 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
623 struct atom_gpio_pin_assignment gpio_pin[8];
624};
625
626
627/*
628 ***************************************************************************
629 Data Table vram_usagebyfirmware structure
630 ***************************************************************************
631*/
632
633struct vram_usagebyfirmware_v2_1
634{
635 struct atom_common_table_header table_header;
636 uint32_t start_address_in_kb;
637 uint16_t used_by_firmware_in_kb;
638 uint16_t used_by_driver_in_kb;
639};
640
641
642/*
643 ***************************************************************************
644 Data Table displayobjectinfo structure
645 ***************************************************************************
646*/
647
648enum atom_object_record_type_id
649{
650 ATOM_I2C_RECORD_TYPE =1,
651 ATOM_HPD_INT_RECORD_TYPE =2,
652 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
653 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
654 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
655 ATOM_ENCODER_CAP_RECORD_TYPE=20,
656 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
657 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
658 ATOM_RECORD_END_TYPE =0xFF,
659};
660
661struct atom_common_record_header
662{
663 uint8_t record_type; //An emun to indicate the record type
664 uint8_t record_size; //The size of the whole record in byte
665};
666
667struct atom_i2c_record
668{
669 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE
670 uint8_t i2c_id;
671 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
672};
673
674struct atom_hpd_int_record
675{
676 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE
677 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
678 uint8_t plugin_pin_state;
679};
680
681// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
682enum atom_encoder_caps_def
683{
684 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
685 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not.
686 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
687 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
688 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
689};
690
691struct atom_encoder_caps_record
692{
693 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
694 uint32_t encodercaps;
695};
696
697enum atom_connector_caps_def
698{
699 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
700 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
701};
702
703struct atom_disp_connector_caps_record
704{
705 struct atom_common_record_header record_header;
706 uint32_t connectcaps;
707};
708
709//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
710struct atom_gpio_pin_control_pair
711{
712 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
713 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
714};
715
716struct atom_object_gpio_cntl_record
717{
718 struct atom_common_record_header record_header;
719 uint8_t flag; // Future expnadibility
720 uint8_t number_of_pins; // Number of GPIO pins used to control the object
721 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
722};
723
724//Definitions for GPIO pin state
725enum atom_gpio_pin_control_pinstate_def
726{
727 GPIO_PIN_TYPE_INPUT = 0x00,
728 GPIO_PIN_TYPE_OUTPUT = 0x10,
729 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
730
731//For GPIO_PIN_TYPE_OUTPUT the following is defined
732 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
733 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
734 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
735 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
736};
737
738// Indexes to GPIO array in GLSync record
739// GLSync record is for Frame Lock/Gen Lock feature.
740enum atom_glsync_record_gpio_index_def
741{
742 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
743 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
744 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
745 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
746 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
747 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
748 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
749 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
750 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
751 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
752};
753
754
755struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
756{
757 struct atom_common_record_header record_header;
758 uint8_t hpd_pin_map[8];
759};
760
761struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
762{
763 struct atom_common_record_header record_header;
764 uint8_t aux_ddc_map[8];
765};
766
767struct atom_connector_forced_tmds_cap_record
768{
769 struct atom_common_record_header record_header;
770 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
771 uint8_t maxtmdsclkrate_in2_5mhz;
772 uint8_t reserved;
773};
774
775struct atom_connector_layout_info
776{
777 uint16_t connectorobjid;
778 uint8_t connector_type;
779 uint8_t position;
780};
781
782// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
783enum atom_connector_layout_info_connector_type_def
784{
785 CONNECTOR_TYPE_DVI_D = 1,
786
787 CONNECTOR_TYPE_HDMI = 4,
788 CONNECTOR_TYPE_DISPLAY_PORT = 5,
789 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
790};
791
792struct atom_bracket_layout_record
793{
794 struct atom_common_record_header record_header;
795 uint8_t bracketlen;
796 uint8_t bracketwidth;
797 uint8_t conn_num;
798 uint8_t reserved;
799 struct atom_connector_layout_info conn_info[1];
800};
801
802enum atom_display_device_tag_def{
803 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
804 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
805 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
806 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
807 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
808 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
809 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
810 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
811};
812
813struct atom_display_object_path_v2
814{
815 uint16_t display_objid; //Connector Object ID or Misc Object ID
816 uint16_t disp_recordoffset;
817 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
818 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view;
819 uint16_t encoder_recordoffset;
820 uint16_t extencoder_recordoffset;
821 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
822 uint8_t priority_id;
823 uint8_t reserved;
824};
825
826struct display_object_info_table_v1_4
827{
828 struct atom_common_table_header table_header;
829 uint16_t supporteddevices;
830 uint8_t number_of_path;
831 uint8_t reserved;
832 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
833};
834
835
836/*
837 ***************************************************************************
838 Data Table dce_info structure
839 ***************************************************************************
840*/
841struct atom_display_controller_info_v4_1
842{
843 struct atom_common_table_header table_header;
844 uint32_t display_caps;
845 uint32_t bootup_dispclk_10khz;
846 uint16_t dce_refclk_10khz;
847 uint16_t i2c_engine_refclk_10khz;
848 uint16_t dvi_ss_percentage; // in unit of 0.001%
849 uint16_t dvi_ss_rate_10hz;
850 uint16_t hdmi_ss_percentage; // in unit of 0.001%
851 uint16_t hdmi_ss_rate_10hz;
852 uint16_t dp_ss_percentage; // in unit of 0.001%
853 uint16_t dp_ss_rate_10hz;
854 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
855 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
856 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
857 uint8_t ss_reserved;
858 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
859 uint8_t reserved1[3];
860 uint16_t dpphy_refclk_10khz;
861 uint16_t reserved2;
862 uint8_t dceip_min_ver;
863 uint8_t dceip_max_ver;
864 uint8_t max_disp_pipe_num;
865 uint8_t max_vbios_active_disp_pipe_num;
866 uint8_t max_ppll_num;
867 uint8_t max_disp_phy_num;
868 uint8_t max_aux_pairs;
869 uint8_t remotedisplayconfig;
870 uint8_t reserved3[8];
871};
872
873
874struct atom_display_controller_info_v4_2
875{
876 struct atom_common_table_header table_header;
877 uint32_t display_caps;
878 uint32_t bootup_dispclk_10khz;
879 uint16_t dce_refclk_10khz;
880 uint16_t i2c_engine_refclk_10khz;
881 uint16_t dvi_ss_percentage; // in unit of 0.001%
882 uint16_t dvi_ss_rate_10hz;
883 uint16_t hdmi_ss_percentage; // in unit of 0.001%
884 uint16_t hdmi_ss_rate_10hz;
885 uint16_t dp_ss_percentage; // in unit of 0.001%
886 uint16_t dp_ss_rate_10hz;
887 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
888 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
889 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
890 uint8_t ss_reserved;
891 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
892 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
893 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
894 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
895 uint16_t dpphy_refclk_10khz;
896 uint16_t reserved2;
897 uint8_t dcnip_min_ver;
898 uint8_t dcnip_max_ver;
899 uint8_t max_disp_pipe_num;
900 uint8_t max_vbios_active_disp_pipe_num;
901 uint8_t max_ppll_num;
902 uint8_t max_disp_phy_num;
903 uint8_t max_aux_pairs;
904 uint8_t remotedisplayconfig;
905 uint8_t reserved3[8];
906};
907
908
909enum dce_info_caps_def
910{
911 // only for VBIOS
912 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02,
913 // only for VBIOS
914 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
915 // only for VBIOS
916 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
917
918};
919
920/*
921 ***************************************************************************
922 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
923 ***************************************************************************
924*/
925struct atom_ext_display_path
926{
927 uint16_t device_tag; //A bit vector to show what devices are supported
928 uint16_t device_acpi_enum; //16bit device ACPI id.
929 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions
930 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
931 uint8_t hpdlut_index; //An index into external HPD pin LUT
932 uint16_t ext_encoder_objid; //external encoder object id
933 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
934 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
935 uint16_t caps;
936 uint16_t reserved;
937};
938
939//usCaps
940enum ext_display_path_cap_def
941{
942 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001,
943 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002,
944 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C,
945};
946
947struct atom_external_display_connection_info
948{
949 struct atom_common_table_header table_header;
950 uint8_t guid[16]; // a GUID is a 16 byte long string
951 struct atom_ext_display_path path[7]; // total of fixed 7 entries.
952 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
953 uint8_t stereopinid; // use for eDP panel
954 uint8_t remotedisplayconfig;
955 uint8_t edptolvdsrxid;
956 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
957 uint8_t reserved[3]; // for potential expansion
958};
959
960/*
961 ***************************************************************************
962 Data Table integratedsysteminfo structure
963 ***************************************************************************
964*/
965
966struct atom_camera_dphy_timing_param
967{
968 uint8_t profile_id; // SENSOR_PROFILES
969 uint32_t param;
970};
971
972struct atom_camera_dphy_elec_param
973{
974 uint16_t param[3];
975};
976
977struct atom_camera_module_info
978{
979 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
980 uint8_t module_name[8];
981 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
982};
983
984struct atom_camera_flashlight_info
985{
986 uint8_t flashlight_id; // 0: Rear, 1: Front
987 uint8_t name[8];
988};
989
990struct atom_camera_data
991{
992 uint32_t versionCode;
993 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
994 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
995 struct atom_camera_dphy_elec_param dphy_param;
996 uint32_t crc_val; // CRC
997};
998
999
1000struct atom_14nm_dpphy_dvihdmi_tuningset
1001{
1002 uint32_t max_symclk_in10khz;
1003 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1004 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1005 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1006 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1007 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1008 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1009 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1010};
1011
1012struct atom_14nm_dpphy_dp_setting{
1013 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1014 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
1015 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1016 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1017};
1018
1019struct atom_14nm_dpphy_dp_tuningset{
1020 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1021 uint8_t version;
1022 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset
1023 uint16_t reserved;
1024 struct atom_14nm_dpphy_dp_setting dptuning[10];
1025};
1026
1027struct atom_14nm_dig_transmitter_info_header_v4_0{
1028 struct atom_common_table_header table_header;
1029 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1030 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl
1031 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl
1032};
1033
1034struct atom_14nm_combphy_tmds_vs_set
1035{
1036 uint8_t sym_clk;
1037 uint8_t dig_mode;
1038 uint8_t phy_sel;
1039 uint16_t common_mar_deemph_nom__margin_deemph_val;
1040 uint8_t common_seldeemph60__deemph_6db_4_val;
1041 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1042 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1043 uint8_t margin_deemph_lane0__deemph_sel_val;
1044};
1045
1046struct atom_i2c_reg_info {
1047 uint8_t ucI2cRegIndex;
1048 uint8_t ucI2cRegVal;
1049};
1050
1051struct atom_hdmi_retimer_redriver_set {
1052 uint8_t HdmiSlvAddr;
1053 uint8_t HdmiRegNum;
1054 uint8_t Hdmi6GRegNum;
1055 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
1056 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
1057};
1058
1059struct atom_integrated_system_info_v1_11
1060{
1061 struct atom_common_table_header table_header;
1062 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1063 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1064 uint32_t system_config;
1065 uint32_t cpucapinfo;
1066 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1067 uint16_t gpuclk_ss_type;
1068 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1069 uint16_t lvds_ss_rate_10hz;
1070 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1071 uint16_t hdmi_ss_rate_10hz;
1072 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1073 uint16_t dvi_ss_rate_10hz;
1074 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1075 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1076 uint16_t backlight_pwm_hz; // pwm frequency in hz
1077 uint8_t memorytype; // enum of atom_sys_mem_type
1078 uint8_t umachannelnumber; // number of memory channels
1079 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1080 uint8_t pwr_on_de_to_vary_bl;
1081 uint8_t pwr_down_vary_bloff_to_de;
1082 uint8_t pwr_down_de_to_digoff;
1083 uint8_t pwr_off_delay;
1084 uint8_t pwr_on_vary_bl_to_blon;
1085 uint8_t pwr_down_bloff_to_vary_bloff;
1086 uint8_t min_allowed_bl_level;
1087 struct atom_external_display_connection_info extdispconninfo;
1088 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1089 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1090 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1091 struct atom_14nm_dpphy_dp_tuningset dp_tuningset;
1092 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;
1093 struct atom_camera_data camera_info;
1094 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1095 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1096 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1097 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1098 uint32_t reserved[108];
1099};
1100
1101
1102// system_config
1103enum atom_system_vbiosmisc_def{
1104 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1105};
1106
1107
1108// gpucapinfo
1109enum atom_system_gpucapinf_def{
1110 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1111};
1112
1113//dpphy_override
1114enum atom_sysinfo_dpphy_override_def{
1115 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1116 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1117 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1118 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1119 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1120};
1121
1122//lvds_misc
1123enum atom_sys_info_lvds_misc_def
1124{
1125 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1126 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1127 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1128};
1129
1130
1131//memorytype DMI Type 17 offset 12h - Memory Type
1132enum atom_dmi_t17_mem_type_def{
1133 OtherMemType = 0x01, ///< Assign 01 to Other
1134 UnknownMemType, ///< Assign 02 to Unknown
1135 DramMemType, ///< Assign 03 to DRAM
1136 EdramMemType, ///< Assign 04 to EDRAM
1137 VramMemType, ///< Assign 05 to VRAM
1138 SramMemType, ///< Assign 06 to SRAM
1139 RamMemType, ///< Assign 07 to RAM
1140 RomMemType, ///< Assign 08 to ROM
1141 FlashMemType, ///< Assign 09 to Flash
1142 EepromMemType, ///< Assign 10 to EEPROM
1143 FepromMemType, ///< Assign 11 to FEPROM
1144 EpromMemType, ///< Assign 12 to EPROM
1145 CdramMemType, ///< Assign 13 to CDRAM
1146 ThreeDramMemType, ///< Assign 14 to 3DRAM
1147 SdramMemType, ///< Assign 15 to SDRAM
1148 SgramMemType, ///< Assign 16 to SGRAM
1149 RdramMemType, ///< Assign 17 to RDRAM
1150 DdrMemType, ///< Assign 18 to DDR
1151 Ddr2MemType, ///< Assign 19 to DDR2
1152 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
1153 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1154 Fbd2MemType, ///< Assign 25 to FBD2
1155 Ddr4MemType, ///< Assign 26 to DDR4
1156 LpDdrMemType, ///< Assign 27 to LPDDR
1157 LpDdr2MemType, ///< Assign 28 to LPDDR2
1158 LpDdr3MemType, ///< Assign 29 to LPDDR3
1159 LpDdr4MemType, ///< Assign 30 to LPDDR4
1160};
1161
1162
1163// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1164struct atom_fusion_system_info_v4
1165{
1166 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1167 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1168};
1169
1170
1171/*
1172 ***************************************************************************
1173 Data Table gfx_info structure
1174 ***************************************************************************
1175*/
1176
1177struct atom_gfx_info_v2_2
1178{
1179 struct atom_common_table_header table_header;
1180 uint8_t gfxip_min_ver;
1181 uint8_t gfxip_max_ver;
1182 uint8_t max_shader_engines;
1183 uint8_t max_tile_pipes;
1184 uint8_t max_cu_per_sh;
1185 uint8_t max_sh_per_se;
1186 uint8_t max_backends_per_se;
1187 uint8_t max_texture_channel_caches;
1188 uint32_t regaddr_cp_dma_src_addr;
1189 uint32_t regaddr_cp_dma_src_addr_hi;
1190 uint32_t regaddr_cp_dma_dst_addr;
1191 uint32_t regaddr_cp_dma_dst_addr_hi;
1192 uint32_t regaddr_cp_dma_command;
1193 uint32_t regaddr_cp_status;
1194 uint32_t regaddr_rlc_gpu_clock_32;
1195 uint32_t rlc_gpu_timer_refclk;
1196};
1197
1198struct atom_gfx_info_v2_3 {
1199 struct atom_common_table_header table_header;
1200 uint8_t gfxip_min_ver;
1201 uint8_t gfxip_max_ver;
1202 uint8_t max_shader_engines;
1203 uint8_t max_tile_pipes;
1204 uint8_t max_cu_per_sh;
1205 uint8_t max_sh_per_se;
1206 uint8_t max_backends_per_se;
1207 uint8_t max_texture_channel_caches;
1208 uint32_t regaddr_cp_dma_src_addr;
1209 uint32_t regaddr_cp_dma_src_addr_hi;
1210 uint32_t regaddr_cp_dma_dst_addr;
1211 uint32_t regaddr_cp_dma_dst_addr_hi;
1212 uint32_t regaddr_cp_dma_command;
1213 uint32_t regaddr_cp_status;
1214 uint32_t regaddr_rlc_gpu_clock_32;
1215 uint32_t rlc_gpu_timer_refclk;
1216 uint8_t active_cu_per_sh;
1217 uint8_t active_rb_per_se;
1218 uint16_t gcgoldenoffset;
1219 uint32_t rm21_sram_vmin_value;
1220};
1221
1222/*
1223 ***************************************************************************
1224 Data Table smu_info structure
1225 ***************************************************************************
1226*/
1227struct atom_smu_info_v3_1
1228{
1229 struct atom_common_table_header table_header;
1230 uint8_t smuip_min_ver;
1231 uint8_t smuip_max_ver;
1232 uint8_t smu_rsd1;
1233 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1234 uint16_t sclk_ss_percentage;
1235 uint16_t sclk_ss_rate_10hz;
1236 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1237 uint16_t gpuclk_ss_rate_10hz;
1238 uint32_t core_refclk_10khz;
1239 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1240 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1241 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1242 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1243 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1244 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1245 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1246 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1247};
1248
1249struct atom_smu_info_v3_2 {
1250 struct atom_common_table_header table_header;
1251 uint8_t smuip_min_ver;
1252 uint8_t smuip_max_ver;
1253 uint8_t smu_rsd1;
1254 uint8_t gpuclk_ss_mode;
1255 uint16_t sclk_ss_percentage;
1256 uint16_t sclk_ss_rate_10hz;
1257 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1258 uint16_t gpuclk_ss_rate_10hz;
1259 uint32_t core_refclk_10khz;
1260 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1261 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1262 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1263 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1264 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1265 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1266 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1267 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1268 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1269 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1270 uint16_t smugoldenoffset;
1271 uint32_t gpupll_vco_freq_10khz;
1272 uint32_t bootup_smnclk_10khz;
1273 uint32_t bootup_socclk_10khz;
1274 uint32_t bootup_mp0clk_10khz;
1275 uint32_t bootup_mp1clk_10khz;
1276 uint32_t bootup_lclk_10khz;
1277 uint32_t bootup_dcefclk_10khz;
1278 uint32_t ctf_threshold_override_value;
1279 uint32_t reserved[5];
1280};
1281
1282struct atom_smu_info_v3_3 {
1283 struct atom_common_table_header table_header;
1284 uint8_t smuip_min_ver;
1285 uint8_t smuip_max_ver;
1286 uint8_t smu_rsd1;
1287 uint8_t gpuclk_ss_mode;
1288 uint16_t sclk_ss_percentage;
1289 uint16_t sclk_ss_rate_10hz;
1290 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1291 uint16_t gpuclk_ss_rate_10hz;
1292 uint32_t core_refclk_10khz;
1293 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1294 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1295 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1296 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1297 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1298 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1299 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1300 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1301 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1302 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1303 uint16_t smugoldenoffset;
1304 uint32_t gpupll_vco_freq_10khz;
1305 uint32_t bootup_smnclk_10khz;
1306 uint32_t bootup_socclk_10khz;
1307 uint32_t bootup_mp0clk_10khz;
1308 uint32_t bootup_mp1clk_10khz;
1309 uint32_t bootup_lclk_10khz;
1310 uint32_t bootup_dcefclk_10khz;
1311 uint32_t ctf_threshold_override_value;
1312 uint32_t syspll3_0_vco_freq_10khz;
1313 uint32_t syspll3_1_vco_freq_10khz;
1314 uint32_t bootup_fclk_10khz;
1315 uint32_t bootup_waflclk_10khz;
1316 uint32_t reserved[3];
1317};
1318
1319/*
1320 ***************************************************************************
1321 Data Table smc_dpm_info structure
1322 ***************************************************************************
1323 */
1324struct atom_smc_dpm_info_v4_1
1325{
1326 struct atom_common_table_header table_header;
1327 uint8_t liquid1_i2c_address;
1328 uint8_t liquid2_i2c_address;
1329 uint8_t vr_i2c_address;
1330 uint8_t plx_i2c_address;
1331
1332 uint8_t liquid_i2c_linescl;
1333 uint8_t liquid_i2c_linesda;
1334 uint8_t vr_i2c_linescl;
1335 uint8_t vr_i2c_linesda;
1336
1337 uint8_t plx_i2c_linescl;
1338 uint8_t plx_i2c_linesda;
1339 uint8_t vrsensorpresent;
1340 uint8_t liquidsensorpresent;
1341
1342 uint16_t maxvoltagestepgfx;
1343 uint16_t maxvoltagestepsoc;
1344
1345 uint8_t vddgfxvrmapping;
1346 uint8_t vddsocvrmapping;
1347 uint8_t vddmem0vrmapping;
1348 uint8_t vddmem1vrmapping;
1349
1350 uint8_t gfxulvphasesheddingmask;
1351 uint8_t soculvphasesheddingmask;
1352 uint8_t padding8_v[2];
1353
1354 uint16_t gfxmaxcurrent;
1355 uint8_t gfxoffset;
1356 uint8_t padding_telemetrygfx;
1357
1358 uint16_t socmaxcurrent;
1359 uint8_t socoffset;
1360 uint8_t padding_telemetrysoc;
1361
1362 uint16_t mem0maxcurrent;
1363 uint8_t mem0offset;
1364 uint8_t padding_telemetrymem0;
1365
1366 uint16_t mem1maxcurrent;
1367 uint8_t mem1offset;
1368 uint8_t padding_telemetrymem1;
1369
1370 uint8_t acdcgpio;
1371 uint8_t acdcpolarity;
1372 uint8_t vr0hotgpio;
1373 uint8_t vr0hotpolarity;
1374
1375 uint8_t vr1hotgpio;
1376 uint8_t vr1hotpolarity;
1377 uint8_t padding1;
1378 uint8_t padding2;
1379
1380 uint8_t ledpin0;
1381 uint8_t ledpin1;
1382 uint8_t ledpin2;
1383 uint8_t padding8_4;
1384
1385 uint8_t pllgfxclkspreadenabled;
1386 uint8_t pllgfxclkspreadpercent;
1387 uint16_t pllgfxclkspreadfreq;
1388
1389 uint8_t uclkspreadenabled;
1390 uint8_t uclkspreadpercent;
1391 uint16_t uclkspreadfreq;
1392
1393 uint8_t socclkspreadenabled;
1394 uint8_t socclkspreadpercent;
1395 uint16_t socclkspreadfreq;
1396
1397 uint8_t acggfxclkspreadenabled;
1398 uint8_t acggfxclkspreadpercent;
1399 uint16_t acggfxclkspreadfreq;
1400
1401 uint32_t boardreserved[10];
1402};
1403
1404/*
1405 ***************************************************************************
1406 Data Table asic_profiling_info structure
1407 ***************************************************************************
1408*/
1409struct atom_asic_profiling_info_v4_1
1410{
1411 struct atom_common_table_header table_header;
1412 uint32_t maxvddc;
1413 uint32_t minvddc;
1414 uint32_t avfs_meannsigma_acontant0;
1415 uint32_t avfs_meannsigma_acontant1;
1416 uint32_t avfs_meannsigma_acontant2;
1417 uint16_t avfs_meannsigma_dc_tol_sigma;
1418 uint16_t avfs_meannsigma_platform_mean;
1419 uint16_t avfs_meannsigma_platform_sigma;
1420 uint32_t gb_vdroop_table_cksoff_a0;
1421 uint32_t gb_vdroop_table_cksoff_a1;
1422 uint32_t gb_vdroop_table_cksoff_a2;
1423 uint32_t gb_vdroop_table_ckson_a0;
1424 uint32_t gb_vdroop_table_ckson_a1;
1425 uint32_t gb_vdroop_table_ckson_a2;
1426 uint32_t avfsgb_fuse_table_cksoff_m1;
1427 uint32_t avfsgb_fuse_table_cksoff_m2;
1428 uint32_t avfsgb_fuse_table_cksoff_b;
1429 uint32_t avfsgb_fuse_table_ckson_m1;
1430 uint32_t avfsgb_fuse_table_ckson_m2;
1431 uint32_t avfsgb_fuse_table_ckson_b;
1432 uint16_t max_voltage_0_25mv;
1433 uint8_t enable_gb_vdroop_table_cksoff;
1434 uint8_t enable_gb_vdroop_table_ckson;
1435 uint8_t enable_gb_fuse_table_cksoff;
1436 uint8_t enable_gb_fuse_table_ckson;
1437 uint16_t psm_age_comfactor;
1438 uint8_t enable_apply_avfs_cksoff_voltage;
1439 uint8_t reserved;
1440 uint32_t dispclk2gfxclk_a;
1441 uint32_t dispclk2gfxclk_b;
1442 uint32_t dispclk2gfxclk_c;
1443 uint32_t pixclk2gfxclk_a;
1444 uint32_t pixclk2gfxclk_b;
1445 uint32_t pixclk2gfxclk_c;
1446 uint32_t dcefclk2gfxclk_a;
1447 uint32_t dcefclk2gfxclk_b;
1448 uint32_t dcefclk2gfxclk_c;
1449 uint32_t phyclk2gfxclk_a;
1450 uint32_t phyclk2gfxclk_b;
1451 uint32_t phyclk2gfxclk_c;
1452};
1453
1454struct atom_asic_profiling_info_v4_2 {
1455 struct atom_common_table_header table_header;
1456 uint32_t maxvddc;
1457 uint32_t minvddc;
1458 uint32_t avfs_meannsigma_acontant0;
1459 uint32_t avfs_meannsigma_acontant1;
1460 uint32_t avfs_meannsigma_acontant2;
1461 uint16_t avfs_meannsigma_dc_tol_sigma;
1462 uint16_t avfs_meannsigma_platform_mean;
1463 uint16_t avfs_meannsigma_platform_sigma;
1464 uint32_t gb_vdroop_table_cksoff_a0;
1465 uint32_t gb_vdroop_table_cksoff_a1;
1466 uint32_t gb_vdroop_table_cksoff_a2;
1467 uint32_t gb_vdroop_table_ckson_a0;
1468 uint32_t gb_vdroop_table_ckson_a1;
1469 uint32_t gb_vdroop_table_ckson_a2;
1470 uint32_t avfsgb_fuse_table_cksoff_m1;
1471 uint32_t avfsgb_fuse_table_cksoff_m2;
1472 uint32_t avfsgb_fuse_table_cksoff_b;
1473 uint32_t avfsgb_fuse_table_ckson_m1;
1474 uint32_t avfsgb_fuse_table_ckson_m2;
1475 uint32_t avfsgb_fuse_table_ckson_b;
1476 uint16_t max_voltage_0_25mv;
1477 uint8_t enable_gb_vdroop_table_cksoff;
1478 uint8_t enable_gb_vdroop_table_ckson;
1479 uint8_t enable_gb_fuse_table_cksoff;
1480 uint8_t enable_gb_fuse_table_ckson;
1481 uint16_t psm_age_comfactor;
1482 uint8_t enable_apply_avfs_cksoff_voltage;
1483 uint8_t reserved;
1484 uint32_t dispclk2gfxclk_a;
1485 uint32_t dispclk2gfxclk_b;
1486 uint32_t dispclk2gfxclk_c;
1487 uint32_t pixclk2gfxclk_a;
1488 uint32_t pixclk2gfxclk_b;
1489 uint32_t pixclk2gfxclk_c;
1490 uint32_t dcefclk2gfxclk_a;
1491 uint32_t dcefclk2gfxclk_b;
1492 uint32_t dcefclk2gfxclk_c;
1493 uint32_t phyclk2gfxclk_a;
1494 uint32_t phyclk2gfxclk_b;
1495 uint32_t phyclk2gfxclk_c;
1496 uint32_t acg_gb_vdroop_table_a0;
1497 uint32_t acg_gb_vdroop_table_a1;
1498 uint32_t acg_gb_vdroop_table_a2;
1499 uint32_t acg_avfsgb_fuse_table_m1;
1500 uint32_t acg_avfsgb_fuse_table_m2;
1501 uint32_t acg_avfsgb_fuse_table_b;
1502 uint8_t enable_acg_gb_vdroop_table;
1503 uint8_t enable_acg_gb_fuse_table;
1504 uint32_t acg_dispclk2gfxclk_a;
1505 uint32_t acg_dispclk2gfxclk_b;
1506 uint32_t acg_dispclk2gfxclk_c;
1507 uint32_t acg_pixclk2gfxclk_a;
1508 uint32_t acg_pixclk2gfxclk_b;
1509 uint32_t acg_pixclk2gfxclk_c;
1510 uint32_t acg_dcefclk2gfxclk_a;
1511 uint32_t acg_dcefclk2gfxclk_b;
1512 uint32_t acg_dcefclk2gfxclk_c;
1513 uint32_t acg_phyclk2gfxclk_a;
1514 uint32_t acg_phyclk2gfxclk_b;
1515 uint32_t acg_phyclk2gfxclk_c;
1516};
1517
1518/*
1519 ***************************************************************************
1520 Data Table multimedia_info structure
1521 ***************************************************************************
1522*/
1523struct atom_multimedia_info_v2_1
1524{
1525 struct atom_common_table_header table_header;
1526 uint8_t uvdip_min_ver;
1527 uint8_t uvdip_max_ver;
1528 uint8_t vceip_min_ver;
1529 uint8_t vceip_max_ver;
1530 uint16_t uvd_enc_max_input_width_pixels;
1531 uint16_t uvd_enc_max_input_height_pixels;
1532 uint16_t vce_enc_max_input_width_pixels;
1533 uint16_t vce_enc_max_input_height_pixels;
1534 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
1535 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
1536};
1537
1538
1539/*
1540 ***************************************************************************
1541 Data Table umc_info structure
1542 ***************************************************************************
1543*/
1544struct atom_umc_info_v3_1
1545{
1546 struct atom_common_table_header table_header;
1547 uint32_t ucode_version;
1548 uint32_t ucode_rom_startaddr;
1549 uint32_t ucode_length;
1550 uint16_t umc_reg_init_offset;
1551 uint16_t customer_ucode_name_offset;
1552 uint16_t mclk_ss_percentage;
1553 uint16_t mclk_ss_rate_10hz;
1554 uint8_t umcip_min_ver;
1555 uint8_t umcip_max_ver;
1556 uint8_t vram_type; //enum of atom_dgpu_vram_type
1557 uint8_t umc_config;
1558 uint32_t mem_refclk_10khz;
1559};
1560
1561
1562/*
1563 ***************************************************************************
1564 Data Table vram_info structure
1565 ***************************************************************************
1566*/
1567struct atom_vram_module_v9
1568{
1569 // Design Specific Values
1570 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
1571 uint32_t channel_enable; // for 32 channel ASIC usage
1572 uint32_t umcch_addrcfg;
1573 uint32_t umcch_addrsel;
1574 uint32_t umcch_colsel;
1575 uint16_t vram_module_size; // Size of atom_vram_module_v9
1576 uint8_t ext_memory_id; // Current memory module ID
1577 uint8_t memory_type; // enum of atom_dgpu_vram_type
1578 uint8_t channel_num; // Number of mem. channels supported in this module
1579 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
1580 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
1581 uint8_t tunningset_id; // MC phy registers set per.
1582 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
1583 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
1584 uint16_t vram_rsd2; // reserved
1585 char dram_pnstring[20]; // part number end with '0'.
1586};
1587
1588
1589struct atom_vram_info_header_v2_3
1590{
1591 struct atom_common_table_header table_header;
1592 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
1593 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
1594 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
1595 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
1596 uint16_t dram_data_remap_tbloffset; // reserved for now
1597 uint16_t vram_rsd2[3];
1598 uint8_t vram_module_num; // indicate number of VRAM module
1599 uint8_t vram_rsd1[2];
1600 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
1601 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
1602};
1603
1604struct atom_umc_register_addr_info{
1605 uint32_t umc_register_addr:24;
1606 uint32_t umc_reg_type_ind:1;
1607 uint32_t umc_reg_rsvd:7;
1608};
1609
1610//atom_umc_register_addr_info.
1611enum atom_umc_register_addr_info_flag{
1612 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
1613};
1614
1615union atom_umc_register_addr_info_access
1616{
1617 struct atom_umc_register_addr_info umc_reg_addr;
1618 uint32_t u32umc_reg_addr;
1619};
1620
1621struct atom_umc_reg_setting_id_config{
1622 uint32_t memclockrange:24;
1623 uint32_t mem_blk_id:8;
1624};
1625
1626union atom_umc_reg_setting_id_config_access
1627{
1628 struct atom_umc_reg_setting_id_config umc_id_access;
1629 uint32_t u32umc_id_access;
1630};
1631
1632struct atom_umc_reg_setting_data_block{
1633 union atom_umc_reg_setting_id_config_access block_id;
1634 uint32_t u32umc_reg_data[1];
1635};
1636
1637struct atom_umc_init_reg_block{
1638 uint16_t umc_reg_num;
1639 uint16_t reserved;
1640 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num;
1641 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
1642};
1643
1644
1645/*
1646 ***************************************************************************
1647 Data Table voltageobject_info structure
1648 ***************************************************************************
1649*/
1650struct atom_i2c_data_entry
1651{
1652 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit
1653 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit
1654};
1655
1656struct atom_voltage_object_header_v4{
1657 uint8_t voltage_type; //enum atom_voltage_type
1658 uint8_t voltage_mode; //enum atom_voltage_object_mode
1659 uint16_t object_size; //Size of Object
1660};
1661
1662// atom_voltage_object_header_v4.voltage_mode
1663enum atom_voltage_object_mode
1664{
1665 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
1666 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
1667 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
1668 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
1669 VOLTAGE_OBJ_EVV = 8,
1670 VOLTAGE_OBJ_MERGED_POWER = 9,
1671};
1672
1673struct atom_i2c_voltage_object_v4
1674{
1675 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
1676 uint8_t regulator_id; //Indicate Voltage Regulator Id
1677 uint8_t i2c_id;
1678 uint8_t i2c_slave_addr;
1679 uint8_t i2c_control_offset;
1680 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
1681 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
1682 uint8_t reserved[2];
1683 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
1684};
1685
1686// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
1687enum atom_i2c_voltage_control_flag
1688{
1689 VOLTAGE_DATA_ONE_BYTE = 0,
1690 VOLTAGE_DATA_TWO_BYTE = 1,
1691};
1692
1693
1694struct atom_voltage_gpio_map_lut
1695{
1696 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
1697 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV
1698};
1699
1700struct atom_gpio_voltage_object_v4
1701{
1702 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
1703 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
1704 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
1705 uint8_t phase_delay_us; // phase delay in unit of micro second
1706 uint8_t reserved;
1707 uint32_t gpio_mask_val; // GPIO Mask value
1708 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
1709};
1710
1711struct atom_svid2_voltage_object_v4
1712{
1713 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2
1714 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
1715 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
1716 uint8_t psi0_enable; //
1717 uint8_t maxvstep;
1718 uint8_t telemetry_offset;
1719 uint8_t telemetry_gain;
1720 uint16_t reserved1;
1721};
1722
1723struct atom_merged_voltage_object_v4
1724{
1725 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
1726 uint8_t merged_powerrail_type; //enum atom_voltage_type
1727 uint8_t reserved[3];
1728};
1729
1730union atom_voltage_object_v4{
1731 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
1732 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
1733 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
1734 struct atom_merged_voltage_object_v4 merged_voltage_obj;
1735};
1736
1737struct atom_voltage_objects_info_v4_1
1738{
1739 struct atom_common_table_header table_header;
1740 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control
1741};
1742
1743
1744/*
1745 ***************************************************************************
1746 All Command Function structure definition
1747 ***************************************************************************
1748*/
1749
1750/*
1751 ***************************************************************************
1752 Structures used by asic_init
1753 ***************************************************************************
1754*/
1755
1756struct asic_init_engine_parameters
1757{
1758 uint32_t sclkfreqin10khz:24;
1759 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
1760};
1761
1762struct asic_init_mem_parameters
1763{
1764 uint32_t mclkfreqin10khz:24;
1765 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
1766};
1767
1768struct asic_init_parameters_v2_1
1769{
1770 struct asic_init_engine_parameters engineparam;
1771 struct asic_init_mem_parameters memparam;
1772};
1773
1774struct asic_init_ps_allocation_v2_1
1775{
1776 struct asic_init_parameters_v2_1 param;
1777 uint32_t reserved[16];
1778};
1779
1780
1781enum atom_asic_init_engine_flag
1782{
1783 b3NORMAL_ENGINE_INIT = 0,
1784 b3SRIOV_SKIP_ASIC_INIT = 0x02,
1785 b3SRIOV_LOAD_UCODE = 0x40,
1786};
1787
1788enum atom_asic_init_mem_flag
1789{
1790 b3NORMAL_MEM_INIT = 0,
1791 b3DRAM_SELF_REFRESH_EXIT =0x20,
1792};
1793
1794/*
1795 ***************************************************************************
1796 Structures used by setengineclock
1797 ***************************************************************************
1798*/
1799
1800struct set_engine_clock_parameters_v2_1
1801{
1802 uint32_t sclkfreqin10khz:24;
1803 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
1804 uint32_t reserved[10];
1805};
1806
1807struct set_engine_clock_ps_allocation_v2_1
1808{
1809 struct set_engine_clock_parameters_v2_1 clockinfo;
1810 uint32_t reserved[10];
1811};
1812
1813
1814enum atom_set_engine_mem_clock_flag
1815{
1816 b3NORMAL_CHANGE_CLOCK = 0,
1817 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
1818 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
1819};
1820
1821/*
1822 ***************************************************************************
1823 Structures used by getengineclock
1824 ***************************************************************************
1825*/
1826struct get_engine_clock_parameter
1827{
1828 uint32_t sclk_10khz; // current engine speed in 10KHz unit
1829 uint32_t reserved;
1830};
1831
1832/*
1833 ***************************************************************************
1834 Structures used by setmemoryclock
1835 ***************************************************************************
1836*/
1837struct set_memory_clock_parameters_v2_1
1838{
1839 uint32_t mclkfreqin10khz:24;
1840 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
1841 uint32_t reserved[10];
1842};
1843
1844struct set_memory_clock_ps_allocation_v2_1
1845{
1846 struct set_memory_clock_parameters_v2_1 clockinfo;
1847 uint32_t reserved[10];
1848};
1849
1850
1851/*
1852 ***************************************************************************
1853 Structures used by getmemoryclock
1854 ***************************************************************************
1855*/
1856struct get_memory_clock_parameter
1857{
1858 uint32_t mclk_10khz; // current engine speed in 10KHz unit
1859 uint32_t reserved;
1860};
1861
1862
1863
1864/*
1865 ***************************************************************************
1866 Structures used by setvoltage
1867 ***************************************************************************
1868*/
1869
1870struct set_voltage_parameters_v1_4
1871{
1872 uint8_t voltagetype; /* enum atom_voltage_type */
1873 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
1874 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
1875};
1876
1877//set_voltage_parameters_v2_1.voltagemode
1878enum atom_set_voltage_command{
1879 ATOM_SET_VOLTAGE = 0,
1880 ATOM_INIT_VOLTAGE_REGULATOR = 3,
1881 ATOM_SET_VOLTAGE_PHASE = 4,
1882 ATOM_GET_LEAKAGE_ID = 8,
1883};
1884
1885struct set_voltage_ps_allocation_v1_4
1886{
1887 struct set_voltage_parameters_v1_4 setvoltageparam;
1888 uint32_t reserved[10];
1889};
1890
1891
1892/*
1893 ***************************************************************************
1894 Structures used by computegpuclockparam
1895 ***************************************************************************
1896*/
1897
1898//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
1899enum atom_gpu_clock_type
1900{
1901 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
1902 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
1903 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
1904};
1905
1906struct compute_gpu_clock_input_parameter_v1_8
1907{
1908 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
1909 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
1910 uint32_t reserved[5];
1911};
1912
1913
1914struct compute_gpu_clock_output_parameter_v1_8
1915{
1916 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
1917 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
1918 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
1919 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
1920 uint16_t pll_ss_slew_frac;
1921 uint8_t pll_ss_enable;
1922 uint8_t reserved;
1923 uint32_t reserved1[2];
1924};
1925
1926
1927
1928/*
1929 ***************************************************************************
1930 Structures used by ReadEfuseValue
1931 ***************************************************************************
1932*/
1933
1934struct read_efuse_input_parameters_v3_1
1935{
1936 uint16_t efuse_start_index;
1937 uint8_t reserved;
1938 uint8_t bitslen;
1939};
1940
1941// ReadEfuseValue input/output parameter
1942union read_efuse_value_parameters_v3_1
1943{
1944 struct read_efuse_input_parameters_v3_1 efuse_info;
1945 uint32_t efusevalue;
1946};
1947
1948
1949/*
1950 ***************************************************************************
1951 Structures used by getsmuclockinfo
1952 ***************************************************************************
1953*/
1954struct atom_get_smu_clock_info_parameters_v3_1
1955{
1956 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
1957 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1958 uint8_t command; // enum of atom_get_smu_clock_info_command
1959 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1960};
1961
1962enum atom_get_smu_clock_info_command
1963{
1964 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
1965 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
1966 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
1967};
1968
1969enum atom_smu9_syspll0_clock_id
1970{
1971 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
1972 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK)
1973 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
1974 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
1975 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK
1976 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK
1977 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK
1978 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK
1979 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
1980 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
1981 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
1982};
1983
1984enum atom_smu11_syspll_id {
1985 SMU11_SYSPLL0_ID = 0,
1986 SMU11_SYSPLL1_0_ID = 1,
1987 SMU11_SYSPLL1_1_ID = 2,
1988 SMU11_SYSPLL1_2_ID = 3,
1989 SMU11_SYSPLL2_ID = 4,
1990 SMU11_SYSPLL3_0_ID = 5,
1991 SMU11_SYSPLL3_1_ID = 6,
1992};
1993
1994
1995enum atom_smu11_syspll0_clock_id {
1996 SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK
1997 SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK
1998 SMU11_SYSPLL0_DCLK_ID = 2, // DCLK
1999 SMU11_SYSPLL0_VCLK_ID = 3, // VCLK
2000 SMU11_SYSPLL0_ECLK_ID = 4, // ECLK
2001 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK
2002};
2003
2004
2005enum atom_smu11_syspll1_0_clock_id {
2006 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a
2007};
2008
2009enum atom_smu11_syspll1_1_clock_id {
2010 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b
2011};
2012
2013enum atom_smu11_syspll1_2_clock_id {
2014 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK
2015};
2016
2017enum atom_smu11_syspll2_clock_id {
2018 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK
2019};
2020
2021enum atom_smu11_syspll3_0_clock_id {
2022 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK
2023 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK
2024 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK
2025};
2026
2027enum atom_smu11_syspll3_1_clock_id {
2028 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK
2029 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK
2030 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK
2031};
2032
2033struct atom_get_smu_clock_info_output_parameters_v3_1
2034{
2035 union {
2036 uint32_t smu_clock_freq_hz;
2037 uint32_t syspllvcofreq_10khz;
2038 uint32_t sysspllrefclk_10khz;
2039 }atom_smu_outputclkfreq;
2040};
2041
2042
2043
2044/*
2045 ***************************************************************************
2046 Structures used by dynamicmemorysettings
2047 ***************************************************************************
2048*/
2049
2050enum atom_dynamic_memory_setting_command
2051{
2052 COMPUTE_MEMORY_PLL_PARAM = 1,
2053 COMPUTE_ENGINE_PLL_PARAM = 2,
2054 ADJUST_MC_SETTING_PARAM = 3,
2055};
2056
2057/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
2058struct dynamic_mclk_settings_parameters_v2_1
2059{
2060 uint32_t mclk_10khz:24; //Input= target mclk
2061 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2062 uint32_t reserved;
2063};
2064
2065/* when command = COMPUTE_ENGINE_PLL_PARAM */
2066struct dynamic_sclk_settings_parameters_v2_1
2067{
2068 uint32_t sclk_10khz:24; //Input= target mclk
2069 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
2070 uint32_t mclk_10khz;
2071 uint32_t reserved;
2072};
2073
2074union dynamic_memory_settings_parameters_v2_1
2075{
2076 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
2077 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
2078};
2079
2080
2081
2082/*
2083 ***************************************************************************
2084 Structures used by memorytraining
2085 ***************************************************************************
2086*/
2087
2088enum atom_umc6_0_ucode_function_call_enum_id
2089{
2090 UMC60_UCODE_FUNC_ID_REINIT = 0,
2091 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
2092 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
2093};
2094
2095
2096struct memory_training_parameters_v2_1
2097{
2098 uint8_t ucode_func_id;
2099 uint8_t ucode_reserved[3];
2100 uint32_t reserved[5];
2101};
2102
2103
2104/*
2105 ***************************************************************************
2106 Structures used by setpixelclock
2107 ***************************************************************************
2108*/
2109
2110struct set_pixel_clock_parameter_v1_7
2111{
2112 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
2113
2114 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2115 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
2116 // indicate which graphic encoder will be used.
2117 uint8_t encoder_mode; // Encoder mode:
2118 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
2119 uint8_t crtc_id; // enum of atom_crtc_def
2120 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2121 uint8_t reserved1[2];
2122 uint32_t reserved2;
2123};
2124
2125//ucMiscInfo
2126enum atom_set_pixel_clock_v1_7_misc_info
2127{
2128 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
2129 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
2130 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
2131 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
2132 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
2133 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
2134 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
2135 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
2136 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
2137 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
2138 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
2139};
2140
2141/* deep_color_ratio */
2142enum atom_set_pixel_clock_v1_7_deepcolor_ratio
2143{
2144 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2145 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2146 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2147 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2148};
2149
2150/*
2151 ***************************************************************************
2152 Structures used by setdceclock
2153 ***************************************************************************
2154*/
2155
2156// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
2157struct set_dce_clock_parameters_v2_1
2158{
2159 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
2160 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2161 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
2162 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
2163 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
2164};
2165
2166//ucDCEClkType
2167enum atom_set_dce_clock_clock_type
2168{
2169 DCE_CLOCK_TYPE_DISPCLK = 0,
2170 DCE_CLOCK_TYPE_DPREFCLK = 1,
2171 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock
2172};
2173
2174//ucDCEClkFlag when ucDCEClkType == DPREFCLK
2175enum atom_set_dce_clock_dprefclk_flag
2176{
2177 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
2178 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
2179 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
2180 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
2181 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
2182};
2183
2184//ucDCEClkFlag when ucDCEClkType == PIXCLK
2185enum atom_set_dce_clock_pixclk_flag
2186{
2187 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
2188 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2189 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2190 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2191 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2192 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
2193};
2194
2195struct set_dce_clock_ps_allocation_v2_1
2196{
2197 struct set_dce_clock_parameters_v2_1 param;
2198 uint32_t ulReserved[2];
2199};
2200
2201
2202/****************************************************************************/
2203// Structures used by BlankCRTC
2204/****************************************************************************/
2205struct blank_crtc_parameters
2206{
2207 uint8_t crtc_id; // enum atom_crtc_def
2208 uint8_t blanking; // enum atom_blank_crtc_command
2209 uint16_t reserved;
2210 uint32_t reserved1;
2211};
2212
2213enum atom_blank_crtc_command
2214{
2215 ATOM_BLANKING = 1,
2216 ATOM_BLANKING_OFF = 0,
2217};
2218
2219/****************************************************************************/
2220// Structures used by enablecrtc
2221/****************************************************************************/
2222struct enable_crtc_parameters
2223{
2224 uint8_t crtc_id; // enum atom_crtc_def
2225 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2226 uint8_t padding[2];
2227};
2228
2229
2230/****************************************************************************/
2231// Structure used by EnableDispPowerGating
2232/****************************************************************************/
2233struct enable_disp_power_gating_parameters_v2_1
2234{
2235 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
2236 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2237 uint8_t padding[2];
2238};
2239
2240struct enable_disp_power_gating_ps_allocation
2241{
2242 struct enable_disp_power_gating_parameters_v2_1 param;
2243 uint32_t ulReserved[4];
2244};
2245
2246/****************************************************************************/
2247// Structure used in setcrtc_usingdtdtiming
2248/****************************************************************************/
2249struct set_crtc_using_dtd_timing_parameters
2250{
2251 uint16_t h_size;
2252 uint16_t h_blanking_time;
2253 uint16_t v_size;
2254 uint16_t v_blanking_time;
2255 uint16_t h_syncoffset;
2256 uint16_t h_syncwidth;
2257 uint16_t v_syncoffset;
2258 uint16_t v_syncwidth;
2259 uint16_t modemiscinfo;
2260 uint8_t h_border;
2261 uint8_t v_border;
2262 uint8_t crtc_id; // enum atom_crtc_def
2263 uint8_t encoder_mode; // atom_encode_mode_def
2264 uint8_t padding[2];
2265};
2266
2267
2268/****************************************************************************/
2269// Structures used by processi2cchanneltransaction
2270/****************************************************************************/
2271struct process_i2c_channel_transaction_parameters
2272{
2273 uint8_t i2cspeed_khz;
2274 union {
2275 uint8_t regindex;
2276 uint8_t status; /* enum atom_process_i2c_flag */
2277 } regind_status;
2278 uint16_t i2c_data_out;
2279 uint8_t flag; /* enum atom_process_i2c_status */
2280 uint8_t trans_bytes;
2281 uint8_t slave_addr;
2282 uint8_t i2c_id;
2283};
2284
2285//ucFlag
2286enum atom_process_i2c_flag
2287{
2288 HW_I2C_WRITE = 1,
2289 HW_I2C_READ = 0,
2290 I2C_2BYTE_ADDR = 0x02,
2291 HW_I2C_SMBUS_BYTE_WR = 0x04,
2292};
2293
2294//status
2295enum atom_process_i2c_status
2296{
2297 HW_ASSISTED_I2C_STATUS_FAILURE =2,
2298 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
2299};
2300
2301
2302/****************************************************************************/
2303// Structures used by processauxchanneltransaction
2304/****************************************************************************/
2305
2306struct process_aux_channel_transaction_parameters_v1_2
2307{
2308 uint16_t aux_request;
2309 uint16_t dataout;
2310 uint8_t channelid;
2311 union {
2312 uint8_t reply_status;
2313 uint8_t aux_delay;
2314 } aux_status_delay;
2315 uint8_t dataout_len;
2316 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
2317};
2318
2319
2320/****************************************************************************/
2321// Structures used by selectcrtc_source
2322/****************************************************************************/
2323
2324struct select_crtc_source_parameters_v2_3
2325{
2326 uint8_t crtc_id; // enum atom_crtc_def
2327 uint8_t encoder_id; // enum atom_dig_def
2328 uint8_t encode_mode; // enum atom_encode_mode_def
2329 uint8_t dst_bpc; // enum atom_panel_bit_per_color
2330};
2331
2332
2333/****************************************************************************/
2334// Structures used by digxencodercontrol
2335/****************************************************************************/
2336
2337// ucAction:
2338enum atom_dig_encoder_control_action
2339{
2340 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
2341 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
2342 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
2343 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
2344 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
2345 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
2346 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
2347 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
2348 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
2349 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
2350 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
2351 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
2352 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
2353 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
2354};
2355
2356//define ucPanelMode
2357enum atom_dig_encoder_control_panelmode
2358{
2359 DP_PANEL_MODE_DISABLE = 0x00,
2360 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
2361 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
2362};
2363
2364//ucDigId
2365enum atom_dig_encoder_control_v5_digid
2366{
2367 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
2368 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
2369 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
2370 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
2371 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
2372 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
2373 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
2374 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
2375};
2376
2377struct dig_encoder_stream_setup_parameters_v1_5
2378{
2379 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2380 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
2381 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2382 uint8_t lanenum; // Lane number
2383 uint32_t pclk_10khz; // Pixel Clock in 10Khz
2384 uint8_t bitpercolor;
2385 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
2386 uint8_t reserved[2];
2387};
2388
2389struct dig_encoder_link_setup_parameters_v1_5
2390{
2391 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2392 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
2393 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2394 uint8_t lanenum; // Lane number
2395 uint8_t symclk_10khz; // Symbol Clock in 10Khz
2396 uint8_t hpd_sel;
2397 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2398 uint8_t reserved[2];
2399};
2400
2401struct dp_panel_mode_set_parameters_v1_5
2402{
2403 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2404 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
2405 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
2406 uint8_t reserved1;
2407 uint32_t reserved2[2];
2408};
2409
2410struct dig_encoder_generic_cmd_parameters_v1_5
2411{
2412 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2413 uint8_t action; // = rest of generic encoder command which does not carry any parameters
2414 uint8_t reserved1[2];
2415 uint32_t reserved2[2];
2416};
2417
2418union dig_encoder_control_parameters_v1_5
2419{
2420 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
2421 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
2422 struct dig_encoder_link_setup_parameters_v1_5 link_param;
2423 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
2424};
2425
2426/*
2427 ***************************************************************************
2428 Structures used by dig1transmittercontrol
2429 ***************************************************************************
2430*/
2431struct dig_transmitter_control_parameters_v1_6
2432{
2433 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
2434 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
2435 union {
2436 uint8_t digmode; // enum atom_encode_mode_def
2437 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
2438 } mode_laneset;
2439 uint8_t lanenum; // Lane number 1, 2, 4, 8
2440 uint32_t symclk_10khz; // Symbol Clock in 10Khz
2441 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
2442 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2443 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
2444 uint8_t reserved;
2445 uint32_t reserved1;
2446};
2447
2448struct dig_transmitter_control_ps_allocation_v1_6
2449{
2450 struct dig_transmitter_control_parameters_v1_6 param;
2451 uint32_t reserved[4];
2452};
2453
2454//ucAction
2455enum atom_dig_transmitter_control_action
2456{
2457 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
2458 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
2459 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
2460 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
2461 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
2462 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
2463 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
2464 ATOM_TRANSMITTER_ACTION_INIT = 7,
2465 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
2466 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
2467 ATOM_TRANSMITTER_ACTION_SETUP = 10,
2468 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
2469 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
2470 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
2471};
2472
2473// digfe_sel
2474enum atom_dig_transmitter_control_digfe_sel
2475{
2476 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
2477 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
2478 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
2479 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
2480 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
2481 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
2482 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
2483};
2484
2485
2486//ucHPDSel
2487enum atom_dig_transmitter_control_hpd_sel
2488{
2489 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
2490 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
2491 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
2492 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
2493 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
2494 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
2495 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
2496};
2497
2498// ucDPLaneSet
2499enum atom_dig_transmitter_control_dplaneset
2500{
2501 DP_LANE_SET__0DB_0_4V = 0x00,
2502 DP_LANE_SET__0DB_0_6V = 0x01,
2503 DP_LANE_SET__0DB_0_8V = 0x02,
2504 DP_LANE_SET__0DB_1_2V = 0x03,
2505 DP_LANE_SET__3_5DB_0_4V = 0x08,
2506 DP_LANE_SET__3_5DB_0_6V = 0x09,
2507 DP_LANE_SET__3_5DB_0_8V = 0x0a,
2508 DP_LANE_SET__6DB_0_4V = 0x10,
2509 DP_LANE_SET__6DB_0_6V = 0x11,
2510 DP_LANE_SET__9_5DB_0_4V = 0x18,
2511};
2512
2513
2514
2515/****************************************************************************/
2516// Structures used by ExternalEncoderControl V2.4
2517/****************************************************************************/
2518
2519struct external_encoder_control_parameters_v2_4
2520{
2521 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
2522 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
2523 uint8_t action; //
2524 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
2525 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
2526 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
2527 uint8_t hpd_id;
2528};
2529
2530
2531// ucAction
2532enum external_encoder_control_action_def
2533{
2534 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
2535 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
2536 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
2537 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
2538 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
2539 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
2540 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
2541 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
2542};
2543
2544// ucConfig
2545enum external_encoder_control_v2_4_config_def
2546{
2547 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
2548 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
2549 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
2550 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
2551 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
2552 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
2553 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
2554 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
2555 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
2556};
2557
2558struct external_encoder_control_ps_allocation_v2_4
2559{
2560 struct external_encoder_control_parameters_v2_4 sExtEncoder;
2561 uint32_t reserved[2];
2562};
2563
2564
2565/*
2566 ***************************************************************************
2567 AMD ACPI Table
2568
2569 ***************************************************************************
2570*/
2571
2572struct amd_acpi_description_header{
2573 uint32_t signature;
2574 uint32_t tableLength; //Length
2575 uint8_t revision;
2576 uint8_t checksum;
2577 uint8_t oemId[6];
2578 uint8_t oemTableId[8]; //UINT64 OemTableId;
2579 uint32_t oemRevision;
2580 uint32_t creatorId;
2581 uint32_t creatorRevision;
2582};
2583
2584struct uefi_acpi_vfct{
2585 struct amd_acpi_description_header sheader;
2586 uint8_t tableUUID[16]; //0x24
2587 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
2588 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
2589 uint32_t reserved[4]; //0x3C
2590};
2591
2592struct vfct_image_header{
2593 uint32_t pcibus; //0x4C
2594 uint32_t pcidevice; //0x50
2595 uint32_t pcifunction; //0x54
2596 uint16_t vendorid; //0x58
2597 uint16_t deviceid; //0x5A
2598 uint16_t ssvid; //0x5C
2599 uint16_t ssid; //0x5E
2600 uint32_t revision; //0x60
2601 uint32_t imagelength; //0x64
2602};
2603
2604
2605struct gop_vbios_content {
2606 struct vfct_image_header vbiosheader;
2607 uint8_t vbioscontent[1];
2608};
2609
2610struct gop_lib1_content {
2611 struct vfct_image_header lib1header;
2612 uint8_t lib1content[1];
2613};
2614
2615
2616
2617/*
2618 ***************************************************************************
2619 Scratch Register definitions
2620 Each number below indicates which scratch regiser request, Active and
2621 Connect all share the same definitions as display_device_tag defines
2622 ***************************************************************************
2623*/
2624
2625enum scratch_register_def{
2626 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
2627 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
2628 ATOM_ACTIVE_INFO_DEF = 3,
2629 ATOM_LCD_INFO_DEF = 4,
2630 ATOM_DEVICE_REQ_INFO_DEF = 5,
2631 ATOM_ACC_CHANGE_INFO_DEF = 6,
2632 ATOM_PRE_OS_MODE_INFO_DEF = 7,
2633 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
2634 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
2635};
2636
2637enum scratch_device_connect_info_bit_def{
2638 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
2639 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
2640 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
2641 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
2642 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
2643 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
2644 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
2645 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
2646 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
2647};
2648
2649enum scratch_bl_bri_level_info_bit_def{
2650 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
2651#ifndef _H2INC
2652 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
2653 ATOM_DEVICE_DPMS_STATE =0x00010000,
2654#endif
2655};
2656
2657enum scratch_active_info_bits_def{
2658 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
2659 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
2660 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
2661 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
2662 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
2663 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
2664 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
2665 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
2666};
2667
2668enum scratch_device_req_info_bits_def{
2669 ATOM_DISPLAY_LCD1_REQ =0x0002,
2670 ATOM_DISPLAY_DFP1_REQ =0x0008,
2671 ATOM_DISPLAY_DFP2_REQ =0x0080,
2672 ATOM_DISPLAY_DFP3_REQ =0x0200,
2673 ATOM_DISPLAY_DFP4_REQ =0x0400,
2674 ATOM_DISPLAY_DFP5_REQ =0x0800,
2675 ATOM_DISPLAY_DFP6_REQ =0x0040,
2676 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
2677};
2678
2679enum scratch_acc_change_info_bitshift_def{
2680 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
2681 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
2682};
2683
2684enum scratch_acc_change_info_bits_def{
2685 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
2686 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
2687};
2688
2689enum scratch_pre_os_mode_info_bits_def{
2690 ATOM_PRE_OS_MODE_MASK =0x00000003,
2691 ATOM_PRE_OS_MODE_VGA =0x00000000,
2692 ATOM_PRE_OS_MODE_VESA =0x00000001,
2693 ATOM_PRE_OS_MODE_GOP =0x00000002,
2694 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
2695 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
2696 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
2697 ATOM_ASIC_INIT_COMPLETE =0x00000200,
2698#ifndef _H2INC
2699 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
2700#endif
2701};
2702
2703
2704
2705/*
2706 ***************************************************************************
2707 ATOM firmware ID header file
2708 !! Please keep it at end of the atomfirmware.h !!
2709 ***************************************************************************
2710*/
2711#include "atomfirmwareid.h"
2712#pragma pack()
2713
2714#endif
2715