Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23
24/****************************************************************************/
25/*Portion I: Definitions shared between VBIOS and Driver */
26/****************************************************************************/
27
28#ifndef _ATOMBIOS_H
29#define _ATOMBIOS_H
30
31#define ATOM_VERSION_MAJOR 0x00020000
32#define ATOM_VERSION_MINOR 0x00000002
33
34#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
35
36/* Endianness should be specified before inclusion,
37 * default to little endian
38 */
39#ifndef ATOM_BIG_ENDIAN
40#error Endian not specified
41#endif
42
43#ifdef _H2INC
44 #ifndef ULONG
45 typedef unsigned long ULONG;
46 #endif
47
48 #ifndef UCHAR
49 typedef unsigned char UCHAR;
50 #endif
51
52 #ifndef USHORT
53 typedef unsigned short USHORT;
54 #endif
55#endif
56
57#define ATOM_DAC_A 0
58#define ATOM_DAC_B 1
59#define ATOM_EXT_DAC 2
60
61#define ATOM_CRTC1 0
62#define ATOM_CRTC2 1
63#define ATOM_CRTC3 2
64#define ATOM_CRTC4 3
65#define ATOM_CRTC5 4
66#define ATOM_CRTC6 5
67
68#define ATOM_UNDERLAY_PIPE0 16
69#define ATOM_UNDERLAY_PIPE1 17
70
71#define ATOM_CRTC_INVALID 0xFF
72
73#define ATOM_DIGA 0
74#define ATOM_DIGB 1
75
76#define ATOM_PPLL1 0
77#define ATOM_PPLL2 1
78#define ATOM_DCPLL 2
79#define ATOM_PPLL0 2
80#define ATOM_PPLL3 3
81
82#define ATOM_PHY_PLL0 4
83#define ATOM_PHY_PLL1 5
84
85#define ATOM_EXT_PLL1 8
86#define ATOM_GCK_DFS 8
87#define ATOM_EXT_PLL2 9
88#define ATOM_FCH_CLK 9
89#define ATOM_EXT_CLOCK 10
90#define ATOM_DP_DTO 11
91
92#define ATOM_COMBOPHY_PLL0 20
93#define ATOM_COMBOPHY_PLL1 21
94#define ATOM_COMBOPHY_PLL2 22
95#define ATOM_COMBOPHY_PLL3 23
96#define ATOM_COMBOPHY_PLL4 24
97#define ATOM_COMBOPHY_PLL5 25
98
99#define ATOM_PPLL_INVALID 0xFF
100
101#define ENCODER_REFCLK_SRC_P1PLL 0
102#define ENCODER_REFCLK_SRC_P2PLL 1
103#define ENCODER_REFCLK_SRC_DCPLL 2
104#define ENCODER_REFCLK_SRC_EXTCLK 3
105#define ENCODER_REFCLK_SRC_INVALID 0xFF
106
107#define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108#define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
109#define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode
110#define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios
111
112#define ATOM_DISABLE 0
113#define ATOM_ENABLE 1
114#define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
115#define ATOM_LCD_BLON (ATOM_ENABLE+2)
116#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
117#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
118#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
119#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
120#define ATOM_INIT (ATOM_DISABLE+7)
121#define ATOM_GET_STATUS (ATOM_DISABLE+8)
122
123#define ATOM_BLANKING 1
124#define ATOM_BLANKING_OFF 0
125
126
127#define ATOM_CRT1 0
128#define ATOM_CRT2 1
129
130#define ATOM_TV_NTSC 1
131#define ATOM_TV_NTSCJ 2
132#define ATOM_TV_PAL 3
133#define ATOM_TV_PALM 4
134#define ATOM_TV_PALCN 5
135#define ATOM_TV_PALN 6
136#define ATOM_TV_PAL60 7
137#define ATOM_TV_SECAM 8
138#define ATOM_TV_CV 16
139
140#define ATOM_DAC1_PS2 1
141#define ATOM_DAC1_CV 2
142#define ATOM_DAC1_NTSC 3
143#define ATOM_DAC1_PAL 4
144
145#define ATOM_DAC2_PS2 ATOM_DAC1_PS2
146#define ATOM_DAC2_CV ATOM_DAC1_CV
147#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
148#define ATOM_DAC2_PAL ATOM_DAC1_PAL
149
150#define ATOM_PM_ON 0
151#define ATOM_PM_STANDBY 1
152#define ATOM_PM_SUSPEND 2
153#define ATOM_PM_OFF 3
154
155// For ATOM_LVDS_INFO_V12
156// Bit0:{=0:single, =1:dual},
157// Bit1 {=0:666RGB, =1:888RGB},
158// Bit2:3:{Grey level}
159// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
160#define ATOM_PANEL_MISC_DUAL 0x00000001
161#define ATOM_PANEL_MISC_888RGB 0x00000002
162#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
163#define ATOM_PANEL_MISC_FPDI 0x00000010
164#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
165#define ATOM_PANEL_MISC_SPATIAL 0x00000020
166#define ATOM_PANEL_MISC_TEMPORAL 0x00000040
167#define ATOM_PANEL_MISC_API_ENABLED 0x00000080
168
169#define MEMTYPE_DDR1 "DDR1"
170#define MEMTYPE_DDR2 "DDR2"
171#define MEMTYPE_DDR3 "DDR3"
172#define MEMTYPE_DDR4 "DDR4"
173
174#define ASIC_BUS_TYPE_PCI "PCI"
175#define ASIC_BUS_TYPE_AGP "AGP"
176#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
177
178//Maximum size of that FireGL flag string
179#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
180#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
181
182#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
183#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
184
185#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
186#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
187
188#define HW_ASSISTED_I2C_STATUS_FAILURE 2
189#define HW_ASSISTED_I2C_STATUS_SUCCESS 1
190
191#pragma pack(1) // BIOS data must use byte alignment
192
193// Define offset to location of ROM header.
194#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
195#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
196
197#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
198#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0!
199#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
200#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
201
202/****************************************************************************/
203// Common header for all tables (Data table, Command table).
204// Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
205// And the pointer actually points to this header.
206/****************************************************************************/
207
208typedef struct _ATOM_COMMON_TABLE_HEADER
209{
210 USHORT usStructureSize;
211 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible
212 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware
213 //Image can't be updated, while Driver needs to carry the new table!
214}ATOM_COMMON_TABLE_HEADER;
215
216/****************************************************************************/
217// Structure stores the ROM header.
218/****************************************************************************/
219typedef struct _ATOM_ROM_HEADER
220{
221 ATOM_COMMON_TABLE_HEADER sHeader;
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
223 //atombios should init it as "ATOM", don't change the position
224 USHORT usBiosRuntimeSegmentAddress;
225 USHORT usProtectedModeInfoOffset;
226 USHORT usConfigFilenameOffset;
227 USHORT usCRC_BlockOffset;
228 USHORT usBIOS_BootupMessageOffset;
229 USHORT usInt10Offset;
230 USHORT usPciBusDevInitCode;
231 USHORT usIoBaseAddress;
232 USHORT usSubsystemVendorID;
233 USHORT usSubsystemID;
234 USHORT usPCI_InfoOffset;
235 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
236 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
237 UCHAR ucExtendedFunctionCode;
238 UCHAR ucReserved;
239}ATOM_ROM_HEADER;
240
241
242typedef struct _ATOM_ROM_HEADER_V2_1
243{
244 ATOM_COMMON_TABLE_HEADER sHeader;
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
246 //atombios should init it as "ATOM", don't change the position
247 USHORT usBiosRuntimeSegmentAddress;
248 USHORT usProtectedModeInfoOffset;
249 USHORT usConfigFilenameOffset;
250 USHORT usCRC_BlockOffset;
251 USHORT usBIOS_BootupMessageOffset;
252 USHORT usInt10Offset;
253 USHORT usPciBusDevInitCode;
254 USHORT usIoBaseAddress;
255 USHORT usSubsystemVendorID;
256 USHORT usSubsystemID;
257 USHORT usPCI_InfoOffset;
258 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
259 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
260 UCHAR ucExtendedFunctionCode;
261 UCHAR ucReserved;
262 ULONG ulPSPDirTableOffset;
263}ATOM_ROM_HEADER_V2_1;
264
265
266//==============================Command Table Portion====================================
267
268
269/****************************************************************************/
270// Structures used in Command.mtb
271/****************************************************************************/
272typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
273 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
274 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
275 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
276 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
277 USHORT DIGxEncoderControl; //Only used by Bios
278 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
279 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
280 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
281 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
282 USHORT GPIOPinControl; //Atomic Table, only used by Bios
283 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
284 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
285 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
286 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
287 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
288 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
289 USHORT MemoryPLLInit; //Atomic Table, used only by Bios
290 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
291 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
292 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
293 USHORT SetUniphyInstance; //Atomic Table, only used by Bios
294 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
295 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
296 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
297 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
298 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
299 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
300 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
301 USHORT GetConditionalGoldenSetting; //Only used by Bios
302 USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1
303 USHORT PatchMCSetting; //only used by BIOS
304 USHORT MC_SEQ_Control; //only used by BIOS
305 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
306 USHORT EnableScaler; //Atomic Table, used only by Bios
307 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
308 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
309 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
310 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
311 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
312 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
313 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
314 USHORT GetSMUClockInfo; //Atomic Table, used only by Bios
315 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
316 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
317 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
318 USHORT LUT_AutoFill; //Atomic Table, only used by Bios
319 USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK
320 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
321 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
322 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
323 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
324 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
325 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
326 USHORT MemoryCleanUp; //Atomic Table, only used by Bios
327 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
328 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
329 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
330 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
331 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
332 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
333 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
334 USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
335 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
336 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
337 USHORT MemoryTraining; //Atomic Table, used only by Bios
338 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
339 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
340 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
341 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
342 USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1
343 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
344 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
345 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
346 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
347 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
348 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
349 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
350 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
351 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
352 USHORT DPEncoderService; //Function Table,only used by Bios
353 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
354}ATOM_MASTER_LIST_OF_COMMAND_TABLES;
355
356// For backward compatible
357#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
358#define DPTranslatorControl DIG2EncoderControl
359#define UNIPHYTransmitterControl DIG1TransmitterControl
360#define LVTMATransmitterControl DIG2TransmitterControl
361#define SetCRTC_DPM_State GetConditionalGoldenSetting
362#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance
363#define HPDInterruptService ReadHWAssistedI2CStatus
364#define EnableVGA_Access GetSCLKOverMCLKRatio
365#define EnableYUV GetDispObjectInfo
366#define DynamicClockGating EnableDispPowerGating
367#define SetupHWAssistedI2CStatus ComputeMemoryClockParam
368#define DAC2OutputControl ReadEfuseValue
369
370#define TMDSAEncoderControl PatchMCSetting
371#define LVDSEncoderControl MC_SEQ_Control
372#define LCD1OutputControl HW_Misc_Operation
373#define TV1OutputControl Gfx_Harvesting
374#define TVEncoderControl SMC_Init
375#define EnableHW_IconCursor SetDCEClock
376#define SetCRTC_Replication GetSMUClockInfo
377
378#define MemoryRefreshConversion Gfx_Init
379
380typedef struct _ATOM_MASTER_COMMAND_TABLE
381{
382 ATOM_COMMON_TABLE_HEADER sHeader;
383 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
384}ATOM_MASTER_COMMAND_TABLE;
385
386/****************************************************************************/
387// Structures used in every command table
388/****************************************************************************/
389typedef struct _ATOM_TABLE_ATTRIBUTE
390{
391#if ATOM_BIG_ENDIAN
392 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
393 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
394 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
395#else
396 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
397 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
398 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
399#endif
400}ATOM_TABLE_ATTRIBUTE;
401
402/****************************************************************************/
403// Common header for all command tables.
404// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
405// And the pointer actually points to this header.
406/****************************************************************************/
407typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
408{
409 ATOM_COMMON_TABLE_HEADER CommonHeader;
410 ATOM_TABLE_ATTRIBUTE TableAttribute;
411}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
412
413/****************************************************************************/
414// Structures used by ComputeMemoryEnginePLLTable
415/****************************************************************************/
416
417#define COMPUTE_MEMORY_PLL_PARAM 1
418#define COMPUTE_ENGINE_PLL_PARAM 2
419#define ADJUST_MC_SETTING_PARAM 3
420
421/****************************************************************************/
422// Structures used by AdjustMemoryControllerTable
423/****************************************************************************/
424typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
425{
426#if ATOM_BIG_ENDIAN
427 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
428 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
429 ULONG ulClockFreq:24;
430#else
431 ULONG ulClockFreq:24;
432 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
433 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
434#endif
435}ATOM_ADJUST_MEMORY_CLOCK_FREQ;
436#define POINTER_RETURN_FLAG 0x80
437
438typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
439{
440 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
441 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
442 UCHAR ucReserved; //may expand to return larger Fbdiv later
443 UCHAR ucFbDiv; //return value
444 UCHAR ucPostDiv; //return value
445}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
446
447typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
448{
449 ULONG ulClock; //When return, [23:0] return real clock
450 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
451 USHORT usFbDiv; //return Feedback value to be written to register
452 UCHAR ucPostDiv; //return post div to be written to register
453}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
454
455#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
456
457#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
458#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
459#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
460#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
461#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
462#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
463#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
464
465#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
466#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
467#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
468#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
469#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
470#define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path
471#define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only
472#define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only
473#define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only
474
475typedef struct _ATOM_COMPUTE_CLOCK_FREQ
476{
477#if ATOM_BIG_ENDIAN
478 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
479 ULONG ulClockFreq:24; // in unit of 10kHz
480#else
481 ULONG ulClockFreq:24; // in unit of 10kHz
482 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
483#endif
484}ATOM_COMPUTE_CLOCK_FREQ;
485
486typedef struct _ATOM_S_MPLL_FB_DIVIDER
487{
488 USHORT usFbDivFrac;
489 USHORT usFbDiv;
490}ATOM_S_MPLL_FB_DIVIDER;
491
492typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
493{
494 union
495 {
496 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
497 ULONG ulClockParams; //ULONG access for BE
498 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
499 };
500 UCHAR ucRefDiv; //Output Parameter
501 UCHAR ucPostDiv; //Output Parameter
502 UCHAR ucCntlFlag; //Output Parameter
503 UCHAR ucReserved;
504}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
505
506// ucCntlFlag
507#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
508#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
509#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
510#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
511
512
513// V4 are only used for APU which PLL outside GPU
514typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
515{
516#if ATOM_BIG_ENDIAN
517 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
518 ULONG ulClock:24; //Input= target clock, output = actual clock
519#else
520 ULONG ulClock:24; //Input= target clock, output = actual clock
521 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
522#endif
523}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
524
525typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
526{
527 union
528 {
529 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
530 ULONG ulClockParams; //ULONG access for BE
531 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
532 };
533 UCHAR ucRefDiv; //Output Parameter
534 UCHAR ucPostDiv; //Output Parameter
535 union
536 {
537 UCHAR ucCntlFlag; //Output Flags
538 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
539 };
540 UCHAR ucReserved;
541}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
542
543
544typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6
545{
546 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
547 ULONG ulReserved[2];
548}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6;
549
550//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
551#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f
552#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00
553#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01
554
555
556typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
557{
558 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
559 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider
560 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
561 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
562 UCHAR ucPllCntlFlag; //Output Flags: control flag
563 UCHAR ucReserved;
564}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6;
565
566//ucPllCntlFlag
567#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
568
569typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7
570{
571 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
572 ULONG ulReserved[5];
573}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7;
574
575//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
576#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f
577#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00
578#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01
579
580typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7
581{
582 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
583 USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536
584 USHORT usSclk_fcw_int; //integer divider of fcwc
585 UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv
586 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
587 UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 )
588 UCHAR ucSscEnable;
589 USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable
590 USHORT usSsc_fcw1_int; //fcw1_int when SSC enable
591 USHORT usReserved;
592 USHORT usPcc_fcw_int;
593 USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable
594 USHORT usPcc_fcw_slew_frac;
595}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7;
596
597// ucInputFlag
598#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
599
600// use for ComputeMemoryClockParamTable
601typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
602{
603 union
604 {
605 ULONG ulClock;
606 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
607 };
608 UCHAR ucDllSpeed; //Output
609 UCHAR ucPostDiv; //Output
610 union{
611 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
612 UCHAR ucPllCntlFlag; //Output:
613 };
614 UCHAR ucBWCntl;
615}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
616
617// definition of ucInputFlag
618#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01
619// definition of ucPllCntlFlag
620#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
621#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04
622#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08
623#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10
624
625//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
626#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04
627
628// use for ComputeMemoryClockParamTable
629typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2
630{
631 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock;
632 ULONG ulReserved;
633}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2;
634
635//Input parameter of DynamicMemorySettingsTable
636//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM
637typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
638{
639 ATOM_COMPUTE_CLOCK_FREQ ulClock;
640 ULONG ulReserved[2];
641}DYNAMICE_MEMORY_SETTINGS_PARAMETER;
642
643//Input parameter of DynamicMemorySettingsTable
644//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM
645typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
646{
647 ATOM_COMPUTE_CLOCK_FREQ ulClock;
648 ULONG ulMemoryClock;
649 ULONG ulReserved;
650}DYNAMICE_ENGINE_SETTINGS_PARAMETER;
651
652//Input parameter of DynamicMemorySettingsTable ver2.1 and above
653//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM
654typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER
655{
656 ATOM_COMPUTE_CLOCK_FREQ ulClock;
657 UCHAR ucMclkDPMState;
658 UCHAR ucReserved[3];
659 ULONG ulReserved;
660}DYNAMICE_MC_DPM_SETTINGS_PARAMETER;
661
662//ucMclkDPMState
663#define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE 0
664#define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1
665#define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2
666
667typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1
668{
669 DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg;
670 DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg;
671 DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg;
672}DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1;
673
674
675/****************************************************************************/
676// Structures used by SetEngineClockTable
677/****************************************************************************/
678typedef struct _SET_ENGINE_CLOCK_PARAMETERS
679{
680 ULONG ulTargetEngineClock; //In 10Khz unit
681}SET_ENGINE_CLOCK_PARAMETERS;
682
683typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
684{
685 ULONG ulTargetEngineClock; //In 10Khz unit
686 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
687}SET_ENGINE_CLOCK_PS_ALLOCATION;
688
689typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2
690{
691 ULONG ulTargetEngineClock; //In 10Khz unit
692 COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved;
693}SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2;
694
695
696/****************************************************************************/
697// Structures used by SetMemoryClockTable
698/****************************************************************************/
699typedef struct _SET_MEMORY_CLOCK_PARAMETERS
700{
701 ULONG ulTargetMemoryClock; //In 10Khz unit
702}SET_MEMORY_CLOCK_PARAMETERS;
703
704typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
705{
706 ULONG ulTargetMemoryClock; //In 10Khz unit
707 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
708}SET_MEMORY_CLOCK_PS_ALLOCATION;
709
710/****************************************************************************/
711// Structures used by ASIC_Init.ctb
712/****************************************************************************/
713typedef struct _ASIC_INIT_PARAMETERS
714{
715 ULONG ulDefaultEngineClock; //In 10Khz unit
716 ULONG ulDefaultMemoryClock; //In 10Khz unit
717}ASIC_INIT_PARAMETERS;
718
719typedef struct _ASIC_INIT_PS_ALLOCATION
720{
721 ASIC_INIT_PARAMETERS sASICInitClocks;
722 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
723}ASIC_INIT_PS_ALLOCATION;
724
725typedef struct _ASIC_INIT_CLOCK_PARAMETERS
726{
727 ULONG ulClkFreqIn10Khz:24;
728 ULONG ucClkFlag:8;
729}ASIC_INIT_CLOCK_PARAMETERS;
730
731typedef struct _ASIC_INIT_PARAMETERS_V1_2
732{
733 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit
734 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit
735}ASIC_INIT_PARAMETERS_V1_2;
736
737typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2
738{
739 ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks;
740 ULONG ulReserved[8];
741}ASIC_INIT_PS_ALLOCATION_V1_2;
742
743/****************************************************************************/
744// Structure used by DynamicClockGatingTable.ctb
745/****************************************************************************/
746typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
747{
748 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
749 UCHAR ucPadding[3];
750}DYNAMIC_CLOCK_GATING_PARAMETERS;
751#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
752
753/****************************************************************************/
754// Structure used by EnableDispPowerGatingTable.ctb
755/****************************************************************************/
756typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
757{
758 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
759 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
760 UCHAR ucPadding[2];
761}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
762
763typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION
764{
765 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
766 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT
767 UCHAR ucPadding[2];
768 ULONG ulReserved[4];
769}ENABLE_DISP_POWER_GATING_PS_ALLOCATION;
770
771/****************************************************************************/
772// Structure used by EnableASIC_StaticPwrMgtTable.ctb
773/****************************************************************************/
774typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
775{
776 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
777 UCHAR ucPadding[3];
778}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
779#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
780
781/****************************************************************************/
782// Structures used by DAC_LoadDetectionTable.ctb
783/****************************************************************************/
784typedef struct _DAC_LOAD_DETECTION_PARAMETERS
785{
786 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
787 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
788 UCHAR ucMisc; //Valid only when table revision =1.3 and above
789}DAC_LOAD_DETECTION_PARAMETERS;
790
791// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
792#define DAC_LOAD_MISC_YPrPb 0x01
793
794typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
795{
796 DAC_LOAD_DETECTION_PARAMETERS sDacload;
797 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
798}DAC_LOAD_DETECTION_PS_ALLOCATION;
799
800/****************************************************************************/
801// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
802/****************************************************************************/
803typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
804{
805 USHORT usPixelClock; // in 10KHz; for bios convenient
806 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
807 UCHAR ucAction; // 0: turn off encoder
808 // 1: setup and turn on encoder
809 // 7: ATOM_ENCODER_INIT Initialize DAC
810}DAC_ENCODER_CONTROL_PARAMETERS;
811
812#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
813
814/****************************************************************************/
815// Structures used by DIG1EncoderControlTable
816// DIG2EncoderControlTable
817// ExternalEncoderControlTable
818/****************************************************************************/
819typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
820{
821 USHORT usPixelClock; // in 10KHz; for bios convenient
822 UCHAR ucConfig;
823 // [2] Link Select:
824 // =0: PHY linkA if bfLane<3
825 // =1: PHY linkB if bfLanes<3
826 // =0: PHY linkA+B if bfLanes=3
827 // [3] Transmitter Sel
828 // =0: UNIPHY or PCIEPHY
829 // =1: LVTMA
830 UCHAR ucAction; // =0: turn off encoder
831 // =1: turn on encoder
832 UCHAR ucEncoderMode;
833 // =0: DP encoder
834 // =1: LVDS encoder
835 // =2: DVI encoder
836 // =3: HDMI encoder
837 // =4: SDVO encoder
838 UCHAR ucLaneNum; // how many lanes to enable
839 UCHAR ucReserved[2];
840}DIG_ENCODER_CONTROL_PARAMETERS;
841#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
842#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
843
844//ucConfig
845#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
846#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
847#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
848#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02
849#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
850#define ATOM_ENCODER_CONFIG_LINKA 0x00
851#define ATOM_ENCODER_CONFIG_LINKB 0x04
852#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
853#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
854#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
855#define ATOM_ENCODER_CONFIG_UNIPHY 0x00
856#define ATOM_ENCODER_CONFIG_LVTMA 0x08
857#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
858#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
859#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
860// ucAction
861// ATOM_ENABLE: Enable Encoder
862// ATOM_DISABLE: Disable Encoder
863
864//ucEncoderMode
865#define ATOM_ENCODER_MODE_DP 0
866#define ATOM_ENCODER_MODE_LVDS 1
867#define ATOM_ENCODER_MODE_DVI 2
868#define ATOM_ENCODER_MODE_HDMI 3
869#define ATOM_ENCODER_MODE_SDVO 4
870#define ATOM_ENCODER_MODE_DP_AUDIO 5
871#define ATOM_ENCODER_MODE_TV 13
872#define ATOM_ENCODER_MODE_CV 14
873#define ATOM_ENCODER_MODE_CRT 15
874#define ATOM_ENCODER_MODE_DVO 16
875#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
876#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
877
878
879typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
880{
881#if ATOM_BIG_ENDIAN
882 UCHAR ucReserved1:2;
883 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
884 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
885 UCHAR ucReserved:1;
886 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
887#else
888 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
889 UCHAR ucReserved:1;
890 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
891 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
892 UCHAR ucReserved1:2;
893#endif
894}ATOM_DIG_ENCODER_CONFIG_V2;
895
896
897typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
898{
899 USHORT usPixelClock; // in 10KHz; for bios convenient
900 ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
901 UCHAR ucAction;
902 UCHAR ucEncoderMode;
903 // =0: DP encoder
904 // =1: LVDS encoder
905 // =2: DVI encoder
906 // =3: HDMI encoder
907 // =4: SDVO encoder
908 UCHAR ucLaneNum; // how many lanes to enable
909 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
910 UCHAR ucReserved;
911}DIG_ENCODER_CONTROL_PARAMETERS_V2;
912
913//ucConfig
914#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
915#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
916#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
917#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
918#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
919#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
920#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
921#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
922#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
923#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
924
925// ucAction:
926// ATOM_DISABLE
927// ATOM_ENABLE
928#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
929#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
930#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
931#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13
932#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
933#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
934#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
935#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
936#define ATOM_ENCODER_CMD_SETUP 0x0f
937#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
938
939// New Command for DIGxEncoderControlTable v1.5
940#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14
941#define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP
942#define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table
943#define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table
944
945// ucStatus
946#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
947#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
948
949//ucTableFormatRevision=1
950//ucTableContentRevision=3
951// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
952typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
953{
954#if ATOM_BIG_ENDIAN
955 UCHAR ucReserved1:1;
956 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
957 UCHAR ucReserved:3;
958 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
959#else
960 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
961 UCHAR ucReserved:3;
962 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
963 UCHAR ucReserved1:1;
964#endif
965}ATOM_DIG_ENCODER_CONFIG_V3;
966
967#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
968#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
969#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
970#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
971#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00
972#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10
973#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20
974#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30
975#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40
976#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50
977
978typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
979{
980 USHORT usPixelClock; // in 10KHz; for bios convenient
981 ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
982 UCHAR ucAction;
983 union{
984 UCHAR ucEncoderMode;
985 // =0: DP encoder
986 // =1: LVDS encoder
987 // =2: DVI encoder
988 // =3: HDMI encoder
989 // =4: SDVO encoder
990 // =5: DP audio
991 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
992 // =0: external DP
993 // =0x1: internal DP2
994 // =0x11: internal DP1 for NutMeg/Travis DP translator
995 };
996 UCHAR ucLaneNum; // how many lanes to enable
997 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
998 UCHAR ucReserved;
999}DIG_ENCODER_CONTROL_PARAMETERS_V3;
1000
1001//ucTableFormatRevision=1
1002//ucTableContentRevision=4
1003// start from NI
1004// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
1005typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
1006{
1007#if ATOM_BIG_ENDIAN
1008 UCHAR ucReserved1:1;
1009 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
1010 UCHAR ucReserved:2;
1011 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
1012#else
1013 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
1014 UCHAR ucReserved:2;
1015 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
1016 UCHAR ucReserved1:1;
1017#endif
1018}ATOM_DIG_ENCODER_CONFIG_V4;
1019
1020#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03
1021#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00
1022#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01
1023#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02
1024#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03
1025#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70
1026#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00
1027#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10
1028#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20
1029#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30
1030#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40
1031#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50
1032#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60
1033
1034typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
1035{
1036 USHORT usPixelClock; // in 10KHz; for bios convenient
1037 union{
1038 ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
1039 UCHAR ucConfig;
1040 };
1041 UCHAR ucAction;
1042 union{
1043 UCHAR ucEncoderMode;
1044 // =0: DP encoder
1045 // =1: LVDS encoder
1046 // =2: DVI encoder
1047 // =3: HDMI encoder
1048 // =4: SDVO encoder
1049 // =5: DP audio
1050 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
1051 // =0: external DP
1052 // =0x1: internal DP2
1053 // =0x11: internal DP1 for NutMeg/Travis DP translator
1054 };
1055 UCHAR ucLaneNum; // how many lanes to enable
1056 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
1057 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
1058}DIG_ENCODER_CONTROL_PARAMETERS_V4;
1059
1060// define ucBitPerColor:
1061#define PANEL_BPC_UNDEFINE 0x00
1062#define PANEL_6BIT_PER_COLOR 0x01
1063#define PANEL_8BIT_PER_COLOR 0x02
1064#define PANEL_10BIT_PER_COLOR 0x03
1065#define PANEL_12BIT_PER_COLOR 0x04
1066#define PANEL_16BIT_PER_COLOR 0x05
1067
1068//define ucPanelMode
1069#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
1070#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
1071#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
1072
1073
1074typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V5
1075{
1076 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1077 UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP
1078 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1079 UCHAR ucLaneNum; // Lane number
1080 ULONG ulPixelClock; // Pixel Clock in 10Khz
1081 UCHAR ucBitPerColor;
1082 UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
1083 UCHAR ucReserved[2];
1084}ENCODER_STREAM_SETUP_PARAMETERS_V5;
1085
1086typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V5
1087{
1088 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1089 UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP
1090 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1091 UCHAR ucLaneNum; // Lane number
1092 ULONG ulSymClock; // Symbol Clock in 10Khz
1093 UCHAR ucHPDSel;
1094 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1095 UCHAR ucReserved[2];
1096}ENCODER_LINK_SETUP_PARAMETERS_V5;
1097
1098typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V5
1099{
1100 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1101 UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP
1102 UCHAR ucPanelMode; // =0: external DP
1103 // =0x1: internal DP2
1104 // =0x11: internal DP1 NutMeg/Travis DP Translator
1105 UCHAR ucReserved;
1106 ULONG ulReserved[2];
1107}DP_PANEL_MODE_SETUP_PARAMETERS_V5;
1108
1109typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V5
1110{
1111 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1112 UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters
1113 UCHAR ucReserved[2];
1114 ULONG ulReserved[2];
1115}ENCODER_GENERIC_CMD_PARAMETERS_V5;
1116
1117//ucDigId
1118#define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER 0x00
1119#define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER 0x01
1120#define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER 0x02
1121#define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER 0x03
1122#define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER 0x04
1123#define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER 0x05
1124#define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER 0x06
1125
1126
1127typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V5
1128{
1129 ENCODER_GENERIC_CMD_PARAMETERS_V5 asCmdParam;
1130 ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam;
1131 ENCODER_LINK_SETUP_PARAMETERS_V5 asLinkParam;
1132 DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam;
1133}DIG_ENCODER_CONTROL_PARAMETERS_V5;
1134
1135
1136/****************************************************************************/
1137// Structures used by UNIPHYTransmitterControlTable
1138// LVTMATransmitterControlTable
1139// DVOOutputControlTable
1140/****************************************************************************/
1141typedef struct _ATOM_DP_VS_MODE
1142{
1143 UCHAR ucLaneSel;
1144 UCHAR ucLaneSet;
1145}ATOM_DP_VS_MODE;
1146
1147typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
1148{
1149 union
1150 {
1151 USHORT usPixelClock; // in 10KHz; for bios convenient
1152 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1153 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1154 };
1155 UCHAR ucConfig;
1156 // [0]=0: 4 lane Link,
1157 // =1: 8 lane Link ( Dual Links TMDS )
1158 // [1]=0: InCoherent mode
1159 // =1: Coherent Mode
1160 // [2] Link Select:
1161 // =0: PHY linkA if bfLane<3
1162 // =1: PHY linkB if bfLanes<3
1163 // =0: PHY linkA+B if bfLanes=3
1164 // [5:4]PCIE lane Sel
1165 // =0: lane 0~3 or 0~7
1166 // =1: lane 4~7
1167 // =2: lane 8~11 or 8~15
1168 // =3: lane 12~15
1169 UCHAR ucAction; // =0: turn off encoder
1170 // =1: turn on encoder
1171 UCHAR ucReserved[4];
1172}DIG_TRANSMITTER_CONTROL_PARAMETERS;
1173
1174#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
1175
1176//ucInitInfo
1177#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
1178
1179//ucConfig
1180#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
1181#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
1182#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
1183#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
1184#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
1185#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
1186#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
1187
1188#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1189#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1190#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1191
1192#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
1193#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
1194#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
1195#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
1196#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
1197#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
1198#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
1199#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
1200#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
1201#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
1202#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
1203
1204//ucAction
1205#define ATOM_TRANSMITTER_ACTION_DISABLE 0
1206#define ATOM_TRANSMITTER_ACTION_ENABLE 1
1207#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
1208#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
1209#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
1210#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
1211#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
1212#define ATOM_TRANSMITTER_ACTION_INIT 7
1213#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
1214#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
1215#define ATOM_TRANSMITTER_ACTION_SETUP 10
1216#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
1217#define ATOM_TRANSMITTER_ACTION_POWER_ON 12
1218#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
1219
1220// Following are used for DigTransmitterControlTable ver1.2
1221typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
1222{
1223#if ATOM_BIG_ENDIAN
1224 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1225 // =1 Dig Transmitter 2 ( Uniphy CD )
1226 // =2 Dig Transmitter 3 ( Uniphy EF )
1227 UCHAR ucReserved:1;
1228 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1229 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1230 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1231 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1232
1233 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1234 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1235#else
1236 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1237 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1238 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1239 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1240 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1241 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1242 UCHAR ucReserved:1;
1243 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1244 // =1 Dig Transmitter 2 ( Uniphy CD )
1245 // =2 Dig Transmitter 3 ( Uniphy EF )
1246#endif
1247}ATOM_DIG_TRANSMITTER_CONFIG_V2;
1248
1249//ucConfig
1250//Bit0
1251#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
1252
1253//Bit1
1254#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
1255
1256//Bit2
1257#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
1258#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
1259#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
1260
1261// Bit3
1262#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
1263#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1264#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1265
1266// Bit4
1267#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
1268
1269// Bit7:6
1270#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
1271#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB
1272#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD
1273#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF
1274
1275typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
1276{
1277 union
1278 {
1279 USHORT usPixelClock; // in 10KHz; for bios convenient
1280 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1281 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1282 };
1283 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
1284 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1285 UCHAR ucReserved[4];
1286}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
1287
1288typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
1289{
1290#if ATOM_BIG_ENDIAN
1291 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1292 // =1 Dig Transmitter 2 ( Uniphy CD )
1293 // =2 Dig Transmitter 3 ( Uniphy EF )
1294 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1295 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1296 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1297 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1298 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1299 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1300#else
1301 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1302 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1303 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1304 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1305 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1306 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1307 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1308 // =1 Dig Transmitter 2 ( Uniphy CD )
1309 // =2 Dig Transmitter 3 ( Uniphy EF )
1310#endif
1311}ATOM_DIG_TRANSMITTER_CONFIG_V3;
1312
1313
1314typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
1315{
1316 union
1317 {
1318 USHORT usPixelClock; // in 10KHz; for bios convenient
1319 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1320 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1321 };
1322 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
1323 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1324 UCHAR ucLaneNum;
1325 UCHAR ucReserved[3];
1326}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
1327
1328//ucConfig
1329//Bit0
1330#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
1331
1332//Bit1
1333#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
1334
1335//Bit2
1336#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
1337#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
1338#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
1339
1340// Bit3
1341#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
1342#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
1343#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
1344
1345// Bit5:4
1346#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
1347#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
1348#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
1349#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
1350
1351// Bit7:6
1352#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
1353#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
1354#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
1355#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
1356
1357
1358/****************************************************************************/
1359// Structures used by UNIPHYTransmitterControlTable V1.4
1360// ASIC Families: NI
1361// ucTableFormatRevision=1
1362// ucTableContentRevision=4
1363/****************************************************************************/
1364typedef struct _ATOM_DP_VS_MODE_V4
1365{
1366 UCHAR ucLaneSel;
1367 union
1368 {
1369 UCHAR ucLaneSet;
1370 struct {
1371#if ATOM_BIG_ENDIAN
1372 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1373 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1374 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1375#else
1376 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1377 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1378 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1379#endif
1380 };
1381 };
1382}ATOM_DP_VS_MODE_V4;
1383
1384typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
1385{
1386#if ATOM_BIG_ENDIAN
1387 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1388 // =1 Dig Transmitter 2 ( Uniphy CD )
1389 // =2 Dig Transmitter 3 ( Uniphy EF )
1390 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1391 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1392 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1393 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1394 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1395 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1396#else
1397 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1398 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1399 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1400 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1401 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1402 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1403 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1404 // =1 Dig Transmitter 2 ( Uniphy CD )
1405 // =2 Dig Transmitter 3 ( Uniphy EF )
1406#endif
1407}ATOM_DIG_TRANSMITTER_CONFIG_V4;
1408
1409typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
1410{
1411 union
1412 {
1413 USHORT usPixelClock; // in 10KHz; for bios convenient
1414 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1415 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
1416 };
1417 union
1418 {
1419 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
1420 UCHAR ucConfig;
1421 };
1422 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1423 UCHAR ucLaneNum;
1424 UCHAR ucReserved[3];
1425}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
1426
1427//ucConfig
1428//Bit0
1429#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01
1430//Bit1
1431#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02
1432//Bit2
1433#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04
1434#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00
1435#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04
1436// Bit3
1437#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08
1438#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00
1439#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08
1440// Bit5:4
1441#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30
1442#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00
1443#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10
1444#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4
1445#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3
1446// Bit7:6
1447#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0
1448#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB
1449#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD
1450#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF
1451
1452
1453typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
1454{
1455#if ATOM_BIG_ENDIAN
1456 UCHAR ucReservd1:1;
1457 UCHAR ucHPDSel:3;
1458 UCHAR ucPhyClkSrcId:2;
1459 UCHAR ucCoherentMode:1;
1460 UCHAR ucReserved:1;
1461#else
1462 UCHAR ucReserved:1;
1463 UCHAR ucCoherentMode:1;
1464 UCHAR ucPhyClkSrcId:2;
1465 UCHAR ucHPDSel:3;
1466 UCHAR ucReservd1:1;
1467#endif
1468}ATOM_DIG_TRANSMITTER_CONFIG_V5;
1469
1470typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1471{
1472 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
1473 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1474 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1475 UCHAR ucLaneNum; // indicate lane number 1-8
1476 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1477 UCHAR ucDigMode; // indicate DIG mode
1478 union{
1479 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1480 UCHAR ucConfig;
1481 };
1482 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1483 UCHAR ucDPLaneSet;
1484 UCHAR ucReserved;
1485 UCHAR ucReserved1;
1486}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
1487
1488//ucPhyId
1489#define ATOM_PHY_ID_UNIPHYA 0
1490#define ATOM_PHY_ID_UNIPHYB 1
1491#define ATOM_PHY_ID_UNIPHYC 2
1492#define ATOM_PHY_ID_UNIPHYD 3
1493#define ATOM_PHY_ID_UNIPHYE 4
1494#define ATOM_PHY_ID_UNIPHYF 5
1495#define ATOM_PHY_ID_UNIPHYG 6
1496
1497// ucDigEncoderSel
1498#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01
1499#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02
1500#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04
1501#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08
1502#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10
1503#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20
1504#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40
1505
1506// ucDigMode
1507#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0
1508#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
1509#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
1510#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3
1511#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
1512#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5
1513
1514// ucDPLaneSet
1515#define DP_LANE_SET__0DB_0_4V 0x00
1516#define DP_LANE_SET__0DB_0_6V 0x01
1517#define DP_LANE_SET__0DB_0_8V 0x02
1518#define DP_LANE_SET__0DB_1_2V 0x03
1519#define DP_LANE_SET__3_5DB_0_4V 0x08
1520#define DP_LANE_SET__3_5DB_0_6V 0x09
1521#define DP_LANE_SET__3_5DB_0_8V 0x0a
1522#define DP_LANE_SET__6DB_0_4V 0x10
1523#define DP_LANE_SET__6DB_0_6V 0x11
1524#define DP_LANE_SET__9_5DB_0_4V 0x18
1525
1526// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1527// Bit1
1528#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02
1529
1530// Bit3:2
1531#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c
1532#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02
1533
1534#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00
1535#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04
1536#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08
1537#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c
1538// Bit6:4
1539#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70
1540#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04
1541
1542#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00
1543#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10
1544#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20
1545#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30
1546#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40
1547#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50
1548#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60
1549
1550#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1551
1552typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6
1553{
1554 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1555 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1556 union
1557 {
1558 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1559 UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
1560 };
1561 UCHAR ucLaneNum; // Lane number
1562 ULONG ulSymClock; // Symbol Clock in 10Khz
1563 UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
1564 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1565 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1566 UCHAR ucReserved;
1567 ULONG ulReserved;
1568}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6;
1569
1570
1571// ucDigEncoderSel
1572#define ATOM_TRANMSITTER_V6__DIGA_SEL 0x01
1573#define ATOM_TRANMSITTER_V6__DIGB_SEL 0x02
1574#define ATOM_TRANMSITTER_V6__DIGC_SEL 0x04
1575#define ATOM_TRANMSITTER_V6__DIGD_SEL 0x08
1576#define ATOM_TRANMSITTER_V6__DIGE_SEL 0x10
1577#define ATOM_TRANMSITTER_V6__DIGF_SEL 0x20
1578#define ATOM_TRANMSITTER_V6__DIGG_SEL 0x40
1579
1580// ucDigMode
1581#define ATOM_TRANSMITTER_DIGMODE_V6_DP 0
1582#define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2
1583#define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 3
1584#define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 5
1585
1586//ucHPDSel
1587#define ATOM_TRANSMITTER_V6_NO_HPD_SEL 0x00
1588#define ATOM_TRANSMITTER_V6_HPD1_SEL 0x01
1589#define ATOM_TRANSMITTER_V6_HPD2_SEL 0x02
1590#define ATOM_TRANSMITTER_V6_HPD3_SEL 0x03
1591#define ATOM_TRANSMITTER_V6_HPD4_SEL 0x04
1592#define ATOM_TRANSMITTER_V6_HPD5_SEL 0x05
1593#define ATOM_TRANSMITTER_V6_HPD6_SEL 0x06
1594
1595
1596/****************************************************************************/
1597// Structures used by ExternalEncoderControlTable V1.3
1598// ASIC Families: Evergreen, Llano, NI
1599// ucTableFormatRevision=1
1600// ucTableContentRevision=3
1601/****************************************************************************/
1602
1603typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1604{
1605 union{
1606 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1607 USHORT usConnectorId; // connector id, valid when ucAction = INIT
1608 };
1609 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1610 UCHAR ucAction; //
1611 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1612 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1613 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1614 UCHAR ucReserved;
1615}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
1616
1617// ucAction
1618#define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00
1619#define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01
1620#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07
1621#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f
1622#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
1623#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
1624#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
1625#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
1626
1627// ucConfig
1628#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
1629#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
1630#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
1631#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02
1632#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70
1633#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00
1634#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10
1635#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20
1636
1637typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
1638{
1639 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
1640 ULONG ulReserved[2];
1641}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
1642
1643
1644/****************************************************************************/
1645// Structures used by DAC1OuputControlTable
1646// DAC2OuputControlTable
1647// LVTMAOutputControlTable (Before DEC30)
1648// TMDSAOutputControlTable (Before DEC30)
1649/****************************************************************************/
1650typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1651{
1652 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1653 // When the display is LCD, in addition to above:
1654 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
1655 // ATOM_LCD_SELFTEST_STOP
1656
1657 UCHAR aucPadding[3]; // padding to DWORD aligned
1658}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
1659
1660#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1661
1662
1663#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1664#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1665
1666#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1667#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1668
1669#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1670#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1671
1672#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1673#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1674
1675#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1676#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1677
1678#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1679#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1680
1681#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1682#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1683
1684#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1685#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
1686#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
1687
1688
1689typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2
1690{
1691 // Possible value of ucAction
1692 // ATOM_TRANSMITTER_ACTION_LCD_BLON
1693 // ATOM_TRANSMITTER_ACTION_LCD_BLOFF
1694 // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
1695 // ATOM_TRANSMITTER_ACTION_POWER_ON
1696 // ATOM_TRANSMITTER_ACTION_POWER_OFF
1697 UCHAR ucAction;
1698 UCHAR ucBriLevel;
1699 USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz
1700}LVTMA_OUTPUT_CONTROL_PARAMETERS_V2;
1701
1702
1703
1704/****************************************************************************/
1705// Structures used by BlankCRTCTable
1706/****************************************************************************/
1707typedef struct _BLANK_CRTC_PARAMETERS
1708{
1709 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1710 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1711 USHORT usBlackColorRCr;
1712 USHORT usBlackColorGY;
1713 USHORT usBlackColorBCb;
1714}BLANK_CRTC_PARAMETERS;
1715#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
1716
1717/****************************************************************************/
1718// Structures used by EnableCRTCTable
1719// EnableCRTCMemReqTable
1720// UpdateCRTC_DoubleBufferRegistersTable
1721/****************************************************************************/
1722typedef struct _ENABLE_CRTC_PARAMETERS
1723{
1724 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1725 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1726 UCHAR ucPadding[2];
1727}ENABLE_CRTC_PARAMETERS;
1728#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
1729
1730/****************************************************************************/
1731// Structures used by SetCRTC_OverScanTable
1732/****************************************************************************/
1733typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
1734{
1735 USHORT usOverscanRight; // right
1736 USHORT usOverscanLeft; // left
1737 USHORT usOverscanBottom; // bottom
1738 USHORT usOverscanTop; // top
1739 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1740 UCHAR ucPadding[3];
1741}SET_CRTC_OVERSCAN_PARAMETERS;
1742#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
1743
1744/****************************************************************************/
1745// Structures used by SetCRTC_ReplicationTable
1746/****************************************************************************/
1747typedef struct _SET_CRTC_REPLICATION_PARAMETERS
1748{
1749 UCHAR ucH_Replication; // horizontal replication
1750 UCHAR ucV_Replication; // vertical replication
1751 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1752 UCHAR ucPadding;
1753}SET_CRTC_REPLICATION_PARAMETERS;
1754#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
1755
1756/****************************************************************************/
1757// Structures used by SelectCRTC_SourceTable
1758/****************************************************************************/
1759typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
1760{
1761 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1762 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1763 UCHAR ucPadding[2];
1764}SELECT_CRTC_SOURCE_PARAMETERS;
1765#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
1766
1767typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
1768{
1769 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1770 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1771 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1772 UCHAR ucPadding;
1773}SELECT_CRTC_SOURCE_PARAMETERS_V2;
1774
1775//ucEncoderID
1776//#define ASIC_INT_DAC1_ENCODER_ID 0x00
1777//#define ASIC_INT_TV_ENCODER_ID 0x02
1778//#define ASIC_INT_DIG1_ENCODER_ID 0x03
1779//#define ASIC_INT_DAC2_ENCODER_ID 0x04
1780//#define ASIC_EXT_TV_ENCODER_ID 0x06
1781//#define ASIC_INT_DVO_ENCODER_ID 0x07
1782//#define ASIC_INT_DIG2_ENCODER_ID 0x09
1783//#define ASIC_EXT_DIG_ENCODER_ID 0x05
1784
1785//ucEncodeMode
1786//#define ATOM_ENCODER_MODE_DP 0
1787//#define ATOM_ENCODER_MODE_LVDS 1
1788//#define ATOM_ENCODER_MODE_DVI 2
1789//#define ATOM_ENCODER_MODE_HDMI 3
1790//#define ATOM_ENCODER_MODE_SDVO 4
1791//#define ATOM_ENCODER_MODE_TV 13
1792//#define ATOM_ENCODER_MODE_CV 14
1793//#define ATOM_ENCODER_MODE_CRT 15
1794
1795
1796typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3
1797{
1798 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1799 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1800 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1801 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR
1802}SELECT_CRTC_SOURCE_PARAMETERS_V3;
1803
1804
1805/****************************************************************************/
1806// Structures used by SetPixelClockTable
1807// GetPixelClockTable
1808/****************************************************************************/
1809//Major revision=1., Minor revision=1
1810typedef struct _PIXEL_CLOCK_PARAMETERS
1811{
1812 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1813 // 0 means disable PPLL
1814 USHORT usRefDiv; // Reference divider
1815 USHORT usFbDiv; // feedback divider
1816 UCHAR ucPostDiv; // post divider
1817 UCHAR ucFracFbDiv; // fractional feedback divider
1818 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1819 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1820 UCHAR ucCRTC; // Which CRTC uses this Ppll
1821 UCHAR ucPadding;
1822}PIXEL_CLOCK_PARAMETERS;
1823
1824//Major revision=1., Minor revision=2, add ucMiscIfno
1825//ucMiscInfo:
1826#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
1827#define MISC_DEVICE_INDEX_MASK 0xF0
1828#define MISC_DEVICE_INDEX_SHIFT 4
1829
1830typedef struct _PIXEL_CLOCK_PARAMETERS_V2
1831{
1832 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1833 // 0 means disable PPLL
1834 USHORT usRefDiv; // Reference divider
1835 USHORT usFbDiv; // feedback divider
1836 UCHAR ucPostDiv; // post divider
1837 UCHAR ucFracFbDiv; // fractional feedback divider
1838 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1839 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1840 UCHAR ucCRTC; // Which CRTC uses this Ppll
1841 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1842}PIXEL_CLOCK_PARAMETERS_V2;
1843
1844//Major revision=1., Minor revision=3, structure/definition change
1845//ucEncoderMode:
1846//ATOM_ENCODER_MODE_DP
1847//ATOM_ENOCDER_MODE_LVDS
1848//ATOM_ENOCDER_MODE_DVI
1849//ATOM_ENOCDER_MODE_HDMI
1850//ATOM_ENOCDER_MODE_SDVO
1851//ATOM_ENCODER_MODE_TV 13
1852//ATOM_ENCODER_MODE_CV 14
1853//ATOM_ENCODER_MODE_CRT 15
1854
1855//ucDVOConfig
1856//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
1857//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
1858//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
1859//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
1860//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
1861//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
1862//#define DVO_ENCODER_CONFIG_24BIT 0x08
1863
1864//ucMiscInfo: also changed, see below
1865#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
1866#define PIXEL_CLOCK_MISC_VGA_MODE 0x02
1867#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
1868#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
1869#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
1870#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
1871#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
1872// V1.4 for RoadRunner
1873#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
1874#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
1875
1876
1877typedef struct _PIXEL_CLOCK_PARAMETERS_V3
1878{
1879 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1880 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1881 USHORT usRefDiv; // Reference divider
1882 USHORT usFbDiv; // feedback divider
1883 UCHAR ucPostDiv; // post divider
1884 UCHAR ucFracFbDiv; // fractional feedback divider
1885 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1886 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1887 union
1888 {
1889 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1890 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1891 };
1892 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1893 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1894 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
1895}PIXEL_CLOCK_PARAMETERS_V3;
1896
1897#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
1898#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
1899
1900
1901typedef struct _PIXEL_CLOCK_PARAMETERS_V5
1902{
1903 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1904 // drive the pixel clock. not used for DCPLL case.
1905 union{
1906 UCHAR ucReserved;
1907 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
1908 };
1909 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
1910 // 0 means disable PPLL/DCPLL.
1911 USHORT usFbDiv; // feedback divider integer part.
1912 UCHAR ucPostDiv; // post divider.
1913 UCHAR ucRefDiv; // Reference divider
1914 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1915 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1916 // indicate which graphic encoder will be used.
1917 UCHAR ucEncoderMode; // Encoder mode:
1918 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1919 // bit[1]= when VGA timing is used.
1920 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1921 // bit[4]= RefClock source for PPLL.
1922 // =0: XTLAIN( default mode )
1923 // =1: other external clock source, which is pre-defined
1924 // by VBIOS depend on the feature required.
1925 // bit[7:5]: reserved.
1926 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1927
1928}PIXEL_CLOCK_PARAMETERS_V5;
1929
1930#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
1931#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
1932#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
1933#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
1934#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
1935#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
1936#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
1937
1938typedef struct _CRTC_PIXEL_CLOCK_FREQ
1939{
1940#if ATOM_BIG_ENDIAN
1941 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1942 // drive the pixel clock. not used for DCPLL case.
1943 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1944 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1945#else
1946 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1947 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1948 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1949 // drive the pixel clock. not used for DCPLL case.
1950#endif
1951}CRTC_PIXEL_CLOCK_FREQ;
1952
1953typedef struct _PIXEL_CLOCK_PARAMETERS_V6
1954{
1955 union{
1956 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
1957 ULONG ulDispEngClkFreq; // dispclk frequency
1958 };
1959 USHORT usFbDiv; // feedback divider integer part.
1960 UCHAR ucPostDiv; // post divider.
1961 UCHAR ucRefDiv; // Reference divider
1962 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1963 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1964 // indicate which graphic encoder will be used.
1965 UCHAR ucEncoderMode; // Encoder mode:
1966 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1967 // bit[1]= when VGA timing is used.
1968 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1969 // bit[4]= RefClock source for PPLL.
1970 // =0: XTLAIN( default mode )
1971 // =1: other external clock source, which is pre-defined
1972 // by VBIOS depend on the feature required.
1973 // bit[7:5]: reserved.
1974 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1975
1976}PIXEL_CLOCK_PARAMETERS_V6;
1977
1978#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01
1979#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02
1980#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
1981#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
1982#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
1983#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
1984#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
1985#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
1986#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
1987#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
1988#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40
1989#define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40
1990
1991typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
1992{
1993 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
1994}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
1995
1996typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
1997{
1998 UCHAR ucStatus;
1999 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
2000 UCHAR ucReserved[2];
2001}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
2002
2003typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
2004{
2005 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
2006}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
2007
2008typedef struct _PIXEL_CLOCK_PARAMETERS_V7
2009{
2010 ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
2011
2012 UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2013 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
2014 // indicate which graphic encoder will be used.
2015 UCHAR ucEncoderMode; // Encoder mode:
2016 UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk
2017 // bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk )
2018 // bit[5:4]= RefClock source for PPLL.
2019 // =0: XTLAIN( default mode )
2020 // =1: pcie
2021 // =2: GENLK
2022 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
2023 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
2024 UCHAR ucReserved[2];
2025 ULONG ulReserved;
2026}PIXEL_CLOCK_PARAMETERS_V7;
2027
2028//ucMiscInfo
2029#define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL 0x01
2030#define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL 0x02
2031#define PIXEL_CLOCK_V7_MISC_YUV420_MODE 0x04
2032#define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN 0x08
2033#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC 0x30
2034#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN 0x00
2035#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE 0x10
2036#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK 0x20
2037
2038//ucDeepColorRatio
2039#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2040#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2041#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2042#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2043
2044// SetDCEClockTable input parameter for DCE11.1
2045typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_1
2046{
2047 ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz.
2048 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
2049 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
2050 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
2051 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
2052}SET_DCE_CLOCK_PARAMETERS_V1_1;
2053
2054
2055typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1
2056{
2057 SET_DCE_CLOCK_PARAMETERS_V1_1 asParam;
2058 ULONG ulReserved[2];
2059}SET_DCE_CLOCK_PS_ALLOCATION_V1_1;
2060
2061//SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag
2062#define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK 0x01
2063#define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01
2064#define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02
2065
2066// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above
2067typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1
2068{
2069 ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
2070 UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2071 UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
2072 UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
2073 UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
2074}SET_DCE_CLOCK_PARAMETERS_V2_1;
2075
2076//ucDCEClkType
2077#define DCE_CLOCK_TYPE_DISPCLK 0
2078#define DCE_CLOCK_TYPE_DPREFCLK 1
2079#define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable
2080
2081//ucDCEClkFlag when ucDCEClkType == DPREFCLK
2082#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK 0x03
2083#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA 0x00
2084#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK 0x01
2085#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE 0x02
2086#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN 0x03
2087
2088//ucDCEClkFlag when ucDCEClkType == PIXCLK
2089#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x03
2090#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2091#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2092#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2093#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2094#define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x04
2095
2096typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_1
2097{
2098 SET_DCE_CLOCK_PARAMETERS_V2_1 asParam;
2099 ULONG ulReserved[2];
2100}SET_DCE_CLOCK_PS_ALLOCATION_V2_1;
2101
2102
2103
2104/****************************************************************************/
2105// Structures used by AdjustDisplayPllTable
2106/****************************************************************************/
2107typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
2108{
2109 USHORT usPixelClock;
2110 UCHAR ucTransmitterID;
2111 UCHAR ucEncodeMode;
2112 union
2113 {
2114 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
2115 UCHAR ucConfig; //if none DVO, not defined yet
2116 };
2117 UCHAR ucReserved[3];
2118}ADJUST_DISPLAY_PLL_PARAMETERS;
2119
2120#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
2121#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
2122
2123typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
2124{
2125 USHORT usPixelClock; // target pixel clock
2126 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
2127 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
2128 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
2129 UCHAR ucExtTransmitterID; // external encoder id.
2130 UCHAR ucReserved[2];
2131}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
2132
2133// usDispPllConfig v1.2 for RoadRunner
2134#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
2135#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
2136#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
2137#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
2138#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
2139#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
2140#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
2141#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
2142#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
2143#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
2144
2145
2146typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
2147{
2148 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
2149 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
2150 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
2151 UCHAR ucReserved[2];
2152}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
2153
2154typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
2155{
2156 union
2157 {
2158 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;
2159 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
2160 };
2161} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
2162
2163/****************************************************************************/
2164// Structures used by EnableYUVTable
2165/****************************************************************************/
2166typedef struct _ENABLE_YUV_PARAMETERS
2167{
2168 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
2169 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
2170 UCHAR ucPadding[2];
2171}ENABLE_YUV_PARAMETERS;
2172#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
2173
2174/****************************************************************************/
2175// Structures used by GetMemoryClockTable
2176/****************************************************************************/
2177typedef struct _GET_MEMORY_CLOCK_PARAMETERS
2178{
2179 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
2180} GET_MEMORY_CLOCK_PARAMETERS;
2181#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
2182
2183/****************************************************************************/
2184// Structures used by GetEngineClockTable
2185/****************************************************************************/
2186typedef struct _GET_ENGINE_CLOCK_PARAMETERS
2187{
2188 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2189} GET_ENGINE_CLOCK_PARAMETERS;
2190#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
2191
2192/****************************************************************************/
2193// Following Structures and constant may be obsolete
2194/****************************************************************************/
2195//Maxium 8 bytes,the data read in will be placed in the parameter space.
2196//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
2197typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
2198{
2199 USHORT usPrescale; //Ratio between Engine clock and I2C clock
2200 USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
2201 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
2202 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
2203 UCHAR ucSlaveAddr; //Read from which slave
2204 UCHAR ucLineNumber; //Read from which HW assisted line
2205}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
2206#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
2207
2208
2209#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
2210#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
2211#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
2212#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
2213#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
2214
2215typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
2216{
2217 USHORT usPrescale; //Ratio between Engine clock and I2C clock
2218 USHORT usByteOffset; //Write to which byte
2219 //Upper portion of usByteOffset is Format of data
2220 //1bytePS+offsetPS
2221 //2bytesPS+offsetPS
2222 //blockID+offsetPS
2223 //blockID+offsetID
2224 //blockID+counterID+offsetID
2225 UCHAR ucData; //PS data1
2226 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
2227 UCHAR ucSlaveAddr; //Write to which slave
2228 UCHAR ucLineNumber; //Write from which HW assisted line
2229}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
2230
2231#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
2232
2233typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
2234{
2235 USHORT usPrescale; //Ratio between Engine clock and I2C clock
2236 UCHAR ucSlaveAddr; //Write to which slave
2237 UCHAR ucLineNumber; //Write from which HW assisted line
2238}SET_UP_HW_I2C_DATA_PARAMETERS;
2239
2240/**************************************************************************/
2241#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
2242
2243
2244/****************************************************************************/
2245// Structures used by PowerConnectorDetectionTable
2246/****************************************************************************/
2247typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
2248{
2249 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2250 UCHAR ucPwrBehaviorId;
2251 USHORT usPwrBudget; //how much power currently boot to in unit of watt
2252}POWER_CONNECTOR_DETECTION_PARAMETERS;
2253
2254typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
2255{
2256 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2257 UCHAR ucReserved;
2258 USHORT usPwrBudget; //how much power currently boot to in unit of watt
2259 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2260}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
2261
2262
2263/****************************LVDS SS Command Table Definitions**********************/
2264
2265/****************************************************************************/
2266// Structures used by EnableSpreadSpectrumOnPPLLTable
2267/****************************************************************************/
2268typedef struct _ENABLE_LVDS_SS_PARAMETERS
2269{
2270 USHORT usSpreadSpectrumPercentage;
2271 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2272 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
2273 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
2274 UCHAR ucPadding[3];
2275}ENABLE_LVDS_SS_PARAMETERS;
2276
2277//ucTableFormatRevision=1,ucTableContentRevision=2
2278typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
2279{
2280 USHORT usSpreadSpectrumPercentage;
2281 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2282 UCHAR ucSpreadSpectrumStep; //
2283 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
2284 UCHAR ucSpreadSpectrumDelay;
2285 UCHAR ucSpreadSpectrumRange;
2286 UCHAR ucPadding;
2287}ENABLE_LVDS_SS_PARAMETERS_V2;
2288
2289//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
2290typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
2291{
2292 USHORT usSpreadSpectrumPercentage;
2293 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2294 UCHAR ucSpreadSpectrumStep; //
2295 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2296 UCHAR ucSpreadSpectrumDelay;
2297 UCHAR ucSpreadSpectrumRange;
2298 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
2299}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
2300
2301 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
2302{
2303 USHORT usSpreadSpectrumPercentage;
2304 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2305 // Bit[1]: 1-Ext. 0-Int.
2306 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2307 // Bits[7:4] reserved
2308 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2309 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
2310 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
2311}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
2312
2313#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
2314#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
2315#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
2316#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
2317#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
2318#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
2319#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
2320#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
2321#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
2322#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
2323#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
2324
2325// Used by DCE5.0
2326 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
2327{
2328 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
2329 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2330 // Bit[1]: 1-Ext. 0-Int.
2331 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2332 // Bits[7:4] reserved
2333 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2334 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
2335 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
2336}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
2337
2338
2339#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00
2340#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01
2341#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02
2342#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c
2343#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00
2344#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04
2345#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08
2346#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL
2347#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF
2348#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0
2349#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00
2350#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
2351
2352#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
2353
2354typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
2355{
2356 PIXEL_CLOCK_PARAMETERS sPCLKInput;
2357 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
2358}SET_PIXEL_CLOCK_PS_ALLOCATION;
2359
2360
2361
2362#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
2363
2364/****************************************************************************/
2365// Structures used by ###
2366/****************************************************************************/
2367typedef struct _MEMORY_TRAINING_PARAMETERS
2368{
2369 ULONG ulTargetMemoryClock; //In 10Khz unit
2370}MEMORY_TRAINING_PARAMETERS;
2371#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
2372
2373
2374typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2
2375{
2376 USHORT usMemTrainingMode;
2377 USHORT usReserved;
2378}MEMORY_TRAINING_PARAMETERS_V1_2;
2379
2380//usMemTrainingMode
2381#define NORMAL_MEMORY_TRAINING_MODE 0
2382#define ENTER_DRAM_SELFREFRESH_MODE 1
2383#define EXIT_DRAM_SELFRESH_MODE 2
2384
2385/****************************LVDS and other encoder command table definitions **********************/
2386
2387
2388/****************************************************************************/
2389// Structures used by LVDSEncoderControlTable (Before DEC30)
2390// LVTMAEncoderControlTable (Before DEC30)
2391// TMDSAEncoderControlTable (Before DEC30)
2392/****************************************************************************/
2393typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
2394{
2395 USHORT usPixelClock; // in 10KHz; for bios convenient
2396 UCHAR ucMisc; // bit0=0: Enable single link
2397 // =1: Enable dual link
2398 // Bit1=0: 666RGB
2399 // =1: 888RGB
2400 UCHAR ucAction; // 0: turn off encoder
2401 // 1: setup and turn on encoder
2402}LVDS_ENCODER_CONTROL_PARAMETERS;
2403
2404#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
2405
2406#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
2407#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
2408
2409#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
2410#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
2411
2412//ucTableFormatRevision=1,ucTableContentRevision=2
2413typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
2414{
2415 USHORT usPixelClock; // in 10KHz; for bios convenient
2416 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2417 UCHAR ucAction; // 0: turn off encoder
2418 // 1: setup and turn on encoder
2419 UCHAR ucTruncate; // bit0=0: Disable truncate
2420 // =1: Enable truncate
2421 // bit4=0: 666RGB
2422 // =1: 888RGB
2423 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2424 // =1: Enable spatial dithering
2425 // bit4=0: 666RGB
2426 // =1: 888RGB
2427 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2428 // =1: Enable temporal dithering
2429 // bit4=0: 666RGB
2430 // =1: 888RGB
2431 // bit5=0: Gray level 2
2432 // =1: Gray level 4
2433 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2434 // =1: 25FRC_SEL pattern F
2435 // bit6:5=0: 50FRC_SEL pattern A
2436 // =1: 50FRC_SEL pattern B
2437 // =2: 50FRC_SEL pattern C
2438 // =3: 50FRC_SEL pattern D
2439 // bit7=0: 75FRC_SEL pattern E
2440 // =1: 75FRC_SEL pattern F
2441}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
2442
2443#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2444
2445#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2446#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2447
2448#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2449#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
2450
2451
2452#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2453#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2454
2455#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2456#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
2457
2458#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
2459#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
2460
2461/****************************************************************************/
2462// Structures used by ###
2463/****************************************************************************/
2464typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
2465{
2466 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2467 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2468 UCHAR ucPadding[2];
2469}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
2470
2471typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
2472{
2473 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
2474 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2475}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
2476
2477#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
2478typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
2479{
2480 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
2481 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
2482}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
2483
2484typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
2485{
2486 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
2487 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2488}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
2489
2490/****************************************************************************/
2491// Structures used by DVOEncoderControlTable
2492/****************************************************************************/
2493//ucTableFormatRevision=1,ucTableContentRevision=3
2494//ucDVOConfig:
2495#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
2496#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
2497#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
2498#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
2499#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
2500#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
2501#define DVO_ENCODER_CONFIG_24BIT 0x08
2502
2503typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
2504{
2505 USHORT usPixelClock;
2506 UCHAR ucDVOConfig;
2507 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2508 UCHAR ucReseved[4];
2509}DVO_ENCODER_CONTROL_PARAMETERS_V3;
2510#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
2511
2512typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4
2513{
2514 USHORT usPixelClock;
2515 UCHAR ucDVOConfig;
2516 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2517 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR
2518 UCHAR ucReseved[3];
2519}DVO_ENCODER_CONTROL_PARAMETERS_V1_4;
2520#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4
2521
2522
2523//ucTableFormatRevision=1
2524//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2525// bit1=0: non-coherent mode
2526// =1: coherent mode
2527
2528//==========================================================================================
2529//Only change is here next time when changing encoder parameter definitions again!
2530#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2531#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
2532
2533#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2534#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
2535
2536#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
2537#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
2538
2539#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
2540#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
2541
2542//==========================================================================================
2543#define PANEL_ENCODER_MISC_DUAL 0x01
2544#define PANEL_ENCODER_MISC_COHERENT 0x02
2545#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
2546#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
2547
2548#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
2549#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
2550#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
2551
2552#define PANEL_ENCODER_TRUNCATE_EN 0x01
2553#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
2554#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
2555#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
2556#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
2557#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
2558#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
2559#define PANEL_ENCODER_25FRC_MASK 0x10
2560#define PANEL_ENCODER_25FRC_E 0x00
2561#define PANEL_ENCODER_25FRC_F 0x10
2562#define PANEL_ENCODER_50FRC_MASK 0x60
2563#define PANEL_ENCODER_50FRC_A 0x00
2564#define PANEL_ENCODER_50FRC_B 0x20
2565#define PANEL_ENCODER_50FRC_C 0x40
2566#define PANEL_ENCODER_50FRC_D 0x60
2567#define PANEL_ENCODER_75FRC_MASK 0x80
2568#define PANEL_ENCODER_75FRC_E 0x00
2569#define PANEL_ENCODER_75FRC_F 0x80
2570
2571/****************************************************************************/
2572// Structures used by SetVoltageTable
2573/****************************************************************************/
2574#define SET_VOLTAGE_TYPE_ASIC_VDDC 1
2575#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
2576#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
2577#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
2578#define SET_VOLTAGE_INIT_MODE 5
2579#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
2580
2581#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
2582#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
2583#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
2584
2585#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
2586#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
2587#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
2588
2589typedef struct _SET_VOLTAGE_PARAMETERS
2590{
2591 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2592 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2593 UCHAR ucVoltageIndex; // An index to tell which voltage level
2594 UCHAR ucReserved;
2595}SET_VOLTAGE_PARAMETERS;
2596
2597typedef struct _SET_VOLTAGE_PARAMETERS_V2
2598{
2599 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2600 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2601 USHORT usVoltageLevel; // real voltage level
2602}SET_VOLTAGE_PARAMETERS_V2;
2603
2604// used by both SetVoltageTable v1.3 and v1.4
2605typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
2606{
2607 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2608 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2609 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2610}SET_VOLTAGE_PARAMETERS_V1_3;
2611
2612//ucVoltageType
2613#define VOLTAGE_TYPE_VDDC 1
2614#define VOLTAGE_TYPE_MVDDC 2
2615#define VOLTAGE_TYPE_MVDDQ 3
2616#define VOLTAGE_TYPE_VDDCI 4
2617#define VOLTAGE_TYPE_VDDGFX 5
2618#define VOLTAGE_TYPE_PCC 6
2619#define VOLTAGE_TYPE_MVPP 7
2620#define VOLTAGE_TYPE_LEDDPM 8
2621#define VOLTAGE_TYPE_PCC_MVDD 9
2622#define VOLTAGE_TYPE_PCIE_VDDC 10
2623#define VOLTAGE_TYPE_PCIE_VDDR 11
2624
2625#define VOLTAGE_TYPE_GENERIC_I2C_1 0x11
2626#define VOLTAGE_TYPE_GENERIC_I2C_2 0x12
2627#define VOLTAGE_TYPE_GENERIC_I2C_3 0x13
2628#define VOLTAGE_TYPE_GENERIC_I2C_4 0x14
2629#define VOLTAGE_TYPE_GENERIC_I2C_5 0x15
2630#define VOLTAGE_TYPE_GENERIC_I2C_6 0x16
2631#define VOLTAGE_TYPE_GENERIC_I2C_7 0x17
2632#define VOLTAGE_TYPE_GENERIC_I2C_8 0x18
2633#define VOLTAGE_TYPE_GENERIC_I2C_9 0x19
2634#define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A
2635
2636//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
2637#define ATOM_SET_VOLTAGE 0 //Set voltage Level
2638#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator
2639#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator
2640#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3
2641#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
2642#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
2643
2644// define vitual voltage id in usVoltageLevel
2645#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
2646#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02
2647#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03
2648#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04
2649#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05
2650#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06
2651#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07
2652#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08
2653
2654typedef struct _SET_VOLTAGE_PS_ALLOCATION
2655{
2656 SET_VOLTAGE_PARAMETERS sASICSetVoltage;
2657 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2658}SET_VOLTAGE_PS_ALLOCATION;
2659
2660// New Added from SI for GetVoltageInfoTable, input parameter structure
2661typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
2662{
2663 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2664 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2665 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2666 ULONG ulReserved;
2667}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
2668
2669// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
2670typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2671{
2672 ULONG ulVotlageGpioState;
2673 ULONG ulVoltageGPioMask;
2674}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2675
2676// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
2677typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2678{
2679 USHORT usVoltageLevel;
2680 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2681 ULONG ulReseved;
2682}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2683
2684// GetVoltageInfo v1.1 ucVoltageMode
2685#define ATOM_GET_VOLTAGE_VID 0x00
2686#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
2687#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
2688#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info
2689
2690// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
2691#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2692// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
2693#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
2694
2695#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
2696#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
2697
2698
2699// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
2700typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
2701{
2702 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2703 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2704 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2705 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2706}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
2707
2708// New in GetVoltageInfo v1.2 ucVoltageMode
2709#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09
2710
2711// New Added from CI Hawaii for EVV feature
2712typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
2713{
2714 USHORT usVoltageLevel; // real voltage level in unit of mv
2715 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
2716 USHORT usTDP_Current; // TDP_Current in unit of 0.01A
2717 USHORT usTDP_Power; // TDP_Current in unit of 0.1W
2718}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
2719
2720
2721// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
2722typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3
2723{
2724 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2725 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2726 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2727 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2728 ULONG ulReserved[3];
2729}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3;
2730
2731// New Added from CI Hawaii for EVV feature
2732typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3
2733{
2734 ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv
2735 ULONG ulReserved[4];
2736}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3;
2737
2738
2739/****************************************************************************/
2740// Structures used by GetSMUClockInfo
2741/****************************************************************************/
2742typedef struct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1
2743{
2744 ULONG ulDfsPllOutputFreq:24;
2745 ULONG ucDfsDivider:8;
2746}GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1;
2747
2748typedef struct _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1
2749{
2750 ULONG ulDfsOutputFreq;
2751}GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1;
2752
2753/****************************************************************************/
2754// Structures used by TVEncoderControlTable
2755/****************************************************************************/
2756typedef struct _TV_ENCODER_CONTROL_PARAMETERS
2757{
2758 USHORT usPixelClock; // in 10KHz; for bios convenient
2759 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2760 UCHAR ucAction; // 0: turn off encoder
2761 // 1: setup and turn on encoder
2762}TV_ENCODER_CONTROL_PARAMETERS;
2763
2764typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
2765{
2766 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
2767 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
2768}TV_ENCODER_CONTROL_PS_ALLOCATION;
2769
2770//==============================Data Table Portion====================================
2771
2772
2773/****************************************************************************/
2774// Structure used in Data.mtb
2775/****************************************************************************/
2776typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
2777{
2778 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
2779 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
2780 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
2781 USHORT StandardVESA_Timing; // Only used by Bios
2782 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
2783 USHORT PaletteData; // Only used by BIOS
2784 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
2785 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
2786 USHORT SMU_Info; // Shared by various SW components,latest version 1.1
2787 USHORT SupportedDevicesInfo; // Will be obsolete from R600
2788 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
2789 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
2790 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
2791 USHORT VESA_ToInternalModeLUT; // Only used by Bios
2792 USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600
2793 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
2794 USHORT GPUVirtualizationInfo; // Will be obsolete from R600
2795 USHORT SaveRestoreInfo; // Only used by Bios
2796 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2797 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
2798 USHORT XTMDS_Info; // Will be obsolete from R600
2799 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2800 USHORT Object_Header; // Shared by various SW components,latest version 1.1
2801 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
2802 USHORT MC_InitParameter; // Only used by command table
2803 USHORT ASIC_VDDC_Info; // Will be obsolete from R600
2804 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
2805 USHORT TV_VideoMode; // Only used by command table
2806 USHORT VRAM_Info; // Only used by command table, latest version 1.3
2807 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
2808 USHORT IntegratedSystemInfo; // Shared by various SW components
2809 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2810 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
2811 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
2812 USHORT ServiceInfo;
2813}ATOM_MASTER_LIST_OF_DATA_TABLES;
2814
2815typedef struct _ATOM_MASTER_DATA_TABLE
2816{
2817 ATOM_COMMON_TABLE_HEADER sHeader;
2818 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
2819}ATOM_MASTER_DATA_TABLE;
2820
2821// For backward compatible
2822#define LVDS_Info LCD_Info
2823#define DAC_Info PaletteData
2824#define TMDS_Info DIGTransmitterInfo
2825#define CompassionateData GPUVirtualizationInfo
2826#define AnalogTV_Info SMU_Info
2827#define ComponentVideoInfo GFX_Info
2828
2829/****************************************************************************/
2830// Structure used in MultimediaCapabilityInfoTable
2831/****************************************************************************/
2832typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
2833{
2834 ATOM_COMMON_TABLE_HEADER sHeader;
2835 ULONG ulSignature; // HW info table signature string "$ATI"
2836 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2837 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2838 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2839 UCHAR ucHostPortInfo; // Provides host port configuration information
2840}ATOM_MULTIMEDIA_CAPABILITY_INFO;
2841
2842
2843/****************************************************************************/
2844// Structure used in MultimediaConfigInfoTable
2845/****************************************************************************/
2846typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
2847{
2848 ATOM_COMMON_TABLE_HEADER sHeader;
2849 ULONG ulSignature; // MM info table signature sting "$MMT"
2850 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2851 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2852 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
2853 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2854 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2855 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2856 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2857 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2858 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2859 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2860 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2861 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2862}ATOM_MULTIMEDIA_CONFIG_INFO;
2863
2864
2865/****************************************************************************/
2866// Structures used in FirmwareInfoTable
2867/****************************************************************************/
2868
2869// usBIOSCapability Defintion:
2870// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2871// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2872// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2873// Others: Reserved
2874#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
2875#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
2876#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
2877#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2878#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
2879#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
2880#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
2881#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
2882#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
2883#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
2884#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
2885#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
2886#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
2887#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
2888
2889
2890#ifndef _H2INC
2891
2892//Please don't add or expand this bitfield structure below, this one will retire soon.!
2893typedef struct _ATOM_FIRMWARE_CAPABILITY
2894{
2895#if ATOM_BIG_ENDIAN
2896 USHORT Reserved:1;
2897 USHORT SCL2Redefined:1;
2898 USHORT PostWithoutModeSet:1;
2899 USHORT HyperMemory_Size:4;
2900 USHORT HyperMemory_Support:1;
2901 USHORT PPMode_Assigned:1;
2902 USHORT WMI_SUPPORT:1;
2903 USHORT GPUControlsBL:1;
2904 USHORT EngineClockSS_Support:1;
2905 USHORT MemoryClockSS_Support:1;
2906 USHORT ExtendedDesktopSupport:1;
2907 USHORT DualCRTC_Support:1;
2908 USHORT FirmwarePosted:1;
2909#else
2910 USHORT FirmwarePosted:1;
2911 USHORT DualCRTC_Support:1;
2912 USHORT ExtendedDesktopSupport:1;
2913 USHORT MemoryClockSS_Support:1;
2914 USHORT EngineClockSS_Support:1;
2915 USHORT GPUControlsBL:1;
2916 USHORT WMI_SUPPORT:1;
2917 USHORT PPMode_Assigned:1;
2918 USHORT HyperMemory_Support:1;
2919 USHORT HyperMemory_Size:4;
2920 USHORT PostWithoutModeSet:1;
2921 USHORT SCL2Redefined:1;
2922 USHORT Reserved:1;
2923#endif
2924}ATOM_FIRMWARE_CAPABILITY;
2925
2926typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2927{
2928 ATOM_FIRMWARE_CAPABILITY sbfAccess;
2929 USHORT susAccess;
2930}ATOM_FIRMWARE_CAPABILITY_ACCESS;
2931
2932#else
2933
2934typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2935{
2936 USHORT susAccess;
2937}ATOM_FIRMWARE_CAPABILITY_ACCESS;
2938
2939#endif
2940
2941typedef struct _ATOM_FIRMWARE_INFO
2942{
2943 ATOM_COMMON_TABLE_HEADER sHeader;
2944 ULONG ulFirmwareRevision;
2945 ULONG ulDefaultEngineClock; //In 10Khz unit
2946 ULONG ulDefaultMemoryClock; //In 10Khz unit
2947 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2948 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2949 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2950 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2951 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2952 ULONG ulASICMaxEngineClock; //In 10Khz unit
2953 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2954 UCHAR ucASICMaxTemperature;
2955 UCHAR ucPadding[3]; //Don't use them
2956 ULONG aulReservedForBIOS[3]; //Don't use them
2957 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2958 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2959 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2960 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2961 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2962 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2963 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2964 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2965 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2966 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
2967 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2968 USHORT usReferenceClock; //In 10Khz unit
2969 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2970 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2971 UCHAR ucDesign_ID; //Indicate what is the board design
2972 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2973}ATOM_FIRMWARE_INFO;
2974
2975typedef struct _ATOM_FIRMWARE_INFO_V1_2
2976{
2977 ATOM_COMMON_TABLE_HEADER sHeader;
2978 ULONG ulFirmwareRevision;
2979 ULONG ulDefaultEngineClock; //In 10Khz unit
2980 ULONG ulDefaultMemoryClock; //In 10Khz unit
2981 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2982 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2983 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2984 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2985 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2986 ULONG ulASICMaxEngineClock; //In 10Khz unit
2987 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2988 UCHAR ucASICMaxTemperature;
2989 UCHAR ucMinAllowedBL_Level;
2990 UCHAR ucPadding[2]; //Don't use them
2991 ULONG aulReservedForBIOS[2]; //Don't use them
2992 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2993 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2994 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2995 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2996 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2997 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2998 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2999 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3000 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3001 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3002 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3003 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3004 USHORT usReferenceClock; //In 10Khz unit
3005 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3006 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3007 UCHAR ucDesign_ID; //Indicate what is the board design
3008 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3009}ATOM_FIRMWARE_INFO_V1_2;
3010
3011typedef struct _ATOM_FIRMWARE_INFO_V1_3
3012{
3013 ATOM_COMMON_TABLE_HEADER sHeader;
3014 ULONG ulFirmwareRevision;
3015 ULONG ulDefaultEngineClock; //In 10Khz unit
3016 ULONG ulDefaultMemoryClock; //In 10Khz unit
3017 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3018 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3019 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3020 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3021 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3022 ULONG ulASICMaxEngineClock; //In 10Khz unit
3023 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3024 UCHAR ucASICMaxTemperature;
3025 UCHAR ucMinAllowedBL_Level;
3026 UCHAR ucPadding[2]; //Don't use them
3027 ULONG aulReservedForBIOS; //Don't use them
3028 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3029 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3030 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3031 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3032 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3033 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3034 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3035 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3036 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3037 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3038 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3039 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3040 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3041 USHORT usReferenceClock; //In 10Khz unit
3042 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3043 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3044 UCHAR ucDesign_ID; //Indicate what is the board design
3045 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3046}ATOM_FIRMWARE_INFO_V1_3;
3047
3048typedef struct _ATOM_FIRMWARE_INFO_V1_4
3049{
3050 ATOM_COMMON_TABLE_HEADER sHeader;
3051 ULONG ulFirmwareRevision;
3052 ULONG ulDefaultEngineClock; //In 10Khz unit
3053 ULONG ulDefaultMemoryClock; //In 10Khz unit
3054 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3055 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3056 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3057 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3058 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3059 ULONG ulASICMaxEngineClock; //In 10Khz unit
3060 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3061 UCHAR ucASICMaxTemperature;
3062 UCHAR ucMinAllowedBL_Level;
3063 USHORT usBootUpVDDCVoltage; //In MV unit
3064 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
3065 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
3066 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3067 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3068 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3069 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3070 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3071 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3072 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3073 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3074 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3075 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3076 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3077 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3078 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3079 USHORT usReferenceClock; //In 10Khz unit
3080 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
3081 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3082 UCHAR ucDesign_ID; //Indicate what is the board design
3083 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3084}ATOM_FIRMWARE_INFO_V1_4;
3085
3086//the structure below to be used from Cypress
3087typedef struct _ATOM_FIRMWARE_INFO_V2_1
3088{
3089 ATOM_COMMON_TABLE_HEADER sHeader;
3090 ULONG ulFirmwareRevision;
3091 ULONG ulDefaultEngineClock; //In 10Khz unit
3092 ULONG ulDefaultMemoryClock; //In 10Khz unit
3093 ULONG ulReserved1;
3094 ULONG ulReserved2;
3095 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3096 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3097 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3098 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
3099 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
3100 UCHAR ucReserved1; //Was ucASICMaxTemperature;
3101 UCHAR ucMinAllowedBL_Level;
3102 USHORT usBootUpVDDCVoltage; //In MV unit
3103 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
3104 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
3105 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3106 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3107 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
3108 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
3109 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
3110 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
3111 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
3112 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
3113 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
3114 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3115 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3116 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
3117 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3118 USHORT usCoreReferenceClock; //In 10Khz unit
3119 USHORT usMemoryReferenceClock; //In 10Khz unit
3120 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
3121 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3122 UCHAR ucReserved4[3];
3123
3124}ATOM_FIRMWARE_INFO_V2_1;
3125
3126//the structure below to be used from NI
3127//ucTableFormatRevision=2
3128//ucTableContentRevision=2
3129
3130typedef struct _PRODUCT_BRANDING
3131{
3132 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level
3133 UCHAR ucReserved:2; // Bit[3:2] Reserved
3134 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID
3135}PRODUCT_BRANDING;
3136
3137typedef struct _ATOM_FIRMWARE_INFO_V2_2
3138{
3139 ATOM_COMMON_TABLE_HEADER sHeader;
3140 ULONG ulFirmwareRevision;
3141 ULONG ulDefaultEngineClock; //In 10Khz unit
3142 ULONG ulDefaultMemoryClock; //In 10Khz unit
3143 ULONG ulSPLL_OutputFreq; //In 10Khz unit
3144 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
3145 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
3146 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
3147 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3148 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
3149 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
3150 UCHAR ucReserved3; //Was ucASICMaxTemperature;
3151 UCHAR ucMinAllowedBL_Level;
3152 USHORT usBootUpVDDCVoltage; //In MV unit
3153 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
3154 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
3155 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3156 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3157 UCHAR ucRemoteDisplayConfig;
3158 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
3159 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
3160 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
3161 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC
3162 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
3163 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
3164 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
3165 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
3166 USHORT usCoreReferenceClock; //In 10Khz unit
3167 USHORT usMemoryReferenceClock; //In 10Khz unit
3168 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
3169 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3170 UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION]
3171 PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level.
3172 UCHAR ucReserved9;
3173 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output;
3174 USHORT usBootUpVDDGFXVoltage; //In unit of mv;
3175 ULONG ulReserved10[3]; // New added comparing to previous version
3176}ATOM_FIRMWARE_INFO_V2_2;
3177
3178#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2
3179
3180
3181// definition of ucRemoteDisplayConfig
3182#define REMOTE_DISPLAY_DISABLE 0x00
3183#define REMOTE_DISPLAY_ENABLE 0x01
3184
3185/****************************************************************************/
3186// Structures used in IntegratedSystemInfoTable
3187/****************************************************************************/
3188#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2
3189#define IGP_CAP_FLAG_AC_CARD 0x4
3190#define IGP_CAP_FLAG_SDVO_CARD 0x8
3191#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10
3192
3193typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
3194{
3195 ATOM_COMMON_TABLE_HEADER sHeader;
3196 ULONG ulBootUpEngineClock; //in 10kHz unit
3197 ULONG ulBootUpMemoryClock; //in 10kHz unit
3198 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
3199 ULONG ulMinSystemMemoryClock; //in 10kHz unit
3200 UCHAR ucNumberOfCyclesInPeriodHi;
3201 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
3202 USHORT usReserved1;
3203 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage
3204 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage
3205 ULONG ulReserved[2];
3206
3207 USHORT usFSBClock; //In MHz unit
3208 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
3209 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
3210 //Bit[4]==1: P/2 mode, ==0: P/1 mode
3211 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
3212 USHORT usK8MemoryClock; //in MHz unit
3213 USHORT usK8SyncStartDelay; //in 0.01 us unit
3214 USHORT usK8DataReturnTime; //in 0.01 us unit
3215 UCHAR ucMaxNBVoltage;
3216 UCHAR ucMinNBVoltage;
3217 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
3218 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
3219 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
3220 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
3221 UCHAR ucMaxNBVoltageHigh;
3222 UCHAR ucMinNBVoltageHigh;
3223}ATOM_INTEGRATED_SYSTEM_INFO;
3224
3225/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
3226ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock
3227 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
3228ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
3229 For AMD IGP,for now this can be 0
3230ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
3231 For AMD IGP,for now this can be 0
3232
3233usFSBClock: For Intel IGP,it's FSB Freq
3234 For AMD IGP,it's HT Link Speed
3235
3236usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200
3237usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation
3238usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation
3239
3240VC:Voltage Control
3241ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
3242ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
3243
3244ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
3245ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
3246
3247ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
3248ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
3249
3250
3251usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
3252usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
3253*/
3254
3255
3256/*
3257The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
3258Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
3259The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
3260
3261SW components can access the IGP system infor structure in the same way as before
3262*/
3263
3264
3265typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
3266{
3267 ATOM_COMMON_TABLE_HEADER sHeader;
3268 ULONG ulBootUpEngineClock; //in 10kHz unit
3269 ULONG ulReserved1[2]; //must be 0x0 for the reserved
3270 ULONG ulBootUpUMAClock; //in 10kHz unit
3271 ULONG ulBootUpSidePortClock; //in 10kHz unit
3272 ULONG ulMinSidePortClock; //in 10kHz unit
3273 ULONG ulReserved2[6]; //must be 0x0 for the reserved
3274 ULONG ulSystemConfig; //see explanation below
3275 ULONG ulBootUpReqDisplayVector;
3276 ULONG ulOtherDisplayMisc;
3277 ULONG ulDDISlot1Config;
3278 ULONG ulDDISlot2Config;
3279 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3280 UCHAR ucUMAChannelNumber;
3281 UCHAR ucDockingPinBit;
3282 UCHAR ucDockingPinPolarity;
3283 ULONG ulDockingPinCFGInfo;
3284 ULONG ulCPUCapInfo;
3285 USHORT usNumberOfCyclesInPeriod;
3286 USHORT usMaxNBVoltage;
3287 USHORT usMinNBVoltage;
3288 USHORT usBootUpNBVoltage;
3289 ULONG ulHTLinkFreq; //in 10Khz
3290 USHORT usMinHTLinkWidth;
3291 USHORT usMaxHTLinkWidth;
3292 USHORT usUMASyncStartDelay;
3293 USHORT usUMADataReturnTime;
3294 USHORT usLinkStatusZeroTime;
3295 USHORT usDACEfuse; //for storing badgap value (for RS880 only)
3296 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
3297 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
3298 USHORT usMaxUpStreamHTLinkWidth;
3299 USHORT usMaxDownStreamHTLinkWidth;
3300 USHORT usMinUpStreamHTLinkWidth;
3301 USHORT usMinDownStreamHTLinkWidth;
3302 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
3303 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
3304 ULONG ulReserved3[96]; //must be 0x0
3305}ATOM_INTEGRATED_SYSTEM_INFO_V2;
3306
3307/*
3308ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
3309ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
3310ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
3311
3312ulSystemConfig:
3313Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
3314Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
3315 =0: system boots up at driver control state. Power state depends on PowerPlay table.
3316Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
3317Bit[3]=1: Only one power state(Performance) will be supported.
3318 =0: Multiple power states supported from PowerPlay table.
3319Bit[4]=1: CLMC is supported and enabled on current system.
3320 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
3321Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
3322 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
3323Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
3324 =0: Voltage settings is determined by powerplay table.
3325Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
3326 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
3327Bit[8]=1: CDLF is supported and enabled on current system.
3328 =0: CDLF is not supported or enabled on current system.
3329Bit[9]=1: DLL Shut Down feature is enabled on current system.
3330 =0: DLL Shut Down feature is not enabled or supported on current system.
3331
3332ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
3333
3334ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
3335 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
3336
3337ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
3338 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
3339 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
3340 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
3341 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
3342 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
3343
3344 [15:8] - Lane configuration attribute;
3345 [23:16]- Connector type, possible value:
3346 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
3347 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
3348 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
3349 CONNECTOR_OBJECT_ID_DISPLAYPORT
3350 CONNECTOR_OBJECT_ID_eDP
3351 [31:24]- Reserved
3352
3353ulDDISlot2Config: Same as Slot1.
3354ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
3355For IGP, Hypermemory is the only memory type showed in CCC.
3356
3357ucUMAChannelNumber: how many channels for the UMA;
3358
3359ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
3360ucDockingPinBit: which bit in this register to read the pin status;
3361ucDockingPinPolarity:Polarity of the pin when docked;
3362
3363ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
3364
3365usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
3366
3367usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
3368usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
3369 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
3370 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
3371 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
3372
3373usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3374
3375
3376ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
3377usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
3378 If CDLW enabled, both upstream and downstream width should be the same during bootup.
3379usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
3380 If CDLW enabled, both upstream and downstream width should be the same during bootup.
3381
3382usUMASyncStartDelay: Memory access latency, required for watermark calculation
3383usUMADataReturnTime: Memory access latency, required for watermark calculation
3384usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
3385for Griffin or Greyhound. SBIOS needs to convert to actual time by:
3386 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
3387 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
3388 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
3389 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
3390
3391ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
3392 This must be less than or equal to ulHTLinkFreq(bootup frequency).
3393ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
3394 This must be less than or equal to ulHighVoltageHTLinkFreq.
3395
3396usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
3397usMaxDownStreamHTLinkWidth: same as above.
3398usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
3399usMinDownStreamHTLinkWidth: same as above.
3400*/
3401
3402// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3403#define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0
3404#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
3405#define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2
3406#define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3
3407#define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4
3408#define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5
3409
3410#define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code
3411
3412#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001
3413#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002
3414#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004
3415#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008
3416#define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010
3417#define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020
3418#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040
3419#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080
3420#define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100
3421#define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200
3422
3423#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF
3424
3425#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F
3426#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0
3427#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01
3428#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02
3429#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04
3430#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08
3431
3432#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00
3433#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100
3434#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01
3435
3436#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000
3437
3438// IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
3439typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
3440{
3441 ATOM_COMMON_TABLE_HEADER sHeader;
3442 ULONG ulBootUpEngineClock; //in 10kHz unit
3443 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
3444 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
3445 ULONG ulBootUpUMAClock; //in 10kHz unit
3446 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3447 ULONG ulBootUpReqDisplayVector;
3448 ULONG ulOtherDisplayMisc;
3449 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3450 ULONG ulSystemConfig; //TBD
3451 ULONG ulCPUCapInfo; //TBD
3452 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3453 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3454 USHORT usBootUpNBVoltage; //boot up NB voltage
3455 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
3456 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
3457 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3458 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
3459 ULONG ulDDISlot2Config;
3460 ULONG ulDDISlot3Config;
3461 ULONG ulDDISlot4Config;
3462 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3463 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3464 UCHAR ucUMAChannelNumber;
3465 USHORT usReserved;
3466 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3467 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
3468 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
3469 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
3470 ULONG ulReserved6[61]; //must be 0x0
3471}ATOM_INTEGRATED_SYSTEM_INFO_V5;
3472
3473
3474
3475/****************************************************************************/
3476// Structure used in GPUVirtualizationInfoTable
3477/****************************************************************************/
3478typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1
3479{
3480 ATOM_COMMON_TABLE_HEADER sHeader;
3481 ULONG ulMCUcodeRomStartAddr;
3482 ULONG ulMCUcodeLength;
3483 ULONG ulSMCUcodeRomStartAddr;
3484 ULONG ulSMCUcodeLength;
3485 ULONG ulRLCVUcodeRomStartAddr;
3486 ULONG ulRLCVUcodeLength;
3487 ULONG ulTOCUcodeStartAddr;
3488 ULONG ulTOCUcodeLength;
3489 ULONG ulSMCPatchTableStartAddr;
3490 ULONG ulSmcPatchTableLength;
3491 ULONG ulSystemFlag;
3492}ATOM_GPU_VIRTUALIZATION_INFO_V2_1;
3493
3494
3495#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000
3496#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001
3497#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002
3498#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003
3499#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004
3500#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005
3501#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006
3502#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007
3503#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008
3504#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009
3505#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A
3506#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B
3507#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C
3508#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D
3509
3510// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
3511#define ASIC_INT_DAC1_ENCODER_ID 0x00
3512#define ASIC_INT_TV_ENCODER_ID 0x02
3513#define ASIC_INT_DIG1_ENCODER_ID 0x03
3514#define ASIC_INT_DAC2_ENCODER_ID 0x04
3515#define ASIC_EXT_TV_ENCODER_ID 0x06
3516#define ASIC_INT_DVO_ENCODER_ID 0x07
3517#define ASIC_INT_DIG2_ENCODER_ID 0x09
3518#define ASIC_EXT_DIG_ENCODER_ID 0x05
3519#define ASIC_EXT_DIG2_ENCODER_ID 0x08
3520#define ASIC_INT_DIG3_ENCODER_ID 0x0a
3521#define ASIC_INT_DIG4_ENCODER_ID 0x0b
3522#define ASIC_INT_DIG5_ENCODER_ID 0x0c
3523#define ASIC_INT_DIG6_ENCODER_ID 0x0d
3524#define ASIC_INT_DIG7_ENCODER_ID 0x0e
3525
3526//define Encoder attribute
3527#define ATOM_ANALOG_ENCODER 0
3528#define ATOM_DIGITAL_ENCODER 1
3529#define ATOM_DP_ENCODER 2
3530
3531#define ATOM_ENCODER_ENUM_MASK 0x70
3532#define ATOM_ENCODER_ENUM_ID1 0x00
3533#define ATOM_ENCODER_ENUM_ID2 0x10
3534#define ATOM_ENCODER_ENUM_ID3 0x20
3535#define ATOM_ENCODER_ENUM_ID4 0x30
3536#define ATOM_ENCODER_ENUM_ID5 0x40
3537#define ATOM_ENCODER_ENUM_ID6 0x50
3538
3539#define ATOM_DEVICE_CRT1_INDEX 0x00000000
3540#define ATOM_DEVICE_LCD1_INDEX 0x00000001
3541#define ATOM_DEVICE_TV1_INDEX 0x00000002
3542#define ATOM_DEVICE_DFP1_INDEX 0x00000003
3543#define ATOM_DEVICE_CRT2_INDEX 0x00000004
3544#define ATOM_DEVICE_LCD2_INDEX 0x00000005
3545#define ATOM_DEVICE_DFP6_INDEX 0x00000006
3546#define ATOM_DEVICE_DFP2_INDEX 0x00000007
3547#define ATOM_DEVICE_CV_INDEX 0x00000008
3548#define ATOM_DEVICE_DFP3_INDEX 0x00000009
3549#define ATOM_DEVICE_DFP4_INDEX 0x0000000A
3550#define ATOM_DEVICE_DFP5_INDEX 0x0000000B
3551
3552#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C
3553#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D
3554#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E
3555#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F
3556#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
3557#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO
3558#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
3559
3560#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
3561
3562#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX )
3563#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX )
3564#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX )
3565#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX )
3566#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX )
3567#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX )
3568#define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX )
3569#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX )
3570#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX )
3571#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX )
3572#define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX )
3573#define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX )
3574
3575
3576#define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
3577#define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
3578#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT
3579#define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
3580
3581#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0
3582#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004
3583#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001
3584#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002
3585#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003
3586#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004
3587#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005
3588#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006
3589#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007
3590#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008
3591#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009
3592#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A
3593#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B
3594#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E
3595#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F
3596
3597
3598#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F
3599#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000
3600#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000
3601#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001
3602#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002
3603#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003
3604
3605#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000
3606
3607#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F
3608#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000
3609
3610#define ATOM_DEVICE_I2C_ID_MASK 0x00000070
3611#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004
3612#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001
3613#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002
3614#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600
3615#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690
3616
3617#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080
3618#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007
3619#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000
3620#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001
3621
3622// usDeviceSupport:
3623// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3624// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3625// Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3626// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3627// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3628// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3629// Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3630// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3631// Bit 8 = 0 - no CV support= 1- CV is supported
3632// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3633// Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3634// Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3635//
3636//
3637
3638/****************************************************************************/
3639// Structure used in MclkSS_InfoTable
3640/****************************************************************************/
3641// ucI2C_ConfigID
3642// [7:0] - I2C LINE Associate ID
3643// = 0 - no I2C
3644// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3645// = 0, [6:0]=SW assisted I2C ID
3646// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3647// = 2, HW engine for Multimedia use
3648// = 3-7 Reserved for future I2C engines
3649// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3650
3651typedef struct _ATOM_I2C_ID_CONFIG
3652{
3653#if ATOM_BIG_ENDIAN
3654 UCHAR bfHW_Capable:1;
3655 UCHAR bfHW_EngineID:3;
3656 UCHAR bfI2C_LineMux:4;
3657#else
3658 UCHAR bfI2C_LineMux:4;
3659 UCHAR bfHW_EngineID:3;
3660 UCHAR bfHW_Capable:1;
3661#endif
3662}ATOM_I2C_ID_CONFIG;
3663
3664typedef union _ATOM_I2C_ID_CONFIG_ACCESS
3665{
3666 ATOM_I2C_ID_CONFIG sbfAccess;
3667 UCHAR ucAccess;
3668}ATOM_I2C_ID_CONFIG_ACCESS;
3669
3670
3671/****************************************************************************/
3672// Structure used in GPIO_I2C_InfoTable
3673/****************************************************************************/
3674typedef struct _ATOM_GPIO_I2C_ASSIGMENT
3675{
3676 USHORT usClkMaskRegisterIndex;
3677 USHORT usClkEnRegisterIndex;
3678 USHORT usClkY_RegisterIndex;
3679 USHORT usClkA_RegisterIndex;
3680 USHORT usDataMaskRegisterIndex;
3681 USHORT usDataEnRegisterIndex;
3682 USHORT usDataY_RegisterIndex;
3683 USHORT usDataA_RegisterIndex;
3684 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
3685 UCHAR ucClkMaskShift;
3686 UCHAR ucClkEnShift;
3687 UCHAR ucClkY_Shift;
3688 UCHAR ucClkA_Shift;
3689 UCHAR ucDataMaskShift;
3690 UCHAR ucDataEnShift;
3691 UCHAR ucDataY_Shift;
3692 UCHAR ucDataA_Shift;
3693 UCHAR ucReserved1;
3694 UCHAR ucReserved2;
3695}ATOM_GPIO_I2C_ASSIGMENT;
3696
3697typedef struct _ATOM_GPIO_I2C_INFO
3698{
3699 ATOM_COMMON_TABLE_HEADER sHeader;
3700 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
3701}ATOM_GPIO_I2C_INFO;
3702
3703/****************************************************************************/
3704// Common Structure used in other structures
3705/****************************************************************************/
3706
3707#ifndef _H2INC
3708
3709//Please don't add or expand this bitfield structure below, this one will retire soon.!
3710typedef struct _ATOM_MODE_MISC_INFO
3711{
3712#if ATOM_BIG_ENDIAN
3713 USHORT Reserved:6;
3714 USHORT RGB888:1;
3715 USHORT DoubleClock:1;
3716 USHORT Interlace:1;
3717 USHORT CompositeSync:1;
3718 USHORT V_ReplicationBy2:1;
3719 USHORT H_ReplicationBy2:1;
3720 USHORT VerticalCutOff:1;
3721 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3722 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3723 USHORT HorizontalCutOff:1;
3724#else
3725 USHORT HorizontalCutOff:1;
3726 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3727 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3728 USHORT VerticalCutOff:1;
3729 USHORT H_ReplicationBy2:1;
3730 USHORT V_ReplicationBy2:1;
3731 USHORT CompositeSync:1;
3732 USHORT Interlace:1;
3733 USHORT DoubleClock:1;
3734 USHORT RGB888:1;
3735 USHORT Reserved:6;
3736#endif
3737}ATOM_MODE_MISC_INFO;
3738
3739typedef union _ATOM_MODE_MISC_INFO_ACCESS
3740{
3741 ATOM_MODE_MISC_INFO sbfAccess;
3742 USHORT usAccess;
3743}ATOM_MODE_MISC_INFO_ACCESS;
3744
3745#else
3746
3747typedef union _ATOM_MODE_MISC_INFO_ACCESS
3748{
3749 USHORT usAccess;
3750}ATOM_MODE_MISC_INFO_ACCESS;
3751
3752#endif
3753
3754// usModeMiscInfo-
3755#define ATOM_H_CUTOFF 0x01
3756#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
3757#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
3758#define ATOM_V_CUTOFF 0x08
3759#define ATOM_H_REPLICATIONBY2 0x10
3760#define ATOM_V_REPLICATIONBY2 0x20
3761#define ATOM_COMPOSITESYNC 0x40
3762#define ATOM_INTERLACE 0x80
3763#define ATOM_DOUBLE_CLOCK_MODE 0x100
3764#define ATOM_RGB888_MODE 0x200
3765
3766//usRefreshRate-
3767#define ATOM_REFRESH_43 43
3768#define ATOM_REFRESH_47 47
3769#define ATOM_REFRESH_56 56
3770#define ATOM_REFRESH_60 60
3771#define ATOM_REFRESH_65 65
3772#define ATOM_REFRESH_70 70
3773#define ATOM_REFRESH_72 72
3774#define ATOM_REFRESH_75 75
3775#define ATOM_REFRESH_85 85
3776
3777// ATOM_MODE_TIMING data are exactly the same as VESA timing data.
3778// Translation from EDID to ATOM_MODE_TIMING, use the following formula.
3779//
3780// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3781// = EDID_HA + EDID_HBL
3782// VESA_HDISP = VESA_ACTIVE = EDID_HA
3783// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
3784// = EDID_HA + EDID_HSO
3785// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW
3786// VESA_BORDER = EDID_BORDER
3787
3788
3789/****************************************************************************/
3790// Structure used in SetCRTC_UsingDTDTimingTable
3791/****************************************************************************/
3792typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
3793{
3794 USHORT usH_Size;
3795 USHORT usH_Blanking_Time;
3796 USHORT usV_Size;
3797 USHORT usV_Blanking_Time;
3798 USHORT usH_SyncOffset;
3799 USHORT usH_SyncWidth;
3800 USHORT usV_SyncOffset;
3801 USHORT usV_SyncWidth;
3802 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3803 UCHAR ucH_Border; // From DFP EDID
3804 UCHAR ucV_Border;
3805 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3806 UCHAR ucPadding[3];
3807}SET_CRTC_USING_DTD_TIMING_PARAMETERS;
3808
3809/****************************************************************************/
3810// Structure used in SetCRTC_TimingTable
3811/****************************************************************************/
3812typedef struct _SET_CRTC_TIMING_PARAMETERS
3813{
3814 USHORT usH_Total; // horizontal total
3815 USHORT usH_Disp; // horizontal display
3816 USHORT usH_SyncStart; // horozontal Sync start
3817 USHORT usH_SyncWidth; // horizontal Sync width
3818 USHORT usV_Total; // vertical total
3819 USHORT usV_Disp; // vertical display
3820 USHORT usV_SyncStart; // vertical Sync start
3821 USHORT usV_SyncWidth; // vertical Sync width
3822 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3823 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3824 UCHAR ucOverscanRight; // right
3825 UCHAR ucOverscanLeft; // left
3826 UCHAR ucOverscanBottom; // bottom
3827 UCHAR ucOverscanTop; // top
3828 UCHAR ucReserved;
3829}SET_CRTC_TIMING_PARAMETERS;
3830#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
3831
3832
3833/****************************************************************************/
3834// Structure used in StandardVESA_TimingTable
3835// AnalogTV_InfoTable
3836// ComponentVideoInfoTable
3837/****************************************************************************/
3838typedef struct _ATOM_MODE_TIMING
3839{
3840 USHORT usCRTC_H_Total;
3841 USHORT usCRTC_H_Disp;
3842 USHORT usCRTC_H_SyncStart;
3843 USHORT usCRTC_H_SyncWidth;
3844 USHORT usCRTC_V_Total;
3845 USHORT usCRTC_V_Disp;
3846 USHORT usCRTC_V_SyncStart;
3847 USHORT usCRTC_V_SyncWidth;
3848 USHORT usPixelClock; //in 10Khz unit
3849 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3850 USHORT usCRTC_OverscanRight;
3851 USHORT usCRTC_OverscanLeft;
3852 USHORT usCRTC_OverscanBottom;
3853 USHORT usCRTC_OverscanTop;
3854 USHORT usReserve;
3855 UCHAR ucInternalModeNumber;
3856 UCHAR ucRefreshRate;
3857}ATOM_MODE_TIMING;
3858
3859typedef struct _ATOM_DTD_FORMAT
3860{
3861 USHORT usPixClk;
3862 USHORT usHActive;
3863 USHORT usHBlanking_Time;
3864 USHORT usVActive;
3865 USHORT usVBlanking_Time;
3866 USHORT usHSyncOffset;
3867 USHORT usHSyncWidth;
3868 USHORT usVSyncOffset;
3869 USHORT usVSyncWidth;
3870 USHORT usImageHSize;
3871 USHORT usImageVSize;
3872 UCHAR ucHBorder;
3873 UCHAR ucVBorder;
3874 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3875 UCHAR ucInternalModeNumber;
3876 UCHAR ucRefreshRate;
3877}ATOM_DTD_FORMAT;
3878
3879/****************************************************************************/
3880// Structure used in LVDS_InfoTable
3881// * Need a document to describe this table
3882/****************************************************************************/
3883#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
3884#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
3885#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
3886#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
3887#define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040
3888
3889//ucTableFormatRevision=1
3890//ucTableContentRevision=1
3891typedef struct _ATOM_LVDS_INFO
3892{
3893 ATOM_COMMON_TABLE_HEADER sHeader;
3894 ATOM_DTD_FORMAT sLCDTiming;
3895 USHORT usModePatchTableOffset;
3896 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3897 USHORT usOffDelayInMs;
3898 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3899 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3900 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3901 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3902 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3903 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3904 UCHAR ucPanelDefaultRefreshRate;
3905 UCHAR ucPanelIdentification;
3906 UCHAR ucSS_Id;
3907}ATOM_LVDS_INFO;
3908
3909//ucTableFormatRevision=1
3910//ucTableContentRevision=2
3911typedef struct _ATOM_LVDS_INFO_V12
3912{
3913 ATOM_COMMON_TABLE_HEADER sHeader;
3914 ATOM_DTD_FORMAT sLCDTiming;
3915 USHORT usExtInfoTableOffset;
3916 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec.
3917 USHORT usOffDelayInMs;
3918 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3919 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3920 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3921 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3922 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3923 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3924 UCHAR ucPanelDefaultRefreshRate;
3925 UCHAR ucPanelIdentification;
3926 UCHAR ucSS_Id;
3927 USHORT usLCDVenderID;
3928 USHORT usLCDProductID;
3929 UCHAR ucLCDPanel_SpecialHandlingCap;
3930 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3931 UCHAR ucReserved[2];
3932}ATOM_LVDS_INFO_V12;
3933
3934//Definitions for ucLCDPanel_SpecialHandlingCap:
3935
3936//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3937//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3938#define LCDPANEL_CAP_READ_EDID 0x1
3939
3940//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3941//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3942//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3943#define LCDPANEL_CAP_DRR_SUPPORTED 0x2
3944
3945//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3946#define LCDPANEL_CAP_eDP 0x4
3947
3948
3949//Color Bit Depth definition in EDID V1.4 @BYTE 14h
3950//Bit 6 5 4
3951 // 0 0 0 - Color bit depth is undefined
3952 // 0 0 1 - 6 Bits per Primary Color
3953 // 0 1 0 - 8 Bits per Primary Color
3954 // 0 1 1 - 10 Bits per Primary Color
3955 // 1 0 0 - 12 Bits per Primary Color
3956 // 1 0 1 - 14 Bits per Primary Color
3957 // 1 1 0 - 16 Bits per Primary Color
3958 // 1 1 1 - Reserved
3959
3960#define PANEL_COLOR_BIT_DEPTH_MASK 0x70
3961
3962// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3963#define PANEL_RANDOM_DITHER 0x80
3964#define PANEL_RANDOM_DITHER_MASK 0x80
3965
3966#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this
3967
3968
3969typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT
3970{
3971 UCHAR ucSupportedRefreshRate;
3972 UCHAR ucMinRefreshRateForDRR;
3973}ATOM_LCD_REFRESH_RATE_SUPPORT;
3974
3975/****************************************************************************/
3976// Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12
3977// ASIC Families: NI
3978// ucTableFormatRevision=1
3979// ucTableContentRevision=3
3980/****************************************************************************/
3981typedef struct _ATOM_LCD_INFO_V13
3982{
3983 ATOM_COMMON_TABLE_HEADER sHeader;
3984 ATOM_DTD_FORMAT sLCDTiming;
3985 USHORT usExtInfoTableOffset;
3986 union
3987 {
3988 USHORT usSupportedRefreshRate;
3989 ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport;
3990 };
3991 ULONG ulReserved0;
3992 UCHAR ucLCD_Misc; // Reorganized in V13
3993 // Bit0: {=0:single, =1:dual},
3994 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
3995 // Bit3:2: {Grey level}
3996 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3997 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it?
3998 UCHAR ucPanelDefaultRefreshRate;
3999 UCHAR ucPanelIdentification;
4000 UCHAR ucSS_Id;
4001 USHORT usLCDVenderID;
4002 USHORT usLCDProductID;
4003 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
4004 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
4005 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
4006 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
4007 // Bit7-3: Reserved
4008 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
4009 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13
4010
4011 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
4012 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
4013 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
4014 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
4015
4016 UCHAR ucOffDelay_in4Ms;
4017 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
4018 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
4019 UCHAR ucReserved1;
4020
4021 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
4022 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
4023 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
4024 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
4025
4026 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode.
4027 UCHAR uceDPToLVDSRxId;
4028 UCHAR ucLcdReservd;
4029 ULONG ulReserved[2];
4030}ATOM_LCD_INFO_V13;
4031
4032#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13
4033
4034//Definitions for ucLCD_Misc
4035#define ATOM_PANEL_MISC_V13_DUAL 0x00000001
4036#define ATOM_PANEL_MISC_V13_FPDI 0x00000002
4037#define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C
4038#define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2
4039#define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70
4040#define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10
4041#define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20
4042
4043//Color Bit Depth definition in EDID V1.4 @BYTE 14h
4044//Bit 6 5 4
4045 // 0 0 0 - Color bit depth is undefined
4046 // 0 0 1 - 6 Bits per Primary Color
4047 // 0 1 0 - 8 Bits per Primary Color
4048 // 0 1 1 - 10 Bits per Primary Color
4049 // 1 0 0 - 12 Bits per Primary Color
4050 // 1 0 1 - 14 Bits per Primary Color
4051 // 1 1 0 - 16 Bits per Primary Color
4052 // 1 1 1 - Reserved
4053
4054//Definitions for ucLCDPanel_SpecialHandlingCap:
4055
4056//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
4057//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
4058#define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
4059
4060//If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
4061//with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
4062//refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
4063#define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
4064
4065//Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
4066#define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version
4067
4068//uceDPToLVDSRxId
4069#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
4070#define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init
4071#define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init
4072
4073typedef struct _ATOM_PATCH_RECORD_MODE
4074{
4075 UCHAR ucRecordType;
4076 USHORT usHDisp;
4077 USHORT usVDisp;
4078}ATOM_PATCH_RECORD_MODE;
4079
4080typedef struct _ATOM_LCD_RTS_RECORD
4081{
4082 UCHAR ucRecordType;
4083 UCHAR ucRTSValue;
4084}ATOM_LCD_RTS_RECORD;
4085
4086//!! If the record below exits, it shoud always be the first record for easy use in command table!!!
4087// The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
4088typedef struct _ATOM_LCD_MODE_CONTROL_CAP
4089{
4090 UCHAR ucRecordType;
4091 USHORT usLCDCap;
4092}ATOM_LCD_MODE_CONTROL_CAP;
4093
4094#define LCD_MODE_CAP_BL_OFF 1
4095#define LCD_MODE_CAP_CRTC_OFF 2
4096#define LCD_MODE_CAP_PANEL_OFF 4
4097
4098
4099typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
4100{
4101 UCHAR ucRecordType;
4102 UCHAR ucFakeEDIDLength; // = 128 means EDID lenght is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128
4103 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
4104} ATOM_FAKE_EDID_PATCH_RECORD;
4105
4106typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD
4107{
4108 UCHAR ucRecordType;
4109 USHORT usHSize;
4110 USHORT usVSize;
4111}ATOM_PANEL_RESOLUTION_PATCH_RECORD;
4112
4113#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
4114#define LCD_RTS_RECORD_TYPE 2
4115#define LCD_CAP_RECORD_TYPE 3
4116#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4
4117#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5
4118#define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6
4119#define ATOM_RECORD_END_TYPE 0xFF
4120
4121/****************************Spread Spectrum Info Table Definitions **********************/
4122
4123//ucTableFormatRevision=1
4124//ucTableContentRevision=2
4125typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
4126{
4127 USHORT usSpreadSpectrumPercentage;
4128 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
4129 UCHAR ucSS_Step;
4130 UCHAR ucSS_Delay;
4131 UCHAR ucSS_Id;
4132 UCHAR ucRecommendedRef_Div;
4133 UCHAR ucSS_Range; //it was reserved for V11
4134}ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
4135
4136#define ATOM_MAX_SS_ENTRY 16
4137#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
4138#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
4139#define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz
4140#define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz
4141
4142
4143
4144#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
4145#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
4146#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
4147#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
4148#define ATOM_INTERNAL_SS_MASK 0x00000000
4149#define ATOM_EXTERNAL_SS_MASK 0x00000002
4150#define EXEC_SS_STEP_SIZE_SHIFT 2
4151#define EXEC_SS_DELAY_SHIFT 4
4152#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4
4153
4154typedef struct _ATOM_SPREAD_SPECTRUM_INFO
4155{
4156 ATOM_COMMON_TABLE_HEADER sHeader;
4157 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
4158}ATOM_SPREAD_SPECTRUM_INFO;
4159
4160
4161/****************************************************************************/
4162// Structure used in AnalogTV_InfoTable (Top level)
4163/****************************************************************************/
4164//ucTVBootUpDefaultStd definiton:
4165
4166//ATOM_TV_NTSC 1
4167//ATOM_TV_NTSCJ 2
4168//ATOM_TV_PAL 3
4169//ATOM_TV_PALM 4
4170//ATOM_TV_PALCN 5
4171//ATOM_TV_PALN 6
4172//ATOM_TV_PAL60 7
4173//ATOM_TV_SECAM 8
4174
4175//ucTVSuppportedStd definition:
4176#define NTSC_SUPPORT 0x1
4177#define NTSCJ_SUPPORT 0x2
4178
4179#define PAL_SUPPORT 0x4
4180#define PALM_SUPPORT 0x8
4181#define PALCN_SUPPORT 0x10
4182#define PALN_SUPPORT 0x20
4183#define PAL60_SUPPORT 0x40
4184#define SECAM_SUPPORT 0x80
4185
4186#define MAX_SUPPORTED_TV_TIMING 2
4187
4188typedef struct _ATOM_ANALOG_TV_INFO
4189{
4190 ATOM_COMMON_TABLE_HEADER sHeader;
4191 UCHAR ucTV_SuppportedStandard;
4192 UCHAR ucTV_BootUpDefaultStandard;
4193 UCHAR ucExt_TV_ASIC_ID;
4194 UCHAR ucExt_TV_ASIC_SlaveAddr;
4195 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];
4196}ATOM_ANALOG_TV_INFO;
4197
4198typedef struct _ATOM_DPCD_INFO
4199{
4200 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
4201 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
4202 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
4203 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
4204}ATOM_DPCD_INFO;
4205
4206#define ATOM_DPCD_MAX_LANE_MASK 0x1F
4207
4208/**************************************************************************/
4209// VRAM usage and their defintions
4210
4211// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
4212// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
4213// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
4214// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
4215// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
4216
4217// Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU).
4218//#ifndef VESA_MEMORY_IN_64K_BLOCK
4219//#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!)
4220//#endif
4221
4222#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes
4223#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes
4224#define ATOM_HWICON_INFOTABLE_SIZE 32
4225#define MAX_DTD_MODE_IN_VRAM 6
4226#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT)
4227#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
4228//20 bytes for Encoder Type and DPCD in STD EDID area
4229#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
4230#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 )
4231
4232#define ATOM_HWICON1_SURFACE_ADDR 0
4233#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
4234#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
4235#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
4236#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4237#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4238
4239#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4240#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4241#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4242
4243#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4244
4245#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4246#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4247#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4248
4249#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4250#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4251#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4252
4253#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4254#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4255#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4256
4257#define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4258#define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4259#define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4260
4261#define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4262#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4263#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4264
4265#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4266#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4267#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4268
4269#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4270#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4271#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4272
4273#define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4274#define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4275#define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4276
4277#define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4278#define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
4279#define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
4280
4281#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
4282
4283#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024)
4284#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512
4285
4286//The size below is in Kb!
4287#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
4288
4289#define ATOM_VRAM_RESERVE_V2_SIZE 32
4290
4291#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L
4292#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
4293#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
4294#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
4295#define ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 0x2
4296
4297/***********************************************************************************/
4298// Structure used in VRAM_UsageByFirmwareTable
4299// Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
4300// at running time.
4301// note2: From RV770, the memory is more than 32bit addressable, so we will change
4302// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
4303// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
4304// (in offset to start of memory address) is KB aligned instead of byte aligend.
4305// Note3:
4306/* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged
4307constant across VGA or non VGA adapter,
4308for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have:
4309
4310If (ulStartAddrUsedByFirmware!=0)
4311FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
4312Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
4313else //Non VGA case
4314 if (FB_Size<=2Gb)
4315 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
4316 else
4317 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
4318
4319CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
4320
4321/***********************************************************************************/
4322#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
4323
4324typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
4325{
4326 ULONG ulStartAddrUsedByFirmware;
4327 USHORT usFirmwareUseInKb;
4328 USHORT usReserved;
4329}ATOM_FIRMWARE_VRAM_RESERVE_INFO;
4330
4331typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
4332{
4333 ATOM_COMMON_TABLE_HEADER sHeader;
4334 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
4335}ATOM_VRAM_USAGE_BY_FIRMWARE;
4336
4337// change verion to 1.5, when allow driver to allocate the vram area for command table access.
4338typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
4339{
4340 ULONG ulStartAddrUsedByFirmware;
4341 USHORT usFirmwareUseInKb;
4342 USHORT usFBUsedByDrvInKb;
4343}ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
4344
4345typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
4346{
4347 ATOM_COMMON_TABLE_HEADER sHeader;
4348 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
4349}ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
4350
4351/****************************************************************************/
4352// Structure used in GPIO_Pin_LUTTable
4353/****************************************************************************/
4354typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
4355{
4356 USHORT usGpioPin_AIndex;
4357 UCHAR ucGpioPinBitShift;
4358 UCHAR ucGPIO_ID;
4359}ATOM_GPIO_PIN_ASSIGNMENT;
4360
4361//ucGPIO_ID pre-define id for multiple usage
4362// GPIO use to control PCIE_VDDC in certain SLT board
4363#define PCIE_VDDC_CONTROL_GPIO_PINID 56
4364
4365//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable
4366#define PP_AC_DC_SWITCH_GPIO_PINID 60
4367//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
4368#define VDDC_VRHOT_GPIO_PINID 61
4369//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled
4370#define VDDC_PCC_GPIO_PINID 62
4371// Only used on certain SLT/PA board to allow utility to cut Efuse.
4372#define EFUSE_CUT_ENABLE_GPIO_PINID 63
4373// ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO=
4374#define DRAM_SELF_REFRESH_GPIO_PINID 64
4375// Thermal interrupt output->system thermal chip GPIO pin
4376#define THERMAL_INT_OUTPUT_GPIO_PINID 65
4377
4378
4379typedef struct _ATOM_GPIO_PIN_LUT
4380{
4381 ATOM_COMMON_TABLE_HEADER sHeader;
4382 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
4383}ATOM_GPIO_PIN_LUT;
4384
4385/****************************************************************************/
4386// Structure used in ComponentVideoInfoTable
4387/****************************************************************************/
4388#define GPIO_PIN_ACTIVE_HIGH 0x1
4389#define MAX_SUPPORTED_CV_STANDARDS 5
4390
4391// definitions for ATOM_D_INFO.ucSettings
4392#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0]
4393#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out
4394#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
4395
4396typedef struct _ATOM_GPIO_INFO
4397{
4398 USHORT usAOffset;
4399 UCHAR ucSettings;
4400 UCHAR ucReserved;
4401}ATOM_GPIO_INFO;
4402
4403// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
4404#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2
4405
4406// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
4407#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
4408#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0]
4409
4410// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
4411//Line 3 out put 5V.
4412#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9
4413#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9
4414#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0
4415
4416//Line 3 out put 2.2V
4417#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box
4418#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box
4419#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
4420
4421//Line 3 out put 0V
4422#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3
4423#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3
4424#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4
4425
4426#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0]
4427
4428#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
4429
4430//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
4431#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
4432#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
4433
4434
4435typedef struct _ATOM_COMPONENT_VIDEO_INFO
4436{
4437 ATOM_COMMON_TABLE_HEADER sHeader;
4438 USHORT usMask_PinRegisterIndex;
4439 USHORT usEN_PinRegisterIndex;
4440 USHORT usY_PinRegisterIndex;
4441 USHORT usA_PinRegisterIndex;
4442 UCHAR ucBitShift;
4443 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
4444 ATOM_DTD_FORMAT sReserved; // must be zeroed out
4445 UCHAR ucMiscInfo;
4446 UCHAR uc480i;
4447 UCHAR uc480p;
4448 UCHAR uc720p;
4449 UCHAR uc1080i;
4450 UCHAR ucLetterBoxMode;
4451 UCHAR ucReserved[3];
4452 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4453 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
4454 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
4455}ATOM_COMPONENT_VIDEO_INFO;
4456
4457//ucTableFormatRevision=2
4458//ucTableContentRevision=1
4459typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
4460{
4461 ATOM_COMMON_TABLE_HEADER sHeader;
4462 UCHAR ucMiscInfo;
4463 UCHAR uc480i;
4464 UCHAR uc480p;
4465 UCHAR uc720p;
4466 UCHAR uc1080i;
4467 UCHAR ucReserved;
4468 UCHAR ucLetterBoxMode;
4469 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4470 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
4471 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
4472}ATOM_COMPONENT_VIDEO_INFO_V21;
4473
4474#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21
4475
4476/****************************************************************************/
4477// Structure used in object_InfoTable
4478/****************************************************************************/
4479typedef struct _ATOM_OBJECT_HEADER
4480{
4481 ATOM_COMMON_TABLE_HEADER sHeader;
4482 USHORT usDeviceSupport;
4483 USHORT usConnectorObjectTableOffset;
4484 USHORT usRouterObjectTableOffset;
4485 USHORT usEncoderObjectTableOffset;
4486 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
4487 USHORT usDisplayPathTableOffset;
4488}ATOM_OBJECT_HEADER;
4489
4490typedef struct _ATOM_OBJECT_HEADER_V3
4491{
4492 ATOM_COMMON_TABLE_HEADER sHeader;
4493 USHORT usDeviceSupport;
4494 USHORT usConnectorObjectTableOffset;
4495 USHORT usRouterObjectTableOffset;
4496 USHORT usEncoderObjectTableOffset;
4497 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent.
4498 USHORT usDisplayPathTableOffset;
4499 USHORT usMiscObjectTableOffset;
4500}ATOM_OBJECT_HEADER_V3;
4501
4502
4503typedef struct _ATOM_DISPLAY_OBJECT_PATH
4504{
4505 USHORT usDeviceTag; //supported device
4506 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
4507 USHORT usConnObjectId; //Connector Object ID
4508 USHORT usGPUObjectId; //GPU ID
4509 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
4510}ATOM_DISPLAY_OBJECT_PATH;
4511
4512typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
4513{
4514 USHORT usDeviceTag; //supported device
4515 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH
4516 USHORT usConnObjectId; //Connector Object ID
4517 USHORT usGPUObjectId; //GPU ID
4518 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
4519}ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
4520
4521typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
4522{
4523 UCHAR ucNumOfDispPath;
4524 UCHAR ucVersion;
4525 UCHAR ucPadding[2];
4526 ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
4527}ATOM_DISPLAY_OBJECT_PATH_TABLE;
4528
4529typedef struct _ATOM_OBJECT //each object has this structure
4530{
4531 USHORT usObjectID;
4532 USHORT usSrcDstTableOffset;
4533 USHORT usRecordOffset; //this pointing to a bunch of records defined below
4534 USHORT usReserved;
4535}ATOM_OBJECT;
4536
4537typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure
4538{
4539 UCHAR ucNumberOfObjects;
4540 UCHAR ucPadding[3];
4541 ATOM_OBJECT asObjects[1];
4542}ATOM_OBJECT_TABLE;
4543
4544typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure
4545{
4546 UCHAR ucNumberOfSrc;
4547 USHORT usSrcObjectID[1];
4548 UCHAR ucNumberOfDst;
4549 USHORT usDstObjectID[1];
4550}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
4551
4552
4553//Two definitions below are for OPM on MXM module designs
4554
4555#define EXT_HPDPIN_LUTINDEX_0 0
4556#define EXT_HPDPIN_LUTINDEX_1 1
4557#define EXT_HPDPIN_LUTINDEX_2 2
4558#define EXT_HPDPIN_LUTINDEX_3 3
4559#define EXT_HPDPIN_LUTINDEX_4 4
4560#define EXT_HPDPIN_LUTINDEX_5 5
4561#define EXT_HPDPIN_LUTINDEX_6 6
4562#define EXT_HPDPIN_LUTINDEX_7 7
4563#define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)
4564
4565#define EXT_AUXDDC_LUTINDEX_0 0
4566#define EXT_AUXDDC_LUTINDEX_1 1
4567#define EXT_AUXDDC_LUTINDEX_2 2
4568#define EXT_AUXDDC_LUTINDEX_3 3
4569#define EXT_AUXDDC_LUTINDEX_4 4
4570#define EXT_AUXDDC_LUTINDEX_5 5
4571#define EXT_AUXDDC_LUTINDEX_6 6
4572#define EXT_AUXDDC_LUTINDEX_7 7
4573#define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
4574
4575//ucChannelMapping are defined as following
4576//for DP connector, eDP, DP to VGA/LVDS
4577//Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4578//Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4579//Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4580//Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4581typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
4582{
4583#if ATOM_BIG_ENDIAN
4584 UCHAR ucDP_Lane3_Source:2;
4585 UCHAR ucDP_Lane2_Source:2;
4586 UCHAR ucDP_Lane1_Source:2;
4587 UCHAR ucDP_Lane0_Source:2;
4588#else
4589 UCHAR ucDP_Lane0_Source:2;
4590 UCHAR ucDP_Lane1_Source:2;
4591 UCHAR ucDP_Lane2_Source:2;
4592 UCHAR ucDP_Lane3_Source:2;
4593#endif
4594}ATOM_DP_CONN_CHANNEL_MAPPING;
4595
4596//for DVI/HDMI, in dual link case, both links have to have same mapping.
4597//Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4598//Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4599//Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4600//Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4601typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
4602{
4603#if ATOM_BIG_ENDIAN
4604 UCHAR ucDVI_CLK_Source:2;
4605 UCHAR ucDVI_DATA0_Source:2;
4606 UCHAR ucDVI_DATA1_Source:2;
4607 UCHAR ucDVI_DATA2_Source:2;
4608#else
4609 UCHAR ucDVI_DATA2_Source:2;
4610 UCHAR ucDVI_DATA1_Source:2;
4611 UCHAR ucDVI_DATA0_Source:2;
4612 UCHAR ucDVI_CLK_Source:2;
4613#endif
4614}ATOM_DVI_CONN_CHANNEL_MAPPING;
4615
4616typedef struct _EXT_DISPLAY_PATH
4617{
4618 USHORT usDeviceTag; //A bit vector to show what devices are supported
4619 USHORT usDeviceACPIEnum; //16bit device ACPI id.
4620 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions
4621 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
4622 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
4623 USHORT usExtEncoderObjId; //external encoder object id
4624 union{
4625 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
4626 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
4627 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
4628 };
4629 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4630 USHORT usCaps;
4631 USHORT usReserved;
4632}EXT_DISPLAY_PATH;
4633
4634#define NUMBER_OF_UCHAR_FOR_GUID 16
4635#define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
4636
4637//usCaps
4638#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x0001
4639#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x0002
4640#define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C
4641#define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip
4642#define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip
4643#define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recoverter chip
4644
4645
4646
4647
4648typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
4649{
4650 ATOM_COMMON_TABLE_HEADER sHeader;
4651 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
4652 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
4653 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
4654 UCHAR uc3DStereoPinId; // use for eDP panel
4655 UCHAR ucRemoteDisplayConfig;
4656 UCHAR uceDPToLVDSRxId;
4657 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value
4658 UCHAR Reserved[3]; // for potential expansion
4659}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
4660
4661//Related definitions, all records are differnt but they have a commond header
4662typedef struct _ATOM_COMMON_RECORD_HEADER
4663{
4664 UCHAR ucRecordType; //An emun to indicate the record type
4665 UCHAR ucRecordSize; //The size of the whole record in byte
4666}ATOM_COMMON_RECORD_HEADER;
4667
4668
4669#define ATOM_I2C_RECORD_TYPE 1
4670#define ATOM_HPD_INT_RECORD_TYPE 2
4671#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3
4672#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4
4673#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4674#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4675#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
4676#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4677#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9
4678#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10
4679#define ATOM_CONNECTOR_CF_RECORD_TYPE 11
4680#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12
4681#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13
4682#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14
4683#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
4684#define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table
4685#define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table
4686#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
4687#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19
4688#define ATOM_ENCODER_CAP_RECORD_TYPE 20
4689#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21
4690#define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 22
4691
4692//Must be updated when new record type is added,equal to that record definition!
4693#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE
4694
4695typedef struct _ATOM_I2C_RECORD
4696{
4697 ATOM_COMMON_RECORD_HEADER sheader;
4698 ATOM_I2C_ID_CONFIG sucI2cId;
4699 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
4700}ATOM_I2C_RECORD;
4701
4702typedef struct _ATOM_HPD_INT_RECORD
4703{
4704 ATOM_COMMON_RECORD_HEADER sheader;
4705 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4706 UCHAR ucPlugged_PinState;
4707}ATOM_HPD_INT_RECORD;
4708
4709
4710typedef struct _ATOM_OUTPUT_PROTECTION_RECORD
4711{
4712 ATOM_COMMON_RECORD_HEADER sheader;
4713 UCHAR ucProtectionFlag;
4714 UCHAR ucReserved;
4715}ATOM_OUTPUT_PROTECTION_RECORD;
4716
4717typedef struct _ATOM_CONNECTOR_DEVICE_TAG
4718{
4719 ULONG ulACPIDeviceEnum; //Reserved for now
4720 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
4721 USHORT usPadding;
4722}ATOM_CONNECTOR_DEVICE_TAG;
4723
4724typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD
4725{
4726 ATOM_COMMON_RECORD_HEADER sheader;
4727 UCHAR ucNumberOfDevice;
4728 UCHAR ucReserved;
4729 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
4730}ATOM_CONNECTOR_DEVICE_TAG_RECORD;
4731
4732
4733typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
4734{
4735 ATOM_COMMON_RECORD_HEADER sheader;
4736 UCHAR ucConfigGPIOID;
4737 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
4738 UCHAR ucFlowinGPIPID;
4739 UCHAR ucExtInGPIPID;
4740}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
4741
4742typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD
4743{
4744 ATOM_COMMON_RECORD_HEADER sheader;
4745 UCHAR ucCTL1GPIO_ID;
4746 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4747 UCHAR ucCTL2GPIO_ID;
4748 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4749 UCHAR ucCTL3GPIO_ID;
4750 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4751 UCHAR ucCTLFPGA_IN_ID;
4752 UCHAR ucPadding[3];
4753}ATOM_ENCODER_FPGA_CONTROL_RECORD;
4754
4755typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
4756{
4757 ATOM_COMMON_RECORD_HEADER sheader;
4758 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4759 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
4760}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
4761
4762typedef struct _ATOM_JTAG_RECORD
4763{
4764 ATOM_COMMON_RECORD_HEADER sheader;
4765 UCHAR ucTMSGPIO_ID;
4766 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4767 UCHAR ucTCKGPIO_ID;
4768 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4769 UCHAR ucTDOGPIO_ID;
4770 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4771 UCHAR ucTDIGPIO_ID;
4772 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4773 UCHAR ucPadding[2];
4774}ATOM_JTAG_RECORD;
4775
4776
4777//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
4778typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
4779{
4780 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
4781 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4782}ATOM_GPIO_PIN_CONTROL_PAIR;
4783
4784typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD
4785{
4786 ATOM_COMMON_RECORD_HEADER sheader;
4787 UCHAR ucFlags; // Future expnadibility
4788 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
4789 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
4790}ATOM_OBJECT_GPIO_CNTL_RECORD;
4791
4792//Definitions for GPIO pin state
4793#define GPIO_PIN_TYPE_INPUT 0x00
4794#define GPIO_PIN_TYPE_OUTPUT 0x10
4795#define GPIO_PIN_TYPE_HW_CONTROL 0x20
4796
4797//For GPIO_PIN_TYPE_OUTPUT the following is defined
4798#define GPIO_PIN_OUTPUT_STATE_MASK 0x01
4799#define GPIO_PIN_OUTPUT_STATE_SHIFT 0
4800#define GPIO_PIN_STATE_ACTIVE_LOW 0x0
4801#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1
4802
4803// Indexes to GPIO array in GLSync record
4804// GLSync record is for Frame Lock/Gen Lock feature.
4805#define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0
4806#define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1
4807#define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2
4808#define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3
4809#define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4
4810#define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
4811#define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6
4812#define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
4813#define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8
4814#define ATOM_GPIO_INDEX_GLSYNC_MAX 9
4815
4816typedef struct _ATOM_ENCODER_DVO_CF_RECORD
4817{
4818 ATOM_COMMON_RECORD_HEADER sheader;
4819 ULONG ulStrengthControl; // DVOA strength control for CF
4820 UCHAR ucPadding[2];
4821}ATOM_ENCODER_DVO_CF_RECORD;
4822
4823// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
4824#define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
4825#define ATOM_ENCODER_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not.
4826#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
4827#define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not.
4828#define ATOM_ENCODER_CAP_RECORD_HBR3_EN 0x08 // DP1.3 HBR3 is supported by board.
4829
4830typedef struct _ATOM_ENCODER_CAP_RECORD
4831{
4832 ATOM_COMMON_RECORD_HEADER sheader;
4833 union {
4834 USHORT usEncoderCap;
4835 struct {
4836#if ATOM_BIG_ENDIAN
4837 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4838 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4839 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4840#else
4841 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4842 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4843 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future
4844#endif
4845 };
4846 };
4847}ATOM_ENCODER_CAP_RECORD;
4848
4849// Used after SI
4850typedef struct _ATOM_ENCODER_CAP_RECORD_V2
4851{
4852 ATOM_COMMON_RECORD_HEADER sheader;
4853 union {
4854 USHORT usEncoderCap;
4855 struct {
4856#if ATOM_BIG_ENDIAN
4857 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future
4858 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4859 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
4860 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4861 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4862#else
4863 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable
4864 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4865 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU)
4866 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable
4867 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future
4868#endif
4869 };
4870 };
4871}ATOM_ENCODER_CAP_RECORD_V2;
4872
4873
4874// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
4875#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
4876#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2
4877
4878typedef struct _ATOM_CONNECTOR_CF_RECORD
4879{
4880 ATOM_COMMON_RECORD_HEADER sheader;
4881 USHORT usMaxPixClk;
4882 UCHAR ucFlowCntlGpioId;
4883 UCHAR ucSwapCntlGpioId;
4884 UCHAR ucConnectedDvoBundle;
4885 UCHAR ucPadding;
4886}ATOM_CONNECTOR_CF_RECORD;
4887
4888typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
4889{
4890 ATOM_COMMON_RECORD_HEADER sheader;
4891 ATOM_DTD_FORMAT asTiming;
4892}ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
4893
4894typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
4895{
4896 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
4897 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
4898 UCHAR ucReserved;
4899}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
4900
4901
4902typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
4903{
4904 ATOM_COMMON_RECORD_HEADER sheader;
4905 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
4906 UCHAR ucMuxControlPin;
4907 UCHAR ucMuxState[2]; //for alligment purpose
4908}ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
4909
4910typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
4911{
4912 ATOM_COMMON_RECORD_HEADER sheader;
4913 UCHAR ucMuxType;
4914 UCHAR ucMuxControlPin;
4915 UCHAR ucMuxState[2]; //for alligment purpose
4916}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
4917
4918// define ucMuxType
4919#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f
4920#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01
4921
4922typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
4923{
4924 ATOM_COMMON_RECORD_HEADER sheader;
4925 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
4926}ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
4927
4928typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
4929{
4930 ATOM_COMMON_RECORD_HEADER sheader;
4931 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID
4932}ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
4933
4934typedef struct _ATOM_OBJECT_LINK_RECORD
4935{
4936 ATOM_COMMON_RECORD_HEADER sheader;
4937 USHORT usObjectID; //could be connector, encorder or other object in object.h
4938}ATOM_OBJECT_LINK_RECORD;
4939
4940typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
4941{
4942 ATOM_COMMON_RECORD_HEADER sheader;
4943 USHORT usReserved;
4944}ATOM_CONNECTOR_REMOTE_CAP_RECORD;
4945
4946
4947typedef struct _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD
4948{
4949 ATOM_COMMON_RECORD_HEADER sheader;
4950 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
4951 UCHAR ucMaxTmdsClkRateIn2_5Mhz;
4952 UCHAR ucReserved;
4953} ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD;
4954
4955
4956typedef struct _ATOM_CONNECTOR_LAYOUT_INFO
4957{
4958 USHORT usConnectorObjectId;
4959 UCHAR ucConnectorType;
4960 UCHAR ucPosition;
4961}ATOM_CONNECTOR_LAYOUT_INFO;
4962
4963// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
4964#define CONNECTOR_TYPE_DVI_D 1
4965#define CONNECTOR_TYPE_DVI_I 2
4966#define CONNECTOR_TYPE_VGA 3
4967#define CONNECTOR_TYPE_HDMI 4
4968#define CONNECTOR_TYPE_DISPLAY_PORT 5
4969#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6
4970
4971typedef struct _ATOM_BRACKET_LAYOUT_RECORD
4972{
4973 ATOM_COMMON_RECORD_HEADER sheader;
4974 UCHAR ucLength;
4975 UCHAR ucWidth;
4976 UCHAR ucConnNum;
4977 UCHAR ucReserved;
4978 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1];
4979}ATOM_BRACKET_LAYOUT_RECORD;
4980
4981
4982/****************************************************************************/
4983// Structure used in XXXX
4984/****************************************************************************/
4985typedef struct _ATOM_VOLTAGE_INFO_HEADER
4986{
4987 USHORT usVDDCBaseLevel; //In number of 50mv unit
4988 USHORT usReserved; //For possible extension table offset
4989 UCHAR ucNumOfVoltageEntries;
4990 UCHAR ucBytesPerVoltageEntry;
4991 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
4992 UCHAR ucDefaultVoltageEntry;
4993 UCHAR ucVoltageControlI2cLine;
4994 UCHAR ucVoltageControlAddress;
4995 UCHAR ucVoltageControlOffset;
4996}ATOM_VOLTAGE_INFO_HEADER;
4997
4998typedef struct _ATOM_VOLTAGE_INFO
4999{
5000 ATOM_COMMON_TABLE_HEADER sHeader;
5001 ATOM_VOLTAGE_INFO_HEADER viHeader;
5002 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
5003}ATOM_VOLTAGE_INFO;
5004
5005
5006typedef struct _ATOM_VOLTAGE_FORMULA
5007{
5008 USHORT usVoltageBaseLevel; // In number of 1mv unit
5009 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit
5010 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
5011 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
5012 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
5013 UCHAR ucReserved;
5014 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
5015}ATOM_VOLTAGE_FORMULA;
5016
5017typedef struct _VOLTAGE_LUT_ENTRY
5018{
5019 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code
5020 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
5021}VOLTAGE_LUT_ENTRY;
5022
5023typedef struct _ATOM_VOLTAGE_FORMULA_V2
5024{
5025 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
5026 UCHAR ucReserved[3];
5027 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
5028}ATOM_VOLTAGE_FORMULA_V2;
5029
5030typedef struct _ATOM_VOLTAGE_CONTROL
5031{
5032 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
5033 UCHAR ucVoltageControlI2cLine;
5034 UCHAR ucVoltageControlAddress;
5035 UCHAR ucVoltageControlOffset;
5036 USHORT usGpioPin_AIndex; //GPIO_PAD register index
5037 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
5038 UCHAR ucReserved;
5039}ATOM_VOLTAGE_CONTROL;
5040
5041// Define ucVoltageControlId
5042#define VOLTAGE_CONTROLLED_BY_HW 0x00
5043#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F
5044#define VOLTAGE_CONTROLLED_BY_GPIO 0x80
5045#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage
5046#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
5047#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage
5048#define VOLTAGE_CONTROL_ID_DS4402 0x04
5049#define VOLTAGE_CONTROL_ID_UP6266 0x05
5050#define VOLTAGE_CONTROL_ID_SCORPIO 0x06
5051#define VOLTAGE_CONTROL_ID_VT1556M 0x07
5052#define VOLTAGE_CONTROL_ID_CHL822x 0x08
5053#define VOLTAGE_CONTROL_ID_VT1586M 0x09
5054#define VOLTAGE_CONTROL_ID_UP1637 0x0A
5055#define VOLTAGE_CONTROL_ID_CHL8214 0x0B
5056#define VOLTAGE_CONTROL_ID_UP1801 0x0C
5057#define VOLTAGE_CONTROL_ID_ST6788A 0x0D
5058#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E
5059#define VOLTAGE_CONTROL_ID_AD527x 0x0F
5060#define VOLTAGE_CONTROL_ID_NCP81022 0x10
5061#define VOLTAGE_CONTROL_ID_LTC2635 0x11
5062#define VOLTAGE_CONTROL_ID_NCP4208 0x12
5063#define VOLTAGE_CONTROL_ID_IR35xx 0x13
5064#define VOLTAGE_CONTROL_ID_RT9403 0x14
5065
5066#define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40
5067
5068typedef struct _ATOM_VOLTAGE_OBJECT
5069{
5070 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5071 UCHAR ucSize; //Size of Object
5072 ATOM_VOLTAGE_CONTROL asControl; //describ how to control
5073 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID
5074}ATOM_VOLTAGE_OBJECT;
5075
5076typedef struct _ATOM_VOLTAGE_OBJECT_V2
5077{
5078 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5079 UCHAR ucSize; //Size of Object
5080 ATOM_VOLTAGE_CONTROL asControl; //describ how to control
5081 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID
5082}ATOM_VOLTAGE_OBJECT_V2;
5083
5084typedef struct _ATOM_VOLTAGE_OBJECT_INFO
5085{
5086 ATOM_COMMON_TABLE_HEADER sHeader;
5087 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control
5088}ATOM_VOLTAGE_OBJECT_INFO;
5089
5090typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2
5091{
5092 ATOM_COMMON_TABLE_HEADER sHeader;
5093 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control
5094}ATOM_VOLTAGE_OBJECT_INFO_V2;
5095
5096typedef struct _ATOM_LEAKID_VOLTAGE
5097{
5098 UCHAR ucLeakageId;
5099 UCHAR ucReserved;
5100 USHORT usVoltage;
5101}ATOM_LEAKID_VOLTAGE;
5102
5103typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
5104 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5105 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
5106 USHORT usSize; //Size of Object
5107}ATOM_VOLTAGE_OBJECT_HEADER_V3;
5108
5109// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode
5110#define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
5111#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3
5112#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
5113#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3
5114#define VOLTAGE_OBJ_EVV 8
5115#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
5116#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
5117#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
5118
5119typedef struct _VOLTAGE_LUT_ENTRY_V2
5120{
5121 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
5122 USHORT usVoltageValue; // The corresponding Voltage Value, in mV
5123}VOLTAGE_LUT_ENTRY_V2;
5124
5125typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
5126{
5127 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register
5128 USHORT usVoltageId;
5129 USHORT usLeakageId; // The corresponding Voltage Value, in mV
5130}LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
5131
5132
5133typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3
5134{
5135 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
5136 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
5137 UCHAR ucVoltageControlI2cLine;
5138 UCHAR ucVoltageControlAddress;
5139 UCHAR ucVoltageControlOffset;
5140 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5141 UCHAR ulReserved[3];
5142 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff
5143}ATOM_I2C_VOLTAGE_OBJECT_V3;
5144
5145// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
5146#define VOLTAGE_DATA_ONE_BYTE 0
5147#define VOLTAGE_DATA_TWO_BYTE 1
5148
5149typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3
5150{
5151 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
5152 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
5153 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table
5154 UCHAR ucPhaseDelay; // phase delay in unit of micro second
5155 UCHAR ucReserved;
5156 ULONG ulGpioMaskVal; // GPIO Mask value
5157 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
5158}ATOM_GPIO_VOLTAGE_OBJECT_V3;
5159
5160typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
5161{
5162 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12
5163 UCHAR ucLeakageCntlId; // default is 0
5164 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
5165 UCHAR ucReserved[2];
5166 ULONG ulMaxVoltageLevel;
5167 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
5168}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
5169
5170
5171typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3
5172{
5173 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2
5174// 14:7 � PSI0_VID
5175// 6 � PSI0_EN
5176// 5 � PSI1
5177// 4:2 � load line slope trim.
5178// 1:0 � offset trim,
5179 USHORT usLoadLine_PSI;
5180// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
5181 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
5182 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
5183 ULONG ulReserved;
5184}ATOM_SVID2_VOLTAGE_OBJECT_V3;
5185
5186
5187
5188typedef struct _ATOM_MERGED_VOLTAGE_OBJECT_V3
5189{
5190 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
5191 UCHAR ucMergedVType; // VDDC/VDCCI/....
5192 UCHAR ucReserved[3];
5193}ATOM_MERGED_VOLTAGE_OBJECT_V3;
5194
5195
5196typedef struct _ATOM_EVV_DPM_INFO
5197{
5198 ULONG ulDPMSclk; // DPM state SCLK
5199 USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv
5200 UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable
5201 UCHAR ucDPMState; // DPMState0~7
5202} ATOM_EVV_DPM_INFO;
5203
5204// ucVoltageMode = VOLTAGE_OBJ_EVV
5205typedef struct _ATOM_EVV_VOLTAGE_OBJECT_V3
5206{
5207 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2
5208 ATOM_EVV_DPM_INFO asEvvDpmList[8];
5209}ATOM_EVV_VOLTAGE_OBJECT_V3;
5210
5211
5212typedef union _ATOM_VOLTAGE_OBJECT_V3{
5213 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
5214 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
5215 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
5216 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj;
5217 ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvObj;
5218}ATOM_VOLTAGE_OBJECT_V3;
5219
5220typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1
5221{
5222 ATOM_COMMON_TABLE_HEADER sHeader;
5223 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control
5224}ATOM_VOLTAGE_OBJECT_INFO_V3_1;
5225
5226
5227typedef struct _ATOM_ASIC_PROFILE_VOLTAGE
5228{
5229 UCHAR ucProfileId;
5230 UCHAR ucReserved;
5231 USHORT usSize;
5232 USHORT usEfuseSpareStartAddr;
5233 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
5234 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage
5235}ATOM_ASIC_PROFILE_VOLTAGE;
5236
5237//ucProfileId
5238#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
5239#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
5240#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2
5241
5242typedef struct _ATOM_ASIC_PROFILING_INFO
5243{
5244 ATOM_COMMON_TABLE_HEADER asHeader;
5245 ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
5246}ATOM_ASIC_PROFILING_INFO;
5247
5248typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1
5249{
5250 ATOM_COMMON_TABLE_HEADER asHeader;
5251 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table
5252 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher)
5253
5254 UCHAR ucElbVDDC_Num;
5255 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 )
5256 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
5257
5258 UCHAR ucElbVDDCI_Num;
5259 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 )
5260 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array
5261}ATOM_ASIC_PROFILING_INFO_V2_1;
5262
5263
5264//Here is parameter to convert Efuse value to Measure value
5265//Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
5266typedef struct _EFUSE_LOGISTIC_FUNC_PARAM
5267{
5268 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
5269 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5270 UCHAR ucEfuseLength; // Efuse bits length,
5271 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
5272 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2
5273}EFUSE_LOGISTIC_FUNC_PARAM;
5274
5275//Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
5276typedef struct _EFUSE_LINEAR_FUNC_PARAM
5277{
5278 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
5279 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5280 UCHAR ucEfuseLength; // Efuse bits length,
5281 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number
5282 ULONG ulEfuseMin; // Min
5283}EFUSE_LINEAR_FUNC_PARAM;
5284
5285
5286typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1
5287{
5288 ATOM_COMMON_TABLE_HEADER asHeader;
5289 ULONG ulEvvDerateTdp;
5290 ULONG ulEvvDerateTdc;
5291 ULONG ulBoardCoreTemp;
5292 ULONG ulMaxVddc;
5293 ULONG ulMinVddc;
5294 ULONG ulLoadLineSlop;
5295 ULONG ulLeakageTemp;
5296 ULONG ulLeakageVoltage;
5297 EFUSE_LINEAR_FUNC_PARAM sCACm;
5298 EFUSE_LINEAR_FUNC_PARAM sCACb;
5299 EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
5300 EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
5301 EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
5302 USHORT usLkgEuseIndex;
5303 UCHAR ucLkgEfuseBitLSB;
5304 UCHAR ucLkgEfuseLength;
5305 ULONG ulLkgEncodeLn_MaxDivMin;
5306 ULONG ulLkgEncodeMax;
5307 ULONG ulLkgEncodeMin;
5308 ULONG ulEfuseLogisticAlpha;
5309 USHORT usPowerDpm0;
5310 USHORT usCurrentDpm0;
5311 USHORT usPowerDpm1;
5312 USHORT usCurrentDpm1;
5313 USHORT usPowerDpm2;
5314 USHORT usCurrentDpm2;
5315 USHORT usPowerDpm3;
5316 USHORT usCurrentDpm3;
5317 USHORT usPowerDpm4;
5318 USHORT usCurrentDpm4;
5319 USHORT usPowerDpm5;
5320 USHORT usCurrentDpm5;
5321 USHORT usPowerDpm6;
5322 USHORT usCurrentDpm6;
5323 USHORT usPowerDpm7;
5324 USHORT usCurrentDpm7;
5325}ATOM_ASIC_PROFILING_INFO_V3_1;
5326
5327
5328typedef struct _ATOM_ASIC_PROFILING_INFO_V3_2
5329{
5330 ATOM_COMMON_TABLE_HEADER asHeader;
5331 ULONG ulEvvLkgFactor;
5332 ULONG ulBoardCoreTemp;
5333 ULONG ulMaxVddc;
5334 ULONG ulMinVddc;
5335 ULONG ulLoadLineSlop;
5336 ULONG ulLeakageTemp;
5337 ULONG ulLeakageVoltage;
5338 EFUSE_LINEAR_FUNC_PARAM sCACm;
5339 EFUSE_LINEAR_FUNC_PARAM sCACb;
5340 EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
5341 EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
5342 EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
5343 USHORT usLkgEuseIndex;
5344 UCHAR ucLkgEfuseBitLSB;
5345 UCHAR ucLkgEfuseLength;
5346 ULONG ulLkgEncodeLn_MaxDivMin;
5347 ULONG ulLkgEncodeMax;
5348 ULONG ulLkgEncodeMin;
5349 ULONG ulEfuseLogisticAlpha;
5350 USHORT usPowerDpm0;
5351 USHORT usPowerDpm1;
5352 USHORT usPowerDpm2;
5353 USHORT usPowerDpm3;
5354 USHORT usPowerDpm4;
5355 USHORT usPowerDpm5;
5356 USHORT usPowerDpm6;
5357 USHORT usPowerDpm7;
5358 ULONG ulTdpDerateDPM0;
5359 ULONG ulTdpDerateDPM1;
5360 ULONG ulTdpDerateDPM2;
5361 ULONG ulTdpDerateDPM3;
5362 ULONG ulTdpDerateDPM4;
5363 ULONG ulTdpDerateDPM5;
5364 ULONG ulTdpDerateDPM6;
5365 ULONG ulTdpDerateDPM7;
5366}ATOM_ASIC_PROFILING_INFO_V3_2;
5367
5368
5369// for Tonga/Fiji speed EVV algorithm
5370typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3
5371{
5372 ATOM_COMMON_TABLE_HEADER asHeader;
5373 ULONG ulEvvLkgFactor;
5374 ULONG ulBoardCoreTemp;
5375 ULONG ulMaxVddc;
5376 ULONG ulMinVddc;
5377 ULONG ulLoadLineSlop;
5378 ULONG ulLeakageTemp;
5379 ULONG ulLeakageVoltage;
5380 EFUSE_LINEAR_FUNC_PARAM sCACm;
5381 EFUSE_LINEAR_FUNC_PARAM sCACb;
5382 EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
5383 EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
5384 EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
5385 USHORT usLkgEuseIndex;
5386 UCHAR ucLkgEfuseBitLSB;
5387 UCHAR ucLkgEfuseLength;
5388 ULONG ulLkgEncodeLn_MaxDivMin;
5389 ULONG ulLkgEncodeMax;
5390 ULONG ulLkgEncodeMin;
5391 ULONG ulEfuseLogisticAlpha;
5392
5393 union{
5394 USHORT usPowerDpm0;
5395 USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m max is postive
5396 };
5397 USHORT usPowerDpm1;
5398 USHORT usPowerDpm2;
5399 USHORT usPowerDpm3;
5400 USHORT usPowerDpm4;
5401 USHORT usPowerDpm5;
5402 USHORT usPowerDpm6;
5403 USHORT usPowerDpm7;
5404 ULONG ulTdpDerateDPM0;
5405 ULONG ulTdpDerateDPM1;
5406 ULONG ulTdpDerateDPM2;
5407 ULONG ulTdpDerateDPM3;
5408 ULONG ulTdpDerateDPM4;
5409 ULONG ulTdpDerateDPM5;
5410 ULONG ulTdpDerateDPM6;
5411 ULONG ulTdpDerateDPM7;
5412 EFUSE_LINEAR_FUNC_PARAM sRoFuse;
5413 ULONG ulRoAlpha;
5414 ULONG ulRoBeta;
5415 ULONG ulRoGamma;
5416 ULONG ulRoEpsilon;
5417 ULONG ulATermRo;
5418 ULONG ulBTermRo;
5419 ULONG ulCTermRo;
5420 ULONG ulSclkMargin;
5421 ULONG ulFmaxPercent;
5422 ULONG ulCRPercent;
5423 ULONG ulSFmaxPercent;
5424 ULONG ulSCRPercent;
5425 ULONG ulSDCMargine;
5426}ATOM_ASIC_PROFILING_INFO_V3_3;
5427
5428// for Fiji speed EVV algorithm
5429typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4
5430{
5431 ATOM_COMMON_TABLE_HEADER asHeader;
5432 ULONG ulEvvLkgFactor;
5433 ULONG ulBoardCoreTemp;
5434 ULONG ulMaxVddc;
5435 ULONG ulMinVddc;
5436 ULONG ulLoadLineSlop;
5437 ULONG ulLeakageTemp;
5438 ULONG ulLeakageVoltage;
5439 EFUSE_LINEAR_FUNC_PARAM sCACm;
5440 EFUSE_LINEAR_FUNC_PARAM sCACb;
5441 EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
5442 EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
5443 EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
5444 USHORT usLkgEuseIndex;
5445 UCHAR ucLkgEfuseBitLSB;
5446 UCHAR ucLkgEfuseLength;
5447 ULONG ulLkgEncodeLn_MaxDivMin;
5448 ULONG ulLkgEncodeMax;
5449 ULONG ulLkgEncodeMin;
5450 ULONG ulEfuseLogisticAlpha;
5451 USHORT usPowerDpm0;
5452 USHORT usPowerDpm1;
5453 USHORT usPowerDpm2;
5454 USHORT usPowerDpm3;
5455 USHORT usPowerDpm4;
5456 USHORT usPowerDpm5;
5457 USHORT usPowerDpm6;
5458 USHORT usPowerDpm7;
5459 ULONG ulTdpDerateDPM0;
5460 ULONG ulTdpDerateDPM1;
5461 ULONG ulTdpDerateDPM2;
5462 ULONG ulTdpDerateDPM3;
5463 ULONG ulTdpDerateDPM4;
5464 ULONG ulTdpDerateDPM5;
5465 ULONG ulTdpDerateDPM6;
5466 ULONG ulTdpDerateDPM7;
5467 EFUSE_LINEAR_FUNC_PARAM sRoFuse;
5468 ULONG ulEvvDefaultVddc;
5469 ULONG ulEvvNoCalcVddc;
5470 USHORT usParamNegFlag;
5471 USHORT usSpeed_Model;
5472 ULONG ulSM_A0;
5473 ULONG ulSM_A1;
5474 ULONG ulSM_A2;
5475 ULONG ulSM_A3;
5476 ULONG ulSM_A4;
5477 ULONG ulSM_A5;
5478 ULONG ulSM_A6;
5479 ULONG ulSM_A7;
5480 UCHAR ucSM_A0_sign;
5481 UCHAR ucSM_A1_sign;
5482 UCHAR ucSM_A2_sign;
5483 UCHAR ucSM_A3_sign;
5484 UCHAR ucSM_A4_sign;
5485 UCHAR ucSM_A5_sign;
5486 UCHAR ucSM_A6_sign;
5487 UCHAR ucSM_A7_sign;
5488 ULONG ulMargin_RO_a;
5489 ULONG ulMargin_RO_b;
5490 ULONG ulMargin_RO_c;
5491 ULONG ulMargin_fixed;
5492 ULONG ulMargin_Fmax_mean;
5493 ULONG ulMargin_plat_mean;
5494 ULONG ulMargin_Fmax_sigma;
5495 ULONG ulMargin_plat_sigma;
5496 ULONG ulMargin_DC_sigma;
5497 ULONG ulReserved[8]; // Reserved for future ASIC
5498}ATOM_ASIC_PROFILING_INFO_V3_4;
5499
5500// for Polaris10/Polaris11 speed EVV algorithm
5501typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5
5502{
5503 ATOM_COMMON_TABLE_HEADER asHeader;
5504 ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv
5505 ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv
5506 USHORT usLkgEuseIndex; //Efuse Lkg_FT address ( BYTE address )
5507 UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD
5508 UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length
5509 ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 )
5510 ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
5511 ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 )
5512 EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1.
5513 ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/>
5514 ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/>
5515 ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/>
5516 ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/>
5517 ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/>
5518 ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/>
5519 ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/>
5520 ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/>
5521 ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/>
5522 ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/>
5523 ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/>
5524 UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/>
5525 UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/>
5526 UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/>
5527 UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/>
5528 UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/>
5529 UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/>
5530 UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/>
5531 UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/>
5532 ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1"
5533 ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1"
5534 ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1"
5535 ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/>
5536 ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/>
5537 ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/>
5538 ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/>
5539 ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/>
5540 ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/>
5541 ULONG ulReserved[12];
5542}ATOM_ASIC_PROFILING_INFO_V3_5;
5543
5544/* for Polars10/11 AVFS parameters */
5545typedef struct _ATOM_ASIC_PROFILING_INFO_V3_6
5546{
5547 ATOM_COMMON_TABLE_HEADER asHeader;
5548 ULONG ulMaxVddc;
5549 ULONG ulMinVddc;
5550 USHORT usLkgEuseIndex;
5551 UCHAR ucLkgEfuseBitLSB;
5552 UCHAR ucLkgEfuseLength;
5553 ULONG ulLkgEncodeLn_MaxDivMin;
5554 ULONG ulLkgEncodeMax;
5555 ULONG ulLkgEncodeMin;
5556 EFUSE_LINEAR_FUNC_PARAM sRoFuse;
5557 ULONG ulEvvDefaultVddc;
5558 ULONG ulEvvNoCalcVddc;
5559 ULONG ulSpeed_Model;
5560 ULONG ulSM_A0;
5561 ULONG ulSM_A1;
5562 ULONG ulSM_A2;
5563 ULONG ulSM_A3;
5564 ULONG ulSM_A4;
5565 ULONG ulSM_A5;
5566 ULONG ulSM_A6;
5567 ULONG ulSM_A7;
5568 UCHAR ucSM_A0_sign;
5569 UCHAR ucSM_A1_sign;
5570 UCHAR ucSM_A2_sign;
5571 UCHAR ucSM_A3_sign;
5572 UCHAR ucSM_A4_sign;
5573 UCHAR ucSM_A5_sign;
5574 UCHAR ucSM_A6_sign;
5575 UCHAR ucSM_A7_sign;
5576 ULONG ulMargin_RO_a;
5577 ULONG ulMargin_RO_b;
5578 ULONG ulMargin_RO_c;
5579 ULONG ulMargin_fixed;
5580 ULONG ulMargin_Fmax_mean;
5581 ULONG ulMargin_plat_mean;
5582 ULONG ulMargin_Fmax_sigma;
5583 ULONG ulMargin_plat_sigma;
5584 ULONG ulMargin_DC_sigma;
5585 ULONG ulLoadLineSlop;
5586 ULONG ulaTDClimitPerDPM[8];
5587 ULONG ulaNoCalcVddcPerDPM[8];
5588 ULONG ulAVFS_meanNsigma_Acontant0;
5589 ULONG ulAVFS_meanNsigma_Acontant1;
5590 ULONG ulAVFS_meanNsigma_Acontant2;
5591 USHORT usAVFS_meanNsigma_DC_tol_sigma;
5592 USHORT usAVFS_meanNsigma_Platform_mean;
5593 USHORT usAVFS_meanNsigma_Platform_sigma;
5594 ULONG ulGB_VDROOP_TABLE_CKSOFF_a0;
5595 ULONG ulGB_VDROOP_TABLE_CKSOFF_a1;
5596 ULONG ulGB_VDROOP_TABLE_CKSOFF_a2;
5597 ULONG ulGB_VDROOP_TABLE_CKSON_a0;
5598 ULONG ulGB_VDROOP_TABLE_CKSON_a1;
5599 ULONG ulGB_VDROOP_TABLE_CKSON_a2;
5600 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
5601 USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2;
5602 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b;
5603 ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1;
5604 USHORT usAVFSGB_FUSE_TABLE_CKSON_m2;
5605 ULONG ulAVFSGB_FUSE_TABLE_CKSON_b;
5606 USHORT usMaxVoltage_0_25mv;
5607 UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF;
5608 UCHAR ucEnableGB_VDROOP_TABLE_CKSON;
5609 UCHAR ucEnableGB_FUSE_TABLE_CKSOFF;
5610 UCHAR ucEnableGB_FUSE_TABLE_CKSON;
5611 USHORT usPSM_Age_ComFactor;
5612 UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage;
5613 UCHAR ucReserved;
5614}ATOM_ASIC_PROFILING_INFO_V3_6;
5615
5616
5617typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{
5618 ULONG ulMaxSclkFreq;
5619 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5620 UCHAR ucPostdiv; // divide by 2^n
5621 USHORT ucFcw_pcc;
5622 USHORT ucFcw_trans_upper;
5623 USHORT ucRcw_trans_lower;
5624}ATOM_SCLK_FCW_RANGE_ENTRY_V1;
5625
5626
5627// SMU_InfoTable for Polaris10/Polaris11
5628typedef struct _ATOM_SMU_INFO_V2_1
5629{
5630 ATOM_COMMON_TABLE_HEADER asHeader;
5631 UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1
5632 UCHAR ucReserved[3];
5633 ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8];
5634}ATOM_SMU_INFO_V2_1;
5635
5636
5637// GFX_InfoTable for Polaris10/Polaris11
5638typedef struct _ATOM_GFX_INFO_V2_1
5639{
5640 ATOM_COMMON_TABLE_HEADER asHeader;
5641 UCHAR GfxIpMinVer;
5642 UCHAR GfxIpMajVer;
5643 UCHAR max_shader_engines;
5644 UCHAR max_tile_pipes;
5645 UCHAR max_cu_per_sh;
5646 UCHAR max_sh_per_se;
5647 UCHAR max_backends_per_se;
5648 UCHAR max_texture_channel_caches;
5649}ATOM_GFX_INFO_V2_1;
5650
5651
5652typedef struct _ATOM_POWER_SOURCE_OBJECT
5653{
5654 UCHAR ucPwrSrcId; // Power source
5655 UCHAR ucPwrSensorType; // GPIO, I2C or none
5656 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
5657 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
5658 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
5659 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
5660 UCHAR ucPwrSensActiveState; // high active or low active
5661 UCHAR ucReserve[3]; // reserve
5662 USHORT usSensPwr; // in unit of watt
5663}ATOM_POWER_SOURCE_OBJECT;
5664
5665typedef struct _ATOM_POWER_SOURCE_INFO
5666{
5667 ATOM_COMMON_TABLE_HEADER asHeader;
5668 UCHAR asPwrbehave[16];
5669 ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
5670}ATOM_POWER_SOURCE_INFO;
5671
5672
5673//Define ucPwrSrcId
5674#define POWERSOURCE_PCIE_ID1 0x00
5675#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01
5676#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02
5677#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04
5678#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08
5679
5680//define ucPwrSensorId
5681#define POWER_SENSOR_ALWAYS 0x00
5682#define POWER_SENSOR_GPIO 0x01
5683#define POWER_SENSOR_I2C 0x02
5684
5685typedef struct _ATOM_CLK_VOLT_CAPABILITY
5686{
5687 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
5688 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5689}ATOM_CLK_VOLT_CAPABILITY;
5690
5691
5692typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2
5693{
5694 USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv,
5695 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5696}ATOM_CLK_VOLT_CAPABILITY_V2;
5697
5698typedef struct _ATOM_AVAILABLE_SCLK_LIST
5699{
5700 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
5701 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK
5702 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK
5703}ATOM_AVAILABLE_SCLK_LIST;
5704
5705// ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
5706#define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0]
5707
5708// this IntegrateSystemInfoTable is used for Liano/Ontario APU
5709typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
5710{
5711 ATOM_COMMON_TABLE_HEADER sHeader;
5712 ULONG ulBootUpEngineClock;
5713 ULONG ulDentistVCOFreq;
5714 ULONG ulBootUpUMAClock;
5715 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
5716 ULONG ulBootUpReqDisplayVector;
5717 ULONG ulOtherDisplayMisc;
5718 ULONG ulGPUCapInfo;
5719 ULONG ulSB_MMIO_Base_Addr;
5720 USHORT usRequestedPWMFreqInHz;
5721 UCHAR ucHtcTmpLmt;
5722 UCHAR ucHtcHystLmt;
5723 ULONG ulMinEngineClock;
5724 ULONG ulSystemConfig;
5725 ULONG ulCPUCapInfo;
5726 USHORT usNBP0Voltage;
5727 USHORT usNBP1Voltage;
5728 USHORT usBootUpNBVoltage;
5729 USHORT usExtDispConnInfoOffset;
5730 USHORT usPanelRefreshRateRange;
5731 UCHAR ucMemoryType;
5732 UCHAR ucUMAChannelNumber;
5733 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
5734 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
5735 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
5736 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
5737 ULONG ulGMCRestoreResetTime;
5738 ULONG ulMinimumNClk;
5739 ULONG ulIdleNClk;
5740 ULONG ulDDR_DLL_PowerUpTime;
5741 ULONG ulDDR_PLL_PowerUpTime;
5742 USHORT usPCIEClkSSPercentage;
5743 USHORT usPCIEClkSSType;
5744 USHORT usLvdsSSPercentage;
5745 USHORT usLvdsSSpreadRateIn10Hz;
5746 USHORT usHDMISSPercentage;
5747 USHORT usHDMISSpreadRateIn10Hz;
5748 USHORT usDVISSPercentage;
5749 USHORT usDVISSpreadRateIn10Hz;
5750 ULONG SclkDpmBoostMargin;
5751 ULONG SclkDpmThrottleMargin;
5752 USHORT SclkDpmTdpLimitPG;
5753 USHORT SclkDpmTdpLimitBoost;
5754 ULONG ulBoostEngineCLock;
5755 UCHAR ulBoostVid_2bit;
5756 UCHAR EnableBoost;
5757 USHORT GnbTdpLimit;
5758 USHORT usMaxLVDSPclkFreqInSingleLink;
5759 UCHAR ucLvdsMisc;
5760 UCHAR ucLVDSReserved;
5761 ULONG ulReserved3[15];
5762 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
5763}ATOM_INTEGRATED_SYSTEM_INFO_V6;
5764
5765// ulGPUCapInfo
5766#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
5767#define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08
5768
5769//ucLVDSMisc:
5770#define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01
5771#define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02
5772#define SYS_INFO_LVDSMISC__888_BPC 0x04
5773#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08
5774#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10
5775// new since Trinity
5776#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20
5777
5778// not used any more
5779#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04
5780#define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08
5781
5782/**********************************************************************************************************************
5783 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
5784ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
5785ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5786ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5787sDISPCLK_Voltage: Report Display clock voltage requirement.
5788
5789ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
5790 ATOM_DEVICE_CRT1_SUPPORT 0x0001
5791 ATOM_DEVICE_CRT2_SUPPORT 0x0010
5792 ATOM_DEVICE_DFP1_SUPPORT 0x0008
5793 ATOM_DEVICE_DFP6_SUPPORT 0x0040
5794 ATOM_DEVICE_DFP2_SUPPORT 0x0080
5795 ATOM_DEVICE_DFP3_SUPPORT 0x0200
5796 ATOM_DEVICE_DFP4_SUPPORT 0x0400
5797 ATOM_DEVICE_DFP5_SUPPORT 0x0800
5798 ATOM_DEVICE_LCD1_SUPPORT 0x0002
5799ulOtherDisplayMisc: Other display related flags, not defined yet.
5800ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
5801 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
5802 bit[3]=0: Enable HW AUX mode detection logic
5803 =1: Disable HW AUX mode dettion logic
5804ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
5805
5806usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5807 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
5808
5809 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5810 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5811 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5812 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5813 and enabling VariBri under the driver environment from PP table is optional.
5814
5815 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5816 that BL control from GPU is expected.
5817 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5818 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
5819 it's per platform
5820 and enabling VariBri under the driver environment from PP table is optional.
5821
5822ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
5823 Threshold on value to enter HTC_active state.
5824ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
5825 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
5826ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
5827ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
5828 =1: PCIE Power Gating Enabled
5829 Bit[1]=0: DDR-DLL shut-down feature disabled.
5830 1: DDR-DLL shut-down feature enabled.
5831 Bit[2]=0: DDR-PLL Power down feature disabled.
5832 1: DDR-PLL Power down feature enabled.
5833ulCPUCapInfo: TBD
5834usNBP0Voltage: VID for voltage on NB P0 State
5835usNBP1Voltage: VID for voltage on NB P1 State
5836usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
5837usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
5838usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
5839 to indicate a range.
5840 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
5841 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
5842 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
5843 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
5844ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5845ucUMAChannelNumber: System memory channel numbers.
5846ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
5847ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
5848ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
5849sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
5850ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
5851ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5852ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5853ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
5854ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
5855usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
5856usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
5857usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
5858usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
5859usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
5860usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
5861usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
5862usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
5863usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
5864ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
5865 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
5866 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5867 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
5868 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
5869**********************************************************************************************************************/
5870
5871// this Table is used for Liano/Ontario APU
5872typedef struct _ATOM_FUSION_SYSTEM_INFO_V1
5873{
5874 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo;
5875 ULONG ulPowerplayTable[128];
5876}ATOM_FUSION_SYSTEM_INFO_V1;
5877
5878
5879typedef struct _ATOM_TDP_CONFIG_BITS
5880{
5881#if ATOM_BIG_ENDIAN
5882 ULONG uReserved:2;
5883 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5884 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5885 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5886#else
5887 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5888 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5889 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5890 ULONG uReserved:2;
5891#endif
5892}ATOM_TDP_CONFIG_BITS;
5893
5894typedef union _ATOM_TDP_CONFIG
5895{
5896 ATOM_TDP_CONFIG_BITS TDP_config;
5897 ULONG TDP_config_all;
5898}ATOM_TDP_CONFIG;
5899
5900/**********************************************************************************************************************
5901 ATOM_FUSION_SYSTEM_INFO_V1 Description
5902sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
5903ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
5904**********************************************************************************************************************/
5905
5906// this IntegrateSystemInfoTable is used for Trinity APU
5907typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
5908{
5909 ATOM_COMMON_TABLE_HEADER sHeader;
5910 ULONG ulBootUpEngineClock;
5911 ULONG ulDentistVCOFreq;
5912 ULONG ulBootUpUMAClock;
5913 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
5914 ULONG ulBootUpReqDisplayVector;
5915 ULONG ulOtherDisplayMisc;
5916 ULONG ulGPUCapInfo;
5917 ULONG ulSB_MMIO_Base_Addr;
5918 USHORT usRequestedPWMFreqInHz;
5919 UCHAR ucHtcTmpLmt;
5920 UCHAR ucHtcHystLmt;
5921 ULONG ulMinEngineClock;
5922 ULONG ulSystemConfig;
5923 ULONG ulCPUCapInfo;
5924 USHORT usNBP0Voltage;
5925 USHORT usNBP1Voltage;
5926 USHORT usBootUpNBVoltage;
5927 USHORT usExtDispConnInfoOffset;
5928 USHORT usPanelRefreshRateRange;
5929 UCHAR ucMemoryType;
5930 UCHAR ucUMAChannelNumber;
5931 UCHAR strVBIOSMsg[40];
5932 ATOM_TDP_CONFIG asTdpConfig;
5933 ULONG ulReserved[19];
5934 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
5935 ULONG ulGMCRestoreResetTime;
5936 ULONG ulMinimumNClk;
5937 ULONG ulIdleNClk;
5938 ULONG ulDDR_DLL_PowerUpTime;
5939 ULONG ulDDR_PLL_PowerUpTime;
5940 USHORT usPCIEClkSSPercentage;
5941 USHORT usPCIEClkSSType;
5942 USHORT usLvdsSSPercentage;
5943 USHORT usLvdsSSpreadRateIn10Hz;
5944 USHORT usHDMISSPercentage;
5945 USHORT usHDMISSpreadRateIn10Hz;
5946 USHORT usDVISSPercentage;
5947 USHORT usDVISSpreadRateIn10Hz;
5948 ULONG SclkDpmBoostMargin;
5949 ULONG SclkDpmThrottleMargin;
5950 USHORT SclkDpmTdpLimitPG;
5951 USHORT SclkDpmTdpLimitBoost;
5952 ULONG ulBoostEngineCLock;
5953 UCHAR ulBoostVid_2bit;
5954 UCHAR EnableBoost;
5955 USHORT GnbTdpLimit;
5956 USHORT usMaxLVDSPclkFreqInSingleLink;
5957 UCHAR ucLvdsMisc;
5958 UCHAR ucTravisLVDSVolAdjust;
5959 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5960 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5961 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5962 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5963 UCHAR ucLVDSOffToOnDelay_in4Ms;
5964 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5965 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5966 UCHAR ucMinAllowedBL_Level;
5967 ULONG ulLCDBitDepthControlVal;
5968 ULONG ulNbpStateMemclkFreq[4];
5969 USHORT usNBP2Voltage;
5970 USHORT usNBP3Voltage;
5971 ULONG ulNbpStateNClkFreq[4];
5972 UCHAR ucNBDPMEnable;
5973 UCHAR ucReserved[3];
5974 UCHAR ucDPMState0VclkFid;
5975 UCHAR ucDPMState0DclkFid;
5976 UCHAR ucDPMState1VclkFid;
5977 UCHAR ucDPMState1DclkFid;
5978 UCHAR ucDPMState2VclkFid;
5979 UCHAR ucDPMState2DclkFid;
5980 UCHAR ucDPMState3VclkFid;
5981 UCHAR ucDPMState3DclkFid;
5982 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
5983}ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
5984
5985// ulOtherDisplayMisc
5986#define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01
5987#define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02
5988#define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04
5989#define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08
5990
5991// ulGPUCapInfo
5992#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01
5993#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02
5994#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08
5995#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10
5996//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
5997#define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000
5998
5999//ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML
6000#define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000
6001
6002/**********************************************************************************************************************
6003 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
6004ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
6005ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6006ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6007sDISPCLK_Voltage: Report Display clock voltage requirement.
6008
6009ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:
6010 ATOM_DEVICE_CRT1_SUPPORT 0x0001
6011 ATOM_DEVICE_DFP1_SUPPORT 0x0008
6012 ATOM_DEVICE_DFP6_SUPPORT 0x0040
6013 ATOM_DEVICE_DFP2_SUPPORT 0x0080
6014 ATOM_DEVICE_DFP3_SUPPORT 0x0200
6015 ATOM_DEVICE_DFP4_SUPPORT 0x0400
6016 ATOM_DEVICE_DFP5_SUPPORT 0x0800
6017 ATOM_DEVICE_LCD1_SUPPORT 0x0002
6018ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
6019 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
6020 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6021 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
6022 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6023 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
6024 bit[3]=0: VBIOS fast boot is disable
6025 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
6026ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
6027 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
6028 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
6029 =1: DP mode use single PLL mode
6030 bit[3]=0: Enable AUX HW mode detection logic
6031 =1: Disable AUX HW mode detection logic
6032
6033ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
6034
6035usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
6036 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
6037
6038 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
6039 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
6040 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
6041 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6042 and enabling VariBri under the driver environment from PP table is optional.
6043
6044 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
6045 that BL control from GPU is expected.
6046 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
6047 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
6048 it's per platform
6049 and enabling VariBri under the driver environment from PP table is optional.
6050
6051ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt.
6052 Threshold on value to enter HTC_active state.
6053ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
6054 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
6055ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
6056ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
6057 =1: PCIE Power Gating Enabled
6058 Bit[1]=0: DDR-DLL shut-down feature disabled.
6059 1: DDR-DLL shut-down feature enabled.
6060 Bit[2]=0: DDR-PLL Power down feature disabled.
6061 1: DDR-PLL Power down feature enabled.
6062ulCPUCapInfo: TBD
6063usNBP0Voltage: VID for voltage on NB P0 State
6064usNBP1Voltage: VID for voltage on NB P1 State
6065usNBP2Voltage: VID for voltage on NB P2 State
6066usNBP3Voltage: VID for voltage on NB P3 State
6067usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
6068usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
6069usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
6070 to indicate a range.
6071 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
6072 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
6073 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
6074 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
6075ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
6076ucUMAChannelNumber: System memory channel numbers.
6077ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
6078ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
6079ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
6080sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
6081ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
6082ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
6083ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
6084ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
6085ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
6086usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
6087usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
6088usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
6089usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6090usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
6091usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6092usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
6093usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6094usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
6095ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
6096 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
6097 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6098 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
6099 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
6100 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
6101ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
6102 value to program Travis register LVDS_CTRL_4
6103ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
6104 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6105 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6106ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
6107 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6108 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6109
6110ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
6111 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6112 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6113
6114ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
6115 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6116 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6117
6118ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
6119 =0 means to use VBIOS default delay which is 125 ( 500ms ).
6120 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6121
6122ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
6123 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
6124 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6125 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6126
6127ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
6128 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
6129 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6130 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6131
6132ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
6133
6134ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate.
6135
6136**********************************************************************************************************************/
6137
6138// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU
6139typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8
6140{
6141 ATOM_COMMON_TABLE_HEADER sHeader;
6142 ULONG ulBootUpEngineClock;
6143 ULONG ulDentistVCOFreq;
6144 ULONG ulBootUpUMAClock;
6145 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4];
6146 ULONG ulBootUpReqDisplayVector;
6147 ULONG ulVBIOSMisc;
6148 ULONG ulGPUCapInfo;
6149 ULONG ulDISP_CLK2Freq;
6150 USHORT usRequestedPWMFreqInHz;
6151 UCHAR ucHtcTmpLmt;
6152 UCHAR ucHtcHystLmt;
6153 ULONG ulReserved2;
6154 ULONG ulSystemConfig;
6155 ULONG ulCPUCapInfo;
6156 ULONG ulReserved3;
6157 USHORT usGPUReservedSysMemSize;
6158 USHORT usExtDispConnInfoOffset;
6159 USHORT usPanelRefreshRateRange;
6160 UCHAR ucMemoryType;
6161 UCHAR ucUMAChannelNumber;
6162 UCHAR strVBIOSMsg[40];
6163 ATOM_TDP_CONFIG asTdpConfig;
6164 ULONG ulReserved[19];
6165 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5];
6166 ULONG ulGMCRestoreResetTime;
6167 ULONG ulReserved4;
6168 ULONG ulIdleNClk;
6169 ULONG ulDDR_DLL_PowerUpTime;
6170 ULONG ulDDR_PLL_PowerUpTime;
6171 USHORT usPCIEClkSSPercentage;
6172 USHORT usPCIEClkSSType;
6173 USHORT usLvdsSSPercentage;
6174 USHORT usLvdsSSpreadRateIn10Hz;
6175 USHORT usHDMISSPercentage;
6176 USHORT usHDMISSpreadRateIn10Hz;
6177 USHORT usDVISSPercentage;
6178 USHORT usDVISSpreadRateIn10Hz;
6179 ULONG ulGPUReservedSysMemBaseAddrLo;
6180 ULONG ulGPUReservedSysMemBaseAddrHi;
6181 ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage;
6182 ULONG ulReserved5;
6183 USHORT usMaxLVDSPclkFreqInSingleLink;
6184 UCHAR ucLvdsMisc;
6185 UCHAR ucTravisLVDSVolAdjust;
6186 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6187 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6188 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6189 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6190 UCHAR ucLVDSOffToOnDelay_in4Ms;
6191 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6192 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6193 UCHAR ucMinAllowedBL_Level;
6194 ULONG ulLCDBitDepthControlVal;
6195 ULONG ulNbpStateMemclkFreq[4];
6196 ULONG ulPSPVersion;
6197 ULONG ulNbpStateNClkFreq[4];
6198 USHORT usNBPStateVoltage[4];
6199 USHORT usBootUpNBVoltage;
6200 USHORT usReserved2;
6201 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
6202}ATOM_INTEGRATED_SYSTEM_INFO_V1_8;
6203
6204/**********************************************************************************************************************
6205 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description
6206ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
6207ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
6208ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
6209sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels).
6210
6211ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects:
6212 ATOM_DEVICE_CRT1_SUPPORT 0x0001
6213 ATOM_DEVICE_DFP1_SUPPORT 0x0008
6214 ATOM_DEVICE_DFP6_SUPPORT 0x0040
6215 ATOM_DEVICE_DFP2_SUPPORT 0x0080
6216 ATOM_DEVICE_DFP3_SUPPORT 0x0200
6217 ATOM_DEVICE_DFP4_SUPPORT 0x0400
6218 ATOM_DEVICE_DFP5_SUPPORT 0x0800
6219 ATOM_DEVICE_LCD1_SUPPORT 0x0002
6220
6221ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface
6222 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
6223 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
6224 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
6225 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
6226 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
6227 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
6228 bit[3]=0: VBIOS fast boot is disable
6229 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
6230
6231ulGPUCapInfo: bit[0~2]= Reserved
6232 bit[3]=0: Enable AUX HW mode detection logic
6233 =1: Disable AUX HW mode detection logic
6234 bit[4]=0: Disable DFS bypass feature
6235 =1: Enable DFS bypass feature
6236
6237usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
6238 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
6239
6240 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
6241 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
6242 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
6243 Changing BL using VBIOS function is functional in both driver and non-driver present environment;
6244 and enabling VariBri under the driver environment from PP table is optional.
6245
6246 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
6247 that BL control from GPU is expected.
6248 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
6249 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
6250 it's per platform
6251 and enabling VariBri under the driver environment from PP table is optional.
6252
6253ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state.
6254ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt.
6255 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
6256
6257ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled
6258 =1: PCIE Power Gating Enabled
6259 Bit[1]=0: DDR-DLL shut-down feature disabled.
6260 1: DDR-DLL shut-down feature enabled.
6261 Bit[2]=0: DDR-PLL Power down feature disabled.
6262 1: DDR-PLL Power down feature enabled.
6263 Bit[3]=0: GNB DPM is disabled
6264 =1: GNB DPM is enabled
6265ulCPUCapInfo: TBD
6266
6267usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure
6268usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
6269 to indicate a range.
6270 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
6271 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
6272 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
6273 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
6274
6275ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
6276ucUMAChannelNumber: System memory channel numbers.
6277
6278strVBIOSMsg[40]: VBIOS boot up customized message string
6279
6280sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
6281
6282ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
6283ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
6284ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns.
6285ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns.
6286
6287usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
6288usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
6289usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
6290usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6291usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
6292usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6293usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting.
6294usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
6295
6296usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB.
6297ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory.
6298ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory.
6299
6300usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
6301ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
6302 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
6303 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
6304 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
6305 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
6306 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
6307ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
6308 value to program Travis register LVDS_CTRL_4
6309ucLVDSPwrOnSeqDIGONtoDE_in4Ms:
6310 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
6311 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6312 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6313ucLVDSPwrOnDEtoVARY_BL_in4Ms:
6314 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
6315 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
6316 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6317ucLVDSPwrOffVARY_BLtoDE_in4Ms:
6318 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
6319 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6320 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6321ucLVDSPwrOffDEtoDIGON_in4Ms:
6322 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
6323 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
6324 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6325ucLVDSOffToOnDelay_in4Ms:
6326 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
6327 =0 means to use VBIOS default delay which is 125 ( 500ms ).
6328 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6329ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
6330 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
6331 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6332 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6333
6334ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
6335 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
6336 =0 means to use VBIOS default delay which is 0 ( 0ms ).
6337 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
6338ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
6339
6340ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL
6341
6342ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
6343ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
6344usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
6345usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
6346sExtDispConnInfo: Display connector information table provided to VBIOS
6347
6348**********************************************************************************************************************/
6349
6350typedef struct _ATOM_I2C_REG_INFO
6351{
6352 UCHAR ucI2cRegIndex;
6353 UCHAR ucI2cRegVal;
6354}ATOM_I2C_REG_INFO;
6355
6356// this IntegrateSystemInfoTable is used for Carrizo
6357typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
6358{
6359 ATOM_COMMON_TABLE_HEADER sHeader;
6360 ULONG ulBootUpEngineClock;
6361 ULONG ulDentistVCOFreq;
6362 ULONG ulBootUpUMAClock;
6363 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error
6364 ULONG ulBootUpReqDisplayVector;
6365 ULONG ulVBIOSMisc;
6366 ULONG ulGPUCapInfo;
6367 ULONG ulDISP_CLK2Freq;
6368 USHORT usRequestedPWMFreqInHz;
6369 UCHAR ucHtcTmpLmt;
6370 UCHAR ucHtcHystLmt;
6371 ULONG ulReserved2;
6372 ULONG ulSystemConfig;
6373 ULONG ulCPUCapInfo;
6374 ULONG ulReserved3;
6375 USHORT usGPUReservedSysMemSize;
6376 USHORT usExtDispConnInfoOffset;
6377 USHORT usPanelRefreshRateRange;
6378 UCHAR ucMemoryType;
6379 UCHAR ucUMAChannelNumber;
6380 UCHAR strVBIOSMsg[40];
6381 ATOM_TDP_CONFIG asTdpConfig;
6382 UCHAR ucExtHDMIReDrvSlvAddr;
6383 UCHAR ucExtHDMIReDrvRegNum;
6384 ATOM_I2C_REG_INFO asExtHDMIRegSetting[9];
6385 ULONG ulReserved[2];
6386 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8];
6387 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error
6388 ULONG ulGMCRestoreResetTime;
6389 ULONG ulReserved4;
6390 ULONG ulIdleNClk;
6391 ULONG ulDDR_DLL_PowerUpTime;
6392 ULONG ulDDR_PLL_PowerUpTime;
6393 USHORT usPCIEClkSSPercentage;
6394 USHORT usPCIEClkSSType;
6395 USHORT usLvdsSSPercentage;
6396 USHORT usLvdsSSpreadRateIn10Hz;
6397 USHORT usHDMISSPercentage;
6398 USHORT usHDMISSpreadRateIn10Hz;
6399 USHORT usDVISSPercentage;
6400 USHORT usDVISSpreadRateIn10Hz;
6401 ULONG ulGPUReservedSysMemBaseAddrLo;
6402 ULONG ulGPUReservedSysMemBaseAddrHi;
6403 ULONG ulReserved5[3];
6404 USHORT usMaxLVDSPclkFreqInSingleLink;
6405 UCHAR ucLvdsMisc;
6406 UCHAR ucTravisLVDSVolAdjust;
6407 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6408 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6409 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6410 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6411 UCHAR ucLVDSOffToOnDelay_in4Ms;
6412 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6413 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6414 UCHAR ucMinAllowedBL_Level;
6415 ULONG ulLCDBitDepthControlVal;
6416 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed.
6417 ULONG ulPSPVersion;
6418 ULONG ulNbpStateNClkFreq[4];
6419 USHORT usNBPStateVoltage[4];
6420 USHORT usBootUpNBVoltage;
6421 UCHAR ucEDPv1_4VSMode;
6422 UCHAR ucReserved2;
6423 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
6424}ATOM_INTEGRATED_SYSTEM_INFO_V1_9;
6425
6426
6427// definition for ucEDPv1_4VSMode
6428#define EDP_VS_LEGACY_MODE 0
6429#define EDP_VS_LOW_VDIFF_MODE 1
6430#define EDP_VS_HIGH_VDIFF_MODE 2
6431#define EDP_VS_STRETCH_MODE 3
6432#define EDP_VS_SINGLE_VDIFF_MODE 4
6433#define EDP_VS_VARIABLE_PREM_MODE 5
6434
6435
6436// ulGPUCapInfo
6437#define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT 0x08
6438#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS 0x10
6439//ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
6440#define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE 0x00010000
6441//ulGPUCapInfo[18]=1 indicate the IOMMU is not available
6442#define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE 0x00040000
6443//ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened.
6444#define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE 0x00080000
6445
6446
6447typedef struct _DPHY_TIMING_PARA
6448{
6449 UCHAR ucProfileID; // SENSOR_PROFILES
6450 ULONG ucPara;
6451} DPHY_TIMING_PARA;
6452
6453typedef struct _DPHY_ELEC_PARA
6454{
6455 USHORT usPara[3];
6456} DPHY_ELEC_PARA;
6457
6458typedef struct _CAMERA_MODULE_INFO
6459{
6460 UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user
6461 UCHAR strModuleName[8];
6462 DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor
6463} CAMERA_MODULE_INFO;
6464
6465typedef struct _FLASHLIGHT_INFO
6466{
6467 UCHAR ucID; // 0: Rear, 1: Front
6468 UCHAR strName[8];
6469} FLASHLIGHT_INFO;
6470
6471typedef struct _CAMERA_DATA
6472{
6473 ULONG ulVersionCode;
6474 CAMERA_MODULE_INFO asCameraInfo[3]; // Assuming 3 camera sensors max
6475 FLASHLIGHT_INFO asFlashInfo; // Assuming 1 flashlight max
6476 DPHY_ELEC_PARA asDphyElecPara;
6477 ULONG ulCrcVal; // CRC
6478}CAMERA_DATA;
6479
6480typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10
6481{
6482 ATOM_COMMON_TABLE_HEADER sHeader;
6483 ULONG ulBootUpEngineClock;
6484 ULONG ulDentistVCOFreq;
6485 ULONG ulBootUpUMAClock;
6486 ULONG ulReserved0[8];
6487 ULONG ulBootUpReqDisplayVector;
6488 ULONG ulVBIOSMisc;
6489 ULONG ulGPUCapInfo;
6490 ULONG ulReserved1;
6491 USHORT usRequestedPWMFreqInHz;
6492 UCHAR ucHtcTmpLmt;
6493 UCHAR ucHtcHystLmt;
6494 ULONG ulReserved2;
6495 ULONG ulSystemConfig;
6496 ULONG ulCPUCapInfo;
6497 ULONG ulReserved3;
6498 USHORT usGPUReservedSysMemSize;
6499 USHORT usExtDispConnInfoOffset;
6500 USHORT usPanelRefreshRateRange;
6501 UCHAR ucMemoryType;
6502 UCHAR ucUMAChannelNumber;
6503 ULONG ulMsgReserved[10];
6504 ATOM_TDP_CONFIG asTdpConfig;
6505 ULONG ulReserved[7];
6506 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8];
6507 ULONG ulReserved6[10];
6508 ULONG ulGMCRestoreResetTime;
6509 ULONG ulReserved4;
6510 ULONG ulIdleNClk;
6511 ULONG ulDDR_DLL_PowerUpTime;
6512 ULONG ulDDR_PLL_PowerUpTime;
6513 USHORT usPCIEClkSSPercentage;
6514 USHORT usPCIEClkSSType;
6515 USHORT usLvdsSSPercentage;
6516 USHORT usLvdsSSpreadRateIn10Hz;
6517 USHORT usHDMISSPercentage;
6518 USHORT usHDMISSpreadRateIn10Hz;
6519 USHORT usDVISSPercentage;
6520 USHORT usDVISSpreadRateIn10Hz;
6521 ULONG ulGPUReservedSysMemBaseAddrLo;
6522 ULONG ulGPUReservedSysMemBaseAddrHi;
6523 ULONG ulReserved5[3];
6524 USHORT usMaxLVDSPclkFreqInSingleLink;
6525 UCHAR ucLvdsMisc;
6526 UCHAR ucTravisLVDSVolAdjust;
6527 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6528 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6529 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6530 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6531 UCHAR ucLVDSOffToOnDelay_in4Ms;
6532 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6533 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6534 UCHAR ucMinAllowedBL_Level;
6535 ULONG ulLCDBitDepthControlVal;
6536 ULONG ulNbpStateMemclkFreq[2];
6537 ULONG ulReserved7[2];
6538 ULONG ulPSPVersion;
6539 ULONG ulNbpStateNClkFreq[4];
6540 USHORT usNBPStateVoltage[4];
6541 USHORT usBootUpNBVoltage;
6542 UCHAR ucEDPv1_4VSMode;
6543 UCHAR ucReserved2;
6544 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
6545 CAMERA_DATA asCameraInfo;
6546 ULONG ulReserved8[29];
6547}ATOM_INTEGRATED_SYSTEM_INFO_V1_10;
6548
6549
6550// this Table is used for Kaveri/Kabini APU
6551typedef struct _ATOM_FUSION_SYSTEM_INFO_V2
6552{
6553 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
6554 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure
6555}ATOM_FUSION_SYSTEM_INFO_V2;
6556
6557
6558typedef struct _ATOM_FUSION_SYSTEM_INFO_V3
6559{
6560 ATOM_INTEGRATED_SYSTEM_INFO_V1_10 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
6561 ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable
6562}ATOM_FUSION_SYSTEM_INFO_V3;
6563
6564#define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x800
6565
6566/**************************************************************************/
6567// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
6568//Memory SS Info Table
6569//Define Memory Clock SS chip ID
6570#define ICS91719 1
6571#define ICS91720 2
6572
6573//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
6574typedef struct _ATOM_I2C_DATA_RECORD
6575{
6576 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
6577 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually
6578}ATOM_I2C_DATA_RECORD;
6579
6580
6581//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
6582typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
6583{
6584 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap.
6585 UCHAR ucSSChipID; //SS chip being used
6586 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
6587 UCHAR ucNumOfI2CDataRecords; //number of data block
6588 ATOM_I2C_DATA_RECORD asI2CData[1];
6589}ATOM_I2C_DEVICE_SETUP_INFO;
6590
6591//==========================================================================================
6592typedef struct _ATOM_ASIC_MVDD_INFO
6593{
6594 ATOM_COMMON_TABLE_HEADER sHeader;
6595 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
6596}ATOM_ASIC_MVDD_INFO;
6597
6598//==========================================================================================
6599#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO
6600
6601//==========================================================================================
6602/**************************************************************************/
6603
6604typedef struct _ATOM_ASIC_SS_ASSIGNMENT
6605{
6606 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
6607 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
6608 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
6609 UCHAR ucClockIndication; //Indicate which clock source needs SS
6610 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
6611 UCHAR ucReserved[2];
6612}ATOM_ASIC_SS_ASSIGNMENT;
6613
6614//Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type.
6615//SS is not required or enabled if a match is not found.
6616#define ASIC_INTERNAL_MEMORY_SS 1
6617#define ASIC_INTERNAL_ENGINE_SS 2
6618#define ASIC_INTERNAL_UVD_SS 3
6619#define ASIC_INTERNAL_SS_ON_TMDS 4
6620#define ASIC_INTERNAL_SS_ON_HDMI 5
6621#define ASIC_INTERNAL_SS_ON_LVDS 6
6622#define ASIC_INTERNAL_SS_ON_DP 7
6623#define ASIC_INTERNAL_SS_ON_DCPLL 8
6624#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9
6625#define ASIC_INTERNAL_VCE_SS 10
6626#define ASIC_INTERNAL_GPUPLL_SS 11
6627
6628
6629typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
6630{
6631 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6632 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
6633 USHORT usSpreadSpectrumPercentage; //in unit of 0.01%
6634 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
6635 UCHAR ucClockIndication; //Indicate which clock source needs SS
6636 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
6637 UCHAR ucReserved[2];
6638}ATOM_ASIC_SS_ASSIGNMENT_V2;
6639
6640//ucSpreadSpectrumMode
6641//#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000
6642//#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000
6643//#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001
6644//#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001
6645//#define ATOM_INTERNAL_SS_MASK 0x00000000
6646//#define ATOM_EXTERNAL_SS_MASK 0x00000002
6647
6648typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
6649{
6650 ATOM_COMMON_TABLE_HEADER sHeader;
6651 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
6652}ATOM_ASIC_INTERNAL_SS_INFO;
6653
6654typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
6655{
6656 ATOM_COMMON_TABLE_HEADER sHeader;
6657 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only.
6658}ATOM_ASIC_INTERNAL_SS_INFO_V2;
6659
6660typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
6661{
6662 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
6663 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
6664 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4
6665 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq
6666 UCHAR ucClockIndication; //Indicate which clock source needs SS
6667 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
6668 UCHAR ucReserved[2];
6669}ATOM_ASIC_SS_ASSIGNMENT_V3;
6670
6671//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode
6672#define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01
6673#define SS_MODE_V3_EXTERNAL_SS_MASK 0x02
6674#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10
6675
6676typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
6677{
6678 ATOM_COMMON_TABLE_HEADER sHeader;
6679 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only.
6680}ATOM_ASIC_INTERNAL_SS_INFO_V3;
6681
6682
6683//==============================Scratch Pad Definition Portion===============================
6684#define ATOM_DEVICE_CONNECT_INFO_DEF 0
6685#define ATOM_ROM_LOCATION_DEF 1
6686#define ATOM_TV_STANDARD_DEF 2
6687#define ATOM_ACTIVE_INFO_DEF 3
6688#define ATOM_LCD_INFO_DEF 4
6689#define ATOM_DOS_REQ_INFO_DEF 5
6690#define ATOM_ACC_CHANGE_INFO_DEF 6
6691#define ATOM_DOS_MODE_INFO_DEF 7
6692#define ATOM_I2C_CHANNEL_STATUS_DEF 8
6693#define ATOM_I2C_CHANNEL_STATUS1_DEF 9
6694#define ATOM_INTERNAL_TIMER_DEF 10
6695
6696// BIOS_0_SCRATCH Definition
6697#define ATOM_S0_CRT1_MONO 0x00000001L
6698#define ATOM_S0_CRT1_COLOR 0x00000002L
6699#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
6700
6701#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L
6702#define ATOM_S0_TV1_SVIDEO_A 0x00000008L
6703#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
6704
6705#define ATOM_S0_CV_A 0x00000010L
6706#define ATOM_S0_CV_DIN_A 0x00000020L
6707#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
6708
6709
6710#define ATOM_S0_CRT2_MONO 0x00000100L
6711#define ATOM_S0_CRT2_COLOR 0x00000200L
6712#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
6713
6714#define ATOM_S0_TV1_COMPOSITE 0x00000400L
6715#define ATOM_S0_TV1_SVIDEO 0x00000800L
6716#define ATOM_S0_TV1_SCART 0x00004000L
6717#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
6718
6719#define ATOM_S0_CV 0x00001000L
6720#define ATOM_S0_CV_DIN 0x00002000L
6721#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN)
6722
6723#define ATOM_S0_DFP1 0x00010000L
6724#define ATOM_S0_DFP2 0x00020000L
6725#define ATOM_S0_LCD1 0x00040000L
6726#define ATOM_S0_LCD2 0x00080000L
6727#define ATOM_S0_DFP6 0x00100000L
6728#define ATOM_S0_DFP3 0x00200000L
6729#define ATOM_S0_DFP4 0x00400000L
6730#define ATOM_S0_DFP5 0x00800000L
6731
6732
6733#define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
6734
6735#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with
6736 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx
6737
6738#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L
6739#define ATOM_S0_THERMAL_STATE_SHIFT 26
6740
6741#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
6742#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
6743
6744#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
6745#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2
6746#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
6747#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
6748
6749//Byte aligned defintion for BIOS usage
6750#define ATOM_S0_CRT1_MONOb0 0x01
6751#define ATOM_S0_CRT1_COLORb0 0x02
6752#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
6753
6754#define ATOM_S0_TV1_COMPOSITEb0 0x04
6755#define ATOM_S0_TV1_SVIDEOb0 0x08
6756#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
6757
6758#define ATOM_S0_CVb0 0x10
6759#define ATOM_S0_CV_DINb0 0x20
6760#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
6761
6762#define ATOM_S0_CRT2_MONOb1 0x01
6763#define ATOM_S0_CRT2_COLORb1 0x02
6764#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
6765
6766#define ATOM_S0_TV1_COMPOSITEb1 0x04
6767#define ATOM_S0_TV1_SVIDEOb1 0x08
6768#define ATOM_S0_TV1_SCARTb1 0x40
6769#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
6770
6771#define ATOM_S0_CVb1 0x10
6772#define ATOM_S0_CV_DINb1 0x20
6773#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
6774
6775#define ATOM_S0_DFP1b2 0x01
6776#define ATOM_S0_DFP2b2 0x02
6777#define ATOM_S0_LCD1b2 0x04
6778#define ATOM_S0_LCD2b2 0x08
6779#define ATOM_S0_DFP6b2 0x10
6780#define ATOM_S0_DFP3b2 0x20
6781#define ATOM_S0_DFP4b2 0x40
6782#define ATOM_S0_DFP5b2 0x80
6783
6784
6785#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C
6786#define ATOM_S0_THERMAL_STATE_SHIFTb3 2
6787
6788#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
6789#define ATOM_S0_LCD1_SHIFT 18
6790
6791// BIOS_1_SCRATCH Definition
6792#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL
6793#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L
6794
6795// BIOS_2_SCRATCH Definition
6796#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL
6797#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L
6798#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
6799
6800#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L
6801#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
6802#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L
6803
6804#define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L
6805#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L
6806
6807#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0
6808#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1
6809#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2
6810#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3
6811#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
6812#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L
6813
6814
6815//Byte aligned defintion for BIOS usage
6816#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F
6817#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
6818#define ATOM_S2_DEVICE_DPMS_STATEb2 0x01
6819
6820#define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
6821#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20
6822#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0
6823
6824
6825// BIOS_3_SCRATCH Definition
6826#define ATOM_S3_CRT1_ACTIVE 0x00000001L
6827#define ATOM_S3_LCD1_ACTIVE 0x00000002L
6828#define ATOM_S3_TV1_ACTIVE 0x00000004L
6829#define ATOM_S3_DFP1_ACTIVE 0x00000008L
6830#define ATOM_S3_CRT2_ACTIVE 0x00000010L
6831#define ATOM_S3_LCD2_ACTIVE 0x00000020L
6832#define ATOM_S3_DFP6_ACTIVE 0x00000040L
6833#define ATOM_S3_DFP2_ACTIVE 0x00000080L
6834#define ATOM_S3_CV_ACTIVE 0x00000100L
6835#define ATOM_S3_DFP3_ACTIVE 0x00000200L
6836#define ATOM_S3_DFP4_ACTIVE 0x00000400L
6837#define ATOM_S3_DFP5_ACTIVE 0x00000800L
6838
6839
6840#define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL
6841
6842#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L
6843#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
6844
6845#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L
6846#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L
6847#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L
6848#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L
6849#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L
6850#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L
6851#define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L
6852#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L
6853#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L
6854#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L
6855#define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L
6856#define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L
6857
6858
6859#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
6860#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L
6861//Below two definitions are not supported in pplib, but in the old powerplay in DAL
6862#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L
6863#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L
6864
6865
6866
6867//Byte aligned defintion for BIOS usage
6868#define ATOM_S3_CRT1_ACTIVEb0 0x01
6869#define ATOM_S3_LCD1_ACTIVEb0 0x02
6870#define ATOM_S3_TV1_ACTIVEb0 0x04
6871#define ATOM_S3_DFP1_ACTIVEb0 0x08
6872#define ATOM_S3_CRT2_ACTIVEb0 0x10
6873#define ATOM_S3_LCD2_ACTIVEb0 0x20
6874#define ATOM_S3_DFP6_ACTIVEb0 0x40
6875#define ATOM_S3_DFP2_ACTIVEb0 0x80
6876#define ATOM_S3_CV_ACTIVEb1 0x01
6877#define ATOM_S3_DFP3_ACTIVEb1 0x02
6878#define ATOM_S3_DFP4_ACTIVEb1 0x04
6879#define ATOM_S3_DFP5_ACTIVEb1 0x08
6880
6881
6882#define ATOM_S3_ACTIVE_CRTC1w0 0xFFF
6883
6884#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01
6885#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02
6886#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04
6887#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08
6888#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10
6889#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20
6890#define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40
6891#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80
6892#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01
6893#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02
6894#define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04
6895#define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08
6896
6897
6898#define ATOM_S3_ACTIVE_CRTC2w1 0xFFF
6899
6900
6901// BIOS_4_SCRATCH Definition
6902#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL
6903#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L
6904#define ATOM_S4_LCD1_REFRESH_SHIFT 8
6905
6906//Byte aligned defintion for BIOS usage
6907#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF
6908#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0
6909#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0
6910
6911// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
6912#define ATOM_S5_DOS_REQ_CRT1b0 0x01
6913#define ATOM_S5_DOS_REQ_LCD1b0 0x02
6914#define ATOM_S5_DOS_REQ_TV1b0 0x04
6915#define ATOM_S5_DOS_REQ_DFP1b0 0x08
6916#define ATOM_S5_DOS_REQ_CRT2b0 0x10
6917#define ATOM_S5_DOS_REQ_LCD2b0 0x20
6918#define ATOM_S5_DOS_REQ_DFP6b0 0x40
6919#define ATOM_S5_DOS_REQ_DFP2b0 0x80
6920#define ATOM_S5_DOS_REQ_CVb1 0x01
6921#define ATOM_S5_DOS_REQ_DFP3b1 0x02
6922#define ATOM_S5_DOS_REQ_DFP4b1 0x04
6923#define ATOM_S5_DOS_REQ_DFP5b1 0x08
6924
6925
6926#define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF
6927
6928#define ATOM_S5_DOS_REQ_CRT1 0x0001
6929#define ATOM_S5_DOS_REQ_LCD1 0x0002
6930#define ATOM_S5_DOS_REQ_TV1 0x0004
6931#define ATOM_S5_DOS_REQ_DFP1 0x0008
6932#define ATOM_S5_DOS_REQ_CRT2 0x0010
6933#define ATOM_S5_DOS_REQ_LCD2 0x0020
6934#define ATOM_S5_DOS_REQ_DFP6 0x0040
6935#define ATOM_S5_DOS_REQ_DFP2 0x0080
6936#define ATOM_S5_DOS_REQ_CV 0x0100
6937#define ATOM_S5_DOS_REQ_DFP3 0x0200
6938#define ATOM_S5_DOS_REQ_DFP4 0x0400
6939#define ATOM_S5_DOS_REQ_DFP5 0x0800
6940
6941#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0
6942#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0
6943#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0
6944#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1
6945#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
6946 (ATOM_S5_DOS_FORCE_CVb3<<8))
6947// BIOS_6_SCRATCH Definition
6948#define ATOM_S6_DEVICE_CHANGE 0x00000001L
6949#define ATOM_S6_SCALER_CHANGE 0x00000002L
6950#define ATOM_S6_LID_CHANGE 0x00000004L
6951#define ATOM_S6_DOCKING_CHANGE 0x00000008L
6952#define ATOM_S6_ACC_MODE 0x00000010L
6953#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L
6954#define ATOM_S6_LID_STATE 0x00000040L
6955#define ATOM_S6_DOCK_STATE 0x00000080L
6956#define ATOM_S6_CRITICAL_STATE 0x00000100L
6957#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L
6958#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L
6959#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L
6960#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD
6961#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD
6962
6963#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
6964#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
6965
6966#define ATOM_S6_ACC_REQ_CRT1 0x00010000L
6967#define ATOM_S6_ACC_REQ_LCD1 0x00020000L
6968#define ATOM_S6_ACC_REQ_TV1 0x00040000L
6969#define ATOM_S6_ACC_REQ_DFP1 0x00080000L
6970#define ATOM_S6_ACC_REQ_CRT2 0x00100000L
6971#define ATOM_S6_ACC_REQ_LCD2 0x00200000L
6972#define ATOM_S6_ACC_REQ_DFP6 0x00400000L
6973#define ATOM_S6_ACC_REQ_DFP2 0x00800000L
6974#define ATOM_S6_ACC_REQ_CV 0x01000000L
6975#define ATOM_S6_ACC_REQ_DFP3 0x02000000L
6976#define ATOM_S6_ACC_REQ_DFP4 0x04000000L
6977#define ATOM_S6_ACC_REQ_DFP5 0x08000000L
6978
6979#define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L
6980#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L
6981#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L
6982#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L
6983#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L
6984
6985//Byte aligned defintion for BIOS usage
6986#define ATOM_S6_DEVICE_CHANGEb0 0x01
6987#define ATOM_S6_SCALER_CHANGEb0 0x02
6988#define ATOM_S6_LID_CHANGEb0 0x04
6989#define ATOM_S6_DOCKING_CHANGEb0 0x08
6990#define ATOM_S6_ACC_MODEb0 0x10
6991#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20
6992#define ATOM_S6_LID_STATEb0 0x40
6993#define ATOM_S6_DOCK_STATEb0 0x80
6994#define ATOM_S6_CRITICAL_STATEb1 0x01
6995#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02
6996#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04
6997#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
6998#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10
6999#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
7000
7001#define ATOM_S6_ACC_REQ_CRT1b2 0x01
7002#define ATOM_S6_ACC_REQ_LCD1b2 0x02
7003#define ATOM_S6_ACC_REQ_TV1b2 0x04
7004#define ATOM_S6_ACC_REQ_DFP1b2 0x08
7005#define ATOM_S6_ACC_REQ_CRT2b2 0x10
7006#define ATOM_S6_ACC_REQ_LCD2b2 0x20
7007#define ATOM_S6_ACC_REQ_DFP6b2 0x40
7008#define ATOM_S6_ACC_REQ_DFP2b2 0x80
7009#define ATOM_S6_ACC_REQ_CVb3 0x01
7010#define ATOM_S6_ACC_REQ_DFP3b3 0x02
7011#define ATOM_S6_ACC_REQ_DFP4b3 0x04
7012#define ATOM_S6_ACC_REQ_DFP5b3 0x08
7013
7014#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0
7015#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
7016#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
7017#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40
7018#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80
7019
7020#define ATOM_S6_DEVICE_CHANGE_SHIFT 0
7021#define ATOM_S6_SCALER_CHANGE_SHIFT 1
7022#define ATOM_S6_LID_CHANGE_SHIFT 2
7023#define ATOM_S6_DOCKING_CHANGE_SHIFT 3
7024#define ATOM_S6_ACC_MODE_SHIFT 4
7025#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5
7026#define ATOM_S6_LID_STATE_SHIFT 6
7027#define ATOM_S6_DOCK_STATE_SHIFT 7
7028#define ATOM_S6_CRITICAL_STATE_SHIFT 8
7029#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9
7030#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10
7031#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11
7032#define ATOM_S6_REQ_SCALER_SHIFT 12
7033#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13
7034#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14
7035#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15
7036#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28
7037#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29
7038#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30
7039#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31
7040
7041// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
7042#define ATOM_S7_DOS_MODE_TYPEb0 0x03
7043#define ATOM_S7_DOS_MODE_VGAb0 0x00
7044#define ATOM_S7_DOS_MODE_VESAb0 0x01
7045#define ATOM_S7_DOS_MODE_EXTb0 0x02
7046#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C
7047#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0
7048#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01
7049#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02
7050#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200
7051#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF
7052
7053#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
7054
7055// BIOS_8_SCRATCH Definition
7056#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF
7057#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000
7058
7059#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0
7060#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16
7061
7062// BIOS_9_SCRATCH Definition
7063#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
7064#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF
7065#endif
7066#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
7067#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000
7068#endif
7069#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
7070#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
7071#endif
7072#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
7073#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16
7074#endif
7075
7076
7077#define ATOM_FLAG_SET 0x20
7078#define ATOM_FLAG_CLEAR 0
7079#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
7080#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
7081#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
7082#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
7083#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
7084
7085#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
7086#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
7087
7088#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
7089#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
7090#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
7091
7092#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
7093#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
7094#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
7095
7096#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
7097#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
7098
7099#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
7100#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
7101
7102#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
7103#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
7104
7105#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
7106
7107#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
7108
7109#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
7110#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
7111#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
7112#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
7113
7114/****************************************************************************/
7115//Portion II: Definitinos only used in Driver
7116/****************************************************************************/
7117
7118// Macros used by driver
7119
7120#ifdef __cplusplus
7121#define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
7122
7123#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
7124#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
7125#else // not __cplusplus
7126#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
7127
7128#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
7129#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
7130#endif // __cplusplus
7131
7132#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
7133#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
7134
7135/****************************************************************************/
7136//Portion III: Definitinos only used in VBIOS
7137/****************************************************************************/
7138#define ATOM_DAC_SRC 0x80
7139#define ATOM_SRC_DAC1 0
7140#define ATOM_SRC_DAC2 0x80
7141
7142
7143
7144typedef struct _MEMORY_PLLINIT_PARAMETERS
7145{
7146 ULONG ulTargetMemoryClock; //In 10Khz unit
7147 UCHAR ucAction; //not define yet
7148 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
7149 UCHAR ucFbDiv; //FB value
7150 UCHAR ucPostDiv; //Post div
7151}MEMORY_PLLINIT_PARAMETERS;
7152
7153#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS
7154
7155
7156#define GPIO_PIN_WRITE 0x01
7157#define GPIO_PIN_READ 0x00
7158
7159typedef struct _GPIO_PIN_CONTROL_PARAMETERS
7160{
7161 UCHAR ucGPIO_ID; //return value, read from GPIO pins
7162 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
7163 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
7164 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
7165}GPIO_PIN_CONTROL_PARAMETERS;
7166
7167typedef struct _ENABLE_SCALER_PARAMETERS
7168{
7169 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
7170 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
7171 UCHAR ucTVStandard; //
7172 UCHAR ucPadding[1];
7173}ENABLE_SCALER_PARAMETERS;
7174#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
7175
7176//ucEnable:
7177#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0
7178#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
7179#define SCALER_ENABLE_2TAP_ALPHA_MODE 2
7180#define SCALER_ENABLE_MULTITAP_MODE 3
7181
7182typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
7183{
7184 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
7185 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
7186 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
7187 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
7188 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7189}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
7190
7191typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
7192{
7193 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
7194 ENABLE_CRTC_PARAMETERS sReserved;
7195}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
7196
7197typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
7198{
7199 USHORT usHight; // Image Hight
7200 USHORT usWidth; // Image Width
7201 UCHAR ucSurface; // Surface 1 or 2
7202 UCHAR ucPadding[3];
7203}ENABLE_GRAPH_SURFACE_PARAMETERS;
7204
7205typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
7206{
7207 USHORT usHight; // Image Hight
7208 USHORT usWidth; // Image Width
7209 UCHAR ucSurface; // Surface 1 or 2
7210 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7211 UCHAR ucPadding[2];
7212}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
7213
7214typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
7215{
7216 USHORT usHight; // Image Hight
7217 USHORT usWidth; // Image Width
7218 UCHAR ucSurface; // Surface 1 or 2
7219 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7220 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0.
7221}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
7222
7223typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
7224{
7225 USHORT usHight; // Image Hight
7226 USHORT usWidth; // Image Width
7227 USHORT usGraphPitch;
7228 UCHAR ucColorDepth;
7229 UCHAR ucPixelFormat;
7230 UCHAR ucSurface; // Surface 1 or 2
7231 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7232 UCHAR ucModeType;
7233 UCHAR ucReserved;
7234}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;
7235
7236// ucEnable
7237#define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f
7238#define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10
7239
7240typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
7241{
7242 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
7243 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one
7244}ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
7245
7246typedef struct _MEMORY_CLEAN_UP_PARAMETERS
7247{
7248 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address
7249 USHORT usMemorySize; //8Kb blocks aligned
7250}MEMORY_CLEAN_UP_PARAMETERS;
7251
7252#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
7253
7254typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
7255{
7256 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
7257 USHORT usY_Size;
7258}GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
7259
7260typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
7261{
7262 union{
7263 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC
7264 USHORT usSurface;
7265 };
7266 USHORT usY_Size;
7267 USHORT usDispXStart;
7268 USHORT usDispYStart;
7269}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2;
7270
7271
7272typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3
7273{
7274 UCHAR ucLutId;
7275 UCHAR ucAction;
7276 USHORT usLutStartIndex;
7277 USHORT usLutLength;
7278 USHORT usLutOffsetInVram;
7279}PALETTE_DATA_CONTROL_PARAMETERS_V3;
7280
7281// ucAction:
7282#define PALETTE_DATA_AUTO_FILL 1
7283#define PALETTE_DATA_READ 2
7284#define PALETTE_DATA_WRITE 3
7285
7286
7287typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2
7288{
7289 UCHAR ucInterruptId;
7290 UCHAR ucServiceId;
7291 UCHAR ucStatus;
7292 UCHAR ucReserved;
7293}INTERRUPT_SERVICE_PARAMETER_V2;
7294
7295// ucInterruptId
7296#define HDP1_INTERRUPT_ID 1
7297#define HDP2_INTERRUPT_ID 2
7298#define HDP3_INTERRUPT_ID 3
7299#define HDP4_INTERRUPT_ID 4
7300#define HDP5_INTERRUPT_ID 5
7301#define HDP6_INTERRUPT_ID 6
7302#define SW_INTERRUPT_ID 11
7303
7304// ucAction
7305#define INTERRUPT_SERVICE_GEN_SW_INT 1
7306#define INTERRUPT_SERVICE_GET_STATUS 2
7307
7308 // ucStatus
7309#define INTERRUPT_STATUS__INT_TRIGGER 1
7310#define INTERRUPT_STATUS__HPD_HIGH 2
7311
7312typedef struct _EFUSE_INPUT_PARAMETER
7313{
7314 USHORT usEfuseIndex;
7315 UCHAR ucBitShift;
7316 UCHAR ucBitLength;
7317}EFUSE_INPUT_PARAMETER;
7318
7319// ReadEfuseValue command table input/output parameter
7320typedef union _READ_EFUSE_VALUE_PARAMETER
7321{
7322 EFUSE_INPUT_PARAMETER sEfuse;
7323 ULONG ulEfuseValue;
7324}READ_EFUSE_VALUE_PARAMETER;
7325
7326typedef struct _INDIRECT_IO_ACCESS
7327{
7328 ATOM_COMMON_TABLE_HEADER sHeader;
7329 UCHAR IOAccessSequence[256];
7330} INDIRECT_IO_ACCESS;
7331
7332#define INDIRECT_READ 0x00
7333#define INDIRECT_WRITE 0x80
7334
7335#define INDIRECT_IO_MM 0
7336#define INDIRECT_IO_PLL 1
7337#define INDIRECT_IO_MC 2
7338#define INDIRECT_IO_PCIE 3
7339#define INDIRECT_IO_PCIEP 4
7340#define INDIRECT_IO_NBMISC 5
7341#define INDIRECT_IO_SMU 5
7342
7343#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ
7344#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE
7345#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ
7346#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE
7347#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ
7348#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE
7349#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ
7350#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE
7351#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ
7352#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE
7353#define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ
7354#define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE
7355
7356
7357typedef struct _ATOM_OEM_INFO
7358{
7359 ATOM_COMMON_TABLE_HEADER sHeader;
7360 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
7361}ATOM_OEM_INFO;
7362
7363typedef struct _ATOM_TV_MODE
7364{
7365 UCHAR ucVMode_Num; //Video mode number
7366 UCHAR ucTV_Mode_Num; //Internal TV mode number
7367}ATOM_TV_MODE;
7368
7369typedef struct _ATOM_BIOS_INT_TVSTD_MODE
7370{
7371 ATOM_COMMON_TABLE_HEADER sHeader;
7372 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table
7373 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table
7374 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table
7375 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
7376 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table
7377}ATOM_BIOS_INT_TVSTD_MODE;
7378
7379
7380typedef struct _ATOM_TV_MODE_SCALER_PTR
7381{
7382 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients
7383 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients
7384 UCHAR ucTV_Mode_Num;
7385}ATOM_TV_MODE_SCALER_PTR;
7386
7387typedef struct _ATOM_STANDARD_VESA_TIMING
7388{
7389 ATOM_COMMON_TABLE_HEADER sHeader;
7390 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation
7391}ATOM_STANDARD_VESA_TIMING;
7392
7393
7394typedef struct _ATOM_STD_FORMAT
7395{
7396 USHORT usSTD_HDisp;
7397 USHORT usSTD_VDisp;
7398 USHORT usSTD_RefreshRate;
7399 USHORT usReserved;
7400}ATOM_STD_FORMAT;
7401
7402typedef struct _ATOM_VESA_TO_EXTENDED_MODE
7403{
7404 USHORT usVESA_ModeNumber;
7405 USHORT usExtendedModeNumber;
7406}ATOM_VESA_TO_EXTENDED_MODE;
7407
7408typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
7409{
7410 ATOM_COMMON_TABLE_HEADER sHeader;
7411 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
7412}ATOM_VESA_TO_INTENAL_MODE_LUT;
7413
7414/*************** ATOM Memory Related Data Structure ***********************/
7415typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
7416 UCHAR ucMemoryType;
7417 UCHAR ucMemoryVendor;
7418 UCHAR ucAdjMCId;
7419 UCHAR ucDynClkId;
7420 ULONG ulDllResetClkRange;
7421}ATOM_MEMORY_VENDOR_BLOCK;
7422
7423
7424typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
7425#if ATOM_BIG_ENDIAN
7426 ULONG ucMemBlkId:8;
7427 ULONG ulMemClockRange:24;
7428#else
7429 ULONG ulMemClockRange:24;
7430 ULONG ucMemBlkId:8;
7431#endif
7432}ATOM_MEMORY_SETTING_ID_CONFIG;
7433
7434typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
7435{
7436 ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
7437 ULONG ulAccess;
7438}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
7439
7440
7441typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
7442 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
7443 ULONG aulMemData[1];
7444}ATOM_MEMORY_SETTING_DATA_BLOCK;
7445
7446
7447typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
7448 USHORT usRegIndex; // MC register index
7449 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
7450}ATOM_INIT_REG_INDEX_FORMAT;
7451
7452
7453typedef struct _ATOM_INIT_REG_BLOCK{
7454 USHORT usRegIndexTblSize; //size of asRegIndexBuf
7455 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK
7456 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
7457 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
7458}ATOM_INIT_REG_BLOCK;
7459
7460#define END_OF_REG_INDEX_BLOCK 0x0ffff
7461#define END_OF_REG_DATA_BLOCK 0x00000000
7462#define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS
7463#define CLOCK_RANGE_HIGHEST 0x00ffffff
7464
7465#define VALUE_DWORD SIZEOF ULONG
7466#define VALUE_SAME_AS_ABOVE 0
7467#define VALUE_MASK_DWORD 0x84
7468
7469#define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
7470#define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
7471#define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
7472//#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code
7473#define ACCESS_PLACEHOLDER 0x80
7474
7475
7476typedef struct _ATOM_MC_INIT_PARAM_TABLE
7477{
7478 ATOM_COMMON_TABLE_HEADER sHeader;
7479 USHORT usAdjustARB_SEQDataOffset;
7480 USHORT usMCInitMemTypeTblOffset;
7481 USHORT usMCInitCommonTblOffset;
7482 USHORT usMCInitPowerDownTblOffset;
7483 ULONG ulARB_SEQDataBuf[32];
7484 ATOM_INIT_REG_BLOCK asMCInitMemType;
7485 ATOM_INIT_REG_BLOCK asMCInitCommon;
7486}ATOM_MC_INIT_PARAM_TABLE;
7487
7488
7489typedef struct _ATOM_REG_INIT_SETTING
7490{
7491 USHORT usRegIndex;
7492 ULONG ulRegValue;
7493}ATOM_REG_INIT_SETTING;
7494
7495typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1
7496{
7497 ATOM_COMMON_TABLE_HEADER sHeader;
7498 ULONG ulMCUcodeVersion;
7499 ULONG ulMCUcodeRomStartAddr;
7500 ULONG ulMCUcodeLength;
7501 USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings.
7502 USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting
7503}ATOM_MC_INIT_PARAM_TABLE_V2_1;
7504
7505
7506#define _4Mx16 0x2
7507#define _4Mx32 0x3
7508#define _8Mx16 0x12
7509#define _8Mx32 0x13
7510#define _8Mx128 0x15
7511#define _16Mx16 0x22
7512#define _16Mx32 0x23
7513#define _16Mx128 0x25
7514#define _32Mx16 0x32
7515#define _32Mx32 0x33
7516#define _32Mx128 0x35
7517#define _64Mx8 0x41
7518#define _64Mx16 0x42
7519#define _64Mx32 0x43
7520#define _64Mx128 0x45
7521#define _128Mx8 0x51
7522#define _128Mx16 0x52
7523#define _128Mx32 0x53
7524#define _256Mx8 0x61
7525#define _256Mx16 0x62
7526#define _256Mx32 0x63
7527#define _512Mx8 0x71
7528#define _512Mx16 0x72
7529
7530
7531#define SAMSUNG 0x1
7532#define INFINEON 0x2
7533#define ELPIDA 0x3
7534#define ETRON 0x4
7535#define NANYA 0x5
7536#define HYNIX 0x6
7537#define MOSEL 0x7
7538#define WINBOND 0x8
7539#define ESMT 0x9
7540#define MICRON 0xF
7541
7542#define QIMONDA INFINEON
7543#define PROMOS MOSEL
7544#define KRETON INFINEON
7545#define ELIXIR NANYA
7546#define MEZZA ELPIDA
7547
7548
7549/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
7550
7551#define UCODE_ROM_START_ADDRESS 0x1b800
7552#define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
7553
7554//uCode block header for reference
7555
7556typedef struct _MCuCodeHeader
7557{
7558 ULONG ulSignature;
7559 UCHAR ucRevision;
7560 UCHAR ucChecksum;
7561 UCHAR ucReserved1;
7562 UCHAR ucReserved2;
7563 USHORT usParametersLength;
7564 USHORT usUCodeLength;
7565 USHORT usReserved1;
7566 USHORT usReserved2;
7567} MCuCodeHeader;
7568
7569//////////////////////////////////////////////////////////////////////////////////
7570
7571#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16
7572
7573#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF
7574typedef struct _ATOM_VRAM_MODULE_V1
7575{
7576 ULONG ulReserved;
7577 USHORT usEMRSValue;
7578 USHORT usMRSValue;
7579 USHORT usReserved;
7580 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7581 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
7582 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
7583 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
7584 UCHAR ucRow; // Number of Row,in power of 2;
7585 UCHAR ucColumn; // Number of Column,in power of 2;
7586 UCHAR ucBank; // Nunber of Bank;
7587 UCHAR ucRank; // Number of Rank, in power of 2
7588 UCHAR ucChannelNum; // Number of channel;
7589 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7590 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7591 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7592 UCHAR ucReserved[2];
7593}ATOM_VRAM_MODULE_V1;
7594
7595
7596typedef struct _ATOM_VRAM_MODULE_V2
7597{
7598 ULONG ulReserved;
7599 ULONG ulFlags; // To enable/disable functionalities based on memory type
7600 ULONG ulEngineClock; // Override of default engine clock for particular memory type
7601 ULONG ulMemoryClock; // Override of default memory clock for particular memory type
7602 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7603 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7604 USHORT usEMRSValue;
7605 USHORT usMRSValue;
7606 USHORT usReserved;
7607 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7608 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
7609 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
7610 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
7611 UCHAR ucRow; // Number of Row,in power of 2;
7612 UCHAR ucColumn; // Number of Column,in power of 2;
7613 UCHAR ucBank; // Nunber of Bank;
7614 UCHAR ucRank; // Number of Rank, in power of 2
7615 UCHAR ucChannelNum; // Number of channel;
7616 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7617 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7618 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7619 UCHAR ucRefreshRateFactor;
7620 UCHAR ucReserved[3];
7621}ATOM_VRAM_MODULE_V2;
7622
7623
7624typedef struct _ATOM_MEMORY_TIMING_FORMAT
7625{
7626 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7627 union{
7628 USHORT usMRS; // mode register
7629 USHORT usDDR3_MR0;
7630 };
7631 union{
7632 USHORT usEMRS; // extended mode register
7633 USHORT usDDR3_MR1;
7634 };
7635 UCHAR ucCL; // CAS latency
7636 UCHAR ucWL; // WRITE Latency
7637 UCHAR uctRAS; // tRAS
7638 UCHAR uctRC; // tRC
7639 UCHAR uctRFC; // tRFC
7640 UCHAR uctRCDR; // tRCDR
7641 UCHAR uctRCDW; // tRCDW
7642 UCHAR uctRP; // tRP
7643 UCHAR uctRRD; // tRRD
7644 UCHAR uctWR; // tWR
7645 UCHAR uctWTR; // tWTR
7646 UCHAR uctPDIX; // tPDIX
7647 UCHAR uctFAW; // tFAW
7648 UCHAR uctAOND; // tAOND
7649 union
7650 {
7651 struct {
7652 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7653 UCHAR ucReserved;
7654 };
7655 USHORT usDDR3_MR2;
7656 };
7657}ATOM_MEMORY_TIMING_FORMAT;
7658
7659
7660typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
7661{
7662 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7663 USHORT usMRS; // mode register
7664 USHORT usEMRS; // extended mode register
7665 UCHAR ucCL; // CAS latency
7666 UCHAR ucWL; // WRITE Latency
7667 UCHAR uctRAS; // tRAS
7668 UCHAR uctRC; // tRC
7669 UCHAR uctRFC; // tRFC
7670 UCHAR uctRCDR; // tRCDR
7671 UCHAR uctRCDW; // tRCDW
7672 UCHAR uctRP; // tRP
7673 UCHAR uctRRD; // tRRD
7674 UCHAR uctWR; // tWR
7675 UCHAR uctWTR; // tWTR
7676 UCHAR uctPDIX; // tPDIX
7677 UCHAR uctFAW; // tFAW
7678 UCHAR uctAOND; // tAOND
7679 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7680////////////////////////////////////GDDR parameters///////////////////////////////////
7681 UCHAR uctCCDL; //
7682 UCHAR uctCRCRL; //
7683 UCHAR uctCRCWL; //
7684 UCHAR uctCKE; //
7685 UCHAR uctCKRSE; //
7686 UCHAR uctCKRSX; //
7687 UCHAR uctFAW32; //
7688 UCHAR ucMR5lo; //
7689 UCHAR ucMR5hi; //
7690 UCHAR ucTerminator;
7691}ATOM_MEMORY_TIMING_FORMAT_V1;
7692
7693
7694
7695
7696typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
7697{
7698 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
7699 USHORT usMRS; // mode register
7700 USHORT usEMRS; // extended mode register
7701 UCHAR ucCL; // CAS latency
7702 UCHAR ucWL; // WRITE Latency
7703 UCHAR uctRAS; // tRAS
7704 UCHAR uctRC; // tRC
7705 UCHAR uctRFC; // tRFC
7706 UCHAR uctRCDR; // tRCDR
7707 UCHAR uctRCDW; // tRCDW
7708 UCHAR uctRP; // tRP
7709 UCHAR uctRRD; // tRRD
7710 UCHAR uctWR; // tWR
7711 UCHAR uctWTR; // tWTR
7712 UCHAR uctPDIX; // tPDIX
7713 UCHAR uctFAW; // tFAW
7714 UCHAR uctAOND; // tAOND
7715 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7716////////////////////////////////////GDDR parameters///////////////////////////////////
7717 UCHAR uctCCDL; //
7718 UCHAR uctCRCRL; //
7719 UCHAR uctCRCWL; //
7720 UCHAR uctCKE; //
7721 UCHAR uctCKRSE; //
7722 UCHAR uctCKRSX; //
7723 UCHAR uctFAW32; //
7724 UCHAR ucMR4lo; //
7725 UCHAR ucMR4hi; //
7726 UCHAR ucMR5lo; //
7727 UCHAR ucMR5hi; //
7728 UCHAR ucTerminator;
7729 UCHAR ucReserved;
7730}ATOM_MEMORY_TIMING_FORMAT_V2;
7731
7732
7733typedef struct _ATOM_MEMORY_FORMAT
7734{
7735 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock
7736 union{
7737 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7738 USHORT usDDR3_Reserved; // Not used for DDR3 memory
7739 };
7740 union{
7741 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7742 USHORT usDDR3_MR3; // Used for DDR3 memory
7743 };
7744 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
7745 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
7746 UCHAR ucRow; // Number of Row,in power of 2;
7747 UCHAR ucColumn; // Number of Column,in power of 2;
7748 UCHAR ucBank; // Nunber of Bank;
7749 UCHAR ucRank; // Number of Rank, in power of 2
7750 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
7751 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
7752 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
7753 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7754 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7755 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
7756 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock
7757}ATOM_MEMORY_FORMAT;
7758
7759
7760typedef struct _ATOM_VRAM_MODULE_V3
7761{
7762 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
7763 USHORT usSize; // size of ATOM_VRAM_MODULE_V3
7764 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage
7765 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage
7766 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7767 UCHAR ucChannelNum; // board dependent parameter:Number of channel;
7768 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
7769 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7770 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7771 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7772 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec
7773}ATOM_VRAM_MODULE_V3;
7774
7775
7776//ATOM_VRAM_MODULE_V3.ucNPL_RT
7777#define NPL_RT_MASK 0x0f
7778#define BATTERY_ODT_MASK 0xc0
7779
7780#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3
7781
7782typedef struct _ATOM_VRAM_MODULE_V4
7783{
7784 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7785 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7786 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7787 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7788 USHORT usReserved;
7789 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7790 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7791 UCHAR ucChannelNum; // Number of channels present in this module config
7792 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7793 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7794 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7795 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7796 UCHAR ucVREFI; // board dependent parameter
7797 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7798 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7799 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7800 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7801 UCHAR ucReserved[3];
7802
7803//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
7804 union{
7805 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7806 USHORT usDDR3_Reserved;
7807 };
7808 union{
7809 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7810 USHORT usDDR3_MR3; // Used for DDR3 memory
7811 };
7812 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7813 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7814 UCHAR ucReserved2[2];
7815 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
7816}ATOM_VRAM_MODULE_V4;
7817
7818#define VRAM_MODULE_V4_MISC_RANK_MASK 0x3
7819#define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1
7820#define VRAM_MODULE_V4_MISC_BL_MASK 0x4
7821#define VRAM_MODULE_V4_MISC_BL8 0x4
7822#define VRAM_MODULE_V4_MISC_DUAL_CS 0x10
7823
7824typedef struct _ATOM_VRAM_MODULE_V5
7825{
7826 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7827 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7828 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7829 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7830 USHORT usReserved;
7831 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7832 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7833 UCHAR ucChannelNum; // Number of channels present in this module config
7834 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7835 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7836 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7837 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7838 UCHAR ucVREFI; // board dependent parameter
7839 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7840 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7841 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7842 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7843 UCHAR ucReserved[3];
7844
7845//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
7846 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7847 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7848 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7849 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7850 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7851 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7852 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
7853}ATOM_VRAM_MODULE_V5;
7854
7855
7856typedef struct _ATOM_VRAM_MODULE_V6
7857{
7858 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7859 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7860 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7861 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7862 USHORT usReserved;
7863 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7864 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7865 UCHAR ucChannelNum; // Number of channels present in this module config
7866 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7867 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7868 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7869 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7870 UCHAR ucVREFI; // board dependent parameter
7871 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7872 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7873 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7874 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7875 UCHAR ucReserved[3];
7876
7877//compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
7878 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7879 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7880 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7881 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7882 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7883 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7884 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
7885}ATOM_VRAM_MODULE_V6;
7886
7887typedef struct _ATOM_VRAM_MODULE_V7
7888{
7889// Design Specific Values
7890 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7891 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
7892 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7893 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
7894 UCHAR ucExtMemoryID; // Current memory module ID
7895 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7896 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7897 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7898 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7899 UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used.
7900 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7901 UCHAR ucVREFI; // Not used.
7902 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7903 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7904 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7905 USHORT usSEQSettingOffset;
7906 UCHAR ucReserved;
7907// Memory Module specific values
7908 USHORT usEMRS2Value; // EMRS2/MR2 Value.
7909 USHORT usEMRS3Value; // EMRS3/MR3 Value.
7910 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7911 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7912 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7913 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7914 char strMemPNString[20]; // part number end with '0'.
7915}ATOM_VRAM_MODULE_V7;
7916
7917
7918typedef struct _ATOM_VRAM_MODULE_V8
7919{
7920// Design Specific Values
7921 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7922 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7
7923 USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7924 USHORT usEnableChannels; // bit vector which indicate which channels are enabled
7925 UCHAR ucExtMemoryID; // Current memory module ID
7926 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7927 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7928 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7929 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7930 UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit )
7931 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7932 UCHAR ucVREFI; // Not used.
7933 USHORT usReserved; // Not used
7934 USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
7935 UCHAR ucMcTunningSetId; // MC phy registers set per.
7936 UCHAR ucRowNum;
7937// Memory Module specific values
7938 USHORT usEMRS2Value; // EMRS2/MR2 Value.
7939 USHORT usEMRS3Value; // EMRS3/MR3 Value.
7940 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7941 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7942 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7943 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7944
7945 ULONG ulChannelMapCfg1; // channel mapping for channel8~15
7946 ULONG ulBankMapCfg;
7947 ULONG ulReserved;
7948 char strMemPNString[20]; // part number end with '0'.
7949}ATOM_VRAM_MODULE_V8;
7950
7951
7952typedef struct _ATOM_VRAM_INFO_V2
7953{
7954 ATOM_COMMON_TABLE_HEADER sHeader;
7955 UCHAR ucNumOfVRAMModule;
7956 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7957}ATOM_VRAM_INFO_V2;
7958
7959typedef struct _ATOM_VRAM_INFO_V3
7960{
7961 ATOM_COMMON_TABLE_HEADER sHeader;
7962 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7963 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7964 USHORT usRerseved;
7965 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
7966 UCHAR ucNumOfVRAMModule;
7967 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7968 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
7969
7970}ATOM_VRAM_INFO_V3;
7971
7972#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3
7973
7974typedef struct _ATOM_VRAM_INFO_V4
7975{
7976 ATOM_COMMON_TABLE_HEADER sHeader;
7977 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7978 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7979 USHORT usRerseved;
7980 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
7981 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
7982 UCHAR ucReservde[4];
7983 UCHAR ucNumOfVRAMModule;
7984 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7985 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation
7986}ATOM_VRAM_INFO_V4;
7987
7988typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
7989{
7990 ATOM_COMMON_TABLE_HEADER sHeader;
7991 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7992 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7993 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
7994 USHORT usReserved[3];
7995 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
7996 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
7997 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
7998 UCHAR ucReserved;
7999 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
8000}ATOM_VRAM_INFO_HEADER_V2_1;
8001
8002typedef struct _ATOM_VRAM_INFO_HEADER_V2_2
8003{
8004 ATOM_COMMON_TABLE_HEADER sHeader;
8005 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
8006 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
8007 USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
8008 USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set
8009 USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping
8010 USHORT usReserved1;
8011 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
8012 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
8013 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
8014 UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
8015 ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
8016}ATOM_VRAM_INFO_HEADER_V2_2;
8017
8018
8019typedef struct _ATOM_DRAM_DATA_REMAP
8020{
8021 UCHAR ucByteRemapCh0;
8022 UCHAR ucByteRemapCh1;
8023 ULONG ulByte0BitRemapCh0;
8024 ULONG ulByte1BitRemapCh0;
8025 ULONG ulByte2BitRemapCh0;
8026 ULONG ulByte3BitRemapCh0;
8027 ULONG ulByte0BitRemapCh1;
8028 ULONG ulByte1BitRemapCh1;
8029 ULONG ulByte2BitRemapCh1;
8030 ULONG ulByte3BitRemapCh1;
8031}ATOM_DRAM_DATA_REMAP;
8032
8033typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
8034{
8035 ATOM_COMMON_TABLE_HEADER sHeader;
8036 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
8037}ATOM_VRAM_GPIO_DETECTION_INFO;
8038
8039
8040typedef struct _ATOM_MEMORY_TRAINING_INFO
8041{
8042 ATOM_COMMON_TABLE_HEADER sHeader;
8043 UCHAR ucTrainingLoop;
8044 UCHAR ucReserved[3];
8045 ATOM_INIT_REG_BLOCK asMemTrainingSetting;
8046}ATOM_MEMORY_TRAINING_INFO;
8047
8048
8049typedef struct _ATOM_MEMORY_TRAINING_INFO_V3_1
8050{
8051 ATOM_COMMON_TABLE_HEADER sHeader;
8052 ULONG ulMCUcodeVersion;
8053 USHORT usMCIOInitLen; //len of ATOM_REG_INIT_SETTING array
8054 USHORT usMCUcodeLen; //len of ATOM_MC_UCODE_DATA array
8055 USHORT usMCIORegInitOffset; //point of offset of ATOM_REG_INIT_SETTING array
8056 USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array.
8057}ATOM_MEMORY_TRAINING_INFO_V3_1;
8058
8059
8060typedef struct SW_I2C_CNTL_DATA_PARAMETERS
8061{
8062 UCHAR ucControl;
8063 UCHAR ucData;
8064 UCHAR ucSatus;
8065 UCHAR ucTemp;
8066} SW_I2C_CNTL_DATA_PARAMETERS;
8067
8068#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS
8069
8070typedef struct _SW_I2C_IO_DATA_PARAMETERS
8071{
8072 USHORT GPIO_Info;
8073 UCHAR ucAct;
8074 UCHAR ucData;
8075 } SW_I2C_IO_DATA_PARAMETERS;
8076
8077#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS
8078
8079/****************************SW I2C CNTL DEFINITIONS**********************/
8080#define SW_I2C_IO_RESET 0
8081#define SW_I2C_IO_GET 1
8082#define SW_I2C_IO_DRIVE 2
8083#define SW_I2C_IO_SET 3
8084#define SW_I2C_IO_START 4
8085
8086#define SW_I2C_IO_CLOCK 0
8087#define SW_I2C_IO_DATA 0x80
8088
8089#define SW_I2C_IO_ZERO 0
8090#define SW_I2C_IO_ONE 0x100
8091
8092#define SW_I2C_CNTL_READ 0
8093#define SW_I2C_CNTL_WRITE 1
8094#define SW_I2C_CNTL_START 2
8095#define SW_I2C_CNTL_STOP 3
8096#define SW_I2C_CNTL_OPEN 4
8097#define SW_I2C_CNTL_CLOSE 5
8098#define SW_I2C_CNTL_WRITE1BIT 6
8099
8100//==============================VESA definition Portion===============================
8101#define VESA_OEM_PRODUCT_REV '01.00'
8102#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support
8103#define VESA_MODE_WIN_ATTRIBUTE 7
8104#define VESA_WIN_SIZE 64
8105
8106typedef struct _PTR_32_BIT_STRUCTURE
8107{
8108 USHORT Offset16;
8109 USHORT Segment16;
8110} PTR_32_BIT_STRUCTURE;
8111
8112typedef union _PTR_32_BIT_UNION
8113{
8114 PTR_32_BIT_STRUCTURE SegmentOffset;
8115 ULONG Ptr32_Bit;
8116} PTR_32_BIT_UNION;
8117
8118typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
8119{
8120 UCHAR VbeSignature[4];
8121 USHORT VbeVersion;
8122 PTR_32_BIT_UNION OemStringPtr;
8123 UCHAR Capabilities[4];
8124 PTR_32_BIT_UNION VideoModePtr;
8125 USHORT TotalMemory;
8126} VBE_1_2_INFO_BLOCK_UPDATABLE;
8127
8128
8129typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
8130{
8131 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
8132 USHORT OemSoftRev;
8133 PTR_32_BIT_UNION OemVendorNamePtr;
8134 PTR_32_BIT_UNION OemProductNamePtr;
8135 PTR_32_BIT_UNION OemProductRevPtr;
8136} VBE_2_0_INFO_BLOCK_UPDATABLE;
8137
8138typedef union _VBE_VERSION_UNION
8139{
8140 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
8141 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
8142} VBE_VERSION_UNION;
8143
8144typedef struct _VBE_INFO_BLOCK
8145{
8146 VBE_VERSION_UNION UpdatableVBE_Info;
8147 UCHAR Reserved[222];
8148 UCHAR OemData[256];
8149} VBE_INFO_BLOCK;
8150
8151typedef struct _VBE_FP_INFO
8152{
8153 USHORT HSize;
8154 USHORT VSize;
8155 USHORT FPType;
8156 UCHAR RedBPP;
8157 UCHAR GreenBPP;
8158 UCHAR BlueBPP;
8159 UCHAR ReservedBPP;
8160 ULONG RsvdOffScrnMemSize;
8161 ULONG RsvdOffScrnMEmPtr;
8162 UCHAR Reserved[14];
8163} VBE_FP_INFO;
8164
8165typedef struct _VESA_MODE_INFO_BLOCK
8166{
8167// Mandatory information for all VBE revisions
8168 USHORT ModeAttributes; // dw ? ; mode attributes
8169 UCHAR WinAAttributes; // db ? ; window A attributes
8170 UCHAR WinBAttributes; // db ? ; window B attributes
8171 USHORT WinGranularity; // dw ? ; window granularity
8172 USHORT WinSize; // dw ? ; window size
8173 USHORT WinASegment; // dw ? ; window A start segment
8174 USHORT WinBSegment; // dw ? ; window B start segment
8175 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
8176 USHORT BytesPerScanLine;// dw ? ; bytes per scan line
8177
8178//; Mandatory information for VBE 1.2 and above
8179 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters
8180 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters
8181 UCHAR XCharSize; // db ? ; character cell width in pixels
8182 UCHAR YCharSize; // db ? ; character cell height in pixels
8183 UCHAR NumberOfPlanes; // db ? ; number of memory planes
8184 UCHAR BitsPerPixel; // db ? ; bits per pixel
8185 UCHAR NumberOfBanks; // db ? ; number of banks
8186 UCHAR MemoryModel; // db ? ; memory model type
8187 UCHAR BankSize; // db ? ; bank size in KB
8188 UCHAR NumberOfImagePages;// db ? ; number of images
8189 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
8190
8191//; Direct Color fields(required for direct/6 and YUV/7 memory models)
8192 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
8193 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
8194 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
8195 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
8196 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
8197 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
8198 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
8199 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
8200 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
8201
8202//; Mandatory information for VBE 2.0 and above
8203 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
8204 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8205 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
8206
8207//; Mandatory information for VBE 3.0 and above
8208 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes
8209 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
8210 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
8211 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
8212 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
8213 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
8214 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
8215 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
8216 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
8217 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
8218 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
8219 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
8220 UCHAR Reserved; // db 190 dup (0)
8221} VESA_MODE_INFO_BLOCK;
8222
8223// BIOS function CALLS
8224#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code
8225#define ATOM_BIOS_FUNCTION_COP_MODE 0x00
8226#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04
8227#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05
8228#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06
8229#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B
8230#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E
8231#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F
8232#define ATOM_BIOS_FUNCTION_STV_STD 0x16
8233#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17
8234#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18
8235
8236#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82
8237#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83
8238#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84
8239#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A
8240#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B
8241#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80
8242#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80
8243
8244#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D
8245#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E
8246#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F
8247#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03
8248#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
8249#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state
8250#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state
8251#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85
8252#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
8253#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported
8254
8255
8256#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS
8257#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01
8258#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02
8259#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON.
8260#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY
8261#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND
8262#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF
8263#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
8264
8265#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L
8266#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L
8267#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL
8268
8269// structure used for VBIOS only
8270
8271//DispOutInfoTable
8272typedef struct _ASIC_TRANSMITTER_INFO
8273{
8274 USHORT usTransmitterObjId;
8275 USHORT usSupportDevice;
8276 UCHAR ucTransmitterCmdTblId;
8277 UCHAR ucConfig;
8278 UCHAR ucEncoderID; //available 1st encoder ( default )
8279 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
8280 UCHAR uc2ndEncoderID;
8281 UCHAR ucReserved;
8282}ASIC_TRANSMITTER_INFO;
8283
8284#define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01
8285#define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02
8286#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4
8287#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00
8288#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04
8289#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40
8290#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44
8291#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80
8292#define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84
8293
8294typedef struct _ASIC_ENCODER_INFO
8295{
8296 UCHAR ucEncoderID;
8297 UCHAR ucEncoderConfig;
8298 USHORT usEncoderCmdTblId;
8299}ASIC_ENCODER_INFO;
8300
8301typedef struct _ATOM_DISP_OUT_INFO
8302{
8303 ATOM_COMMON_TABLE_HEADER sHeader;
8304 USHORT ptrTransmitterInfo;
8305 USHORT ptrEncoderInfo;
8306 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
8307 ASIC_ENCODER_INFO asEncoderInfo[1];
8308}ATOM_DISP_OUT_INFO;
8309
8310
8311typedef struct _ATOM_DISP_OUT_INFO_V2
8312{
8313 ATOM_COMMON_TABLE_HEADER sHeader;
8314 USHORT ptrTransmitterInfo;
8315 USHORT ptrEncoderInfo;
8316 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
8317 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
8318 ASIC_ENCODER_INFO asEncoderInfo[1];
8319}ATOM_DISP_OUT_INFO_V2;
8320
8321
8322typedef struct _ATOM_DISP_CLOCK_ID {
8323 UCHAR ucPpllId;
8324 UCHAR ucPpllAttribute;
8325}ATOM_DISP_CLOCK_ID;
8326
8327// ucPpllAttribute
8328#define CLOCK_SOURCE_SHAREABLE 0x01
8329#define CLOCK_SOURCE_DP_MODE 0x02
8330#define CLOCK_SOURCE_NONE_DP_MODE 0x04
8331
8332//DispOutInfoTable
8333typedef struct _ASIC_TRANSMITTER_INFO_V2
8334{
8335 USHORT usTransmitterObjId;
8336 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object
8337 UCHAR ucTransmitterCmdTblId;
8338 UCHAR ucConfig;
8339 UCHAR ucEncoderID; // available 1st encoder ( default )
8340 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
8341 UCHAR uc2ndEncoderID;
8342 UCHAR ucReserved;
8343}ASIC_TRANSMITTER_INFO_V2;
8344
8345typedef struct _ATOM_DISP_OUT_INFO_V3
8346{
8347 ATOM_COMMON_TABLE_HEADER sHeader;
8348 USHORT ptrTransmitterInfo;
8349 USHORT ptrEncoderInfo;
8350 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary.
8351 USHORT usReserved;
8352 UCHAR ucDCERevision;
8353 UCHAR ucMaxDispEngineNum;
8354 UCHAR ucMaxActiveDispEngineNum;
8355 UCHAR ucMaxPPLLNum;
8356 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
8357 UCHAR ucDispCaps;
8358 UCHAR ucReserved[2];
8359 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
8360}ATOM_DISP_OUT_INFO_V3;
8361
8362//ucDispCaps
8363#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01
8364#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02
8365
8366typedef enum CORE_REF_CLK_SOURCE{
8367 CLOCK_SRC_XTALIN=0,
8368 CLOCK_SRC_XO_IN=1,
8369 CLOCK_SRC_XO_IN2=2,
8370}CORE_REF_CLK_SOURCE;
8371
8372// DispDevicePriorityInfo
8373typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
8374{
8375 ATOM_COMMON_TABLE_HEADER sHeader;
8376 USHORT asDevicePriority[16];
8377}ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
8378
8379//ProcessAuxChannelTransactionTable
8380typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
8381{
8382 USHORT lpAuxRequest;
8383 USHORT lpDataOut;
8384 UCHAR ucChannelID;
8385 union
8386 {
8387 UCHAR ucReplyStatus;
8388 UCHAR ucDelay;
8389 };
8390 UCHAR ucDataOutLen;
8391 UCHAR ucReserved;
8392}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
8393
8394//ProcessAuxChannelTransactionTable
8395typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
8396{
8397 USHORT lpAuxRequest;
8398 USHORT lpDataOut;
8399 UCHAR ucChannelID;
8400 union
8401 {
8402 UCHAR ucReplyStatus;
8403 UCHAR ucDelay;
8404 };
8405 UCHAR ucDataOutLen;
8406 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
8407}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
8408
8409#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
8410
8411//GetSinkType
8412
8413typedef struct _DP_ENCODER_SERVICE_PARAMETERS
8414{
8415 USHORT ucLinkClock;
8416 union
8417 {
8418 UCHAR ucConfig; // for DP training command
8419 UCHAR ucI2cId; // use for GET_SINK_TYPE command
8420 };
8421 UCHAR ucAction;
8422 UCHAR ucStatus;
8423 UCHAR ucLaneNum;
8424 UCHAR ucReserved[2];
8425}DP_ENCODER_SERVICE_PARAMETERS;
8426
8427// ucAction
8428#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01
8429
8430#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
8431
8432
8433typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
8434{
8435 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
8436 UCHAR ucAuxId;
8437 UCHAR ucAction;
8438 UCHAR ucSinkType; // Iput and Output parameters.
8439 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
8440 UCHAR ucReserved[2];
8441}DP_ENCODER_SERVICE_PARAMETERS_V2;
8442
8443typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
8444{
8445 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
8446 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
8447}DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
8448
8449// ucAction
8450#define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01
8451#define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02
8452
8453
8454// DP_TRAINING_TABLE
8455#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR
8456#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
8457#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 )
8458#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 )
8459#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32)
8460#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40)
8461#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48)
8462#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60)
8463#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64)
8464#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72)
8465#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76)
8466#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80)
8467#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84)
8468
8469
8470typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
8471{
8472 UCHAR ucI2CSpeed;
8473 union
8474 {
8475 UCHAR ucRegIndex;
8476 UCHAR ucStatus;
8477 };
8478 USHORT lpI2CDataOut;
8479 UCHAR ucFlag;
8480 UCHAR ucTransBytes;
8481 UCHAR ucSlaveAddr;
8482 UCHAR ucLineNumber;
8483}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
8484
8485#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
8486
8487//ucFlag
8488#define HW_I2C_WRITE 1
8489#define HW_I2C_READ 0
8490#define I2C_2BYTE_ADDR 0x02
8491
8492/****************************************************************************/
8493// Structures used by HW_Misc_OperationTable
8494/****************************************************************************/
8495typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
8496{
8497 UCHAR ucCmd; // Input: To tell which action to take
8498 UCHAR ucReserved[3];
8499 ULONG ulReserved;
8500}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;
8501
8502typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
8503{
8504 UCHAR ucReturnCode; // Output: Return value base on action was taken
8505 UCHAR ucReserved[3];
8506 ULONG ulReserved;
8507}ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
8508
8509// Actions code
8510#define ATOM_GET_SDI_SUPPORT 0xF0
8511
8512// Return code
8513#define ATOM_UNKNOWN_CMD 0
8514#define ATOM_FEATURE_NOT_SUPPORTED 1
8515#define ATOM_FEATURE_SUPPORTED 2
8516
8517typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
8518{
8519 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output;
8520 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved;
8521}ATOM_HW_MISC_OPERATION_PS_ALLOCATION;
8522
8523/****************************************************************************/
8524
8525typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
8526{
8527 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
8528 UCHAR ucReserved[3];
8529}SET_HWBLOCK_INSTANCE_PARAMETER_V2;
8530
8531#define HWBLKINST_INSTANCE_MASK 0x07
8532#define HWBLKINST_HWBLK_MASK 0xF0
8533#define HWBLKINST_HWBLK_SHIFT 0x04
8534
8535//ucHWBlock
8536#define SELECT_DISP_ENGINE 0
8537#define SELECT_DISP_PLL 1
8538#define SELECT_DCIO_UNIPHY_LINK0 2
8539#define SELECT_DCIO_UNIPHY_LINK1 3
8540#define SELECT_DCIO_IMPCAL 4
8541#define SELECT_DCIO_DIG 6
8542#define SELECT_CRTC_PIXEL_RATE 7
8543#define SELECT_VGA_BLK 8
8544
8545// DIGTransmitterInfoTable structure used to program UNIPHY settings
8546typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{
8547 ATOM_COMMON_TABLE_HEADER sHeader;
8548 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
8549 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
8550 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
8551 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
8552 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
8553}DIG_TRANSMITTER_INFO_HEADER_V3_1;
8554
8555typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{
8556 ATOM_COMMON_TABLE_HEADER sHeader;
8557 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
8558 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
8559 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
8560 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
8561 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
8562 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
8563 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
8564}DIG_TRANSMITTER_INFO_HEADER_V3_2;
8565
8566
8567typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{
8568 ATOM_COMMON_TABLE_HEADER sHeader;
8569 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
8570 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
8571 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
8572 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
8573 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
8574 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
8575 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
8576 USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock
8577 USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
8578 USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
8579 USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock
8580 USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock
8581 USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock
8582}DIG_TRANSMITTER_INFO_HEADER_V3_3;
8583
8584
8585typedef struct _CLOCK_CONDITION_REGESTER_INFO{
8586 USHORT usRegisterIndex;
8587 UCHAR ucStartBit;
8588 UCHAR ucEndBit;
8589}CLOCK_CONDITION_REGESTER_INFO;
8590
8591typedef struct _CLOCK_CONDITION_SETTING_ENTRY{
8592 USHORT usMaxClockFreq;
8593 UCHAR ucEncodeMode;
8594 UCHAR ucPhySel;
8595 ULONG ulAnalogSetting[1];
8596}CLOCK_CONDITION_SETTING_ENTRY;
8597
8598typedef struct _CLOCK_CONDITION_SETTING_INFO{
8599 USHORT usEntrySize;
8600 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
8601}CLOCK_CONDITION_SETTING_INFO;
8602
8603typedef struct _PHY_CONDITION_REG_VAL{
8604 ULONG ulCondition;
8605 ULONG ulRegVal;
8606}PHY_CONDITION_REG_VAL;
8607
8608typedef struct _PHY_CONDITION_REG_VAL_V2{
8609 ULONG ulCondition;
8610 UCHAR ucCondition2;
8611 ULONG ulRegVal;
8612}PHY_CONDITION_REG_VAL_V2;
8613
8614typedef struct _PHY_CONDITION_REG_INFO{
8615 USHORT usRegIndex;
8616 USHORT usSize;
8617 PHY_CONDITION_REG_VAL asRegVal[1];
8618}PHY_CONDITION_REG_INFO;
8619
8620typedef struct _PHY_CONDITION_REG_INFO_V2{
8621 USHORT usRegIndex;
8622 USHORT usSize;
8623 PHY_CONDITION_REG_VAL_V2 asRegVal[1];
8624}PHY_CONDITION_REG_INFO_V2;
8625
8626typedef struct _PHY_ANALOG_SETTING_INFO{
8627 UCHAR ucEncodeMode;
8628 UCHAR ucPhySel;
8629 USHORT usSize;
8630 PHY_CONDITION_REG_INFO asAnalogSetting[1];
8631}PHY_ANALOG_SETTING_INFO;
8632
8633typedef struct _PHY_ANALOG_SETTING_INFO_V2{
8634 UCHAR ucEncodeMode;
8635 UCHAR ucPhySel;
8636 USHORT usSize;
8637 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1];
8638}PHY_ANALOG_SETTING_INFO_V2;
8639
8640
8641typedef struct _GFX_HAVESTING_PARAMETERS {
8642 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM
8643 UCHAR ucReserved; //reserved
8644 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array
8645 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array
8646} GFX_HAVESTING_PARAMETERS;
8647
8648//ucGfxBlkId
8649#define GFX_HARVESTING_CU_ID 0
8650#define GFX_HARVESTING_RB_ID 1
8651#define GFX_HARVESTING_PRIM_ID 2
8652
8653
8654typedef struct _VBIOS_ROM_HEADER{
8655 UCHAR PciRomSignature[2];
8656 UCHAR ucPciRomSizeIn512bytes;
8657 UCHAR ucJumpCoreMainInitBIOS;
8658 USHORT usLabelCoreMainInitBIOS;
8659 UCHAR PciReservedSpace[18];
8660 USHORT usPciDataStructureOffset;
8661 UCHAR Rsvd1d_1a[4];
8662 char strIbm[3];
8663 UCHAR CheckSum[14];
8664 UCHAR ucBiosMsgNumber;
8665 char str761295520[16];
8666 USHORT usLabelCoreVPOSTNoMode;
8667 USHORT usSpecialPostOffset;
8668 UCHAR ucSpeicalPostImageSizeIn512Bytes;
8669 UCHAR Rsved47_45[3];
8670 USHORT usROM_HeaderInformationTableOffset;
8671 UCHAR Rsved4f_4a[6];
8672 char strBuildTimeStamp[20];
8673 UCHAR ucJumpCoreXFuncFarHandler;
8674 USHORT usCoreXFuncFarHandlerOffset;
8675 UCHAR ucRsved67;
8676 UCHAR ucJumpCoreVFuncFarHandler;
8677 USHORT usCoreVFuncFarHandlerOffset;
8678 UCHAR Rsved6d_6b[3];
8679 USHORT usATOM_BIOS_MESSAGE_Offset;
8680}VBIOS_ROM_HEADER;
8681
8682/****************************************************************************/
8683//Portion VI: Definitinos for vbios MC scratch registers that driver used
8684/****************************************************************************/
8685
8686#define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000
8687#define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000
8688#define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000
8689#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000
8690#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000
8691#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000
8692#define MC_MISC0__MEMORY_TYPE__HBM 0x60000000
8693#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000
8694
8695#define ATOM_MEM_TYPE_DDR_STRING "DDR"
8696#define ATOM_MEM_TYPE_DDR2_STRING "DDR2"
8697#define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3"
8698#define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4"
8699#define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5"
8700#define ATOM_MEM_TYPE_HBM_STRING "HBM"
8701#define ATOM_MEM_TYPE_DDR3_STRING "DDR3"
8702
8703/****************************************************************************/
8704//Portion VII: Definitinos being oboselete
8705/****************************************************************************/
8706
8707//==========================================================================================
8708//Remove the definitions below when driver is ready!
8709typedef struct _ATOM_DAC_INFO
8710{
8711 ATOM_COMMON_TABLE_HEADER sHeader;
8712 USHORT usMaxFrequency; // in 10kHz unit
8713 USHORT usReserved;
8714}ATOM_DAC_INFO;
8715
8716
8717typedef struct _COMPASSIONATE_DATA
8718{
8719 ATOM_COMMON_TABLE_HEADER sHeader;
8720
8721 //============================== DAC1 portion
8722 UCHAR ucDAC1_BG_Adjustment;
8723 UCHAR ucDAC1_DAC_Adjustment;
8724 USHORT usDAC1_FORCE_Data;
8725 //============================== DAC2 portion
8726 UCHAR ucDAC2_CRT2_BG_Adjustment;
8727 UCHAR ucDAC2_CRT2_DAC_Adjustment;
8728 USHORT usDAC2_CRT2_FORCE_Data;
8729 USHORT usDAC2_CRT2_MUX_RegisterIndex;
8730 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8731 UCHAR ucDAC2_NTSC_BG_Adjustment;
8732 UCHAR ucDAC2_NTSC_DAC_Adjustment;
8733 USHORT usDAC2_TV1_FORCE_Data;
8734 USHORT usDAC2_TV1_MUX_RegisterIndex;
8735 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8736 UCHAR ucDAC2_CV_BG_Adjustment;
8737 UCHAR ucDAC2_CV_DAC_Adjustment;
8738 USHORT usDAC2_CV_FORCE_Data;
8739 USHORT usDAC2_CV_MUX_RegisterIndex;
8740 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8741 UCHAR ucDAC2_PAL_BG_Adjustment;
8742 UCHAR ucDAC2_PAL_DAC_Adjustment;
8743 USHORT usDAC2_TV2_FORCE_Data;
8744}COMPASSIONATE_DATA;
8745
8746/****************************Supported Device Info Table Definitions**********************/
8747// ucConnectInfo:
8748// [7:4] - connector type
8749// = 1 - VGA connector
8750// = 2 - DVI-I
8751// = 3 - DVI-D
8752// = 4 - DVI-A
8753// = 5 - SVIDEO
8754// = 6 - COMPOSITE
8755// = 7 - LVDS
8756// = 8 - DIGITAL LINK
8757// = 9 - SCART
8758// = 0xA - HDMI_type A
8759// = 0xB - HDMI_type B
8760// = 0xE - Special case1 (DVI+DIN)
8761// Others=TBD
8762// [3:0] - DAC Associated
8763// = 0 - no DAC
8764// = 1 - DACA
8765// = 2 - DACB
8766// = 3 - External DAC
8767// Others=TBD
8768//
8769
8770typedef struct _ATOM_CONNECTOR_INFO
8771{
8772#if ATOM_BIG_ENDIAN
8773 UCHAR bfConnectorType:4;
8774 UCHAR bfAssociatedDAC:4;
8775#else
8776 UCHAR bfAssociatedDAC:4;
8777 UCHAR bfConnectorType:4;
8778#endif
8779}ATOM_CONNECTOR_INFO;
8780
8781typedef union _ATOM_CONNECTOR_INFO_ACCESS
8782{
8783 ATOM_CONNECTOR_INFO sbfAccess;
8784 UCHAR ucAccess;
8785}ATOM_CONNECTOR_INFO_ACCESS;
8786
8787typedef struct _ATOM_CONNECTOR_INFO_I2C
8788{
8789 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
8790 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
8791}ATOM_CONNECTOR_INFO_I2C;
8792
8793
8794typedef struct _ATOM_SUPPORTED_DEVICES_INFO
8795{
8796 ATOM_COMMON_TABLE_HEADER sHeader;
8797 USHORT usDeviceSupport;
8798 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
8799}ATOM_SUPPORTED_DEVICES_INFO;
8800
8801#define NO_INT_SRC_MAPPED 0xFF
8802
8803typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
8804{
8805 UCHAR ucIntSrcBitmap;
8806}ATOM_CONNECTOR_INC_SRC_BITMAP;
8807
8808typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
8809{
8810 ATOM_COMMON_TABLE_HEADER sHeader;
8811 USHORT usDeviceSupport;
8812 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
8813 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
8814}ATOM_SUPPORTED_DEVICES_INFO_2;
8815
8816typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
8817{
8818 ATOM_COMMON_TABLE_HEADER sHeader;
8819 USHORT usDeviceSupport;
8820 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
8821 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
8822}ATOM_SUPPORTED_DEVICES_INFO_2d1;
8823
8824#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
8825
8826
8827
8828typedef struct _ATOM_MISC_CONTROL_INFO
8829{
8830 USHORT usFrequency;
8831 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8832 UCHAR ucPLL_DutyCycle; // PLL duty cycle control
8833 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
8834 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
8835}ATOM_MISC_CONTROL_INFO;
8836
8837
8838#define ATOM_MAX_MISC_INFO 4
8839
8840typedef struct _ATOM_TMDS_INFO
8841{
8842 ATOM_COMMON_TABLE_HEADER sHeader;
8843 USHORT usMaxFrequency; // in 10Khz
8844 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
8845}ATOM_TMDS_INFO;
8846
8847
8848typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
8849{
8850 UCHAR ucTVStandard; //Same as TV standards defined above,
8851 UCHAR ucPadding[1];
8852}ATOM_ENCODER_ANALOG_ATTRIBUTE;
8853
8854typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
8855{
8856 UCHAR ucAttribute; //Same as other digital encoder attributes defined above
8857 UCHAR ucPadding[1];
8858}ATOM_ENCODER_DIGITAL_ATTRIBUTE;
8859
8860typedef union _ATOM_ENCODER_ATTRIBUTE
8861{
8862 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
8863 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
8864}ATOM_ENCODER_ATTRIBUTE;
8865
8866
8867typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
8868{
8869 USHORT usPixelClock;
8870 USHORT usEncoderID;
8871 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
8872 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
8873 ATOM_ENCODER_ATTRIBUTE usDevAttr;
8874}DVO_ENCODER_CONTROL_PARAMETERS;
8875
8876typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
8877{
8878 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
8879 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
8880}DVO_ENCODER_CONTROL_PS_ALLOCATION;
8881
8882
8883#define ATOM_XTMDS_ASIC_SI164_ID 1
8884#define ATOM_XTMDS_ASIC_SI178_ID 2
8885#define ATOM_XTMDS_ASIC_TFP513_ID 3
8886#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
8887#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002
8888#define ATOM_XTMDS_MVPU_FPGA 0x00000004
8889
8890
8891typedef struct _ATOM_XTMDS_INFO
8892{
8893 ATOM_COMMON_TABLE_HEADER sHeader;
8894 USHORT usSingleLinkMaxFrequency;
8895 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip
8896 UCHAR ucXtransimitterID;
8897 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
8898 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
8899 // due to design. This ID is used to alert driver that the sequence is not "standard"!
8900 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
8901 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
8902}ATOM_XTMDS_INFO;
8903
8904typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
8905{
8906 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
8907 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
8908 UCHAR ucPadding[2];
8909}DFP_DPMS_STATUS_CHANGE_PARAMETERS;
8910
8911/****************************Legacy Power Play Table Definitions **********************/
8912
8913//Definitions for ulPowerPlayMiscInfo
8914#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L
8915#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L
8916#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L
8917
8918#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L
8919#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L
8920
8921#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L
8922
8923#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L
8924#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L
8925#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
8926
8927#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L
8928#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L
8929#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L
8930#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L
8931#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L
8932#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
8933#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L
8934
8935#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L
8936#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L
8937#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L
8938#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L
8939#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L
8940
8941#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
8942#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20
8943
8944#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L
8945#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L
8946#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L
8947#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic
8948#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic
8949#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode
8950
8951#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
8952#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28
8953#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L
8954
8955#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L
8956#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L
8957#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L
8958#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L
8959#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L
8960#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L
8961#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
8962 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
8963#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L
8964#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L
8965#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L
8966
8967//ucTableFormatRevision=1
8968//ucTableContentRevision=1
8969typedef struct _ATOM_POWERMODE_INFO
8970{
8971 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8972 ULONG ulReserved1; // must set to 0
8973 ULONG ulReserved2; // must set to 0
8974 USHORT usEngineClock;
8975 USHORT usMemoryClock;
8976 UCHAR ucVoltageDropIndex; // index to GPIO table
8977 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
8978 UCHAR ucMinTemperature;
8979 UCHAR ucMaxTemperature;
8980 UCHAR ucNumPciELanes; // number of PCIE lanes
8981}ATOM_POWERMODE_INFO;
8982
8983//ucTableFormatRevision=2
8984//ucTableContentRevision=1
8985typedef struct _ATOM_POWERMODE_INFO_V2
8986{
8987 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8988 ULONG ulMiscInfo2;
8989 ULONG ulEngineClock;
8990 ULONG ulMemoryClock;
8991 UCHAR ucVoltageDropIndex; // index to GPIO table
8992 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
8993 UCHAR ucMinTemperature;
8994 UCHAR ucMaxTemperature;
8995 UCHAR ucNumPciELanes; // number of PCIE lanes
8996}ATOM_POWERMODE_INFO_V2;
8997
8998//ucTableFormatRevision=2
8999//ucTableContentRevision=2
9000typedef struct _ATOM_POWERMODE_INFO_V3
9001{
9002 ULONG ulMiscInfo; //The power level should be arranged in ascending order
9003 ULONG ulMiscInfo2;
9004 ULONG ulEngineClock;
9005 ULONG ulMemoryClock;
9006 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
9007 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
9008 UCHAR ucMinTemperature;
9009 UCHAR ucMaxTemperature;
9010 UCHAR ucNumPciELanes; // number of PCIE lanes
9011 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
9012}ATOM_POWERMODE_INFO_V3;
9013
9014
9015#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
9016
9017#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01
9018#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02
9019
9020#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01
9021#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02
9022#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03
9023#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04
9024#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05
9025#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06
9026#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog
9027
9028
9029typedef struct _ATOM_POWERPLAY_INFO
9030{
9031 ATOM_COMMON_TABLE_HEADER sHeader;
9032 UCHAR ucOverdriveThermalController;
9033 UCHAR ucOverdriveI2cLine;
9034 UCHAR ucOverdriveIntBitmap;
9035 UCHAR ucOverdriveControllerAddress;
9036 UCHAR ucSizeOfPowerModeEntry;
9037 UCHAR ucNumOfPowerModeEntries;
9038 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
9039}ATOM_POWERPLAY_INFO;
9040
9041typedef struct _ATOM_POWERPLAY_INFO_V2
9042{
9043 ATOM_COMMON_TABLE_HEADER sHeader;
9044 UCHAR ucOverdriveThermalController;
9045 UCHAR ucOverdriveI2cLine;
9046 UCHAR ucOverdriveIntBitmap;
9047 UCHAR ucOverdriveControllerAddress;
9048 UCHAR ucSizeOfPowerModeEntry;
9049 UCHAR ucNumOfPowerModeEntries;
9050 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
9051}ATOM_POWERPLAY_INFO_V2;
9052
9053typedef struct _ATOM_POWERPLAY_INFO_V3
9054{
9055 ATOM_COMMON_TABLE_HEADER sHeader;
9056 UCHAR ucOverdriveThermalController;
9057 UCHAR ucOverdriveI2cLine;
9058 UCHAR ucOverdriveIntBitmap;
9059 UCHAR ucOverdriveControllerAddress;
9060 UCHAR ucSizeOfPowerModeEntry;
9061 UCHAR ucNumOfPowerModeEntries;
9062 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
9063}ATOM_POWERPLAY_INFO_V3;
9064
9065
9066
9067/**************************************************************************/
9068
9069
9070// Following definitions are for compatiblity issue in different SW components.
9071#define ATOM_MASTER_DATA_TABLE_REVISION 0x01
9072#define Object_Info Object_Header
9073#define AdjustARB_SEQ MC_InitParameter
9074#define VRAM_GPIO_DetectionInfo VoltageObjectInfo
9075#define ASIC_VDDCI_Info ASIC_ProfilingInfo
9076#define ASIC_MVDDQ_Info MemoryTrainingInfo
9077#define SS_Info PPLL_SS_Info
9078#define ASIC_MVDDC_Info ASIC_InternalSS_Info
9079#define DispDevicePriorityInfo SaveRestoreInfo
9080#define DispOutInfo TV_VideoMode
9081
9082
9083#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE
9084#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE
9085
9086//New device naming, remove them when both DAL/VBIOS is ready
9087#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
9088#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
9089
9090#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS
9091#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
9092
9093#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS
9094#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
9095
9096#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT
9097#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT
9098
9099#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX
9100#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX
9101
9102#define ATOM_DEVICE_DFP2I_INDEX 0x00000009
9103#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX)
9104
9105#define ATOM_S0_DFP1I ATOM_S0_DFP1
9106#define ATOM_S0_DFP1X ATOM_S0_DFP2
9107
9108#define ATOM_S0_DFP2I 0x00200000L
9109#define ATOM_S0_DFP2Ib2 0x20
9110
9111#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE
9112#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE
9113
9114#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L
9115#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02
9116
9117#define ATOM_S3_DFP2I_ACTIVEb1 0x02
9118
9119#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE
9120#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE
9121
9122#define ATOM_S3_DFP2I_ACTIVE 0x00000200L
9123
9124#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE
9125#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE
9126#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L
9127
9128
9129#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02
9130#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02
9131
9132#define ATOM_S5_DOS_REQ_DFP2I 0x0200
9133#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1
9134#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2
9135
9136#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02
9137#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L
9138
9139#define TMDS1XEncoderControl DVOEncoderControl
9140#define DFP1XOutputControl DVOOutputControl
9141
9142#define ExternalDFPOutputControl DFP1XOutputControl
9143#define EnableExternalTMDS_Encoder TMDS1XEncoderControl
9144
9145#define DFP1IOutputControl TMDSAOutputControl
9146#define DFP2IOutputControl LVTMAOutputControl
9147
9148#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
9149#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
9150
9151#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS
9152#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
9153
9154#define ucDac1Standard ucDacStandard
9155#define ucDac2Standard ucDacStandard
9156
9157#define TMDS1EncoderControl TMDSAEncoderControl
9158#define TMDS2EncoderControl LVTMAEncoderControl
9159
9160#define DFP1OutputControl TMDSAOutputControl
9161#define DFP2OutputControl LVTMAOutputControl
9162#define CRT1OutputControl DAC1OutputControl
9163#define CRT2OutputControl DAC2OutputControl
9164
9165//These two lines will be removed for sure in a few days, will follow up with Michael V.
9166#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL
9167#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL
9168
9169#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L
9170#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
9171#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
9172#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
9173#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE
9174
9175#define ATOM_S6_ACC_REQ_TV2 0x00400000L
9176#define ATOM_DEVICE_TV2_INDEX 0x00000006
9177#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX)
9178#define ATOM_S0_TV2 0x00100000L
9179#define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE
9180#define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE
9181
9182/*********************************************************************************/
9183
9184#pragma pack() // BIOS data must use byte alignment
9185
9186#pragma pack(1)
9187
9188typedef struct _ATOM_HOLE_INFO
9189{
9190 USHORT usOffset; // offset of the hole ( from the start of the binary )
9191 USHORT usLength; // length of the hole ( in bytes )
9192}ATOM_HOLE_INFO;
9193
9194typedef struct _ATOM_SERVICE_DESCRIPTION
9195{
9196 UCHAR ucRevision; // Holes set revision
9197 UCHAR ucAlgorithm; // Hash algorithm
9198 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )
9199 UCHAR ucReserved;
9200 USHORT usSigOffset; // Signature offset ( from the start of the binary )
9201 USHORT usSigLength; // Signature length
9202}ATOM_SERVICE_DESCRIPTION;
9203
9204
9205typedef struct _ATOM_SERVICE_INFO
9206{
9207 ATOM_COMMON_TABLE_HEADER asHeader;
9208 ATOM_SERVICE_DESCRIPTION asDescr;
9209 UCHAR ucholesNo; // number of holes that follow
9210 ATOM_HOLE_INFO holes[1]; // array of hole descriptions
9211}ATOM_SERVICE_INFO;
9212
9213
9214
9215#pragma pack() // BIOS data must use byte alignment
9216
9217//
9218// AMD ACPI Table
9219//
9220#pragma pack(1)
9221
9222typedef struct {
9223 ULONG Signature;
9224 ULONG TableLength; //Length
9225 UCHAR Revision;
9226 UCHAR Checksum;
9227 UCHAR OemId[6];
9228 UCHAR OemTableId[8]; //UINT64 OemTableId;
9229 ULONG OemRevision;
9230 ULONG CreatorId;
9231 ULONG CreatorRevision;
9232} AMD_ACPI_DESCRIPTION_HEADER;
9233/*
9234//EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h
9235typedef struct {
9236 UINT32 Signature; //0x0
9237 UINT32 Length; //0x4
9238 UINT8 Revision; //0x8
9239 UINT8 Checksum; //0x9
9240 UINT8 OemId[6]; //0xA
9241 UINT64 OemTableId; //0x10
9242 UINT32 OemRevision; //0x18
9243 UINT32 CreatorId; //0x1C
9244 UINT32 CreatorRevision; //0x20
9245}EFI_ACPI_DESCRIPTION_HEADER;
9246*/
9247typedef struct {
9248 AMD_ACPI_DESCRIPTION_HEADER SHeader;
9249 UCHAR TableUUID[16]; //0x24
9250 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
9251 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
9252 ULONG Reserved[4]; //0x3C
9253}UEFI_ACPI_VFCT;
9254
9255typedef struct {
9256 ULONG PCIBus; //0x4C
9257 ULONG PCIDevice; //0x50
9258 ULONG PCIFunction; //0x54
9259 USHORT VendorID; //0x58
9260 USHORT DeviceID; //0x5A
9261 USHORT SSVID; //0x5C
9262 USHORT SSID; //0x5E
9263 ULONG Revision; //0x60
9264 ULONG ImageLength; //0x64
9265}VFCT_IMAGE_HEADER;
9266
9267
9268typedef struct {
9269 VFCT_IMAGE_HEADER VbiosHeader;
9270 UCHAR VbiosContent[1];
9271}GOP_VBIOS_CONTENT;
9272
9273typedef struct {
9274 VFCT_IMAGE_HEADER Lib1Header;
9275 UCHAR Lib1Content[1];
9276}GOP_LIB1_CONTENT;
9277
9278#pragma pack()
9279
9280
9281#endif /* _ATOMBIOS_H */
9282
9283#include "pptable.h"
9284