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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <drm/drmP.h>
25#include <drm/drm_cache.h>
26#include "amdgpu.h"
27#include "gmc_v6_0.h"
28#include "amdgpu_ucode.h"
29
30#include "bif/bif_3_0_d.h"
31#include "bif/bif_3_0_sh_mask.h"
32#include "oss/oss_1_0_d.h"
33#include "oss/oss_1_0_sh_mask.h"
34#include "gmc/gmc_6_0_d.h"
35#include "gmc/gmc_6_0_sh_mask.h"
36#include "dce/dce_6_0_d.h"
37#include "dce/dce_6_0_sh_mask.h"
38#include "si_enums.h"
39
40static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
41static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
42static int gmc_v6_0_wait_for_idle(void *handle);
43
44MODULE_FIRMWARE("radeon/tahiti_mc.bin");
45MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
46MODULE_FIRMWARE("radeon/verde_mc.bin");
47MODULE_FIRMWARE("radeon/oland_mc.bin");
48MODULE_FIRMWARE("radeon/si58_mc.bin");
49
50#define MC_SEQ_MISC0__MT__MASK 0xf0000000
51#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
52#define MC_SEQ_MISC0__MT__DDR2 0x20000000
53#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
54#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
55#define MC_SEQ_MISC0__MT__GDDR5 0x50000000
56#define MC_SEQ_MISC0__MT__HBM 0x60000000
57#define MC_SEQ_MISC0__MT__DDR3 0xB0000000
58
59
60static const u32 crtc_offsets[6] =
61{
62 SI_CRTC0_REGISTER_OFFSET,
63 SI_CRTC1_REGISTER_OFFSET,
64 SI_CRTC2_REGISTER_OFFSET,
65 SI_CRTC3_REGISTER_OFFSET,
66 SI_CRTC4_REGISTER_OFFSET,
67 SI_CRTC5_REGISTER_OFFSET
68};
69
70static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
71{
72 u32 blackout;
73
74 gmc_v6_0_wait_for_idle((void *)adev);
75
76 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
77 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
78 /* Block CPU access */
79 WREG32(mmBIF_FB_EN, 0);
80 /* blackout the MC */
81 blackout = REG_SET_FIELD(blackout,
82 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
83 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
84 }
85 /* wait for the MC to settle */
86 udelay(100);
87
88}
89
90static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
91{
92 u32 tmp;
93
94 /* unblackout the MC */
95 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
96 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
97 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
98 /* allow CPU access */
99 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
100 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
101 WREG32(mmBIF_FB_EN, tmp);
102}
103
104static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
105{
106 const char *chip_name;
107 char fw_name[30];
108 int err;
109 bool is_58_fw = false;
110
111 DRM_DEBUG("\n");
112
113 switch (adev->asic_type) {
114 case CHIP_TAHITI:
115 chip_name = "tahiti";
116 break;
117 case CHIP_PITCAIRN:
118 chip_name = "pitcairn";
119 break;
120 case CHIP_VERDE:
121 chip_name = "verde";
122 break;
123 case CHIP_OLAND:
124 chip_name = "oland";
125 break;
126 case CHIP_HAINAN:
127 chip_name = "hainan";
128 break;
129 default: BUG();
130 }
131
132 /* this memory configuration requires special firmware */
133 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
134 is_58_fw = true;
135
136 if (is_58_fw)
137 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
138 else
139 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
140 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
141 if (err)
142 goto out;
143
144 err = amdgpu_ucode_validate(adev->gmc.fw);
145
146out:
147 if (err) {
148 dev_err(adev->dev,
149 "si_mc: Failed to load firmware \"%s\"\n",
150 fw_name);
151 release_firmware(adev->gmc.fw);
152 adev->gmc.fw = NULL;
153 }
154 return err;
155}
156
157static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
158{
159 const __le32 *new_fw_data = NULL;
160 u32 running;
161 const __le32 *new_io_mc_regs = NULL;
162 int i, regs_size, ucode_size;
163 const struct mc_firmware_header_v1_0 *hdr;
164
165 if (!adev->gmc.fw)
166 return -EINVAL;
167
168 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
169
170 amdgpu_ucode_print_mc_hdr(&hdr->header);
171
172 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
173 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
174 new_io_mc_regs = (const __le32 *)
175 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
176 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
177 new_fw_data = (const __le32 *)
178 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
179
180 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
181
182 if (running == 0) {
183
184 /* reset the engine and set to writable */
185 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
186 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
187
188 /* load mc io regs */
189 for (i = 0; i < regs_size; i++) {
190 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
191 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
192 }
193 /* load the MC ucode */
194 for (i = 0; i < ucode_size; i++) {
195 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
196 }
197
198 /* put the engine back into the active state */
199 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
201 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
202
203 /* wait for training to complete */
204 for (i = 0; i < adev->usec_timeout; i++) {
205 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
206 break;
207 udelay(1);
208 }
209 for (i = 0; i < adev->usec_timeout; i++) {
210 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
211 break;
212 udelay(1);
213 }
214
215 }
216
217 return 0;
218}
219
220static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
221 struct amdgpu_gmc *mc)
222{
223 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
224 base <<= 24;
225
226 amdgpu_device_vram_location(adev, &adev->gmc, base);
227 amdgpu_device_gart_location(adev, mc);
228}
229
230static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
231{
232 int i, j;
233
234 /* Initialize HDP */
235 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
236 WREG32((0xb05 + j), 0x00000000);
237 WREG32((0xb06 + j), 0x00000000);
238 WREG32((0xb07 + j), 0x00000000);
239 WREG32((0xb08 + j), 0x00000000);
240 WREG32((0xb09 + j), 0x00000000);
241 }
242 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
243
244 if (gmc_v6_0_wait_for_idle((void *)adev)) {
245 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
246 }
247
248 if (adev->mode_info.num_crtc) {
249 u32 tmp;
250
251 /* Lockout access through VGA aperture*/
252 tmp = RREG32(mmVGA_HDP_CONTROL);
253 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
254 WREG32(mmVGA_HDP_CONTROL, tmp);
255
256 /* disable VGA render */
257 tmp = RREG32(mmVGA_RENDER_CONTROL);
258 tmp &= ~VGA_VSTATUS_CNTL;
259 WREG32(mmVGA_RENDER_CONTROL, tmp);
260 }
261 /* Update configuration */
262 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
263 adev->gmc.vram_start >> 12);
264 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
265 adev->gmc.vram_end >> 12);
266 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
267 adev->vram_scratch.gpu_addr >> 12);
268 WREG32(mmMC_VM_AGP_BASE, 0);
269 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
270 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
271
272 if (gmc_v6_0_wait_for_idle((void *)adev)) {
273 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
274 }
275}
276
277static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
278{
279
280 u32 tmp;
281 int chansize, numchan;
282 int r;
283
284 tmp = RREG32(mmMC_ARB_RAMCFG);
285 if (tmp & (1 << 11)) {
286 chansize = 16;
287 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
288 chansize = 64;
289 } else {
290 chansize = 32;
291 }
292 tmp = RREG32(mmMC_SHARED_CHMAP);
293 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
294 case 0:
295 default:
296 numchan = 1;
297 break;
298 case 1:
299 numchan = 2;
300 break;
301 case 2:
302 numchan = 4;
303 break;
304 case 3:
305 numchan = 8;
306 break;
307 case 4:
308 numchan = 3;
309 break;
310 case 5:
311 numchan = 6;
312 break;
313 case 6:
314 numchan = 10;
315 break;
316 case 7:
317 numchan = 12;
318 break;
319 case 8:
320 numchan = 16;
321 break;
322 }
323 adev->gmc.vram_width = numchan * chansize;
324 /* size in MB on si */
325 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
326 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
327
328 if (!(adev->flags & AMD_IS_APU)) {
329 r = amdgpu_device_resize_fb_bar(adev);
330 if (r)
331 return r;
332 }
333 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
334 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
335 adev->gmc.visible_vram_size = adev->gmc.aper_size;
336
337 /* set the gart size */
338 if (amdgpu_gart_size == -1) {
339 switch (adev->asic_type) {
340 case CHIP_HAINAN: /* no MM engines */
341 default:
342 adev->gmc.gart_size = 256ULL << 20;
343 break;
344 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
345 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
346 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
347 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
348 adev->gmc.gart_size = 1024ULL << 20;
349 break;
350 }
351 } else {
352 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
353 }
354
355 gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
356
357 return 0;
358}
359
360static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
361{
362 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
363}
364
365static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
366 unsigned vmid, uint64_t pd_addr)
367{
368 uint32_t reg;
369
370 /* write new base address */
371 if (vmid < 8)
372 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
373 else
374 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
375 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
376
377 /* bits 0-15 are the VM contexts0-15 */
378 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
379
380 return pd_addr;
381}
382
383static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
384 uint32_t gpu_page_idx, uint64_t addr,
385 uint64_t flags)
386{
387 void __iomem *ptr = (void *)cpu_pt_addr;
388 uint64_t value;
389
390 value = addr & 0xFFFFFFFFFFFFF000ULL;
391 value |= flags;
392 writeq(value, ptr + (gpu_page_idx * 8));
393
394 return 0;
395}
396
397static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
398 uint32_t flags)
399{
400 uint64_t pte_flag = 0;
401
402 if (flags & AMDGPU_VM_PAGE_READABLE)
403 pte_flag |= AMDGPU_PTE_READABLE;
404 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
405 pte_flag |= AMDGPU_PTE_WRITEABLE;
406 if (flags & AMDGPU_VM_PAGE_PRT)
407 pte_flag |= AMDGPU_PTE_PRT;
408
409 return pte_flag;
410}
411
412static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
413 uint64_t *addr, uint64_t *flags)
414{
415 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
416}
417
418static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
419 bool value)
420{
421 u32 tmp;
422
423 tmp = RREG32(mmVM_CONTEXT1_CNTL);
424 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
425 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
426 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
427 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
428 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
429 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
430 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
431 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
432 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
433 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
434 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
435 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
436 WREG32(mmVM_CONTEXT1_CNTL, tmp);
437}
438
439 /**
440 + * gmc_v8_0_set_prt - set PRT VM fault
441 + *
442 + * @adev: amdgpu_device pointer
443 + * @enable: enable/disable VM fault handling for PRT
444 +*/
445static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
446{
447 u32 tmp;
448
449 if (enable && !adev->gmc.prt_warning) {
450 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
451 adev->gmc.prt_warning = true;
452 }
453
454 tmp = RREG32(mmVM_PRT_CNTL);
455 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
456 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
457 enable);
458 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
459 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
460 enable);
461 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
462 L2_CACHE_STORE_INVALID_ENTRIES,
463 enable);
464 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
465 L1_TLB_STORE_INVALID_ENTRIES,
466 enable);
467 WREG32(mmVM_PRT_CNTL, tmp);
468
469 if (enable) {
470 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
471 uint32_t high = adev->vm_manager.max_pfn -
472 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
473
474 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
475 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
476 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
477 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
478 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
479 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
480 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
481 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
482 } else {
483 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
484 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
485 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
486 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
487 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
488 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
489 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
490 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
491 }
492}
493
494static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
495{
496 int r, i;
497 u32 field;
498
499 if (adev->gart.robj == NULL) {
500 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
501 return -EINVAL;
502 }
503 r = amdgpu_gart_table_vram_pin(adev);
504 if (r)
505 return r;
506 /* Setup TLB control */
507 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
508 (0xA << 7) |
509 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
510 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
511 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
512 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
513 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
514 /* Setup L2 cache */
515 WREG32(mmVM_L2_CNTL,
516 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
517 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
518 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
519 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
520 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
521 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
522 WREG32(mmVM_L2_CNTL2,
523 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
524 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
525
526 field = adev->vm_manager.fragment_size;
527 WREG32(mmVM_L2_CNTL3,
528 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
529 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
530 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
531 /* setup context0 */
532 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
533 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
534 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
535 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
536 (u32)(adev->dummy_page_addr >> 12));
537 WREG32(mmVM_CONTEXT0_CNTL2, 0);
538 WREG32(mmVM_CONTEXT0_CNTL,
539 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
540 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
541 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
542
543 WREG32(0x575, 0);
544 WREG32(0x576, 0);
545 WREG32(0x577, 0);
546
547 /* empty context1-15 */
548 /* set vm size, must be a multiple of 4 */
549 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
550 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
551 /* Assign the pt base to something valid for now; the pts used for
552 * the VMs are determined by the application and setup and assigned
553 * on the fly in the vm part of radeon_gart.c
554 */
555 for (i = 1; i < 16; i++) {
556 if (i < 8)
557 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
558 adev->gart.table_addr >> 12);
559 else
560 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
561 adev->gart.table_addr >> 12);
562 }
563
564 /* enable context1-15 */
565 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
566 (u32)(adev->dummy_page_addr >> 12));
567 WREG32(mmVM_CONTEXT1_CNTL2, 4);
568 WREG32(mmVM_CONTEXT1_CNTL,
569 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
570 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
571 ((adev->vm_manager.block_size - 9)
572 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
573 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
574 gmc_v6_0_set_fault_enable_default(adev, false);
575 else
576 gmc_v6_0_set_fault_enable_default(adev, true);
577
578 gmc_v6_0_flush_gpu_tlb(adev, 0);
579 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
580 (unsigned)(adev->gmc.gart_size >> 20),
581 (unsigned long long)adev->gart.table_addr);
582 adev->gart.ready = true;
583 return 0;
584}
585
586static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
587{
588 int r;
589
590 if (adev->gart.robj) {
591 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
592 return 0;
593 }
594 r = amdgpu_gart_init(adev);
595 if (r)
596 return r;
597 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
598 adev->gart.gart_pte_flags = 0;
599 return amdgpu_gart_table_vram_alloc(adev);
600}
601
602static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
603{
604 /*unsigned i;
605
606 for (i = 1; i < 16; ++i) {
607 uint32_t reg;
608 if (i < 8)
609 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
610 else
611 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
612 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
613 }*/
614
615 /* Disable all tables */
616 WREG32(mmVM_CONTEXT0_CNTL, 0);
617 WREG32(mmVM_CONTEXT1_CNTL, 0);
618 /* Setup TLB control */
619 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
620 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
621 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
622 /* Setup L2 cache */
623 WREG32(mmVM_L2_CNTL,
624 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
625 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
626 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
627 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
628 WREG32(mmVM_L2_CNTL2, 0);
629 WREG32(mmVM_L2_CNTL3,
630 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
631 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
632 amdgpu_gart_table_vram_unpin(adev);
633}
634
635static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
636{
637 amdgpu_gart_table_vram_free(adev);
638 amdgpu_gart_fini(adev);
639}
640
641static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
642 u32 status, u32 addr, u32 mc_client)
643{
644 u32 mc_id;
645 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
646 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
647 PROTECTIONS);
648 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
649 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
650
651 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
652 MEMORY_CLIENT_ID);
653
654 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
655 protections, vmid, addr,
656 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
657 MEMORY_CLIENT_RW) ?
658 "write" : "read", block, mc_client, mc_id);
659}
660
661/*
662static const u32 mc_cg_registers[] = {
663 MC_HUB_MISC_HUB_CG,
664 MC_HUB_MISC_SIP_CG,
665 MC_HUB_MISC_VM_CG,
666 MC_XPB_CLK_GAT,
667 ATC_MISC_CG,
668 MC_CITF_MISC_WR_CG,
669 MC_CITF_MISC_RD_CG,
670 MC_CITF_MISC_VM_CG,
671 VM_L2_CG,
672};
673
674static const u32 mc_cg_ls_en[] = {
675 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
676 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
677 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
678 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
679 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
680 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
681 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
682 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
683 VM_L2_CG__MEM_LS_ENABLE_MASK,
684};
685
686static const u32 mc_cg_en[] = {
687 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
688 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
689 MC_HUB_MISC_VM_CG__ENABLE_MASK,
690 MC_XPB_CLK_GAT__ENABLE_MASK,
691 ATC_MISC_CG__ENABLE_MASK,
692 MC_CITF_MISC_WR_CG__ENABLE_MASK,
693 MC_CITF_MISC_RD_CG__ENABLE_MASK,
694 MC_CITF_MISC_VM_CG__ENABLE_MASK,
695 VM_L2_CG__ENABLE_MASK,
696};
697
698static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
699 bool enable)
700{
701 int i;
702 u32 orig, data;
703
704 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
705 orig = data = RREG32(mc_cg_registers[i]);
706 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
707 data |= mc_cg_ls_en[i];
708 else
709 data &= ~mc_cg_ls_en[i];
710 if (data != orig)
711 WREG32(mc_cg_registers[i], data);
712 }
713}
714
715static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
716 bool enable)
717{
718 int i;
719 u32 orig, data;
720
721 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
722 orig = data = RREG32(mc_cg_registers[i]);
723 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
724 data |= mc_cg_en[i];
725 else
726 data &= ~mc_cg_en[i];
727 if (data != orig)
728 WREG32(mc_cg_registers[i], data);
729 }
730}
731
732static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
733 bool enable)
734{
735 u32 orig, data;
736
737 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
738
739 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
740 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
741 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
742 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
743 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
744 } else {
745 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
746 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
747 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
748 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
749 }
750
751 if (orig != data)
752 WREG32_PCIE(ixPCIE_CNTL2, data);
753}
754
755static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
756 bool enable)
757{
758 u32 orig, data;
759
760 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
761
762 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
763 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
764 else
765 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
766
767 if (orig != data)
768 WREG32(mmHDP_HOST_PATH_CNTL, data);
769}
770
771static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
772 bool enable)
773{
774 u32 orig, data;
775
776 orig = data = RREG32(mmHDP_MEM_POWER_LS);
777
778 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
779 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
780 else
781 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
782
783 if (orig != data)
784 WREG32(mmHDP_MEM_POWER_LS, data);
785}
786*/
787
788static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
789{
790 switch (mc_seq_vram_type) {
791 case MC_SEQ_MISC0__MT__GDDR1:
792 return AMDGPU_VRAM_TYPE_GDDR1;
793 case MC_SEQ_MISC0__MT__DDR2:
794 return AMDGPU_VRAM_TYPE_DDR2;
795 case MC_SEQ_MISC0__MT__GDDR3:
796 return AMDGPU_VRAM_TYPE_GDDR3;
797 case MC_SEQ_MISC0__MT__GDDR4:
798 return AMDGPU_VRAM_TYPE_GDDR4;
799 case MC_SEQ_MISC0__MT__GDDR5:
800 return AMDGPU_VRAM_TYPE_GDDR5;
801 case MC_SEQ_MISC0__MT__DDR3:
802 return AMDGPU_VRAM_TYPE_DDR3;
803 default:
804 return AMDGPU_VRAM_TYPE_UNKNOWN;
805 }
806}
807
808static int gmc_v6_0_early_init(void *handle)
809{
810 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
811
812 gmc_v6_0_set_gmc_funcs(adev);
813 gmc_v6_0_set_irq_funcs(adev);
814
815 return 0;
816}
817
818static int gmc_v6_0_late_init(void *handle)
819{
820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
821
822 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
823 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
824 else
825 return 0;
826}
827
828static int gmc_v6_0_sw_init(void *handle)
829{
830 int r;
831 int dma_bits;
832 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
833
834 if (adev->flags & AMD_IS_APU) {
835 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
836 } else {
837 u32 tmp = RREG32(mmMC_SEQ_MISC0);
838 tmp &= MC_SEQ_MISC0__MT__MASK;
839 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
840 }
841
842 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
843 if (r)
844 return r;
845
846 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
847 if (r)
848 return r;
849
850 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
851
852 adev->gmc.mc_mask = 0xffffffffffULL;
853
854 adev->gmc.stolen_size = 256 * 1024;
855
856 adev->need_dma32 = false;
857 dma_bits = adev->need_dma32 ? 32 : 40;
858 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
859 if (r) {
860 adev->need_dma32 = true;
861 dma_bits = 32;
862 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
863 }
864 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
865 if (r) {
866 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
867 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
868 }
869 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
870
871 r = gmc_v6_0_init_microcode(adev);
872 if (r) {
873 dev_err(adev->dev, "Failed to load mc firmware!\n");
874 return r;
875 }
876
877 r = gmc_v6_0_mc_init(adev);
878 if (r)
879 return r;
880
881 r = amdgpu_bo_init(adev);
882 if (r)
883 return r;
884
885 r = gmc_v6_0_gart_init(adev);
886 if (r)
887 return r;
888
889 /*
890 * number of VMs
891 * VMID 0 is reserved for System
892 * amdgpu graphics/compute will use VMIDs 1-7
893 * amdkfd will use VMIDs 8-15
894 */
895 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
896 amdgpu_vm_manager_init(adev);
897
898 /* base offset of vram pages */
899 if (adev->flags & AMD_IS_APU) {
900 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
901
902 tmp <<= 22;
903 adev->vm_manager.vram_base_offset = tmp;
904 } else {
905 adev->vm_manager.vram_base_offset = 0;
906 }
907
908 return 0;
909}
910
911static int gmc_v6_0_sw_fini(void *handle)
912{
913 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
914
915 amdgpu_gem_force_release(adev);
916 amdgpu_vm_manager_fini(adev);
917 gmc_v6_0_gart_fini(adev);
918 amdgpu_bo_fini(adev);
919 release_firmware(adev->gmc.fw);
920 adev->gmc.fw = NULL;
921
922 return 0;
923}
924
925static int gmc_v6_0_hw_init(void *handle)
926{
927 int r;
928 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
929
930 gmc_v6_0_mc_program(adev);
931
932 if (!(adev->flags & AMD_IS_APU)) {
933 r = gmc_v6_0_mc_load_microcode(adev);
934 if (r) {
935 dev_err(adev->dev, "Failed to load MC firmware!\n");
936 return r;
937 }
938 }
939
940 r = gmc_v6_0_gart_enable(adev);
941 if (r)
942 return r;
943
944 return r;
945}
946
947static int gmc_v6_0_hw_fini(void *handle)
948{
949 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
950
951 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
952 gmc_v6_0_gart_disable(adev);
953
954 return 0;
955}
956
957static int gmc_v6_0_suspend(void *handle)
958{
959 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
960
961 gmc_v6_0_hw_fini(adev);
962
963 return 0;
964}
965
966static int gmc_v6_0_resume(void *handle)
967{
968 int r;
969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
970
971 r = gmc_v6_0_hw_init(adev);
972 if (r)
973 return r;
974
975 amdgpu_vmid_reset_all(adev);
976
977 return 0;
978}
979
980static bool gmc_v6_0_is_idle(void *handle)
981{
982 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
983 u32 tmp = RREG32(mmSRBM_STATUS);
984
985 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
986 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
987 return false;
988
989 return true;
990}
991
992static int gmc_v6_0_wait_for_idle(void *handle)
993{
994 unsigned i;
995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
996
997 for (i = 0; i < adev->usec_timeout; i++) {
998 if (gmc_v6_0_is_idle(handle))
999 return 0;
1000 udelay(1);
1001 }
1002 return -ETIMEDOUT;
1003
1004}
1005
1006static int gmc_v6_0_soft_reset(void *handle)
1007{
1008 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1009 u32 srbm_soft_reset = 0;
1010 u32 tmp = RREG32(mmSRBM_STATUS);
1011
1012 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1013 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1014 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1015
1016 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1017 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1018 if (!(adev->flags & AMD_IS_APU))
1019 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1020 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1021 }
1022
1023 if (srbm_soft_reset) {
1024 gmc_v6_0_mc_stop(adev);
1025 if (gmc_v6_0_wait_for_idle(adev)) {
1026 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1027 }
1028
1029
1030 tmp = RREG32(mmSRBM_SOFT_RESET);
1031 tmp |= srbm_soft_reset;
1032 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1033 WREG32(mmSRBM_SOFT_RESET, tmp);
1034 tmp = RREG32(mmSRBM_SOFT_RESET);
1035
1036 udelay(50);
1037
1038 tmp &= ~srbm_soft_reset;
1039 WREG32(mmSRBM_SOFT_RESET, tmp);
1040 tmp = RREG32(mmSRBM_SOFT_RESET);
1041
1042 udelay(50);
1043
1044 gmc_v6_0_mc_resume(adev);
1045 udelay(50);
1046 }
1047
1048 return 0;
1049}
1050
1051static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1052 struct amdgpu_irq_src *src,
1053 unsigned type,
1054 enum amdgpu_interrupt_state state)
1055{
1056 u32 tmp;
1057 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1058 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1059 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1060 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1061 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1062 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1063
1064 switch (state) {
1065 case AMDGPU_IRQ_STATE_DISABLE:
1066 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1067 tmp &= ~bits;
1068 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1069 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1070 tmp &= ~bits;
1071 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1072 break;
1073 case AMDGPU_IRQ_STATE_ENABLE:
1074 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1075 tmp |= bits;
1076 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1077 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1078 tmp |= bits;
1079 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1080 break;
1081 default:
1082 break;
1083 }
1084
1085 return 0;
1086}
1087
1088static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1089 struct amdgpu_irq_src *source,
1090 struct amdgpu_iv_entry *entry)
1091{
1092 u32 addr, status;
1093
1094 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1095 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1096 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1097
1098 if (!addr && !status)
1099 return 0;
1100
1101 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1102 gmc_v6_0_set_fault_enable_default(adev, false);
1103
1104 if (printk_ratelimit()) {
1105 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1106 entry->src_id, entry->src_data[0]);
1107 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1108 addr);
1109 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1110 status);
1111 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1112 }
1113
1114 return 0;
1115}
1116
1117static int gmc_v6_0_set_clockgating_state(void *handle,
1118 enum amd_clockgating_state state)
1119{
1120 return 0;
1121}
1122
1123static int gmc_v6_0_set_powergating_state(void *handle,
1124 enum amd_powergating_state state)
1125{
1126 return 0;
1127}
1128
1129static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1130 .name = "gmc_v6_0",
1131 .early_init = gmc_v6_0_early_init,
1132 .late_init = gmc_v6_0_late_init,
1133 .sw_init = gmc_v6_0_sw_init,
1134 .sw_fini = gmc_v6_0_sw_fini,
1135 .hw_init = gmc_v6_0_hw_init,
1136 .hw_fini = gmc_v6_0_hw_fini,
1137 .suspend = gmc_v6_0_suspend,
1138 .resume = gmc_v6_0_resume,
1139 .is_idle = gmc_v6_0_is_idle,
1140 .wait_for_idle = gmc_v6_0_wait_for_idle,
1141 .soft_reset = gmc_v6_0_soft_reset,
1142 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1143 .set_powergating_state = gmc_v6_0_set_powergating_state,
1144};
1145
1146static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1147 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1148 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1149 .set_pte_pde = gmc_v6_0_set_pte_pde,
1150 .set_prt = gmc_v6_0_set_prt,
1151 .get_vm_pde = gmc_v6_0_get_vm_pde,
1152 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1153};
1154
1155static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1156 .set = gmc_v6_0_vm_fault_interrupt_state,
1157 .process = gmc_v6_0_process_interrupt,
1158};
1159
1160static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1161{
1162 if (adev->gmc.gmc_funcs == NULL)
1163 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1164}
1165
1166static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1167{
1168 adev->gmc.vm_fault.num_types = 1;
1169 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1170}
1171
1172const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1173{
1174 .type = AMD_IP_BLOCK_TYPE_GMC,
1175 .major = 6,
1176 .minor = 0,
1177 .rev = 0,
1178 .funcs = &gmc_v6_0_ip_funcs,
1179};