1/*
  2 * AppliedMicro X-Gene SoC GPIO Driver
  3 *
  4 * Copyright (c) 2014, Applied Micro Circuits Corporation
  5 * Author: Feng Kan <fkan@apm.com>.
  6 *
  7 * This program is free software; you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License version 2 as
  9 * published by the Free Software Foundation.
 10 *
 11 * This program is distributed in the hope that it will be useful,
 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14 * GNU General Public License for more details.
 15 *
 16 * You should have received a copy of the GNU General Public License
 17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 18 */
 19
 20#include <linux/acpi.h>
 21#include <linux/kernel.h>
 22#include <linux/init.h>
 23#include <linux/io.h>
 24#include <linux/spinlock.h>
 25#include <linux/platform_device.h>
 26#include <linux/gpio/driver.h>
 27#include <linux/types.h>
 28#include <linux/bitops.h>
 29
 30#define GPIO_SET_DR_OFFSET	0x0C
 31#define GPIO_DATA_OFFSET	0x14
 32#define GPIO_BANK_STRIDE	0x0C
 33
 34#define XGENE_GPIOS_PER_BANK	16
 35#define XGENE_MAX_GPIO_BANKS	3
 36#define XGENE_MAX_GPIOS		(XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS)
 37
 38#define GPIO_BIT_OFFSET(x)	(x % XGENE_GPIOS_PER_BANK)
 39#define GPIO_BANK_OFFSET(x)	((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE)
 40
 41struct xgene_gpio {
 42	struct gpio_chip	chip;
 43	void __iomem		*base;
 44	spinlock_t		lock;
 45	u32			set_dr_val[XGENE_MAX_GPIO_BANKS];
 46};
 47
 48static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset)
 49{
 50	struct xgene_gpio *chip = gpiochip_get_data(gc);
 51	unsigned long bank_offset;
 52	u32 bit_offset;
 53
 54	bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset);
 55	bit_offset = GPIO_BIT_OFFSET(offset);
 56	return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
 57}
 58
 59static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
 60{
 61	struct xgene_gpio *chip = gpiochip_get_data(gc);
 62	unsigned long bank_offset;
 63	u32 setval, bit_offset;
 64
 65	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
 66	bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK;
 67
 68	setval = ioread32(chip->base + bank_offset);
 69	if (val)
 70		setval |= BIT(bit_offset);
 71	else
 72		setval &= ~BIT(bit_offset);
 73	iowrite32(setval, chip->base + bank_offset);
 74}
 75
 76static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
 77{
 78	struct xgene_gpio *chip = gpiochip_get_data(gc);
 79	unsigned long flags;
 80
 81	spin_lock_irqsave(&chip->lock, flags);
 82	__xgene_gpio_set(gc, offset, val);
 83	spin_unlock_irqrestore(&chip->lock, flags);
 84}
 85
 86static int xgene_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 87{
 88	struct xgene_gpio *chip = gpiochip_get_data(gc);
 89	unsigned long bank_offset, bit_offset;
 90
 91	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
 92	bit_offset = GPIO_BIT_OFFSET(offset);
 93
 94	return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset));
 95}
 96
 97static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
 98{
 99	struct xgene_gpio *chip = gpiochip_get_data(gc);
100	unsigned long flags, bank_offset;
101	u32 dirval, bit_offset;
102
103	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
104	bit_offset = GPIO_BIT_OFFSET(offset);
105
106	spin_lock_irqsave(&chip->lock, flags);
107
108	dirval = ioread32(chip->base + bank_offset);
109	dirval |= BIT(bit_offset);
110	iowrite32(dirval, chip->base + bank_offset);
111
112	spin_unlock_irqrestore(&chip->lock, flags);
113
114	return 0;
115}
116
117static int xgene_gpio_dir_out(struct gpio_chip *gc,
118					unsigned int offset, int val)
119{
120	struct xgene_gpio *chip = gpiochip_get_data(gc);
121	unsigned long flags, bank_offset;
122	u32 dirval, bit_offset;
123
124	bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset);
125	bit_offset = GPIO_BIT_OFFSET(offset);
126
127	spin_lock_irqsave(&chip->lock, flags);
128
129	dirval = ioread32(chip->base + bank_offset);
130	dirval &= ~BIT(bit_offset);
131	iowrite32(dirval, chip->base + bank_offset);
132	__xgene_gpio_set(gc, offset, val);
133
134	spin_unlock_irqrestore(&chip->lock, flags);
135
136	return 0;
137}
138
139static __maybe_unused int xgene_gpio_suspend(struct device *dev)
140{
141	struct xgene_gpio *gpio = dev_get_drvdata(dev);
142	unsigned long bank_offset;
143	unsigned int bank;
144
145	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
146		bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
147		gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset);
148	}
149	return 0;
150}
151
152static __maybe_unused int xgene_gpio_resume(struct device *dev)
153{
154	struct xgene_gpio *gpio = dev_get_drvdata(dev);
155	unsigned long bank_offset;
156	unsigned int bank;
157
158	for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) {
159		bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE;
160		iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset);
161	}
162	return 0;
163}
164
165static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume);
166
167static int xgene_gpio_probe(struct platform_device *pdev)
168{
169	struct resource *res;
170	struct xgene_gpio *gpio;
171	int err = 0;
172
173	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
174	if (!gpio) {
175		err = -ENOMEM;
176		goto err;
177	}
178
179	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
180	if (!res) {
181		err = -EINVAL;
182		goto err;
183	}
184
185	gpio->base = devm_ioremap_nocache(&pdev->dev, res->start,
186							resource_size(res));
187	if (!gpio->base) {
188		err = -ENOMEM;
189		goto err;
190	}
191
192	gpio->chip.ngpio = XGENE_MAX_GPIOS;
193
194	spin_lock_init(&gpio->lock);
195	gpio->chip.parent = &pdev->dev;
196	gpio->chip.get_direction = xgene_gpio_get_direction;
197	gpio->chip.direction_input = xgene_gpio_dir_in;
198	gpio->chip.direction_output = xgene_gpio_dir_out;
199	gpio->chip.get = xgene_gpio_get;
200	gpio->chip.set = xgene_gpio_set;
201	gpio->chip.label = dev_name(&pdev->dev);
202	gpio->chip.base = -1;
203
204	platform_set_drvdata(pdev, gpio);
205
206	err = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
207	if (err) {
208		dev_err(&pdev->dev,
209			"failed to register gpiochip.\n");
210		goto err;
211	}
212
213	dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n");
214	return 0;
215err:
216	dev_err(&pdev->dev, "X-Gene GPIO driver registration failed.\n");
217	return err;
218}
219
220static const struct of_device_id xgene_gpio_of_match[] = {
221	{ .compatible = "apm,xgene-gpio", },
222	{},
223};
224
225#ifdef CONFIG_ACPI
226static const struct acpi_device_id xgene_gpio_acpi_match[] = {
227	{ "APMC0D14", 0 },
228	{ },
229};
230#endif
231
232static struct platform_driver xgene_gpio_driver = {
233	.driver = {
234		.name = "xgene-gpio",
235		.of_match_table = xgene_gpio_of_match,
236		.acpi_match_table = ACPI_PTR(xgene_gpio_acpi_match),
237		.pm     = &xgene_gpio_pm,
238	},
239	.probe = xgene_gpio_probe,
240};
241builtin_platform_driver(xgene_gpio_driver);