1/*
  2 * Copyright (C) 2010 Google, Inc.
  3 *
  4 * Author:
  5 *	Colin Cross <ccross@google.com>
  6 *
  7 * This software is licensed under the terms of the GNU General Public
  8 * License version 2, as published by the Free Software Foundation, and
  9 * may be copied, distributed, and modified under those terms.
 10 *
 11 * This program is distributed in the hope that it will be useful,
 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14 * GNU General Public License for more details.
 15 *
 16 */
 17
 18#include <linux/init.h>
 19#include <linux/err.h>
 20#include <linux/time.h>
 21#include <linux/interrupt.h>
 22#include <linux/irq.h>
 23#include <linux/clockchips.h>
 24#include <linux/clocksource.h>
 25#include <linux/clk.h>
 26#include <linux/io.h>
 27#include <linux/of_address.h>
 28#include <linux/of_irq.h>
 29#include <linux/sched_clock.h>
 30#include <linux/delay.h>
 31
 32#include <asm/mach/time.h>
 33#include <asm/smp_twd.h>
 34
 35#define RTC_SECONDS            0x08
 36#define RTC_SHADOW_SECONDS     0x0c
 37#define RTC_MILLISECONDS       0x10
 38
 39#define TIMERUS_CNTR_1US 0x10
 40#define TIMERUS_USEC_CFG 0x14
 41#define TIMERUS_CNTR_FREEZE 0x4c
 42
 43#define TIMER1_BASE 0x0
 44#define TIMER2_BASE 0x8
 45#define TIMER3_BASE 0x50
 46#define TIMER4_BASE 0x58
 47
 48#define TIMER_PTV 0x0
 49#define TIMER_PCR 0x4
 50
 51static void __iomem *timer_reg_base;
 52static void __iomem *rtc_base;
 53
 54static struct timespec64 persistent_ts;
 55static u64 persistent_ms, last_persistent_ms;
 56
 57static struct delay_timer tegra_delay_timer;
 58
 59#define timer_writel(value, reg) \
 60	writel_relaxed(value, timer_reg_base + (reg))
 61#define timer_readl(reg) \
 62	readl_relaxed(timer_reg_base + (reg))
 63
 64static int tegra_timer_set_next_event(unsigned long cycles,
 65					 struct clock_event_device *evt)
 66{
 67	u32 reg;
 68
 69	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
 70	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
 71
 72	return 0;
 73}
 74
 75static inline void timer_shutdown(struct clock_event_device *evt)
 76{
 77	timer_writel(0, TIMER3_BASE + TIMER_PTV);
 78}
 79
 80static int tegra_timer_shutdown(struct clock_event_device *evt)
 81{
 82	timer_shutdown(evt);
 83	return 0;
 84}
 85
 86static int tegra_timer_set_periodic(struct clock_event_device *evt)
 87{
 88	u32 reg = 0xC0000000 | ((1000000 / HZ) - 1);
 89
 90	timer_shutdown(evt);
 91	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
 92	return 0;
 93}
 94
 95static struct clock_event_device tegra_clockevent = {
 96	.name			= "timer0",
 97	.rating			= 300,
 98	.features		= CLOCK_EVT_FEAT_ONESHOT |
 99				  CLOCK_EVT_FEAT_PERIODIC |
100				  CLOCK_EVT_FEAT_DYNIRQ,
101	.set_next_event		= tegra_timer_set_next_event,
102	.set_state_shutdown	= tegra_timer_shutdown,
103	.set_state_periodic	= tegra_timer_set_periodic,
104	.set_state_oneshot	= tegra_timer_shutdown,
105	.tick_resume		= tegra_timer_shutdown,
106};
107
108static u64 notrace tegra_read_sched_clock(void)
109{
110	return timer_readl(TIMERUS_CNTR_1US);
111}
112
113/*
114 * tegra_rtc_read - Reads the Tegra RTC registers
115 * Care must be taken that this funciton is not called while the
116 * tegra_rtc driver could be executing to avoid race conditions
117 * on the RTC shadow register
118 */
119static u64 tegra_rtc_read_ms(void)
120{
121	u32 ms = readl(rtc_base + RTC_MILLISECONDS);
122	u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
123	return (u64)s * MSEC_PER_SEC + ms;
124}
125
126/*
127 * tegra_read_persistent_clock64 -  Return time from a persistent clock.
128 *
129 * Reads the time from a source which isn't disabled during PM, the
130 * 32k sync timer.  Convert the cycles elapsed since last read into
131 * nsecs and adds to a monotonically increasing timespec64.
132 * Care must be taken that this funciton is not called while the
133 * tegra_rtc driver could be executing to avoid race conditions
134 * on the RTC shadow register
135 */
136static void tegra_read_persistent_clock64(struct timespec64 *ts)
137{
138	u64 delta;
139
140	last_persistent_ms = persistent_ms;
141	persistent_ms = tegra_rtc_read_ms();
142	delta = persistent_ms - last_persistent_ms;
143
144	timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC);
145	*ts = persistent_ts;
146}
147
148static unsigned long tegra_delay_timer_read_counter_long(void)
149{
150	return readl(timer_reg_base + TIMERUS_CNTR_1US);
151}
152
153static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
154{
155	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
156	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
157	evt->event_handler(evt);
158	return IRQ_HANDLED;
159}
160
161static struct irqaction tegra_timer_irq = {
162	.name		= "timer0",
163	.flags		= IRQF_TIMER | IRQF_TRIGGER_HIGH,
164	.handler	= tegra_timer_interrupt,
165	.dev_id		= &tegra_clockevent,
166};
167
168static int __init tegra20_init_timer(struct device_node *np)
169{
170	struct clk *clk;
171	unsigned long rate;
172	int ret;
173
174	timer_reg_base = of_iomap(np, 0);
175	if (!timer_reg_base) {
176		pr_err("Can't map timer registers\n");
177		return -ENXIO;
178	}
179
180	tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
181	if (tegra_timer_irq.irq <= 0) {
182		pr_err("Failed to map timer IRQ\n");
183		return -EINVAL;
184	}
185
186	clk = of_clk_get(np, 0);
187	if (IS_ERR(clk)) {
188		pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
189		rate = 12000000;
190	} else {
191		clk_prepare_enable(clk);
192		rate = clk_get_rate(clk);
193	}
194
195	switch (rate) {
196	case 12000000:
197		timer_writel(0x000b, TIMERUS_USEC_CFG);
198		break;
199	case 13000000:
200		timer_writel(0x000c, TIMERUS_USEC_CFG);
201		break;
202	case 19200000:
203		timer_writel(0x045f, TIMERUS_USEC_CFG);
204		break;
205	case 26000000:
206		timer_writel(0x0019, TIMERUS_USEC_CFG);
207		break;
208	default:
209		WARN(1, "Unknown clock rate");
210	}
211
212	sched_clock_register(tegra_read_sched_clock, 32, 1000000);
213
214	ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
215				    "timer_us", 1000000, 300, 32,
216				    clocksource_mmio_readl_up);
217	if (ret) {
218		pr_err("Failed to register clocksource\n");
219		return ret;
220	}
221
222	tegra_delay_timer.read_current_timer =
223			tegra_delay_timer_read_counter_long;
224	tegra_delay_timer.freq = 1000000;
225	register_current_timer_delay(&tegra_delay_timer);
226
227	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
228	if (ret) {
229		pr_err("Failed to register timer IRQ: %d\n", ret);
230		return ret;
231	}
232
233	tegra_clockevent.cpumask = cpu_all_mask;
234	tegra_clockevent.irq = tegra_timer_irq.irq;
235	clockevents_config_and_register(&tegra_clockevent, 1000000,
236					0x1, 0x1fffffff);
237
238	return 0;
239}
240TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
241
242static int __init tegra20_init_rtc(struct device_node *np)
243{
244	struct clk *clk;
245
246	rtc_base = of_iomap(np, 0);
247	if (!rtc_base) {
248		pr_err("Can't map RTC registers\n");
249		return -ENXIO;
250	}
251
252	/*
253	 * rtc registers are used by read_persistent_clock, keep the rtc clock
254	 * enabled
255	 */
256	clk = of_clk_get(np, 0);
257	if (IS_ERR(clk))
258		pr_warn("Unable to get rtc-tegra clock\n");
259	else
260		clk_prepare_enable(clk);
261
262	return register_persistent_clock(NULL, tegra_read_persistent_clock64);
263}
264TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);