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1/*
2 * Purna Chandra Mandal,<purna.mandal@microchip.com>
3 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 */
14#include <dt-bindings/clock/microchip,pic32-clock.h>
15#include <linux/clk.h>
16#include <linux/clk-provider.h>
17#include <linux/clkdev.h>
18#include <linux/module.h>
19#include <linux/of_address.h>
20#include <linux/of_platform.h>
21#include <linux/platform_device.h>
22#include <asm/traps.h>
23
24#include "clk-core.h"
25
26/* FRC Postscaler */
27#define OSC_FRCDIV_MASK 0x07
28#define OSC_FRCDIV_SHIFT 24
29
30/* SPLL fields */
31#define PLL_ICLK_MASK 0x01
32#define PLL_ICLK_SHIFT 7
33
34#define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags) \
35 { \
36 .ctrl_reg = (__reg), \
37 .init_data = { \
38 .name = (__clk_name), \
39 .parent_names = (const char *[]) { \
40 "sys_clk" \
41 }, \
42 .num_parents = 1, \
43 .ops = &pic32_pbclk_ops, \
44 .flags = (__flags), \
45 }, \
46 }
47
48#define DECLARE_REFO_CLOCK(__clkid, __reg) \
49 { \
50 .ctrl_reg = (__reg), \
51 .init_data = { \
52 .name = "refo" #__clkid "_clk", \
53 .parent_names = (const char *[]) { \
54 "sys_clk", "pb1_clk", "posc_clk", \
55 "frc_clk", "lprc_clk", "sosc_clk", \
56 "sys_pll", "refi" #__clkid "_clk", \
57 "bfrc_clk", \
58 }, \
59 .num_parents = 9, \
60 .flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,\
61 .ops = &pic32_roclk_ops, \
62 }, \
63 .parent_map = (const u32[]) { \
64 0, 1, 2, 3, 4, 5, 7, 8, 9 \
65 }, \
66 }
67
68static const struct pic32_ref_osc_data ref_clks[] = {
69 DECLARE_REFO_CLOCK(1, 0x80),
70 DECLARE_REFO_CLOCK(2, 0xa0),
71 DECLARE_REFO_CLOCK(3, 0xc0),
72 DECLARE_REFO_CLOCK(4, 0xe0),
73 DECLARE_REFO_CLOCK(5, 0x100),
74};
75
76static const struct pic32_periph_clk_data periph_clocks[] = {
77 DECLARE_PERIPHERAL_CLOCK("pb1_clk", 0x140, 0),
78 DECLARE_PERIPHERAL_CLOCK("pb2_clk", 0x150, CLK_IGNORE_UNUSED),
79 DECLARE_PERIPHERAL_CLOCK("pb3_clk", 0x160, 0),
80 DECLARE_PERIPHERAL_CLOCK("pb4_clk", 0x170, 0),
81 DECLARE_PERIPHERAL_CLOCK("pb5_clk", 0x180, 0),
82 DECLARE_PERIPHERAL_CLOCK("pb6_clk", 0x190, 0),
83 DECLARE_PERIPHERAL_CLOCK("cpu_clk", 0x1a0, CLK_IGNORE_UNUSED),
84};
85
86static const struct pic32_sys_clk_data sys_mux_clk = {
87 .slew_reg = 0x1c0,
88 .slew_div = 2, /* step of div_4 -> div_2 -> no_div */
89 .init_data = {
90 .name = "sys_clk",
91 .parent_names = (const char *[]) {
92 "frcdiv_clk", "sys_pll", "posc_clk",
93 "sosc_clk", "lprc_clk", "frcdiv_clk",
94 },
95 .num_parents = 6,
96 .ops = &pic32_sclk_ops,
97 },
98 .parent_map = (const u32[]) {
99 0, 1, 2, 4, 5, 7,
100 },
101};
102
103static const struct pic32_sys_pll_data sys_pll = {
104 .ctrl_reg = 0x020,
105 .status_reg = 0x1d0,
106 .lock_mask = BIT(7),
107 .init_data = {
108 .name = "sys_pll",
109 .parent_names = (const char *[]) {
110 "spll_mux_clk"
111 },
112 .num_parents = 1,
113 .ops = &pic32_spll_ops,
114 },
115};
116
117static const struct pic32_sec_osc_data sosc_clk = {
118 .status_reg = 0x1d0,
119 .enable_mask = BIT(1),
120 .status_mask = BIT(4),
121 .fixed_rate = 32768,
122 .init_data = {
123 .name = "sosc_clk",
124 .parent_names = NULL,
125 .ops = &pic32_sosc_ops,
126 },
127};
128
129static int pic32mzda_critical_clks[] = {
130 PB2CLK, PB7CLK
131};
132
133/* PIC32MZDA clock data */
134struct pic32mzda_clk_data {
135 struct clk *clks[MAXCLKS];
136 struct pic32_clk_common core;
137 struct clk_onecell_data onecell_data;
138 struct notifier_block failsafe_notifier;
139};
140
141static int pic32_fscm_nmi(struct notifier_block *nb,
142 unsigned long action, void *data)
143{
144 struct pic32mzda_clk_data *cd;
145
146 cd = container_of(nb, struct pic32mzda_clk_data, failsafe_notifier);
147
148 /* SYSCLK is now running from BFRCCLK. Report clock failure. */
149 if (readl(cd->core.iobase) & BIT(2))
150 pr_alert("pic32-clk: FSCM detected clk failure.\n");
151
152 /* TODO: detect reason of failure and recover accordingly */
153
154 return NOTIFY_OK;
155}
156
157static int pic32mzda_clk_probe(struct platform_device *pdev)
158{
159 const char *const pll_mux_parents[] = {"posc_clk", "frc_clk"};
160 struct device_node *np = pdev->dev.of_node;
161 struct pic32mzda_clk_data *cd;
162 struct pic32_clk_common *core;
163 struct clk *pll_mux_clk, *clk;
164 struct clk **clks;
165 int nr_clks, i, ret;
166
167 cd = devm_kzalloc(&pdev->dev, sizeof(*cd), GFP_KERNEL);
168 if (!cd)
169 return -ENOMEM;
170
171 core = &cd->core;
172 core->iobase = of_io_request_and_map(np, 0, of_node_full_name(np));
173 if (IS_ERR(core->iobase)) {
174 dev_err(&pdev->dev, "pic32-clk: failed to map registers\n");
175 return PTR_ERR(core->iobase);
176 }
177
178 spin_lock_init(&core->reg_lock);
179 core->dev = &pdev->dev;
180 clks = &cd->clks[0];
181
182 /* register fixed rate clocks */
183 clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL,
184 0, 24000000);
185 clks[FRCCLK] = clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL,
186 0, 8000000);
187 clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL,
188 0, 8000000);
189 clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL,
190 0, 32000);
191 clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL,
192 0, 24000000);
193 /* fixed rate (optional) clock */
194 if (of_find_property(np, "microchip,pic32mzda-sosc", NULL)) {
195 pr_info("pic32-clk: dt requests SOSC.\n");
196 clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core);
197 }
198 /* divider clock */
199 clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
200 "frc_clk", 0,
201 core->iobase,
202 OSC_FRCDIV_SHIFT,
203 OSC_FRCDIV_MASK,
204 CLK_DIVIDER_POWER_OF_TWO,
205 &core->reg_lock);
206 /* PLL ICLK mux */
207 pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk",
208 pll_mux_parents, 2, 0,
209 core->iobase + 0x020,
210 PLL_ICLK_SHIFT, 1, 0, &core->reg_lock);
211 if (IS_ERR(pll_mux_clk))
212 pr_err("spll_mux_clk: clk register failed\n");
213
214 /* PLL */
215 clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core);
216 /* SYSTEM clock */
217 clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core);
218 /* Peripheral bus clocks */
219 for (nr_clks = PB1CLK, i = 0; nr_clks <= PB7CLK; i++, nr_clks++)
220 clks[nr_clks] = pic32_periph_clk_register(&periph_clocks[i],
221 core);
222 /* Reference oscillator clock */
223 for (nr_clks = REF1CLK, i = 0; nr_clks <= REF5CLK; i++, nr_clks++)
224 clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core);
225
226 /* register clkdev */
227 for (i = 0; i < MAXCLKS; i++) {
228 if (IS_ERR(clks[i]))
229 continue;
230 clk_register_clkdev(clks[i], NULL, __clk_get_name(clks[i]));
231 }
232
233 /* register clock provider */
234 cd->onecell_data.clks = clks;
235 cd->onecell_data.clk_num = MAXCLKS;
236 ret = of_clk_add_provider(np, of_clk_src_onecell_get,
237 &cd->onecell_data);
238 if (ret)
239 return ret;
240
241 /* force enable critical clocks */
242 for (i = 0; i < ARRAY_SIZE(pic32mzda_critical_clks); i++) {
243 clk = clks[pic32mzda_critical_clks[i]];
244 if (clk_prepare_enable(clk))
245 dev_err(&pdev->dev, "clk_prepare_enable(%s) failed\n",
246 __clk_get_name(clk));
247 }
248
249 /* register NMI for failsafe clock monitor */
250 cd->failsafe_notifier.notifier_call = pic32_fscm_nmi;
251 return register_nmi_notifier(&cd->failsafe_notifier);
252}
253
254static const struct of_device_id pic32mzda_clk_match_table[] = {
255 { .compatible = "microchip,pic32mzda-clk", },
256 { }
257};
258MODULE_DEVICE_TABLE(of, pic32mzda_clk_match_table);
259
260static struct platform_driver pic32mzda_clk_driver = {
261 .probe = pic32mzda_clk_probe,
262 .driver = {
263 .name = "clk-pic32mzda",
264 .of_match_table = pic32mzda_clk_match_table,
265 },
266};
267
268static int __init microchip_pic32mzda_clk_init(void)
269{
270 return platform_driver_register(&pic32mzda_clk_driver);
271}
272core_initcall(microchip_pic32mzda_clk_init);
273
274MODULE_DESCRIPTION("Microchip PIC32MZDA Clock Driver");
275MODULE_LICENSE("GPL v2");
276MODULE_ALIAS("platform:clk-pic32mzda");