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1/*
2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
4 */
5#include <linux/highmem.h>
6#include <linux/bootmem.h>
7#include <linux/module.h>
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <linux/interrupt.h>
11#include <linux/seq_file.h>
12#include <linux/debugfs.h>
13#include <linux/pfn.h>
14#include <linux/percpu.h>
15#include <linux/gfp.h>
16#include <linux/pci.h>
17
18#include <asm/e820.h>
19#include <asm/processor.h>
20#include <asm/tlbflush.h>
21#include <asm/sections.h>
22#include <asm/setup.h>
23#include <asm/uaccess.h>
24#include <asm/pgalloc.h>
25#include <asm/proto.h>
26#include <asm/pat.h>
27
28/*
29 * The current flushing context - we pass it instead of 5 arguments:
30 */
31struct cpa_data {
32 unsigned long *vaddr;
33 pgprot_t mask_set;
34 pgprot_t mask_clr;
35 int numpages;
36 int flags;
37 unsigned long pfn;
38 unsigned force_split : 1;
39 int curpage;
40 struct page **pages;
41};
42
43/*
44 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
45 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
46 * entries change the page attribute in parallel to some other cpu
47 * splitting a large page entry along with changing the attribute.
48 */
49static DEFINE_SPINLOCK(cpa_lock);
50
51#define CPA_FLUSHTLB 1
52#define CPA_ARRAY 2
53#define CPA_PAGES_ARRAY 4
54
55#ifdef CONFIG_PROC_FS
56static unsigned long direct_pages_count[PG_LEVEL_NUM];
57
58void update_page_count(int level, unsigned long pages)
59{
60 /* Protect against CPA */
61 spin_lock(&pgd_lock);
62 direct_pages_count[level] += pages;
63 spin_unlock(&pgd_lock);
64}
65
66static void split_page_count(int level)
67{
68 direct_pages_count[level]--;
69 direct_pages_count[level - 1] += PTRS_PER_PTE;
70}
71
72void arch_report_meminfo(struct seq_file *m)
73{
74 seq_printf(m, "DirectMap4k: %8lu kB\n",
75 direct_pages_count[PG_LEVEL_4K] << 2);
76#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
77 seq_printf(m, "DirectMap2M: %8lu kB\n",
78 direct_pages_count[PG_LEVEL_2M] << 11);
79#else
80 seq_printf(m, "DirectMap4M: %8lu kB\n",
81 direct_pages_count[PG_LEVEL_2M] << 12);
82#endif
83#ifdef CONFIG_X86_64
84 if (direct_gbpages)
85 seq_printf(m, "DirectMap1G: %8lu kB\n",
86 direct_pages_count[PG_LEVEL_1G] << 20);
87#endif
88}
89#else
90static inline void split_page_count(int level) { }
91#endif
92
93#ifdef CONFIG_X86_64
94
95static inline unsigned long highmap_start_pfn(void)
96{
97 return __pa(_text) >> PAGE_SHIFT;
98}
99
100static inline unsigned long highmap_end_pfn(void)
101{
102 return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
103}
104
105#endif
106
107#ifdef CONFIG_DEBUG_PAGEALLOC
108# define debug_pagealloc 1
109#else
110# define debug_pagealloc 0
111#endif
112
113static inline int
114within(unsigned long addr, unsigned long start, unsigned long end)
115{
116 return addr >= start && addr < end;
117}
118
119/*
120 * Flushing functions
121 */
122
123/**
124 * clflush_cache_range - flush a cache range with clflush
125 * @addr: virtual start address
126 * @size: number of bytes to flush
127 *
128 * clflush is an unordered instruction which needs fencing with mfence
129 * to avoid ordering issues.
130 */
131void clflush_cache_range(void *vaddr, unsigned int size)
132{
133 void *vend = vaddr + size - 1;
134
135 mb();
136
137 for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
138 clflush(vaddr);
139 /*
140 * Flush any possible final partial cacheline:
141 */
142 clflush(vend);
143
144 mb();
145}
146EXPORT_SYMBOL_GPL(clflush_cache_range);
147
148static void __cpa_flush_all(void *arg)
149{
150 unsigned long cache = (unsigned long)arg;
151
152 /*
153 * Flush all to work around Errata in early athlons regarding
154 * large page flushing.
155 */
156 __flush_tlb_all();
157
158 if (cache && boot_cpu_data.x86 >= 4)
159 wbinvd();
160}
161
162static void cpa_flush_all(unsigned long cache)
163{
164 BUG_ON(irqs_disabled());
165
166 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
167}
168
169static void __cpa_flush_range(void *arg)
170{
171 /*
172 * We could optimize that further and do individual per page
173 * tlb invalidates for a low number of pages. Caveat: we must
174 * flush the high aliases on 64bit as well.
175 */
176 __flush_tlb_all();
177}
178
179static void cpa_flush_range(unsigned long start, int numpages, int cache)
180{
181 unsigned int i, level;
182 unsigned long addr;
183
184 BUG_ON(irqs_disabled());
185 WARN_ON(PAGE_ALIGN(start) != start);
186
187 on_each_cpu(__cpa_flush_range, NULL, 1);
188
189 if (!cache)
190 return;
191
192 /*
193 * We only need to flush on one CPU,
194 * clflush is a MESI-coherent instruction that
195 * will cause all other CPUs to flush the same
196 * cachelines:
197 */
198 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
199 pte_t *pte = lookup_address(addr, &level);
200
201 /*
202 * Only flush present addresses:
203 */
204 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
205 clflush_cache_range((void *) addr, PAGE_SIZE);
206 }
207}
208
209static void cpa_flush_array(unsigned long *start, int numpages, int cache,
210 int in_flags, struct page **pages)
211{
212 unsigned int i, level;
213 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
214
215 BUG_ON(irqs_disabled());
216
217 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
218
219 if (!cache || do_wbinvd)
220 return;
221
222 /*
223 * We only need to flush on one CPU,
224 * clflush is a MESI-coherent instruction that
225 * will cause all other CPUs to flush the same
226 * cachelines:
227 */
228 for (i = 0; i < numpages; i++) {
229 unsigned long addr;
230 pte_t *pte;
231
232 if (in_flags & CPA_PAGES_ARRAY)
233 addr = (unsigned long)page_address(pages[i]);
234 else
235 addr = start[i];
236
237 pte = lookup_address(addr, &level);
238
239 /*
240 * Only flush present addresses:
241 */
242 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
243 clflush_cache_range((void *)addr, PAGE_SIZE);
244 }
245}
246
247/*
248 * Certain areas of memory on x86 require very specific protection flags,
249 * for example the BIOS area or kernel text. Callers don't always get this
250 * right (again, ioremap() on BIOS memory is not uncommon) so this function
251 * checks and fixes these known static required protection bits.
252 */
253static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
254 unsigned long pfn)
255{
256 pgprot_t forbidden = __pgprot(0);
257
258 /*
259 * The BIOS area between 640k and 1Mb needs to be executable for
260 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
261 */
262#ifdef CONFIG_PCI_BIOS
263 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
264 pgprot_val(forbidden) |= _PAGE_NX;
265#endif
266
267 /*
268 * The kernel text needs to be executable for obvious reasons
269 * Does not cover __inittext since that is gone later on. On
270 * 64bit we do not enforce !NX on the low mapping
271 */
272 if (within(address, (unsigned long)_text, (unsigned long)_etext))
273 pgprot_val(forbidden) |= _PAGE_NX;
274
275 /*
276 * The .rodata section needs to be read-only. Using the pfn
277 * catches all aliases.
278 */
279 if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
280 __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
281 pgprot_val(forbidden) |= _PAGE_RW;
282
283#if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
284 /*
285 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
286 * kernel text mappings for the large page aligned text, rodata sections
287 * will be always read-only. For the kernel identity mappings covering
288 * the holes caused by this alignment can be anything that user asks.
289 *
290 * This will preserve the large page mappings for kernel text/data
291 * at no extra cost.
292 */
293 if (kernel_set_to_readonly &&
294 within(address, (unsigned long)_text,
295 (unsigned long)__end_rodata_hpage_align)) {
296 unsigned int level;
297
298 /*
299 * Don't enforce the !RW mapping for the kernel text mapping,
300 * if the current mapping is already using small page mapping.
301 * No need to work hard to preserve large page mappings in this
302 * case.
303 *
304 * This also fixes the Linux Xen paravirt guest boot failure
305 * (because of unexpected read-only mappings for kernel identity
306 * mappings). In this paravirt guest case, the kernel text
307 * mapping and the kernel identity mapping share the same
308 * page-table pages. Thus we can't really use different
309 * protections for the kernel text and identity mappings. Also,
310 * these shared mappings are made of small page mappings.
311 * Thus this don't enforce !RW mapping for small page kernel
312 * text mapping logic will help Linux Xen parvirt guest boot
313 * as well.
314 */
315 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
316 pgprot_val(forbidden) |= _PAGE_RW;
317 }
318#endif
319
320 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
321
322 return prot;
323}
324
325/*
326 * Lookup the page table entry for a virtual address. Return a pointer
327 * to the entry and the level of the mapping.
328 *
329 * Note: We return pud and pmd either when the entry is marked large
330 * or when the present bit is not set. Otherwise we would return a
331 * pointer to a nonexisting mapping.
332 */
333pte_t *lookup_address(unsigned long address, unsigned int *level)
334{
335 pgd_t *pgd = pgd_offset_k(address);
336 pud_t *pud;
337 pmd_t *pmd;
338
339 *level = PG_LEVEL_NONE;
340
341 if (pgd_none(*pgd))
342 return NULL;
343
344 pud = pud_offset(pgd, address);
345 if (pud_none(*pud))
346 return NULL;
347
348 *level = PG_LEVEL_1G;
349 if (pud_large(*pud) || !pud_present(*pud))
350 return (pte_t *)pud;
351
352 pmd = pmd_offset(pud, address);
353 if (pmd_none(*pmd))
354 return NULL;
355
356 *level = PG_LEVEL_2M;
357 if (pmd_large(*pmd) || !pmd_present(*pmd))
358 return (pte_t *)pmd;
359
360 *level = PG_LEVEL_4K;
361
362 return pte_offset_kernel(pmd, address);
363}
364EXPORT_SYMBOL_GPL(lookup_address);
365
366/*
367 * Set the new pmd in all the pgds we know about:
368 */
369static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
370{
371 /* change init_mm */
372 set_pte_atomic(kpte, pte);
373#ifdef CONFIG_X86_32
374 if (!SHARED_KERNEL_PMD) {
375 struct page *page;
376
377 list_for_each_entry(page, &pgd_list, lru) {
378 pgd_t *pgd;
379 pud_t *pud;
380 pmd_t *pmd;
381
382 pgd = (pgd_t *)page_address(page) + pgd_index(address);
383 pud = pud_offset(pgd, address);
384 pmd = pmd_offset(pud, address);
385 set_pte_atomic((pte_t *)pmd, pte);
386 }
387 }
388#endif
389}
390
391static int
392try_preserve_large_page(pte_t *kpte, unsigned long address,
393 struct cpa_data *cpa)
394{
395 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn;
396 pte_t new_pte, old_pte, *tmp;
397 pgprot_t old_prot, new_prot, req_prot;
398 int i, do_split = 1;
399 unsigned int level;
400
401 if (cpa->force_split)
402 return 1;
403
404 spin_lock(&pgd_lock);
405 /*
406 * Check for races, another CPU might have split this page
407 * up already:
408 */
409 tmp = lookup_address(address, &level);
410 if (tmp != kpte)
411 goto out_unlock;
412
413 switch (level) {
414 case PG_LEVEL_2M:
415 psize = PMD_PAGE_SIZE;
416 pmask = PMD_PAGE_MASK;
417 break;
418#ifdef CONFIG_X86_64
419 case PG_LEVEL_1G:
420 psize = PUD_PAGE_SIZE;
421 pmask = PUD_PAGE_MASK;
422 break;
423#endif
424 default:
425 do_split = -EINVAL;
426 goto out_unlock;
427 }
428
429 /*
430 * Calculate the number of pages, which fit into this large
431 * page starting at address:
432 */
433 nextpage_addr = (address + psize) & pmask;
434 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
435 if (numpages < cpa->numpages)
436 cpa->numpages = numpages;
437
438 /*
439 * We are safe now. Check whether the new pgprot is the same:
440 */
441 old_pte = *kpte;
442 old_prot = new_prot = req_prot = pte_pgprot(old_pte);
443
444 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
445 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
446
447 /*
448 * old_pte points to the large page base address. So we need
449 * to add the offset of the virtual address:
450 */
451 pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
452 cpa->pfn = pfn;
453
454 new_prot = static_protections(req_prot, address, pfn);
455
456 /*
457 * We need to check the full range, whether
458 * static_protection() requires a different pgprot for one of
459 * the pages in the range we try to preserve:
460 */
461 addr = address & pmask;
462 pfn = pte_pfn(old_pte);
463 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
464 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
465
466 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
467 goto out_unlock;
468 }
469
470 /*
471 * If there are no changes, return. maxpages has been updated
472 * above:
473 */
474 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
475 do_split = 0;
476 goto out_unlock;
477 }
478
479 /*
480 * We need to change the attributes. Check, whether we can
481 * change the large page in one go. We request a split, when
482 * the address is not aligned and the number of pages is
483 * smaller than the number of pages in the large page. Note
484 * that we limited the number of possible pages already to
485 * the number of pages in the large page.
486 */
487 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
488 /*
489 * The address is aligned and the number of pages
490 * covers the full page.
491 */
492 new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
493 __set_pmd_pte(kpte, address, new_pte);
494 cpa->flags |= CPA_FLUSHTLB;
495 do_split = 0;
496 }
497
498out_unlock:
499 spin_unlock(&pgd_lock);
500
501 return do_split;
502}
503
504static int split_large_page(pte_t *kpte, unsigned long address)
505{
506 unsigned long pfn, pfninc = 1;
507 unsigned int i, level;
508 pte_t *pbase, *tmp;
509 pgprot_t ref_prot;
510 struct page *base;
511
512 if (!debug_pagealloc)
513 spin_unlock(&cpa_lock);
514 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
515 if (!debug_pagealloc)
516 spin_lock(&cpa_lock);
517 if (!base)
518 return -ENOMEM;
519
520 spin_lock(&pgd_lock);
521 /*
522 * Check for races, another CPU might have split this page
523 * up for us already:
524 */
525 tmp = lookup_address(address, &level);
526 if (tmp != kpte)
527 goto out_unlock;
528
529 pbase = (pte_t *)page_address(base);
530 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
531 ref_prot = pte_pgprot(pte_clrhuge(*kpte));
532 /*
533 * If we ever want to utilize the PAT bit, we need to
534 * update this function to make sure it's converted from
535 * bit 12 to bit 7 when we cross from the 2MB level to
536 * the 4K level:
537 */
538 WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
539
540#ifdef CONFIG_X86_64
541 if (level == PG_LEVEL_1G) {
542 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
543 pgprot_val(ref_prot) |= _PAGE_PSE;
544 }
545#endif
546
547 /*
548 * Get the target pfn from the original entry:
549 */
550 pfn = pte_pfn(*kpte);
551 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
552 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
553
554 if (address >= (unsigned long)__va(0) &&
555 address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT))
556 split_page_count(level);
557
558#ifdef CONFIG_X86_64
559 if (address >= (unsigned long)__va(1UL<<32) &&
560 address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT))
561 split_page_count(level);
562#endif
563
564 /*
565 * Install the new, split up pagetable.
566 *
567 * We use the standard kernel pagetable protections for the new
568 * pagetable protections, the actual ptes set above control the
569 * primary protection behavior:
570 */
571 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
572
573 /*
574 * Intel Atom errata AAH41 workaround.
575 *
576 * The real fix should be in hw or in a microcode update, but
577 * we also probabilistically try to reduce the window of having
578 * a large TLB mixed with 4K TLBs while instruction fetches are
579 * going on.
580 */
581 __flush_tlb_all();
582
583 base = NULL;
584
585out_unlock:
586 /*
587 * If we dropped out via the lookup_address check under
588 * pgd_lock then stick the page back into the pool:
589 */
590 if (base)
591 __free_page(base);
592 spin_unlock(&pgd_lock);
593
594 return 0;
595}
596
597static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
598 int primary)
599{
600 /*
601 * Ignore all non primary paths.
602 */
603 if (!primary)
604 return 0;
605
606 /*
607 * Ignore the NULL PTE for kernel identity mapping, as it is expected
608 * to have holes.
609 * Also set numpages to '1' indicating that we processed cpa req for
610 * one virtual address page and its pfn. TBD: numpages can be set based
611 * on the initial value and the level returned by lookup_address().
612 */
613 if (within(vaddr, PAGE_OFFSET,
614 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
615 cpa->numpages = 1;
616 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
617 return 0;
618 } else {
619 WARN(1, KERN_WARNING "CPA: called for zero pte. "
620 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
621 *cpa->vaddr);
622
623 return -EFAULT;
624 }
625}
626
627static int __change_page_attr(struct cpa_data *cpa, int primary)
628{
629 unsigned long address;
630 int do_split, err;
631 unsigned int level;
632 pte_t *kpte, old_pte;
633
634 if (cpa->flags & CPA_PAGES_ARRAY) {
635 struct page *page = cpa->pages[cpa->curpage];
636 if (unlikely(PageHighMem(page)))
637 return 0;
638 address = (unsigned long)page_address(page);
639 } else if (cpa->flags & CPA_ARRAY)
640 address = cpa->vaddr[cpa->curpage];
641 else
642 address = *cpa->vaddr;
643repeat:
644 kpte = lookup_address(address, &level);
645 if (!kpte)
646 return __cpa_process_fault(cpa, address, primary);
647
648 old_pte = *kpte;
649 if (!pte_val(old_pte))
650 return __cpa_process_fault(cpa, address, primary);
651
652 if (level == PG_LEVEL_4K) {
653 pte_t new_pte;
654 pgprot_t new_prot = pte_pgprot(old_pte);
655 unsigned long pfn = pte_pfn(old_pte);
656
657 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
658 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
659
660 new_prot = static_protections(new_prot, address, pfn);
661
662 /*
663 * We need to keep the pfn from the existing PTE,
664 * after all we're only going to change it's attributes
665 * not the memory it points to
666 */
667 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
668 cpa->pfn = pfn;
669 /*
670 * Do we really change anything ?
671 */
672 if (pte_val(old_pte) != pte_val(new_pte)) {
673 set_pte_atomic(kpte, new_pte);
674 cpa->flags |= CPA_FLUSHTLB;
675 }
676 cpa->numpages = 1;
677 return 0;
678 }
679
680 /*
681 * Check, whether we can keep the large page intact
682 * and just change the pte:
683 */
684 do_split = try_preserve_large_page(kpte, address, cpa);
685 /*
686 * When the range fits into the existing large page,
687 * return. cp->numpages and cpa->tlbflush have been updated in
688 * try_large_page:
689 */
690 if (do_split <= 0)
691 return do_split;
692
693 /*
694 * We have to split the large page:
695 */
696 err = split_large_page(kpte, address);
697 if (!err) {
698 /*
699 * Do a global flush tlb after splitting the large page
700 * and before we do the actual change page attribute in the PTE.
701 *
702 * With out this, we violate the TLB application note, that says
703 * "The TLBs may contain both ordinary and large-page
704 * translations for a 4-KByte range of linear addresses. This
705 * may occur if software modifies the paging structures so that
706 * the page size used for the address range changes. If the two
707 * translations differ with respect to page frame or attributes
708 * (e.g., permissions), processor behavior is undefined and may
709 * be implementation-specific."
710 *
711 * We do this global tlb flush inside the cpa_lock, so that we
712 * don't allow any other cpu, with stale tlb entries change the
713 * page attribute in parallel, that also falls into the
714 * just split large page entry.
715 */
716 flush_tlb_all();
717 goto repeat;
718 }
719
720 return err;
721}
722
723static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
724
725static int cpa_process_alias(struct cpa_data *cpa)
726{
727 struct cpa_data alias_cpa;
728 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
729 unsigned long vaddr;
730 int ret;
731
732 if (cpa->pfn >= max_pfn_mapped)
733 return 0;
734
735#ifdef CONFIG_X86_64
736 if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT)))
737 return 0;
738#endif
739 /*
740 * No need to redo, when the primary call touched the direct
741 * mapping already:
742 */
743 if (cpa->flags & CPA_PAGES_ARRAY) {
744 struct page *page = cpa->pages[cpa->curpage];
745 if (unlikely(PageHighMem(page)))
746 return 0;
747 vaddr = (unsigned long)page_address(page);
748 } else if (cpa->flags & CPA_ARRAY)
749 vaddr = cpa->vaddr[cpa->curpage];
750 else
751 vaddr = *cpa->vaddr;
752
753 if (!(within(vaddr, PAGE_OFFSET,
754 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
755
756 alias_cpa = *cpa;
757 alias_cpa.vaddr = &laddr;
758 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
759
760 ret = __change_page_attr_set_clr(&alias_cpa, 0);
761 if (ret)
762 return ret;
763 }
764
765#ifdef CONFIG_X86_64
766 /*
767 * If the primary call didn't touch the high mapping already
768 * and the physical address is inside the kernel map, we need
769 * to touch the high mapped kernel as well:
770 */
771 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
772 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
773 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
774 __START_KERNEL_map - phys_base;
775 alias_cpa = *cpa;
776 alias_cpa.vaddr = &temp_cpa_vaddr;
777 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
778
779 /*
780 * The high mapping range is imprecise, so ignore the
781 * return value.
782 */
783 __change_page_attr_set_clr(&alias_cpa, 0);
784 }
785#endif
786
787 return 0;
788}
789
790static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
791{
792 int ret, numpages = cpa->numpages;
793
794 while (numpages) {
795 /*
796 * Store the remaining nr of pages for the large page
797 * preservation check.
798 */
799 cpa->numpages = numpages;
800 /* for array changes, we can't use large page */
801 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
802 cpa->numpages = 1;
803
804 if (!debug_pagealloc)
805 spin_lock(&cpa_lock);
806 ret = __change_page_attr(cpa, checkalias);
807 if (!debug_pagealloc)
808 spin_unlock(&cpa_lock);
809 if (ret)
810 return ret;
811
812 if (checkalias) {
813 ret = cpa_process_alias(cpa);
814 if (ret)
815 return ret;
816 }
817
818 /*
819 * Adjust the number of pages with the result of the
820 * CPA operation. Either a large page has been
821 * preserved or a single page update happened.
822 */
823 BUG_ON(cpa->numpages > numpages);
824 numpages -= cpa->numpages;
825 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
826 cpa->curpage++;
827 else
828 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
829
830 }
831 return 0;
832}
833
834static inline int cache_attr(pgprot_t attr)
835{
836 return pgprot_val(attr) &
837 (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
838}
839
840static int change_page_attr_set_clr(unsigned long *addr, int numpages,
841 pgprot_t mask_set, pgprot_t mask_clr,
842 int force_split, int in_flag,
843 struct page **pages)
844{
845 struct cpa_data cpa;
846 int ret, cache, checkalias;
847 unsigned long baddr = 0;
848
849 /*
850 * Check, if we are requested to change a not supported
851 * feature:
852 */
853 mask_set = canon_pgprot(mask_set);
854 mask_clr = canon_pgprot(mask_clr);
855 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
856 return 0;
857
858 /* Ensure we are PAGE_SIZE aligned */
859 if (in_flag & CPA_ARRAY) {
860 int i;
861 for (i = 0; i < numpages; i++) {
862 if (addr[i] & ~PAGE_MASK) {
863 addr[i] &= PAGE_MASK;
864 WARN_ON_ONCE(1);
865 }
866 }
867 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
868 /*
869 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
870 * No need to cehck in that case
871 */
872 if (*addr & ~PAGE_MASK) {
873 *addr &= PAGE_MASK;
874 /*
875 * People should not be passing in unaligned addresses:
876 */
877 WARN_ON_ONCE(1);
878 }
879 /*
880 * Save address for cache flush. *addr is modified in the call
881 * to __change_page_attr_set_clr() below.
882 */
883 baddr = *addr;
884 }
885
886 /* Must avoid aliasing mappings in the highmem code */
887 kmap_flush_unused();
888
889 vm_unmap_aliases();
890
891 cpa.vaddr = addr;
892 cpa.pages = pages;
893 cpa.numpages = numpages;
894 cpa.mask_set = mask_set;
895 cpa.mask_clr = mask_clr;
896 cpa.flags = 0;
897 cpa.curpage = 0;
898 cpa.force_split = force_split;
899
900 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
901 cpa.flags |= in_flag;
902
903 /* No alias checking for _NX bit modifications */
904 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
905
906 ret = __change_page_attr_set_clr(&cpa, checkalias);
907
908 /*
909 * Check whether we really changed something:
910 */
911 if (!(cpa.flags & CPA_FLUSHTLB))
912 goto out;
913
914 /*
915 * No need to flush, when we did not set any of the caching
916 * attributes:
917 */
918 cache = cache_attr(mask_set);
919
920 /*
921 * On success we use clflush, when the CPU supports it to
922 * avoid the wbindv. If the CPU does not support it and in the
923 * error case we fall back to cpa_flush_all (which uses
924 * wbindv):
925 */
926 if (!ret && cpu_has_clflush) {
927 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
928 cpa_flush_array(addr, numpages, cache,
929 cpa.flags, pages);
930 } else
931 cpa_flush_range(baddr, numpages, cache);
932 } else
933 cpa_flush_all(cache);
934
935out:
936 return ret;
937}
938
939static inline int change_page_attr_set(unsigned long *addr, int numpages,
940 pgprot_t mask, int array)
941{
942 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
943 (array ? CPA_ARRAY : 0), NULL);
944}
945
946static inline int change_page_attr_clear(unsigned long *addr, int numpages,
947 pgprot_t mask, int array)
948{
949 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
950 (array ? CPA_ARRAY : 0), NULL);
951}
952
953static inline int cpa_set_pages_array(struct page **pages, int numpages,
954 pgprot_t mask)
955{
956 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
957 CPA_PAGES_ARRAY, pages);
958}
959
960static inline int cpa_clear_pages_array(struct page **pages, int numpages,
961 pgprot_t mask)
962{
963 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
964 CPA_PAGES_ARRAY, pages);
965}
966
967int _set_memory_uc(unsigned long addr, int numpages)
968{
969 /*
970 * for now UC MINUS. see comments in ioremap_nocache()
971 */
972 return change_page_attr_set(&addr, numpages,
973 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
974}
975
976int set_memory_uc(unsigned long addr, int numpages)
977{
978 int ret;
979
980 /*
981 * for now UC MINUS. see comments in ioremap_nocache()
982 */
983 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
984 _PAGE_CACHE_UC_MINUS, NULL);
985 if (ret)
986 goto out_err;
987
988 ret = _set_memory_uc(addr, numpages);
989 if (ret)
990 goto out_free;
991
992 return 0;
993
994out_free:
995 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
996out_err:
997 return ret;
998}
999EXPORT_SYMBOL(set_memory_uc);
1000
1001int _set_memory_array(unsigned long *addr, int addrinarray,
1002 unsigned long new_type)
1003{
1004 int i, j;
1005 int ret;
1006
1007 /*
1008 * for now UC MINUS. see comments in ioremap_nocache()
1009 */
1010 for (i = 0; i < addrinarray; i++) {
1011 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1012 new_type, NULL);
1013 if (ret)
1014 goto out_free;
1015 }
1016
1017 ret = change_page_attr_set(addr, addrinarray,
1018 __pgprot(_PAGE_CACHE_UC_MINUS), 1);
1019
1020 if (!ret && new_type == _PAGE_CACHE_WC)
1021 ret = change_page_attr_set_clr(addr, addrinarray,
1022 __pgprot(_PAGE_CACHE_WC),
1023 __pgprot(_PAGE_CACHE_MASK),
1024 0, CPA_ARRAY, NULL);
1025 if (ret)
1026 goto out_free;
1027
1028 return 0;
1029
1030out_free:
1031 for (j = 0; j < i; j++)
1032 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1033
1034 return ret;
1035}
1036
1037int set_memory_array_uc(unsigned long *addr, int addrinarray)
1038{
1039 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS);
1040}
1041EXPORT_SYMBOL(set_memory_array_uc);
1042
1043int set_memory_array_wc(unsigned long *addr, int addrinarray)
1044{
1045 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC);
1046}
1047EXPORT_SYMBOL(set_memory_array_wc);
1048
1049int _set_memory_wc(unsigned long addr, int numpages)
1050{
1051 int ret;
1052 unsigned long addr_copy = addr;
1053
1054 ret = change_page_attr_set(&addr, numpages,
1055 __pgprot(_PAGE_CACHE_UC_MINUS), 0);
1056 if (!ret) {
1057 ret = change_page_attr_set_clr(&addr_copy, numpages,
1058 __pgprot(_PAGE_CACHE_WC),
1059 __pgprot(_PAGE_CACHE_MASK),
1060 0, 0, NULL);
1061 }
1062 return ret;
1063}
1064
1065int set_memory_wc(unsigned long addr, int numpages)
1066{
1067 int ret;
1068
1069 if (!pat_enabled)
1070 return set_memory_uc(addr, numpages);
1071
1072 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1073 _PAGE_CACHE_WC, NULL);
1074 if (ret)
1075 goto out_err;
1076
1077 ret = _set_memory_wc(addr, numpages);
1078 if (ret)
1079 goto out_free;
1080
1081 return 0;
1082
1083out_free:
1084 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1085out_err:
1086 return ret;
1087}
1088EXPORT_SYMBOL(set_memory_wc);
1089
1090int _set_memory_wb(unsigned long addr, int numpages)
1091{
1092 return change_page_attr_clear(&addr, numpages,
1093 __pgprot(_PAGE_CACHE_MASK), 0);
1094}
1095
1096int set_memory_wb(unsigned long addr, int numpages)
1097{
1098 int ret;
1099
1100 ret = _set_memory_wb(addr, numpages);
1101 if (ret)
1102 return ret;
1103
1104 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1105 return 0;
1106}
1107EXPORT_SYMBOL(set_memory_wb);
1108
1109int set_memory_array_wb(unsigned long *addr, int addrinarray)
1110{
1111 int i;
1112 int ret;
1113
1114 ret = change_page_attr_clear(addr, addrinarray,
1115 __pgprot(_PAGE_CACHE_MASK), 1);
1116 if (ret)
1117 return ret;
1118
1119 for (i = 0; i < addrinarray; i++)
1120 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1121
1122 return 0;
1123}
1124EXPORT_SYMBOL(set_memory_array_wb);
1125
1126int set_memory_x(unsigned long addr, int numpages)
1127{
1128 if (!(__supported_pte_mask & _PAGE_NX))
1129 return 0;
1130
1131 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1132}
1133EXPORT_SYMBOL(set_memory_x);
1134
1135int set_memory_nx(unsigned long addr, int numpages)
1136{
1137 if (!(__supported_pte_mask & _PAGE_NX))
1138 return 0;
1139
1140 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1141}
1142EXPORT_SYMBOL(set_memory_nx);
1143
1144int set_memory_ro(unsigned long addr, int numpages)
1145{
1146 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1147}
1148EXPORT_SYMBOL_GPL(set_memory_ro);
1149
1150int set_memory_rw(unsigned long addr, int numpages)
1151{
1152 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1153}
1154EXPORT_SYMBOL_GPL(set_memory_rw);
1155
1156int set_memory_np(unsigned long addr, int numpages)
1157{
1158 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1159}
1160
1161int set_memory_4k(unsigned long addr, int numpages)
1162{
1163 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1164 __pgprot(0), 1, 0, NULL);
1165}
1166
1167int set_pages_uc(struct page *page, int numpages)
1168{
1169 unsigned long addr = (unsigned long)page_address(page);
1170
1171 return set_memory_uc(addr, numpages);
1172}
1173EXPORT_SYMBOL(set_pages_uc);
1174
1175static int _set_pages_array(struct page **pages, int addrinarray,
1176 unsigned long new_type)
1177{
1178 unsigned long start;
1179 unsigned long end;
1180 int i;
1181 int free_idx;
1182 int ret;
1183
1184 for (i = 0; i < addrinarray; i++) {
1185 if (PageHighMem(pages[i]))
1186 continue;
1187 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1188 end = start + PAGE_SIZE;
1189 if (reserve_memtype(start, end, new_type, NULL))
1190 goto err_out;
1191 }
1192
1193 ret = cpa_set_pages_array(pages, addrinarray,
1194 __pgprot(_PAGE_CACHE_UC_MINUS));
1195 if (!ret && new_type == _PAGE_CACHE_WC)
1196 ret = change_page_attr_set_clr(NULL, addrinarray,
1197 __pgprot(_PAGE_CACHE_WC),
1198 __pgprot(_PAGE_CACHE_MASK),
1199 0, CPA_PAGES_ARRAY, pages);
1200 if (ret)
1201 goto err_out;
1202 return 0; /* Success */
1203err_out:
1204 free_idx = i;
1205 for (i = 0; i < free_idx; i++) {
1206 if (PageHighMem(pages[i]))
1207 continue;
1208 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1209 end = start + PAGE_SIZE;
1210 free_memtype(start, end);
1211 }
1212 return -EINVAL;
1213}
1214
1215int set_pages_array_uc(struct page **pages, int addrinarray)
1216{
1217 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS);
1218}
1219EXPORT_SYMBOL(set_pages_array_uc);
1220
1221int set_pages_array_wc(struct page **pages, int addrinarray)
1222{
1223 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC);
1224}
1225EXPORT_SYMBOL(set_pages_array_wc);
1226
1227int set_pages_wb(struct page *page, int numpages)
1228{
1229 unsigned long addr = (unsigned long)page_address(page);
1230
1231 return set_memory_wb(addr, numpages);
1232}
1233EXPORT_SYMBOL(set_pages_wb);
1234
1235int set_pages_array_wb(struct page **pages, int addrinarray)
1236{
1237 int retval;
1238 unsigned long start;
1239 unsigned long end;
1240 int i;
1241
1242 retval = cpa_clear_pages_array(pages, addrinarray,
1243 __pgprot(_PAGE_CACHE_MASK));
1244 if (retval)
1245 return retval;
1246
1247 for (i = 0; i < addrinarray; i++) {
1248 if (PageHighMem(pages[i]))
1249 continue;
1250 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1251 end = start + PAGE_SIZE;
1252 free_memtype(start, end);
1253 }
1254
1255 return 0;
1256}
1257EXPORT_SYMBOL(set_pages_array_wb);
1258
1259int set_pages_x(struct page *page, int numpages)
1260{
1261 unsigned long addr = (unsigned long)page_address(page);
1262
1263 return set_memory_x(addr, numpages);
1264}
1265EXPORT_SYMBOL(set_pages_x);
1266
1267int set_pages_nx(struct page *page, int numpages)
1268{
1269 unsigned long addr = (unsigned long)page_address(page);
1270
1271 return set_memory_nx(addr, numpages);
1272}
1273EXPORT_SYMBOL(set_pages_nx);
1274
1275int set_pages_ro(struct page *page, int numpages)
1276{
1277 unsigned long addr = (unsigned long)page_address(page);
1278
1279 return set_memory_ro(addr, numpages);
1280}
1281
1282int set_pages_rw(struct page *page, int numpages)
1283{
1284 unsigned long addr = (unsigned long)page_address(page);
1285
1286 return set_memory_rw(addr, numpages);
1287}
1288
1289#ifdef CONFIG_DEBUG_PAGEALLOC
1290
1291static int __set_pages_p(struct page *page, int numpages)
1292{
1293 unsigned long tempaddr = (unsigned long) page_address(page);
1294 struct cpa_data cpa = { .vaddr = &tempaddr,
1295 .numpages = numpages,
1296 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1297 .mask_clr = __pgprot(0),
1298 .flags = 0};
1299
1300 /*
1301 * No alias checking needed for setting present flag. otherwise,
1302 * we may need to break large pages for 64-bit kernel text
1303 * mappings (this adds to complexity if we want to do this from
1304 * atomic context especially). Let's keep it simple!
1305 */
1306 return __change_page_attr_set_clr(&cpa, 0);
1307}
1308
1309static int __set_pages_np(struct page *page, int numpages)
1310{
1311 unsigned long tempaddr = (unsigned long) page_address(page);
1312 struct cpa_data cpa = { .vaddr = &tempaddr,
1313 .numpages = numpages,
1314 .mask_set = __pgprot(0),
1315 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1316 .flags = 0};
1317
1318 /*
1319 * No alias checking needed for setting not present flag. otherwise,
1320 * we may need to break large pages for 64-bit kernel text
1321 * mappings (this adds to complexity if we want to do this from
1322 * atomic context especially). Let's keep it simple!
1323 */
1324 return __change_page_attr_set_clr(&cpa, 0);
1325}
1326
1327void kernel_map_pages(struct page *page, int numpages, int enable)
1328{
1329 if (PageHighMem(page))
1330 return;
1331 if (!enable) {
1332 debug_check_no_locks_freed(page_address(page),
1333 numpages * PAGE_SIZE);
1334 }
1335
1336 /*
1337 * If page allocator is not up yet then do not call c_p_a():
1338 */
1339 if (!debug_pagealloc_enabled)
1340 return;
1341
1342 /*
1343 * The return value is ignored as the calls cannot fail.
1344 * Large pages for identity mappings are not used at boot time
1345 * and hence no memory allocations during large page split.
1346 */
1347 if (enable)
1348 __set_pages_p(page, numpages);
1349 else
1350 __set_pages_np(page, numpages);
1351
1352 /*
1353 * We should perform an IPI and flush all tlbs,
1354 * but that can deadlock->flush only current cpu:
1355 */
1356 __flush_tlb_all();
1357}
1358
1359#ifdef CONFIG_HIBERNATION
1360
1361bool kernel_page_present(struct page *page)
1362{
1363 unsigned int level;
1364 pte_t *pte;
1365
1366 if (PageHighMem(page))
1367 return false;
1368
1369 pte = lookup_address((unsigned long)page_address(page), &level);
1370 return (pte_val(*pte) & _PAGE_PRESENT);
1371}
1372
1373#endif /* CONFIG_HIBERNATION */
1374
1375#endif /* CONFIG_DEBUG_PAGEALLOC */
1376
1377/*
1378 * The testcases use internal knowledge of the implementation that shouldn't
1379 * be exposed to the rest of the kernel. Include these directly here.
1380 */
1381#ifdef CONFIG_CPA_DEBUG
1382#include "pageattr-test.c"
1383#endif
1/*
2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
4 */
5#include <linux/highmem.h>
6#include <linux/bootmem.h>
7#include <linux/sched.h>
8#include <linux/mm.h>
9#include <linux/interrupt.h>
10#include <linux/seq_file.h>
11#include <linux/debugfs.h>
12#include <linux/pfn.h>
13#include <linux/percpu.h>
14#include <linux/gfp.h>
15#include <linux/pci.h>
16#include <linux/vmalloc.h>
17
18#include <asm/e820/api.h>
19#include <asm/processor.h>
20#include <asm/tlbflush.h>
21#include <asm/sections.h>
22#include <asm/setup.h>
23#include <linux/uaccess.h>
24#include <asm/pgalloc.h>
25#include <asm/proto.h>
26#include <asm/pat.h>
27#include <asm/set_memory.h>
28
29/*
30 * The current flushing context - we pass it instead of 5 arguments:
31 */
32struct cpa_data {
33 unsigned long *vaddr;
34 pgd_t *pgd;
35 pgprot_t mask_set;
36 pgprot_t mask_clr;
37 unsigned long numpages;
38 int flags;
39 unsigned long pfn;
40 unsigned force_split : 1;
41 int curpage;
42 struct page **pages;
43};
44
45/*
46 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
47 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
48 * entries change the page attribute in parallel to some other cpu
49 * splitting a large page entry along with changing the attribute.
50 */
51static DEFINE_SPINLOCK(cpa_lock);
52
53#define CPA_FLUSHTLB 1
54#define CPA_ARRAY 2
55#define CPA_PAGES_ARRAY 4
56
57#ifdef CONFIG_PROC_FS
58static unsigned long direct_pages_count[PG_LEVEL_NUM];
59
60void update_page_count(int level, unsigned long pages)
61{
62 /* Protect against CPA */
63 spin_lock(&pgd_lock);
64 direct_pages_count[level] += pages;
65 spin_unlock(&pgd_lock);
66}
67
68static void split_page_count(int level)
69{
70 if (direct_pages_count[level] == 0)
71 return;
72
73 direct_pages_count[level]--;
74 direct_pages_count[level - 1] += PTRS_PER_PTE;
75}
76
77void arch_report_meminfo(struct seq_file *m)
78{
79 seq_printf(m, "DirectMap4k: %8lu kB\n",
80 direct_pages_count[PG_LEVEL_4K] << 2);
81#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
82 seq_printf(m, "DirectMap2M: %8lu kB\n",
83 direct_pages_count[PG_LEVEL_2M] << 11);
84#else
85 seq_printf(m, "DirectMap4M: %8lu kB\n",
86 direct_pages_count[PG_LEVEL_2M] << 12);
87#endif
88 if (direct_gbpages)
89 seq_printf(m, "DirectMap1G: %8lu kB\n",
90 direct_pages_count[PG_LEVEL_1G] << 20);
91}
92#else
93static inline void split_page_count(int level) { }
94#endif
95
96static inline int
97within(unsigned long addr, unsigned long start, unsigned long end)
98{
99 return addr >= start && addr < end;
100}
101
102static inline int
103within_inclusive(unsigned long addr, unsigned long start, unsigned long end)
104{
105 return addr >= start && addr <= end;
106}
107
108#ifdef CONFIG_X86_64
109
110static inline unsigned long highmap_start_pfn(void)
111{
112 return __pa_symbol(_text) >> PAGE_SHIFT;
113}
114
115static inline unsigned long highmap_end_pfn(void)
116{
117 /* Do not reference physical address outside the kernel. */
118 return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT;
119}
120
121static bool __cpa_pfn_in_highmap(unsigned long pfn)
122{
123 /*
124 * Kernel text has an alias mapping at a high address, known
125 * here as "highmap".
126 */
127 return within_inclusive(pfn, highmap_start_pfn(), highmap_end_pfn());
128}
129
130#else
131
132static bool __cpa_pfn_in_highmap(unsigned long pfn)
133{
134 /* There is no highmap on 32-bit */
135 return false;
136}
137
138#endif
139
140/*
141 * Flushing functions
142 */
143
144/**
145 * clflush_cache_range - flush a cache range with clflush
146 * @vaddr: virtual start address
147 * @size: number of bytes to flush
148 *
149 * clflushopt is an unordered instruction which needs fencing with mfence or
150 * sfence to avoid ordering issues.
151 */
152void clflush_cache_range(void *vaddr, unsigned int size)
153{
154 const unsigned long clflush_size = boot_cpu_data.x86_clflush_size;
155 void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1));
156 void *vend = vaddr + size;
157
158 if (p >= vend)
159 return;
160
161 mb();
162
163 for (; p < vend; p += clflush_size)
164 clflushopt(p);
165
166 mb();
167}
168EXPORT_SYMBOL_GPL(clflush_cache_range);
169
170void arch_invalidate_pmem(void *addr, size_t size)
171{
172 clflush_cache_range(addr, size);
173}
174EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
175
176static void __cpa_flush_all(void *arg)
177{
178 unsigned long cache = (unsigned long)arg;
179
180 /*
181 * Flush all to work around Errata in early athlons regarding
182 * large page flushing.
183 */
184 __flush_tlb_all();
185
186 if (cache && boot_cpu_data.x86 >= 4)
187 wbinvd();
188}
189
190static void cpa_flush_all(unsigned long cache)
191{
192 BUG_ON(irqs_disabled() && !early_boot_irqs_disabled);
193
194 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
195}
196
197static void __cpa_flush_range(void *arg)
198{
199 /*
200 * We could optimize that further and do individual per page
201 * tlb invalidates for a low number of pages. Caveat: we must
202 * flush the high aliases on 64bit as well.
203 */
204 __flush_tlb_all();
205}
206
207static void cpa_flush_range(unsigned long start, int numpages, int cache)
208{
209 unsigned int i, level;
210 unsigned long addr;
211
212 BUG_ON(irqs_disabled() && !early_boot_irqs_disabled);
213 WARN_ON(PAGE_ALIGN(start) != start);
214
215 on_each_cpu(__cpa_flush_range, NULL, 1);
216
217 if (!cache)
218 return;
219
220 /*
221 * We only need to flush on one CPU,
222 * clflush is a MESI-coherent instruction that
223 * will cause all other CPUs to flush the same
224 * cachelines:
225 */
226 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
227 pte_t *pte = lookup_address(addr, &level);
228
229 /*
230 * Only flush present addresses:
231 */
232 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
233 clflush_cache_range((void *) addr, PAGE_SIZE);
234 }
235}
236
237static void cpa_flush_array(unsigned long *start, int numpages, int cache,
238 int in_flags, struct page **pages)
239{
240 unsigned int i, level;
241#ifdef CONFIG_PREEMPT
242 /*
243 * Avoid wbinvd() because it causes latencies on all CPUs,
244 * regardless of any CPU isolation that may be in effect.
245 *
246 * This should be extended for CAT enabled systems independent of
247 * PREEMPT because wbinvd() does not respect the CAT partitions and
248 * this is exposed to unpriviledged users through the graphics
249 * subsystem.
250 */
251 unsigned long do_wbinvd = 0;
252#else
253 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
254#endif
255
256 BUG_ON(irqs_disabled() && !early_boot_irqs_disabled);
257
258 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
259
260 if (!cache || do_wbinvd)
261 return;
262
263 /*
264 * We only need to flush on one CPU,
265 * clflush is a MESI-coherent instruction that
266 * will cause all other CPUs to flush the same
267 * cachelines:
268 */
269 for (i = 0; i < numpages; i++) {
270 unsigned long addr;
271 pte_t *pte;
272
273 if (in_flags & CPA_PAGES_ARRAY)
274 addr = (unsigned long)page_address(pages[i]);
275 else
276 addr = start[i];
277
278 pte = lookup_address(addr, &level);
279
280 /*
281 * Only flush present addresses:
282 */
283 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
284 clflush_cache_range((void *)addr, PAGE_SIZE);
285 }
286}
287
288/*
289 * Certain areas of memory on x86 require very specific protection flags,
290 * for example the BIOS area or kernel text. Callers don't always get this
291 * right (again, ioremap() on BIOS memory is not uncommon) so this function
292 * checks and fixes these known static required protection bits.
293 */
294static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
295 unsigned long pfn)
296{
297 pgprot_t forbidden = __pgprot(0);
298
299 /*
300 * The BIOS area between 640k and 1Mb needs to be executable for
301 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
302 */
303#ifdef CONFIG_PCI_BIOS
304 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
305 pgprot_val(forbidden) |= _PAGE_NX;
306#endif
307
308 /*
309 * The kernel text needs to be executable for obvious reasons
310 * Does not cover __inittext since that is gone later on. On
311 * 64bit we do not enforce !NX on the low mapping
312 */
313 if (within(address, (unsigned long)_text, (unsigned long)_etext))
314 pgprot_val(forbidden) |= _PAGE_NX;
315
316 /*
317 * The .rodata section needs to be read-only. Using the pfn
318 * catches all aliases. This also includes __ro_after_init,
319 * so do not enforce until kernel_set_to_readonly is true.
320 */
321 if (kernel_set_to_readonly &&
322 within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
323 __pa_symbol(__end_rodata) >> PAGE_SHIFT))
324 pgprot_val(forbidden) |= _PAGE_RW;
325
326#if defined(CONFIG_X86_64)
327 /*
328 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
329 * kernel text mappings for the large page aligned text, rodata sections
330 * will be always read-only. For the kernel identity mappings covering
331 * the holes caused by this alignment can be anything that user asks.
332 *
333 * This will preserve the large page mappings for kernel text/data
334 * at no extra cost.
335 */
336 if (kernel_set_to_readonly &&
337 within(address, (unsigned long)_text,
338 (unsigned long)__end_rodata_hpage_align)) {
339 unsigned int level;
340
341 /*
342 * Don't enforce the !RW mapping for the kernel text mapping,
343 * if the current mapping is already using small page mapping.
344 * No need to work hard to preserve large page mappings in this
345 * case.
346 *
347 * This also fixes the Linux Xen paravirt guest boot failure
348 * (because of unexpected read-only mappings for kernel identity
349 * mappings). In this paravirt guest case, the kernel text
350 * mapping and the kernel identity mapping share the same
351 * page-table pages. Thus we can't really use different
352 * protections for the kernel text and identity mappings. Also,
353 * these shared mappings are made of small page mappings.
354 * Thus this don't enforce !RW mapping for small page kernel
355 * text mapping logic will help Linux Xen parvirt guest boot
356 * as well.
357 */
358 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
359 pgprot_val(forbidden) |= _PAGE_RW;
360 }
361#endif
362
363 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
364
365 return prot;
366}
367
368/*
369 * Lookup the page table entry for a virtual address in a specific pgd.
370 * Return a pointer to the entry and the level of the mapping.
371 */
372pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
373 unsigned int *level)
374{
375 p4d_t *p4d;
376 pud_t *pud;
377 pmd_t *pmd;
378
379 *level = PG_LEVEL_NONE;
380
381 if (pgd_none(*pgd))
382 return NULL;
383
384 p4d = p4d_offset(pgd, address);
385 if (p4d_none(*p4d))
386 return NULL;
387
388 *level = PG_LEVEL_512G;
389 if (p4d_large(*p4d) || !p4d_present(*p4d))
390 return (pte_t *)p4d;
391
392 pud = pud_offset(p4d, address);
393 if (pud_none(*pud))
394 return NULL;
395
396 *level = PG_LEVEL_1G;
397 if (pud_large(*pud) || !pud_present(*pud))
398 return (pte_t *)pud;
399
400 pmd = pmd_offset(pud, address);
401 if (pmd_none(*pmd))
402 return NULL;
403
404 *level = PG_LEVEL_2M;
405 if (pmd_large(*pmd) || !pmd_present(*pmd))
406 return (pte_t *)pmd;
407
408 *level = PG_LEVEL_4K;
409
410 return pte_offset_kernel(pmd, address);
411}
412
413/*
414 * Lookup the page table entry for a virtual address. Return a pointer
415 * to the entry and the level of the mapping.
416 *
417 * Note: We return pud and pmd either when the entry is marked large
418 * or when the present bit is not set. Otherwise we would return a
419 * pointer to a nonexisting mapping.
420 */
421pte_t *lookup_address(unsigned long address, unsigned int *level)
422{
423 return lookup_address_in_pgd(pgd_offset_k(address), address, level);
424}
425EXPORT_SYMBOL_GPL(lookup_address);
426
427static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address,
428 unsigned int *level)
429{
430 if (cpa->pgd)
431 return lookup_address_in_pgd(cpa->pgd + pgd_index(address),
432 address, level);
433
434 return lookup_address(address, level);
435}
436
437/*
438 * Lookup the PMD entry for a virtual address. Return a pointer to the entry
439 * or NULL if not present.
440 */
441pmd_t *lookup_pmd_address(unsigned long address)
442{
443 pgd_t *pgd;
444 p4d_t *p4d;
445 pud_t *pud;
446
447 pgd = pgd_offset_k(address);
448 if (pgd_none(*pgd))
449 return NULL;
450
451 p4d = p4d_offset(pgd, address);
452 if (p4d_none(*p4d) || p4d_large(*p4d) || !p4d_present(*p4d))
453 return NULL;
454
455 pud = pud_offset(p4d, address);
456 if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud))
457 return NULL;
458
459 return pmd_offset(pud, address);
460}
461
462/*
463 * This is necessary because __pa() does not work on some
464 * kinds of memory, like vmalloc() or the alloc_remap()
465 * areas on 32-bit NUMA systems. The percpu areas can
466 * end up in this kind of memory, for instance.
467 *
468 * This could be optimized, but it is only intended to be
469 * used at inititalization time, and keeping it
470 * unoptimized should increase the testing coverage for
471 * the more obscure platforms.
472 */
473phys_addr_t slow_virt_to_phys(void *__virt_addr)
474{
475 unsigned long virt_addr = (unsigned long)__virt_addr;
476 phys_addr_t phys_addr;
477 unsigned long offset;
478 enum pg_level level;
479 pte_t *pte;
480
481 pte = lookup_address(virt_addr, &level);
482 BUG_ON(!pte);
483
484 /*
485 * pXX_pfn() returns unsigned long, which must be cast to phys_addr_t
486 * before being left-shifted PAGE_SHIFT bits -- this trick is to
487 * make 32-PAE kernel work correctly.
488 */
489 switch (level) {
490 case PG_LEVEL_1G:
491 phys_addr = (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT;
492 offset = virt_addr & ~PUD_PAGE_MASK;
493 break;
494 case PG_LEVEL_2M:
495 phys_addr = (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT;
496 offset = virt_addr & ~PMD_PAGE_MASK;
497 break;
498 default:
499 phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
500 offset = virt_addr & ~PAGE_MASK;
501 }
502
503 return (phys_addr_t)(phys_addr | offset);
504}
505EXPORT_SYMBOL_GPL(slow_virt_to_phys);
506
507/*
508 * Set the new pmd in all the pgds we know about:
509 */
510static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
511{
512 /* change init_mm */
513 set_pte_atomic(kpte, pte);
514#ifdef CONFIG_X86_32
515 if (!SHARED_KERNEL_PMD) {
516 struct page *page;
517
518 list_for_each_entry(page, &pgd_list, lru) {
519 pgd_t *pgd;
520 p4d_t *p4d;
521 pud_t *pud;
522 pmd_t *pmd;
523
524 pgd = (pgd_t *)page_address(page) + pgd_index(address);
525 p4d = p4d_offset(pgd, address);
526 pud = pud_offset(p4d, address);
527 pmd = pmd_offset(pud, address);
528 set_pte_atomic((pte_t *)pmd, pte);
529 }
530 }
531#endif
532}
533
534static pgprot_t pgprot_clear_protnone_bits(pgprot_t prot)
535{
536 /*
537 * _PAGE_GLOBAL means "global page" for present PTEs.
538 * But, it is also used to indicate _PAGE_PROTNONE
539 * for non-present PTEs.
540 *
541 * This ensures that a _PAGE_GLOBAL PTE going from
542 * present to non-present is not confused as
543 * _PAGE_PROTNONE.
544 */
545 if (!(pgprot_val(prot) & _PAGE_PRESENT))
546 pgprot_val(prot) &= ~_PAGE_GLOBAL;
547
548 return prot;
549}
550
551static int
552try_preserve_large_page(pte_t *kpte, unsigned long address,
553 struct cpa_data *cpa)
554{
555 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn, old_pfn;
556 pte_t new_pte, old_pte, *tmp;
557 pgprot_t old_prot, new_prot, req_prot;
558 int i, do_split = 1;
559 enum pg_level level;
560
561 if (cpa->force_split)
562 return 1;
563
564 spin_lock(&pgd_lock);
565 /*
566 * Check for races, another CPU might have split this page
567 * up already:
568 */
569 tmp = _lookup_address_cpa(cpa, address, &level);
570 if (tmp != kpte)
571 goto out_unlock;
572
573 switch (level) {
574 case PG_LEVEL_2M:
575 old_prot = pmd_pgprot(*(pmd_t *)kpte);
576 old_pfn = pmd_pfn(*(pmd_t *)kpte);
577 break;
578 case PG_LEVEL_1G:
579 old_prot = pud_pgprot(*(pud_t *)kpte);
580 old_pfn = pud_pfn(*(pud_t *)kpte);
581 break;
582 default:
583 do_split = -EINVAL;
584 goto out_unlock;
585 }
586
587 psize = page_level_size(level);
588 pmask = page_level_mask(level);
589
590 /*
591 * Calculate the number of pages, which fit into this large
592 * page starting at address:
593 */
594 nextpage_addr = (address + psize) & pmask;
595 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
596 if (numpages < cpa->numpages)
597 cpa->numpages = numpages;
598
599 /*
600 * We are safe now. Check whether the new pgprot is the same:
601 * Convert protection attributes to 4k-format, as cpa->mask* are set
602 * up accordingly.
603 */
604 old_pte = *kpte;
605 /* Clear PSE (aka _PAGE_PAT) and move PAT bit to correct position */
606 req_prot = pgprot_large_2_4k(old_prot);
607
608 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
609 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
610
611 /*
612 * req_prot is in format of 4k pages. It must be converted to large
613 * page format: the caching mode includes the PAT bit located at
614 * different bit positions in the two formats.
615 */
616 req_prot = pgprot_4k_2_large(req_prot);
617 req_prot = pgprot_clear_protnone_bits(req_prot);
618 if (pgprot_val(req_prot) & _PAGE_PRESENT)
619 pgprot_val(req_prot) |= _PAGE_PSE;
620
621 /*
622 * old_pfn points to the large page base pfn. So we need
623 * to add the offset of the virtual address:
624 */
625 pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT);
626 cpa->pfn = pfn;
627
628 new_prot = static_protections(req_prot, address, pfn);
629
630 /*
631 * We need to check the full range, whether
632 * static_protection() requires a different pgprot for one of
633 * the pages in the range we try to preserve:
634 */
635 addr = address & pmask;
636 pfn = old_pfn;
637 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
638 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
639
640 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
641 goto out_unlock;
642 }
643
644 /*
645 * If there are no changes, return. maxpages has been updated
646 * above:
647 */
648 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
649 do_split = 0;
650 goto out_unlock;
651 }
652
653 /*
654 * We need to change the attributes. Check, whether we can
655 * change the large page in one go. We request a split, when
656 * the address is not aligned and the number of pages is
657 * smaller than the number of pages in the large page. Note
658 * that we limited the number of possible pages already to
659 * the number of pages in the large page.
660 */
661 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
662 /*
663 * The address is aligned and the number of pages
664 * covers the full page.
665 */
666 new_pte = pfn_pte(old_pfn, new_prot);
667 __set_pmd_pte(kpte, address, new_pte);
668 cpa->flags |= CPA_FLUSHTLB;
669 do_split = 0;
670 }
671
672out_unlock:
673 spin_unlock(&pgd_lock);
674
675 return do_split;
676}
677
678static int
679__split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,
680 struct page *base)
681{
682 pte_t *pbase = (pte_t *)page_address(base);
683 unsigned long ref_pfn, pfn, pfninc = 1;
684 unsigned int i, level;
685 pte_t *tmp;
686 pgprot_t ref_prot;
687
688 spin_lock(&pgd_lock);
689 /*
690 * Check for races, another CPU might have split this page
691 * up for us already:
692 */
693 tmp = _lookup_address_cpa(cpa, address, &level);
694 if (tmp != kpte) {
695 spin_unlock(&pgd_lock);
696 return 1;
697 }
698
699 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
700
701 switch (level) {
702 case PG_LEVEL_2M:
703 ref_prot = pmd_pgprot(*(pmd_t *)kpte);
704 /*
705 * Clear PSE (aka _PAGE_PAT) and move
706 * PAT bit to correct position.
707 */
708 ref_prot = pgprot_large_2_4k(ref_prot);
709
710 ref_pfn = pmd_pfn(*(pmd_t *)kpte);
711 break;
712
713 case PG_LEVEL_1G:
714 ref_prot = pud_pgprot(*(pud_t *)kpte);
715 ref_pfn = pud_pfn(*(pud_t *)kpte);
716 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
717
718 /*
719 * Clear the PSE flags if the PRESENT flag is not set
720 * otherwise pmd_present/pmd_huge will return true
721 * even on a non present pmd.
722 */
723 if (!(pgprot_val(ref_prot) & _PAGE_PRESENT))
724 pgprot_val(ref_prot) &= ~_PAGE_PSE;
725 break;
726
727 default:
728 spin_unlock(&pgd_lock);
729 return 1;
730 }
731
732 ref_prot = pgprot_clear_protnone_bits(ref_prot);
733
734 /*
735 * Get the target pfn from the original entry:
736 */
737 pfn = ref_pfn;
738 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
739 set_pte(&pbase[i], pfn_pte(pfn, ref_prot));
740
741 if (virt_addr_valid(address)) {
742 unsigned long pfn = PFN_DOWN(__pa(address));
743
744 if (pfn_range_is_mapped(pfn, pfn + 1))
745 split_page_count(level);
746 }
747
748 /*
749 * Install the new, split up pagetable.
750 *
751 * We use the standard kernel pagetable protections for the new
752 * pagetable protections, the actual ptes set above control the
753 * primary protection behavior:
754 */
755 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
756
757 /*
758 * Intel Atom errata AAH41 workaround.
759 *
760 * The real fix should be in hw or in a microcode update, but
761 * we also probabilistically try to reduce the window of having
762 * a large TLB mixed with 4K TLBs while instruction fetches are
763 * going on.
764 */
765 __flush_tlb_all();
766 spin_unlock(&pgd_lock);
767
768 return 0;
769}
770
771static int split_large_page(struct cpa_data *cpa, pte_t *kpte,
772 unsigned long address)
773{
774 struct page *base;
775
776 if (!debug_pagealloc_enabled())
777 spin_unlock(&cpa_lock);
778 base = alloc_pages(GFP_KERNEL, 0);
779 if (!debug_pagealloc_enabled())
780 spin_lock(&cpa_lock);
781 if (!base)
782 return -ENOMEM;
783
784 if (__split_large_page(cpa, kpte, address, base))
785 __free_page(base);
786
787 return 0;
788}
789
790static bool try_to_free_pte_page(pte_t *pte)
791{
792 int i;
793
794 for (i = 0; i < PTRS_PER_PTE; i++)
795 if (!pte_none(pte[i]))
796 return false;
797
798 free_page((unsigned long)pte);
799 return true;
800}
801
802static bool try_to_free_pmd_page(pmd_t *pmd)
803{
804 int i;
805
806 for (i = 0; i < PTRS_PER_PMD; i++)
807 if (!pmd_none(pmd[i]))
808 return false;
809
810 free_page((unsigned long)pmd);
811 return true;
812}
813
814static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end)
815{
816 pte_t *pte = pte_offset_kernel(pmd, start);
817
818 while (start < end) {
819 set_pte(pte, __pte(0));
820
821 start += PAGE_SIZE;
822 pte++;
823 }
824
825 if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) {
826 pmd_clear(pmd);
827 return true;
828 }
829 return false;
830}
831
832static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd,
833 unsigned long start, unsigned long end)
834{
835 if (unmap_pte_range(pmd, start, end))
836 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
837 pud_clear(pud);
838}
839
840static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end)
841{
842 pmd_t *pmd = pmd_offset(pud, start);
843
844 /*
845 * Not on a 2MB page boundary?
846 */
847 if (start & (PMD_SIZE - 1)) {
848 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
849 unsigned long pre_end = min_t(unsigned long, end, next_page);
850
851 __unmap_pmd_range(pud, pmd, start, pre_end);
852
853 start = pre_end;
854 pmd++;
855 }
856
857 /*
858 * Try to unmap in 2M chunks.
859 */
860 while (end - start >= PMD_SIZE) {
861 if (pmd_large(*pmd))
862 pmd_clear(pmd);
863 else
864 __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE);
865
866 start += PMD_SIZE;
867 pmd++;
868 }
869
870 /*
871 * 4K leftovers?
872 */
873 if (start < end)
874 return __unmap_pmd_range(pud, pmd, start, end);
875
876 /*
877 * Try again to free the PMD page if haven't succeeded above.
878 */
879 if (!pud_none(*pud))
880 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
881 pud_clear(pud);
882}
883
884static void unmap_pud_range(p4d_t *p4d, unsigned long start, unsigned long end)
885{
886 pud_t *pud = pud_offset(p4d, start);
887
888 /*
889 * Not on a GB page boundary?
890 */
891 if (start & (PUD_SIZE - 1)) {
892 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
893 unsigned long pre_end = min_t(unsigned long, end, next_page);
894
895 unmap_pmd_range(pud, start, pre_end);
896
897 start = pre_end;
898 pud++;
899 }
900
901 /*
902 * Try to unmap in 1G chunks?
903 */
904 while (end - start >= PUD_SIZE) {
905
906 if (pud_large(*pud))
907 pud_clear(pud);
908 else
909 unmap_pmd_range(pud, start, start + PUD_SIZE);
910
911 start += PUD_SIZE;
912 pud++;
913 }
914
915 /*
916 * 2M leftovers?
917 */
918 if (start < end)
919 unmap_pmd_range(pud, start, end);
920
921 /*
922 * No need to try to free the PUD page because we'll free it in
923 * populate_pgd's error path
924 */
925}
926
927static int alloc_pte_page(pmd_t *pmd)
928{
929 pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL);
930 if (!pte)
931 return -1;
932
933 set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE));
934 return 0;
935}
936
937static int alloc_pmd_page(pud_t *pud)
938{
939 pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL);
940 if (!pmd)
941 return -1;
942
943 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
944 return 0;
945}
946
947static void populate_pte(struct cpa_data *cpa,
948 unsigned long start, unsigned long end,
949 unsigned num_pages, pmd_t *pmd, pgprot_t pgprot)
950{
951 pte_t *pte;
952
953 pte = pte_offset_kernel(pmd, start);
954
955 pgprot = pgprot_clear_protnone_bits(pgprot);
956
957 while (num_pages-- && start < end) {
958 set_pte(pte, pfn_pte(cpa->pfn, pgprot));
959
960 start += PAGE_SIZE;
961 cpa->pfn++;
962 pte++;
963 }
964}
965
966static long populate_pmd(struct cpa_data *cpa,
967 unsigned long start, unsigned long end,
968 unsigned num_pages, pud_t *pud, pgprot_t pgprot)
969{
970 long cur_pages = 0;
971 pmd_t *pmd;
972 pgprot_t pmd_pgprot;
973
974 /*
975 * Not on a 2M boundary?
976 */
977 if (start & (PMD_SIZE - 1)) {
978 unsigned long pre_end = start + (num_pages << PAGE_SHIFT);
979 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
980
981 pre_end = min_t(unsigned long, pre_end, next_page);
982 cur_pages = (pre_end - start) >> PAGE_SHIFT;
983 cur_pages = min_t(unsigned int, num_pages, cur_pages);
984
985 /*
986 * Need a PTE page?
987 */
988 pmd = pmd_offset(pud, start);
989 if (pmd_none(*pmd))
990 if (alloc_pte_page(pmd))
991 return -1;
992
993 populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot);
994
995 start = pre_end;
996 }
997
998 /*
999 * We mapped them all?
1000 */
1001 if (num_pages == cur_pages)
1002 return cur_pages;
1003
1004 pmd_pgprot = pgprot_4k_2_large(pgprot);
1005
1006 while (end - start >= PMD_SIZE) {
1007
1008 /*
1009 * We cannot use a 1G page so allocate a PMD page if needed.
1010 */
1011 if (pud_none(*pud))
1012 if (alloc_pmd_page(pud))
1013 return -1;
1014
1015 pmd = pmd_offset(pud, start);
1016
1017 set_pmd(pmd, __pmd(cpa->pfn << PAGE_SHIFT | _PAGE_PSE |
1018 massage_pgprot(pmd_pgprot)));
1019
1020 start += PMD_SIZE;
1021 cpa->pfn += PMD_SIZE >> PAGE_SHIFT;
1022 cur_pages += PMD_SIZE >> PAGE_SHIFT;
1023 }
1024
1025 /*
1026 * Map trailing 4K pages.
1027 */
1028 if (start < end) {
1029 pmd = pmd_offset(pud, start);
1030 if (pmd_none(*pmd))
1031 if (alloc_pte_page(pmd))
1032 return -1;
1033
1034 populate_pte(cpa, start, end, num_pages - cur_pages,
1035 pmd, pgprot);
1036 }
1037 return num_pages;
1038}
1039
1040static int populate_pud(struct cpa_data *cpa, unsigned long start, p4d_t *p4d,
1041 pgprot_t pgprot)
1042{
1043 pud_t *pud;
1044 unsigned long end;
1045 long cur_pages = 0;
1046 pgprot_t pud_pgprot;
1047
1048 end = start + (cpa->numpages << PAGE_SHIFT);
1049
1050 /*
1051 * Not on a Gb page boundary? => map everything up to it with
1052 * smaller pages.
1053 */
1054 if (start & (PUD_SIZE - 1)) {
1055 unsigned long pre_end;
1056 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
1057
1058 pre_end = min_t(unsigned long, end, next_page);
1059 cur_pages = (pre_end - start) >> PAGE_SHIFT;
1060 cur_pages = min_t(int, (int)cpa->numpages, cur_pages);
1061
1062 pud = pud_offset(p4d, start);
1063
1064 /*
1065 * Need a PMD page?
1066 */
1067 if (pud_none(*pud))
1068 if (alloc_pmd_page(pud))
1069 return -1;
1070
1071 cur_pages = populate_pmd(cpa, start, pre_end, cur_pages,
1072 pud, pgprot);
1073 if (cur_pages < 0)
1074 return cur_pages;
1075
1076 start = pre_end;
1077 }
1078
1079 /* We mapped them all? */
1080 if (cpa->numpages == cur_pages)
1081 return cur_pages;
1082
1083 pud = pud_offset(p4d, start);
1084 pud_pgprot = pgprot_4k_2_large(pgprot);
1085
1086 /*
1087 * Map everything starting from the Gb boundary, possibly with 1G pages
1088 */
1089 while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) {
1090 set_pud(pud, __pud(cpa->pfn << PAGE_SHIFT | _PAGE_PSE |
1091 massage_pgprot(pud_pgprot)));
1092
1093 start += PUD_SIZE;
1094 cpa->pfn += PUD_SIZE >> PAGE_SHIFT;
1095 cur_pages += PUD_SIZE >> PAGE_SHIFT;
1096 pud++;
1097 }
1098
1099 /* Map trailing leftover */
1100 if (start < end) {
1101 long tmp;
1102
1103 pud = pud_offset(p4d, start);
1104 if (pud_none(*pud))
1105 if (alloc_pmd_page(pud))
1106 return -1;
1107
1108 tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages,
1109 pud, pgprot);
1110 if (tmp < 0)
1111 return cur_pages;
1112
1113 cur_pages += tmp;
1114 }
1115 return cur_pages;
1116}
1117
1118/*
1119 * Restrictions for kernel page table do not necessarily apply when mapping in
1120 * an alternate PGD.
1121 */
1122static int populate_pgd(struct cpa_data *cpa, unsigned long addr)
1123{
1124 pgprot_t pgprot = __pgprot(_KERNPG_TABLE);
1125 pud_t *pud = NULL; /* shut up gcc */
1126 p4d_t *p4d;
1127 pgd_t *pgd_entry;
1128 long ret;
1129
1130 pgd_entry = cpa->pgd + pgd_index(addr);
1131
1132 if (pgd_none(*pgd_entry)) {
1133 p4d = (p4d_t *)get_zeroed_page(GFP_KERNEL);
1134 if (!p4d)
1135 return -1;
1136
1137 set_pgd(pgd_entry, __pgd(__pa(p4d) | _KERNPG_TABLE));
1138 }
1139
1140 /*
1141 * Allocate a PUD page and hand it down for mapping.
1142 */
1143 p4d = p4d_offset(pgd_entry, addr);
1144 if (p4d_none(*p4d)) {
1145 pud = (pud_t *)get_zeroed_page(GFP_KERNEL);
1146 if (!pud)
1147 return -1;
1148
1149 set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE));
1150 }
1151
1152 pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr);
1153 pgprot_val(pgprot) |= pgprot_val(cpa->mask_set);
1154
1155 ret = populate_pud(cpa, addr, p4d, pgprot);
1156 if (ret < 0) {
1157 /*
1158 * Leave the PUD page in place in case some other CPU or thread
1159 * already found it, but remove any useless entries we just
1160 * added to it.
1161 */
1162 unmap_pud_range(p4d, addr,
1163 addr + (cpa->numpages << PAGE_SHIFT));
1164 return ret;
1165 }
1166
1167 cpa->numpages = ret;
1168 return 0;
1169}
1170
1171static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
1172 int primary)
1173{
1174 if (cpa->pgd) {
1175 /*
1176 * Right now, we only execute this code path when mapping
1177 * the EFI virtual memory map regions, no other users
1178 * provide a ->pgd value. This may change in the future.
1179 */
1180 return populate_pgd(cpa, vaddr);
1181 }
1182
1183 /*
1184 * Ignore all non primary paths.
1185 */
1186 if (!primary) {
1187 cpa->numpages = 1;
1188 return 0;
1189 }
1190
1191 /*
1192 * Ignore the NULL PTE for kernel identity mapping, as it is expected
1193 * to have holes.
1194 * Also set numpages to '1' indicating that we processed cpa req for
1195 * one virtual address page and its pfn. TBD: numpages can be set based
1196 * on the initial value and the level returned by lookup_address().
1197 */
1198 if (within(vaddr, PAGE_OFFSET,
1199 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
1200 cpa->numpages = 1;
1201 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
1202 return 0;
1203
1204 } else if (__cpa_pfn_in_highmap(cpa->pfn)) {
1205 /* Faults in the highmap are OK, so do not warn: */
1206 return -EFAULT;
1207 } else {
1208 WARN(1, KERN_WARNING "CPA: called for zero pte. "
1209 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
1210 *cpa->vaddr);
1211
1212 return -EFAULT;
1213 }
1214}
1215
1216static int __change_page_attr(struct cpa_data *cpa, int primary)
1217{
1218 unsigned long address;
1219 int do_split, err;
1220 unsigned int level;
1221 pte_t *kpte, old_pte;
1222
1223 if (cpa->flags & CPA_PAGES_ARRAY) {
1224 struct page *page = cpa->pages[cpa->curpage];
1225 if (unlikely(PageHighMem(page)))
1226 return 0;
1227 address = (unsigned long)page_address(page);
1228 } else if (cpa->flags & CPA_ARRAY)
1229 address = cpa->vaddr[cpa->curpage];
1230 else
1231 address = *cpa->vaddr;
1232repeat:
1233 kpte = _lookup_address_cpa(cpa, address, &level);
1234 if (!kpte)
1235 return __cpa_process_fault(cpa, address, primary);
1236
1237 old_pte = *kpte;
1238 if (pte_none(old_pte))
1239 return __cpa_process_fault(cpa, address, primary);
1240
1241 if (level == PG_LEVEL_4K) {
1242 pte_t new_pte;
1243 pgprot_t new_prot = pte_pgprot(old_pte);
1244 unsigned long pfn = pte_pfn(old_pte);
1245
1246 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
1247 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
1248
1249 new_prot = static_protections(new_prot, address, pfn);
1250
1251 new_prot = pgprot_clear_protnone_bits(new_prot);
1252
1253 /*
1254 * We need to keep the pfn from the existing PTE,
1255 * after all we're only going to change it's attributes
1256 * not the memory it points to
1257 */
1258 new_pte = pfn_pte(pfn, new_prot);
1259 cpa->pfn = pfn;
1260 /*
1261 * Do we really change anything ?
1262 */
1263 if (pte_val(old_pte) != pte_val(new_pte)) {
1264 set_pte_atomic(kpte, new_pte);
1265 cpa->flags |= CPA_FLUSHTLB;
1266 }
1267 cpa->numpages = 1;
1268 return 0;
1269 }
1270
1271 /*
1272 * Check, whether we can keep the large page intact
1273 * and just change the pte:
1274 */
1275 do_split = try_preserve_large_page(kpte, address, cpa);
1276 /*
1277 * When the range fits into the existing large page,
1278 * return. cp->numpages and cpa->tlbflush have been updated in
1279 * try_large_page:
1280 */
1281 if (do_split <= 0)
1282 return do_split;
1283
1284 /*
1285 * We have to split the large page:
1286 */
1287 err = split_large_page(cpa, kpte, address);
1288 if (!err) {
1289 /*
1290 * Do a global flush tlb after splitting the large page
1291 * and before we do the actual change page attribute in the PTE.
1292 *
1293 * With out this, we violate the TLB application note, that says
1294 * "The TLBs may contain both ordinary and large-page
1295 * translations for a 4-KByte range of linear addresses. This
1296 * may occur if software modifies the paging structures so that
1297 * the page size used for the address range changes. If the two
1298 * translations differ with respect to page frame or attributes
1299 * (e.g., permissions), processor behavior is undefined and may
1300 * be implementation-specific."
1301 *
1302 * We do this global tlb flush inside the cpa_lock, so that we
1303 * don't allow any other cpu, with stale tlb entries change the
1304 * page attribute in parallel, that also falls into the
1305 * just split large page entry.
1306 */
1307 flush_tlb_all();
1308 goto repeat;
1309 }
1310
1311 return err;
1312}
1313
1314static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
1315
1316static int cpa_process_alias(struct cpa_data *cpa)
1317{
1318 struct cpa_data alias_cpa;
1319 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
1320 unsigned long vaddr;
1321 int ret;
1322
1323 if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1))
1324 return 0;
1325
1326 /*
1327 * No need to redo, when the primary call touched the direct
1328 * mapping already:
1329 */
1330 if (cpa->flags & CPA_PAGES_ARRAY) {
1331 struct page *page = cpa->pages[cpa->curpage];
1332 if (unlikely(PageHighMem(page)))
1333 return 0;
1334 vaddr = (unsigned long)page_address(page);
1335 } else if (cpa->flags & CPA_ARRAY)
1336 vaddr = cpa->vaddr[cpa->curpage];
1337 else
1338 vaddr = *cpa->vaddr;
1339
1340 if (!(within(vaddr, PAGE_OFFSET,
1341 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
1342
1343 alias_cpa = *cpa;
1344 alias_cpa.vaddr = &laddr;
1345 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
1346
1347 ret = __change_page_attr_set_clr(&alias_cpa, 0);
1348 if (ret)
1349 return ret;
1350 }
1351
1352#ifdef CONFIG_X86_64
1353 /*
1354 * If the primary call didn't touch the high mapping already
1355 * and the physical address is inside the kernel map, we need
1356 * to touch the high mapped kernel as well:
1357 */
1358 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
1359 __cpa_pfn_in_highmap(cpa->pfn)) {
1360 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
1361 __START_KERNEL_map - phys_base;
1362 alias_cpa = *cpa;
1363 alias_cpa.vaddr = &temp_cpa_vaddr;
1364 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
1365
1366 /*
1367 * The high mapping range is imprecise, so ignore the
1368 * return value.
1369 */
1370 __change_page_attr_set_clr(&alias_cpa, 0);
1371 }
1372#endif
1373
1374 return 0;
1375}
1376
1377static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
1378{
1379 unsigned long numpages = cpa->numpages;
1380 int ret;
1381
1382 while (numpages) {
1383 /*
1384 * Store the remaining nr of pages for the large page
1385 * preservation check.
1386 */
1387 cpa->numpages = numpages;
1388 /* for array changes, we can't use large page */
1389 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
1390 cpa->numpages = 1;
1391
1392 if (!debug_pagealloc_enabled())
1393 spin_lock(&cpa_lock);
1394 ret = __change_page_attr(cpa, checkalias);
1395 if (!debug_pagealloc_enabled())
1396 spin_unlock(&cpa_lock);
1397 if (ret)
1398 return ret;
1399
1400 if (checkalias) {
1401 ret = cpa_process_alias(cpa);
1402 if (ret)
1403 return ret;
1404 }
1405
1406 /*
1407 * Adjust the number of pages with the result of the
1408 * CPA operation. Either a large page has been
1409 * preserved or a single page update happened.
1410 */
1411 BUG_ON(cpa->numpages > numpages || !cpa->numpages);
1412 numpages -= cpa->numpages;
1413 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
1414 cpa->curpage++;
1415 else
1416 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
1417
1418 }
1419 return 0;
1420}
1421
1422static int change_page_attr_set_clr(unsigned long *addr, int numpages,
1423 pgprot_t mask_set, pgprot_t mask_clr,
1424 int force_split, int in_flag,
1425 struct page **pages)
1426{
1427 struct cpa_data cpa;
1428 int ret, cache, checkalias;
1429 unsigned long baddr = 0;
1430
1431 memset(&cpa, 0, sizeof(cpa));
1432
1433 /*
1434 * Check, if we are requested to set a not supported
1435 * feature. Clearing non-supported features is OK.
1436 */
1437 mask_set = canon_pgprot(mask_set);
1438
1439 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
1440 return 0;
1441
1442 /* Ensure we are PAGE_SIZE aligned */
1443 if (in_flag & CPA_ARRAY) {
1444 int i;
1445 for (i = 0; i < numpages; i++) {
1446 if (addr[i] & ~PAGE_MASK) {
1447 addr[i] &= PAGE_MASK;
1448 WARN_ON_ONCE(1);
1449 }
1450 }
1451 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
1452 /*
1453 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
1454 * No need to cehck in that case
1455 */
1456 if (*addr & ~PAGE_MASK) {
1457 *addr &= PAGE_MASK;
1458 /*
1459 * People should not be passing in unaligned addresses:
1460 */
1461 WARN_ON_ONCE(1);
1462 }
1463 /*
1464 * Save address for cache flush. *addr is modified in the call
1465 * to __change_page_attr_set_clr() below.
1466 */
1467 baddr = *addr;
1468 }
1469
1470 /* Must avoid aliasing mappings in the highmem code */
1471 kmap_flush_unused();
1472
1473 vm_unmap_aliases();
1474
1475 cpa.vaddr = addr;
1476 cpa.pages = pages;
1477 cpa.numpages = numpages;
1478 cpa.mask_set = mask_set;
1479 cpa.mask_clr = mask_clr;
1480 cpa.flags = 0;
1481 cpa.curpage = 0;
1482 cpa.force_split = force_split;
1483
1484 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
1485 cpa.flags |= in_flag;
1486
1487 /* No alias checking for _NX bit modifications */
1488 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
1489
1490 ret = __change_page_attr_set_clr(&cpa, checkalias);
1491
1492 /*
1493 * Check whether we really changed something:
1494 */
1495 if (!(cpa.flags & CPA_FLUSHTLB))
1496 goto out;
1497
1498 /*
1499 * No need to flush, when we did not set any of the caching
1500 * attributes:
1501 */
1502 cache = !!pgprot2cachemode(mask_set);
1503
1504 /*
1505 * On success we use CLFLUSH, when the CPU supports it to
1506 * avoid the WBINVD. If the CPU does not support it and in the
1507 * error case we fall back to cpa_flush_all (which uses
1508 * WBINVD):
1509 */
1510 if (!ret && boot_cpu_has(X86_FEATURE_CLFLUSH)) {
1511 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
1512 cpa_flush_array(addr, numpages, cache,
1513 cpa.flags, pages);
1514 } else
1515 cpa_flush_range(baddr, numpages, cache);
1516 } else
1517 cpa_flush_all(cache);
1518
1519out:
1520 return ret;
1521}
1522
1523static inline int change_page_attr_set(unsigned long *addr, int numpages,
1524 pgprot_t mask, int array)
1525{
1526 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
1527 (array ? CPA_ARRAY : 0), NULL);
1528}
1529
1530static inline int change_page_attr_clear(unsigned long *addr, int numpages,
1531 pgprot_t mask, int array)
1532{
1533 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
1534 (array ? CPA_ARRAY : 0), NULL);
1535}
1536
1537static inline int cpa_set_pages_array(struct page **pages, int numpages,
1538 pgprot_t mask)
1539{
1540 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
1541 CPA_PAGES_ARRAY, pages);
1542}
1543
1544static inline int cpa_clear_pages_array(struct page **pages, int numpages,
1545 pgprot_t mask)
1546{
1547 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
1548 CPA_PAGES_ARRAY, pages);
1549}
1550
1551int _set_memory_uc(unsigned long addr, int numpages)
1552{
1553 /*
1554 * for now UC MINUS. see comments in ioremap_nocache()
1555 * If you really need strong UC use ioremap_uc(), but note
1556 * that you cannot override IO areas with set_memory_*() as
1557 * these helpers cannot work with IO memory.
1558 */
1559 return change_page_attr_set(&addr, numpages,
1560 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1561 0);
1562}
1563
1564int set_memory_uc(unsigned long addr, int numpages)
1565{
1566 int ret;
1567
1568 /*
1569 * for now UC MINUS. see comments in ioremap_nocache()
1570 */
1571 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1572 _PAGE_CACHE_MODE_UC_MINUS, NULL);
1573 if (ret)
1574 goto out_err;
1575
1576 ret = _set_memory_uc(addr, numpages);
1577 if (ret)
1578 goto out_free;
1579
1580 return 0;
1581
1582out_free:
1583 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1584out_err:
1585 return ret;
1586}
1587EXPORT_SYMBOL(set_memory_uc);
1588
1589static int _set_memory_array(unsigned long *addr, int addrinarray,
1590 enum page_cache_mode new_type)
1591{
1592 enum page_cache_mode set_type;
1593 int i, j;
1594 int ret;
1595
1596 for (i = 0; i < addrinarray; i++) {
1597 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1598 new_type, NULL);
1599 if (ret)
1600 goto out_free;
1601 }
1602
1603 /* If WC, set to UC- first and then WC */
1604 set_type = (new_type == _PAGE_CACHE_MODE_WC) ?
1605 _PAGE_CACHE_MODE_UC_MINUS : new_type;
1606
1607 ret = change_page_attr_set(addr, addrinarray,
1608 cachemode2pgprot(set_type), 1);
1609
1610 if (!ret && new_type == _PAGE_CACHE_MODE_WC)
1611 ret = change_page_attr_set_clr(addr, addrinarray,
1612 cachemode2pgprot(
1613 _PAGE_CACHE_MODE_WC),
1614 __pgprot(_PAGE_CACHE_MASK),
1615 0, CPA_ARRAY, NULL);
1616 if (ret)
1617 goto out_free;
1618
1619 return 0;
1620
1621out_free:
1622 for (j = 0; j < i; j++)
1623 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1624
1625 return ret;
1626}
1627
1628int set_memory_array_uc(unsigned long *addr, int addrinarray)
1629{
1630 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
1631}
1632EXPORT_SYMBOL(set_memory_array_uc);
1633
1634int set_memory_array_wc(unsigned long *addr, int addrinarray)
1635{
1636 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC);
1637}
1638EXPORT_SYMBOL(set_memory_array_wc);
1639
1640int set_memory_array_wt(unsigned long *addr, int addrinarray)
1641{
1642 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT);
1643}
1644EXPORT_SYMBOL_GPL(set_memory_array_wt);
1645
1646int _set_memory_wc(unsigned long addr, int numpages)
1647{
1648 int ret;
1649 unsigned long addr_copy = addr;
1650
1651 ret = change_page_attr_set(&addr, numpages,
1652 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1653 0);
1654 if (!ret) {
1655 ret = change_page_attr_set_clr(&addr_copy, numpages,
1656 cachemode2pgprot(
1657 _PAGE_CACHE_MODE_WC),
1658 __pgprot(_PAGE_CACHE_MASK),
1659 0, 0, NULL);
1660 }
1661 return ret;
1662}
1663
1664int set_memory_wc(unsigned long addr, int numpages)
1665{
1666 int ret;
1667
1668 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1669 _PAGE_CACHE_MODE_WC, NULL);
1670 if (ret)
1671 return ret;
1672
1673 ret = _set_memory_wc(addr, numpages);
1674 if (ret)
1675 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1676
1677 return ret;
1678}
1679EXPORT_SYMBOL(set_memory_wc);
1680
1681int _set_memory_wt(unsigned long addr, int numpages)
1682{
1683 return change_page_attr_set(&addr, numpages,
1684 cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0);
1685}
1686
1687int set_memory_wt(unsigned long addr, int numpages)
1688{
1689 int ret;
1690
1691 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1692 _PAGE_CACHE_MODE_WT, NULL);
1693 if (ret)
1694 return ret;
1695
1696 ret = _set_memory_wt(addr, numpages);
1697 if (ret)
1698 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1699
1700 return ret;
1701}
1702EXPORT_SYMBOL_GPL(set_memory_wt);
1703
1704int _set_memory_wb(unsigned long addr, int numpages)
1705{
1706 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1707 return change_page_attr_clear(&addr, numpages,
1708 __pgprot(_PAGE_CACHE_MASK), 0);
1709}
1710
1711int set_memory_wb(unsigned long addr, int numpages)
1712{
1713 int ret;
1714
1715 ret = _set_memory_wb(addr, numpages);
1716 if (ret)
1717 return ret;
1718
1719 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1720 return 0;
1721}
1722EXPORT_SYMBOL(set_memory_wb);
1723
1724int set_memory_array_wb(unsigned long *addr, int addrinarray)
1725{
1726 int i;
1727 int ret;
1728
1729 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1730 ret = change_page_attr_clear(addr, addrinarray,
1731 __pgprot(_PAGE_CACHE_MASK), 1);
1732 if (ret)
1733 return ret;
1734
1735 for (i = 0; i < addrinarray; i++)
1736 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1737
1738 return 0;
1739}
1740EXPORT_SYMBOL(set_memory_array_wb);
1741
1742int set_memory_x(unsigned long addr, int numpages)
1743{
1744 if (!(__supported_pte_mask & _PAGE_NX))
1745 return 0;
1746
1747 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1748}
1749EXPORT_SYMBOL(set_memory_x);
1750
1751int set_memory_nx(unsigned long addr, int numpages)
1752{
1753 if (!(__supported_pte_mask & _PAGE_NX))
1754 return 0;
1755
1756 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1757}
1758EXPORT_SYMBOL(set_memory_nx);
1759
1760int set_memory_ro(unsigned long addr, int numpages)
1761{
1762 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1763}
1764
1765int set_memory_rw(unsigned long addr, int numpages)
1766{
1767 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1768}
1769
1770int set_memory_np(unsigned long addr, int numpages)
1771{
1772 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1773}
1774
1775int set_memory_4k(unsigned long addr, int numpages)
1776{
1777 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1778 __pgprot(0), 1, 0, NULL);
1779}
1780
1781int set_memory_nonglobal(unsigned long addr, int numpages)
1782{
1783 return change_page_attr_clear(&addr, numpages,
1784 __pgprot(_PAGE_GLOBAL), 0);
1785}
1786
1787static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc)
1788{
1789 struct cpa_data cpa;
1790 unsigned long start;
1791 int ret;
1792
1793 /* Nothing to do if memory encryption is not active */
1794 if (!mem_encrypt_active())
1795 return 0;
1796
1797 /* Should not be working on unaligned addresses */
1798 if (WARN_ONCE(addr & ~PAGE_MASK, "misaligned address: %#lx\n", addr))
1799 addr &= PAGE_MASK;
1800
1801 start = addr;
1802
1803 memset(&cpa, 0, sizeof(cpa));
1804 cpa.vaddr = &addr;
1805 cpa.numpages = numpages;
1806 cpa.mask_set = enc ? __pgprot(_PAGE_ENC) : __pgprot(0);
1807 cpa.mask_clr = enc ? __pgprot(0) : __pgprot(_PAGE_ENC);
1808 cpa.pgd = init_mm.pgd;
1809
1810 /* Must avoid aliasing mappings in the highmem code */
1811 kmap_flush_unused();
1812 vm_unmap_aliases();
1813
1814 /*
1815 * Before changing the encryption attribute, we need to flush caches.
1816 */
1817 if (static_cpu_has(X86_FEATURE_CLFLUSH))
1818 cpa_flush_range(start, numpages, 1);
1819 else
1820 cpa_flush_all(1);
1821
1822 ret = __change_page_attr_set_clr(&cpa, 1);
1823
1824 /*
1825 * After changing the encryption attribute, we need to flush TLBs
1826 * again in case any speculative TLB caching occurred (but no need
1827 * to flush caches again). We could just use cpa_flush_all(), but
1828 * in case TLB flushing gets optimized in the cpa_flush_range()
1829 * path use the same logic as above.
1830 */
1831 if (static_cpu_has(X86_FEATURE_CLFLUSH))
1832 cpa_flush_range(start, numpages, 0);
1833 else
1834 cpa_flush_all(0);
1835
1836 return ret;
1837}
1838
1839int set_memory_encrypted(unsigned long addr, int numpages)
1840{
1841 return __set_memory_enc_dec(addr, numpages, true);
1842}
1843EXPORT_SYMBOL_GPL(set_memory_encrypted);
1844
1845int set_memory_decrypted(unsigned long addr, int numpages)
1846{
1847 return __set_memory_enc_dec(addr, numpages, false);
1848}
1849EXPORT_SYMBOL_GPL(set_memory_decrypted);
1850
1851int set_pages_uc(struct page *page, int numpages)
1852{
1853 unsigned long addr = (unsigned long)page_address(page);
1854
1855 return set_memory_uc(addr, numpages);
1856}
1857EXPORT_SYMBOL(set_pages_uc);
1858
1859static int _set_pages_array(struct page **pages, int addrinarray,
1860 enum page_cache_mode new_type)
1861{
1862 unsigned long start;
1863 unsigned long end;
1864 enum page_cache_mode set_type;
1865 int i;
1866 int free_idx;
1867 int ret;
1868
1869 for (i = 0; i < addrinarray; i++) {
1870 if (PageHighMem(pages[i]))
1871 continue;
1872 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1873 end = start + PAGE_SIZE;
1874 if (reserve_memtype(start, end, new_type, NULL))
1875 goto err_out;
1876 }
1877
1878 /* If WC, set to UC- first and then WC */
1879 set_type = (new_type == _PAGE_CACHE_MODE_WC) ?
1880 _PAGE_CACHE_MODE_UC_MINUS : new_type;
1881
1882 ret = cpa_set_pages_array(pages, addrinarray,
1883 cachemode2pgprot(set_type));
1884 if (!ret && new_type == _PAGE_CACHE_MODE_WC)
1885 ret = change_page_attr_set_clr(NULL, addrinarray,
1886 cachemode2pgprot(
1887 _PAGE_CACHE_MODE_WC),
1888 __pgprot(_PAGE_CACHE_MASK),
1889 0, CPA_PAGES_ARRAY, pages);
1890 if (ret)
1891 goto err_out;
1892 return 0; /* Success */
1893err_out:
1894 free_idx = i;
1895 for (i = 0; i < free_idx; i++) {
1896 if (PageHighMem(pages[i]))
1897 continue;
1898 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1899 end = start + PAGE_SIZE;
1900 free_memtype(start, end);
1901 }
1902 return -EINVAL;
1903}
1904
1905int set_pages_array_uc(struct page **pages, int addrinarray)
1906{
1907 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
1908}
1909EXPORT_SYMBOL(set_pages_array_uc);
1910
1911int set_pages_array_wc(struct page **pages, int addrinarray)
1912{
1913 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC);
1914}
1915EXPORT_SYMBOL(set_pages_array_wc);
1916
1917int set_pages_array_wt(struct page **pages, int addrinarray)
1918{
1919 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT);
1920}
1921EXPORT_SYMBOL_GPL(set_pages_array_wt);
1922
1923int set_pages_wb(struct page *page, int numpages)
1924{
1925 unsigned long addr = (unsigned long)page_address(page);
1926
1927 return set_memory_wb(addr, numpages);
1928}
1929EXPORT_SYMBOL(set_pages_wb);
1930
1931int set_pages_array_wb(struct page **pages, int addrinarray)
1932{
1933 int retval;
1934 unsigned long start;
1935 unsigned long end;
1936 int i;
1937
1938 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1939 retval = cpa_clear_pages_array(pages, addrinarray,
1940 __pgprot(_PAGE_CACHE_MASK));
1941 if (retval)
1942 return retval;
1943
1944 for (i = 0; i < addrinarray; i++) {
1945 if (PageHighMem(pages[i]))
1946 continue;
1947 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1948 end = start + PAGE_SIZE;
1949 free_memtype(start, end);
1950 }
1951
1952 return 0;
1953}
1954EXPORT_SYMBOL(set_pages_array_wb);
1955
1956int set_pages_x(struct page *page, int numpages)
1957{
1958 unsigned long addr = (unsigned long)page_address(page);
1959
1960 return set_memory_x(addr, numpages);
1961}
1962EXPORT_SYMBOL(set_pages_x);
1963
1964int set_pages_nx(struct page *page, int numpages)
1965{
1966 unsigned long addr = (unsigned long)page_address(page);
1967
1968 return set_memory_nx(addr, numpages);
1969}
1970EXPORT_SYMBOL(set_pages_nx);
1971
1972int set_pages_ro(struct page *page, int numpages)
1973{
1974 unsigned long addr = (unsigned long)page_address(page);
1975
1976 return set_memory_ro(addr, numpages);
1977}
1978
1979int set_pages_rw(struct page *page, int numpages)
1980{
1981 unsigned long addr = (unsigned long)page_address(page);
1982
1983 return set_memory_rw(addr, numpages);
1984}
1985
1986#ifdef CONFIG_DEBUG_PAGEALLOC
1987
1988static int __set_pages_p(struct page *page, int numpages)
1989{
1990 unsigned long tempaddr = (unsigned long) page_address(page);
1991 struct cpa_data cpa = { .vaddr = &tempaddr,
1992 .pgd = NULL,
1993 .numpages = numpages,
1994 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1995 .mask_clr = __pgprot(0),
1996 .flags = 0};
1997
1998 /*
1999 * No alias checking needed for setting present flag. otherwise,
2000 * we may need to break large pages for 64-bit kernel text
2001 * mappings (this adds to complexity if we want to do this from
2002 * atomic context especially). Let's keep it simple!
2003 */
2004 return __change_page_attr_set_clr(&cpa, 0);
2005}
2006
2007static int __set_pages_np(struct page *page, int numpages)
2008{
2009 unsigned long tempaddr = (unsigned long) page_address(page);
2010 struct cpa_data cpa = { .vaddr = &tempaddr,
2011 .pgd = NULL,
2012 .numpages = numpages,
2013 .mask_set = __pgprot(0),
2014 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
2015 .flags = 0};
2016
2017 /*
2018 * No alias checking needed for setting not present flag. otherwise,
2019 * we may need to break large pages for 64-bit kernel text
2020 * mappings (this adds to complexity if we want to do this from
2021 * atomic context especially). Let's keep it simple!
2022 */
2023 return __change_page_attr_set_clr(&cpa, 0);
2024}
2025
2026void __kernel_map_pages(struct page *page, int numpages, int enable)
2027{
2028 if (PageHighMem(page))
2029 return;
2030 if (!enable) {
2031 debug_check_no_locks_freed(page_address(page),
2032 numpages * PAGE_SIZE);
2033 }
2034
2035 /*
2036 * The return value is ignored as the calls cannot fail.
2037 * Large pages for identity mappings are not used at boot time
2038 * and hence no memory allocations during large page split.
2039 */
2040 if (enable)
2041 __set_pages_p(page, numpages);
2042 else
2043 __set_pages_np(page, numpages);
2044
2045 /*
2046 * We should perform an IPI and flush all tlbs,
2047 * but that can deadlock->flush only current cpu:
2048 */
2049 __flush_tlb_all();
2050
2051 arch_flush_lazy_mmu_mode();
2052}
2053
2054#ifdef CONFIG_HIBERNATION
2055
2056bool kernel_page_present(struct page *page)
2057{
2058 unsigned int level;
2059 pte_t *pte;
2060
2061 if (PageHighMem(page))
2062 return false;
2063
2064 pte = lookup_address((unsigned long)page_address(page), &level);
2065 return (pte_val(*pte) & _PAGE_PRESENT);
2066}
2067
2068#endif /* CONFIG_HIBERNATION */
2069
2070#endif /* CONFIG_DEBUG_PAGEALLOC */
2071
2072int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
2073 unsigned numpages, unsigned long page_flags)
2074{
2075 int retval = -EINVAL;
2076
2077 struct cpa_data cpa = {
2078 .vaddr = &address,
2079 .pfn = pfn,
2080 .pgd = pgd,
2081 .numpages = numpages,
2082 .mask_set = __pgprot(0),
2083 .mask_clr = __pgprot(0),
2084 .flags = 0,
2085 };
2086
2087 if (!(__supported_pte_mask & _PAGE_NX))
2088 goto out;
2089
2090 if (!(page_flags & _PAGE_NX))
2091 cpa.mask_clr = __pgprot(_PAGE_NX);
2092
2093 if (!(page_flags & _PAGE_RW))
2094 cpa.mask_clr = __pgprot(_PAGE_RW);
2095
2096 if (!(page_flags & _PAGE_ENC))
2097 cpa.mask_clr = pgprot_encrypted(cpa.mask_clr);
2098
2099 cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags);
2100
2101 retval = __change_page_attr_set_clr(&cpa, 0);
2102 __flush_tlb_all();
2103
2104out:
2105 return retval;
2106}
2107
2108/*
2109 * The testcases use internal knowledge of the implementation that shouldn't
2110 * be exposed to the rest of the kernel. Include these directly here.
2111 */
2112#ifdef CONFIG_CPA_DEBUG
2113#include "pageattr-test.c"
2114#endif