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1/*
2 * sc-ip22.c: Indy cache management functions.
3 *
4 * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
5 * derived from r4xx0.c by David S. Miller (davem@davemloft.net).
6 */
7#include <linux/init.h>
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/mm.h>
11
12#include <asm/bcache.h>
13#include <asm/page.h>
14#include <asm/pgtable.h>
15#include <asm/system.h>
16#include <asm/bootinfo.h>
17#include <asm/sgi/ip22.h>
18#include <asm/sgi/mc.h>
19
20/* Secondary cache size in bytes, if present. */
21static unsigned long scache_size;
22
23#undef DEBUG_CACHE
24
25#define SC_SIZE 0x00080000
26#define SC_LINE 32
27#define CI_MASK (SC_SIZE - SC_LINE)
28#define SC_INDEX(n) ((n) & CI_MASK)
29
30static inline void indy_sc_wipe(unsigned long first, unsigned long last)
31{
32 unsigned long tmp;
33
34 __asm__ __volatile__(
35 ".set\tpush\t\t\t# indy_sc_wipe\n\t"
36 ".set\tnoreorder\n\t"
37 ".set\tmips3\n\t"
38 ".set\tnoat\n\t"
39 "mfc0\t%2, $12\n\t"
40 "li\t$1, 0x80\t\t\t# Go 64 bit\n\t"
41 "mtc0\t$1, $12\n\t"
42
43 "dli\t$1, 0x9000000080000000\n\t"
44 "or\t%0, $1\t\t\t# first line to flush\n\t"
45 "or\t%1, $1\t\t\t# last line to flush\n\t"
46 ".set\tat\n\t"
47
48 "1:\tsw\t$0, 0(%0)\n\t"
49 "bne\t%0, %1, 1b\n\t"
50 " daddu\t%0, 32\n\t"
51
52 "mtc0\t%2, $12\t\t\t# Back to 32 bit\n\t"
53 "nop; nop; nop; nop;\n\t"
54 ".set\tpop"
55 : "=r" (first), "=r" (last), "=&r" (tmp)
56 : "0" (first), "1" (last));
57}
58
59static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size)
60{
61 unsigned long first_line, last_line;
62 unsigned long flags;
63
64#ifdef DEBUG_CACHE
65 printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size);
66#endif
67
68 /* Catch bad driver code */
69 BUG_ON(size == 0);
70
71 /* Which lines to flush? */
72 first_line = SC_INDEX(addr);
73 last_line = SC_INDEX(addr + size - 1);
74
75 local_irq_save(flags);
76 if (first_line <= last_line) {
77 indy_sc_wipe(first_line, last_line);
78 goto out;
79 }
80
81 indy_sc_wipe(first_line, SC_SIZE - SC_LINE);
82 indy_sc_wipe(0, last_line);
83out:
84 local_irq_restore(flags);
85}
86
87static void indy_sc_enable(void)
88{
89 unsigned long addr, tmp1, tmp2;
90
91 /* This is really cool... */
92#ifdef DEBUG_CACHE
93 printk("Enabling R4600 SCACHE\n");
94#endif
95 __asm__ __volatile__(
96 ".set\tpush\n\t"
97 ".set\tnoreorder\n\t"
98 ".set\tmips3\n\t"
99 "mfc0\t%2, $12\n\t"
100 "nop; nop; nop; nop;\n\t"
101 "li\t%1, 0x80\n\t"
102 "mtc0\t%1, $12\n\t"
103 "nop; nop; nop; nop;\n\t"
104 "li\t%0, 0x1\n\t"
105 "dsll\t%0, 31\n\t"
106 "lui\t%1, 0x9000\n\t"
107 "dsll32\t%1, 0\n\t"
108 "or\t%0, %1, %0\n\t"
109 "sb\t$0, 0(%0)\n\t"
110 "mtc0\t$0, $12\n\t"
111 "nop; nop; nop; nop;\n\t"
112 "mtc0\t%2, $12\n\t"
113 "nop; nop; nop; nop;\n\t"
114 ".set\tpop"
115 : "=r" (tmp1), "=r" (tmp2), "=r" (addr));
116}
117
118static void indy_sc_disable(void)
119{
120 unsigned long tmp1, tmp2, tmp3;
121
122#ifdef DEBUG_CACHE
123 printk("Disabling R4600 SCACHE\n");
124#endif
125 __asm__ __volatile__(
126 ".set\tpush\n\t"
127 ".set\tnoreorder\n\t"
128 ".set\tmips3\n\t"
129 "li\t%0, 0x1\n\t"
130 "dsll\t%0, 31\n\t"
131 "lui\t%1, 0x9000\n\t"
132 "dsll32\t%1, 0\n\t"
133 "or\t%0, %1, %0\n\t"
134 "mfc0\t%2, $12\n\t"
135 "nop; nop; nop; nop\n\t"
136 "li\t%1, 0x80\n\t"
137 "mtc0\t%1, $12\n\t"
138 "nop; nop; nop; nop\n\t"
139 "sh\t$0, 0(%0)\n\t"
140 "mtc0\t$0, $12\n\t"
141 "nop; nop; nop; nop\n\t"
142 "mtc0\t%2, $12\n\t"
143 "nop; nop; nop; nop\n\t"
144 ".set\tpop"
145 : "=r" (tmp1), "=r" (tmp2), "=r" (tmp3));
146}
147
148static inline int __init indy_sc_probe(void)
149{
150 unsigned int size = ip22_eeprom_read(&sgimc->eeprom, 17);
151 if (size == 0)
152 return 0;
153
154 size <<= PAGE_SHIFT;
155 printk(KERN_INFO "R4600/R5000 SCACHE size %dK, linesize 32 bytes.\n",
156 size >> 10);
157 scache_size = size;
158
159 return 1;
160}
161
162/* XXX Check with wje if the Indy caches can differenciate between
163 writeback + invalidate and just invalidate. */
164static struct bcache_ops indy_sc_ops = {
165 .bc_enable = indy_sc_enable,
166 .bc_disable = indy_sc_disable,
167 .bc_wback_inv = indy_sc_wback_invalidate,
168 .bc_inv = indy_sc_wback_invalidate
169};
170
171void __cpuinit indy_sc_init(void)
172{
173 if (indy_sc_probe()) {
174 indy_sc_enable();
175 bcops = &indy_sc_ops;
176 }
177}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * sc-ip22.c: Indy cache management functions.
4 *
5 * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
6 * derived from r4xx0.c by David S. Miller (davem@davemloft.net).
7 */
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/mm.h>
12
13#include <asm/bcache.h>
14#include <asm/page.h>
15#include <asm/pgtable.h>
16#include <asm/bootinfo.h>
17#include <asm/sgi/ip22.h>
18#include <asm/sgi/mc.h>
19
20/* Secondary cache size in bytes, if present. */
21static unsigned long scache_size;
22
23#undef DEBUG_CACHE
24
25#define SC_SIZE 0x00080000
26#define SC_LINE 32
27#define CI_MASK (SC_SIZE - SC_LINE)
28#define SC_INDEX(n) ((n) & CI_MASK)
29
30static inline void indy_sc_wipe(unsigned long first, unsigned long last)
31{
32 unsigned long tmp;
33
34 __asm__ __volatile__(
35 " .set push # indy_sc_wipe \n"
36 " .set noreorder \n"
37 " .set mips3 \n"
38 " .set noat \n"
39 " mfc0 %2, $12 \n"
40 " li $1, 0x80 # Go 64 bit \n"
41 " mtc0 $1, $12 \n"
42 " \n"
43 " # \n"
44 " # Open code a dli $1, 0x9000000080000000 \n"
45 " # \n"
46 " # Required because binutils 2.25 will happily accept \n"
47 " # 64 bit instructions in .set mips3 mode but puke on \n"
48 " # 64 bit constants when generating 32 bit ELF \n"
49 " # \n"
50 " lui $1,0x9000 \n"
51 " dsll $1,$1,0x10 \n"
52 " ori $1,$1,0x8000 \n"
53 " dsll $1,$1,0x10 \n"
54 " \n"
55 " or %0, $1 # first line to flush \n"
56 " or %1, $1 # last line to flush \n"
57 " .set at \n"
58 " \n"
59 "1: sw $0, 0(%0) \n"
60 " bne %0, %1, 1b \n"
61 " daddu %0, 32 \n"
62 " \n"
63 " mtc0 %2, $12 # Back to 32 bit \n"
64 " nop # pipeline hazard \n"
65 " nop \n"
66 " nop \n"
67 " nop \n"
68 " .set pop \n"
69 : "=r" (first), "=r" (last), "=&r" (tmp)
70 : "0" (first), "1" (last));
71}
72
73static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size)
74{
75 unsigned long first_line, last_line;
76 unsigned long flags;
77
78#ifdef DEBUG_CACHE
79 printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size);
80#endif
81
82 /* Catch bad driver code */
83 BUG_ON(size == 0);
84
85 /* Which lines to flush? */
86 first_line = SC_INDEX(addr);
87 last_line = SC_INDEX(addr + size - 1);
88
89 local_irq_save(flags);
90 if (first_line <= last_line) {
91 indy_sc_wipe(first_line, last_line);
92 goto out;
93 }
94
95 indy_sc_wipe(first_line, SC_SIZE - SC_LINE);
96 indy_sc_wipe(0, last_line);
97out:
98 local_irq_restore(flags);
99}
100
101static void indy_sc_enable(void)
102{
103 unsigned long addr, tmp1, tmp2;
104
105 /* This is really cool... */
106#ifdef DEBUG_CACHE
107 printk("Enabling R4600 SCACHE\n");
108#endif
109 __asm__ __volatile__(
110 ".set\tpush\n\t"
111 ".set\tnoreorder\n\t"
112 ".set\tmips3\n\t"
113 "mfc0\t%2, $12\n\t"
114 "nop; nop; nop; nop;\n\t"
115 "li\t%1, 0x80\n\t"
116 "mtc0\t%1, $12\n\t"
117 "nop; nop; nop; nop;\n\t"
118 "li\t%0, 0x1\n\t"
119 "dsll\t%0, 31\n\t"
120 "lui\t%1, 0x9000\n\t"
121 "dsll32\t%1, 0\n\t"
122 "or\t%0, %1, %0\n\t"
123 "sb\t$0, 0(%0)\n\t"
124 "mtc0\t$0, $12\n\t"
125 "nop; nop; nop; nop;\n\t"
126 "mtc0\t%2, $12\n\t"
127 "nop; nop; nop; nop;\n\t"
128 ".set\tpop"
129 : "=r" (tmp1), "=r" (tmp2), "=r" (addr));
130}
131
132static void indy_sc_disable(void)
133{
134 unsigned long tmp1, tmp2, tmp3;
135
136#ifdef DEBUG_CACHE
137 printk("Disabling R4600 SCACHE\n");
138#endif
139 __asm__ __volatile__(
140 ".set\tpush\n\t"
141 ".set\tnoreorder\n\t"
142 ".set\tmips3\n\t"
143 "li\t%0, 0x1\n\t"
144 "dsll\t%0, 31\n\t"
145 "lui\t%1, 0x9000\n\t"
146 "dsll32\t%1, 0\n\t"
147 "or\t%0, %1, %0\n\t"
148 "mfc0\t%2, $12\n\t"
149 "nop; nop; nop; nop\n\t"
150 "li\t%1, 0x80\n\t"
151 "mtc0\t%1, $12\n\t"
152 "nop; nop; nop; nop\n\t"
153 "sh\t$0, 0(%0)\n\t"
154 "mtc0\t$0, $12\n\t"
155 "nop; nop; nop; nop\n\t"
156 "mtc0\t%2, $12\n\t"
157 "nop; nop; nop; nop\n\t"
158 ".set\tpop"
159 : "=r" (tmp1), "=r" (tmp2), "=r" (tmp3));
160}
161
162static inline int __init indy_sc_probe(void)
163{
164 unsigned int size = ip22_eeprom_read(&sgimc->eeprom, 17);
165 if (size == 0)
166 return 0;
167
168 size <<= PAGE_SHIFT;
169 printk(KERN_INFO "R4600/R5000 SCACHE size %dK, linesize 32 bytes.\n",
170 size >> 10);
171 scache_size = size;
172
173 return 1;
174}
175
176/* XXX Check with wje if the Indy caches can differentiate between
177 writeback + invalidate and just invalidate. */
178static struct bcache_ops indy_sc_ops = {
179 .bc_enable = indy_sc_enable,
180 .bc_disable = indy_sc_disable,
181 .bc_wback_inv = indy_sc_wback_invalidate,
182 .bc_inv = indy_sc_wback_invalidate
183};
184
185void indy_sc_init(void)
186{
187 if (indy_sc_probe()) {
188 indy_sc_enable();
189 bcops = &indy_sc_ops;
190 }
191}