1/*
 2 * This file is subject to the terms and conditions of the GNU General Public
 3 * License.  See the file "COPYING" in the main directory of this archive
 4 * for more details.
 5 *
 6 * Copyright (c) 2010 Cavium Networks, Inc.
 7 */
 8
 9#include <linux/jump_label.h>
10#include <linux/kernel.h>
11#include <linux/memory.h>
12#include <linux/mutex.h>
13#include <linux/types.h>
14#include <linux/cpu.h>
15
16#include <asm/cacheflush.h>
17#include <asm/inst.h>
18
19#ifdef HAVE_JUMP_LABEL
20
21#define J_RANGE_MASK ((1ul << 28) - 1)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
22
23void arch_jump_label_transform(struct jump_entry *e,
24			       enum jump_label_type type)
25{
 
26	union mips_instruction insn;
27	union mips_instruction *insn_p =
28		(union mips_instruction *)(unsigned long)e->code;
29
30	/* Jump only works within a 256MB aligned region. */
31	BUG_ON((e->target & ~J_RANGE_MASK) != (e->code & ~J_RANGE_MASK));
32
33	/* Target must have 4 byte alignment. */
34	BUG_ON((e->target & 3) != 0);
35
36	if (type == JUMP_LABEL_ENABLE) {
37		insn.j_format.opcode = j_op;
38		insn.j_format.target = (e->target & J_RANGE_MASK) >> 2;
 
 
 
39	} else {
40		insn.word = 0; /* nop */
41	}
42
43	get_online_cpus();
44	mutex_lock(&text_mutex);
45	*insn_p = insn;
 
 
 
 
46
47	flush_icache_range((unsigned long)insn_p,
48			   (unsigned long)insn_p + sizeof(*insn_p));
49
50	mutex_unlock(&text_mutex);
51	put_online_cpus();
52}
53
54#endif /* HAVE_JUMP_LABEL */

 1/*
 2 * This file is subject to the terms and conditions of the GNU General Public
 3 * License.  See the file "COPYING" in the main directory of this archive
 4 * for more details.
 5 *
 6 * Copyright (c) 2010 Cavium Networks, Inc.
 7 */
 8
 9#include <linux/jump_label.h>
10#include <linux/kernel.h>
11#include <linux/memory.h>
12#include <linux/mutex.h>
13#include <linux/types.h>
14#include <linux/cpu.h>
15
16#include <asm/cacheflush.h>
17#include <asm/inst.h>
18
19#ifdef HAVE_JUMP_LABEL
20
21/*
22 * Define parameters for the standard MIPS and the microMIPS jump
23 * instruction encoding respectively:
24 *
25 * - the ISA bit of the target, either 0 or 1 respectively,
26 *
27 * - the amount the jump target address is shifted right to fit in the
28 *   immediate field of the machine instruction, either 2 or 1,
29 *
30 * - the mask determining the size of the jump region relative to the
31 *   delay-slot instruction, either 256MB or 128MB,
32 *
33 * - the jump target alignment, either 4 or 2 bytes.
34 */
35#define J_ISA_BIT	IS_ENABLED(CONFIG_CPU_MICROMIPS)
36#define J_RANGE_SHIFT	(2 - J_ISA_BIT)
37#define J_RANGE_MASK	((1ul << (26 + J_RANGE_SHIFT)) - 1)
38#define J_ALIGN_MASK	((1ul << J_RANGE_SHIFT) - 1)
39
40void arch_jump_label_transform(struct jump_entry *e,
41			       enum jump_label_type type)
42{
43	union mips_instruction *insn_p;
44	union mips_instruction insn;
 
 
45
46	insn_p = (union mips_instruction *)msk_isa16_mode(e->code);
 
47
48	/* Jump only works within an aligned region its delay slot is in. */
49	BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK));
50
51	/* Target must have the right alignment and ISA must be preserved. */
52	BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT);
53
54	if (type == JUMP_LABEL_JMP) {
55		insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
56		insn.j_format.target = e->target >> J_RANGE_SHIFT;
57	} else {
58		insn.word = 0; /* nop */
59	}
60
 
61	mutex_lock(&text_mutex);
62	if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) {
63		insn_p->halfword[0] = insn.word >> 16;
64		insn_p->halfword[1] = insn.word;
65	} else
66		*insn_p = insn;
67
68	flush_icache_range((unsigned long)insn_p,
69			   (unsigned long)insn_p + sizeof(*insn_p));
70
71	mutex_unlock(&text_mutex);
 
72}
73
74#endif /* HAVE_JUMP_LABEL */