1/*
  2 * Copyright 2017 IBM Corp.
  3 *
  4 * This program is free software; you can redistribute it and/or
  5 * modify it under the terms of the GNU General Public License
  6 * as published by the Free Software Foundation; either version
  7 * 2 of the License, or (at your option) any later version.
  8 */
  9
 10#ifndef _MISC_CXLLIB_H
 11#define _MISC_CXLLIB_H
 12
 13#include <linux/pci.h>
 14#include <asm/reg.h>
 15
 16/*
 17 * cxl driver exports a in-kernel 'library' API which can be called by
 18 * other drivers to help interacting with an IBM XSL.
 19 */
 20
 21/*
 22 * tells whether capi is supported on the PCIe slot where the
 23 * device is seated
 24 *
 25 * Input:
 26 *	dev: device whose slot needs to be checked
 27 *	flags: 0 for the time being
 28 */
 29bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags);
 30
 31
 32/*
 33 * Returns the configuration parameters to be used by the XSL or device
 34 *
 35 * Input:
 36 *	dev: device, used to find PHB
 37 * Output:
 38 *	struct cxllib_xsl_config:
 39 *		version
 40 *		capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF
 41 *		capi BAR size
 42 *		data send control (XSL_DSNCTL)
 43 *		dummy read address (XSL_DRA)
 44 */
 45#define CXL_XSL_CONFIG_VERSION1		1
 46struct cxllib_xsl_config {
 47	u32	version;     /* format version for register encoding */
 48	u32	log_bar_size;/* log size of the capi_window */
 49	u64	bar_addr;    /* address of the start of capi window */
 50	u64	dsnctl;      /* matches definition of XSL_DSNCTL */
 51	u64	dra;         /* real address that can be used for dummy read */
 52};
 53
 54int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg);
 55
 56
 57/*
 58 * Activate capi for the pci host bridge associated with the device.
 59 * Can be extended to deactivate once we know how to do it.
 60 * Device must be ready to accept messages from the CAPP unit and
 61 * respond accordingly (TLB invalidates, ...)
 62 *
 63 * PHB is switched to capi mode through calls to skiboot.
 64 * CAPP snooping is activated
 65 *
 66 * Input:
 67 *	dev: device whose PHB should switch mode
 68 *	mode: mode to switch to i.e. CAPI or PCI
 69 *	flags: options related to the mode
 70 */
 71enum cxllib_mode {
 72	CXL_MODE_CXL,
 73	CXL_MODE_PCI,
 74};
 75
 76#define CXL_MODE_NO_DMA       0
 77#define CXL_MODE_DMA_TVT0     1
 78#define CXL_MODE_DMA_TVT1     2
 79
 80int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
 81			unsigned long flags);
 82
 83
 84/*
 85 * Set the device for capi DMA.
 86 * Define its dma_ops and dma offset so that allocations will be using TVT#1
 87 *
 88 * Input:
 89 *	dev: device to set
 90 *	flags: options. CXL_MODE_DMA_TVT1 should be used
 91 */
 92int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags);
 93
 94
 95/*
 96 * Get the Process Element structure for the given thread
 97 *
 98 * Input:
 99 *    task: task_struct for the context of the translation
100 *    translation_mode: whether addresses should be translated
101 * Output:
102 *    attr: attributes to fill up the Process Element structure from CAIA
103 */
104struct cxllib_pe_attributes {
105	u64 sr;
106	u32 lpid;
107	u32 tid;
108	u32 pid;
109};
110#define CXL_TRANSLATED_MODE 0
111#define CXL_REAL_MODE 1
112
113int cxllib_get_PE_attributes(struct task_struct *task,
114	     unsigned long translation_mode, struct cxllib_pe_attributes *attr);
115
116
117/*
118 * Handle memory fault.
119 * Fault in all the pages of the specified buffer for the permissions
120 * provided in ‘flags’
121 *
122 * Shouldn't be called from interrupt context
123 *
124 * Input:
125 *	mm: struct mm for the thread faulting the pages
126 *	addr: base address of the buffer to page in
127 *	size: size of the buffer to page in
128 *	flags: permission requested (DSISR_ISSTORE...)
129 */
130int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags);
131
132
133#endif /* _MISC_CXLLIB_H */