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1/*
2 * Renesas USB driver
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
15 *
16 */
17#ifndef RENESAS_USB_DRIVER_H
18#define RENESAS_USB_DRIVER_H
19
20#include <linux/platform_device.h>
21#include <linux/usb/renesas_usbhs.h>
22
23struct usbhs_priv;
24
25#include "./mod.h"
26#include "./pipe.h"
27
28/*
29 *
30 * register define
31 *
32 */
33#define SYSCFG 0x0000
34#define BUSWAIT 0x0002
35#define DVSTCTR 0x0008
36#define CFIFO 0x0014
37#define CFIFOSEL 0x0020
38#define CFIFOCTR 0x0022
39#define D0FIFO 0x0100
40#define D0FIFOSEL 0x0028
41#define D0FIFOCTR 0x002A
42#define D1FIFO 0x0120
43#define D1FIFOSEL 0x002C
44#define D1FIFOCTR 0x002E
45#define INTENB0 0x0030
46#define INTENB1 0x0032
47#define BRDYENB 0x0036
48#define NRDYENB 0x0038
49#define BEMPENB 0x003A
50#define INTSTS0 0x0040
51#define INTSTS1 0x0042
52#define BRDYSTS 0x0046
53#define NRDYSTS 0x0048
54#define BEMPSTS 0x004A
55#define FRMNUM 0x004C
56#define USBREQ 0x0054 /* USB request type register */
57#define USBVAL 0x0056 /* USB request value register */
58#define USBINDX 0x0058 /* USB request index register */
59#define USBLENG 0x005A /* USB request length register */
60#define DCPCFG 0x005C
61#define DCPMAXP 0x005E
62#define DCPCTR 0x0060
63#define PIPESEL 0x0064
64#define PIPECFG 0x0068
65#define PIPEBUF 0x006A
66#define PIPEMAXP 0x006C
67#define PIPEPERI 0x006E
68#define PIPEnCTR 0x0070
69#define PIPE1TRE 0x0090
70#define PIPE1TRN 0x0092
71#define PIPE2TRE 0x0094
72#define PIPE2TRN 0x0096
73#define PIPE3TRE 0x0098
74#define PIPE3TRN 0x009A
75#define PIPE4TRE 0x009C
76#define PIPE4TRN 0x009E
77#define PIPE5TRE 0x00A0
78#define PIPE5TRN 0x00A2
79#define PIPEBTRE 0x00A4
80#define PIPEBTRN 0x00A6
81#define PIPECTRE 0x00A8
82#define PIPECTRN 0x00AA
83#define PIPEDTRE 0x00AC
84#define PIPEDTRN 0x00AE
85#define PIPEETRE 0x00B0
86#define PIPEETRN 0x00B2
87#define PIPEFTRE 0x00B4
88#define PIPEFTRN 0x00B6
89#define PIPE9TRE 0x00B8
90#define PIPE9TRN 0x00BA
91#define PIPEATRE 0x00BC
92#define PIPEATRN 0x00BE
93
94/* SYSCFG */
95#define SCKE (1 << 10) /* USB Module Clock Enable */
96#define HSE (1 << 7) /* High-Speed Operation Enable */
97#define DCFM (1 << 6) /* Controller Function Select */
98#define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
99#define DPRPU (1 << 4) /* D+ Line Resistance Control */
100#define USBE (1 << 0) /* USB Module Operation Enable */
101
102/* DVSTCTR */
103#define EXTLP (1 << 10) /* Controls the EXTLP pin output state */
104#define PWEN (1 << 9) /* Controls the PWEN pin output state */
105#define RHST (0x7) /* Reset Handshake */
106#define RHST_LOW_SPEED 1 /* Low-speed connection */
107#define RHST_FULL_SPEED 2 /* Full-speed connection */
108#define RHST_HIGH_SPEED 3 /* High-speed connection */
109
110/* CFIFOSEL */
111#define DREQE (1 << 12) /* DMA Transfer Request Enable */
112#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */
113
114/* CFIFOCTR */
115#define BVAL (1 << 15) /* Buffer Memory Enable Flag */
116#define BCLR (1 << 14) /* CPU buffer clear */
117#define FRDY (1 << 13) /* FIFO Port Ready */
118#define DTLN_MASK (0x0FFF) /* Receive Data Length */
119
120/* INTENB0 */
121#define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */
122#define RSME (1 << 14) /* Enable IRQ Resume */
123#define SOFE (1 << 13) /* Enable IRQ Frame Number Update */
124#define DVSE (1 << 12) /* Enable IRQ Device State Transition */
125#define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
126#define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */
127#define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */
128#define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */
129
130/* INTENB1 */
131#define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */
132#define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */
133#define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */
134#define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */
135#define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */
136#define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */
137
138/* INTSTS0 */
139#define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */
140#define DVST (1 << 12) /* Device State Transition Interrupt Status */
141#define CTRT (1 << 11) /* Control Stage Interrupt Status */
142#define BEMP (1 << 10) /* Buffer Empty Interrupt Status */
143#define BRDY (1 << 8) /* Buffer Ready Interrupt Status */
144#define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */
145#define VALID (1 << 3) /* USB Request Receive */
146
147#define DVSQ_MASK (0x3 << 4) /* Device State */
148#define POWER_STATE (0 << 4)
149#define DEFAULT_STATE (1 << 4)
150#define ADDRESS_STATE (2 << 4)
151#define CONFIGURATION_STATE (3 << 4)
152
153#define CTSQ_MASK (0x7) /* Control Transfer Stage */
154#define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
155#define READ_DATA_STAGE 1 /* Control read data stage */
156#define READ_STATUS_STAGE 2 /* Control read status stage */
157#define WRITE_DATA_STAGE 3 /* Control write data stage */
158#define WRITE_STATUS_STAGE 4 /* Control write status stage */
159#define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
160#define SEQUENCE_ERROR 6 /* Control transfer sequence error */
161
162/* PIPECFG */
163/* DCPCFG */
164#define TYPE_NONE (0 << 14) /* Transfer Type */
165#define TYPE_BULK (1 << 14)
166#define TYPE_INT (2 << 14)
167#define TYPE_ISO (3 << 14)
168#define DBLB (1 << 9) /* Double Buffer Mode */
169#define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */
170#define DIR_OUT (1 << 4) /* Transfer Direction */
171
172/* PIPEMAXP */
173/* DCPMAXP */
174#define DEVSEL_MASK (0xF << 12) /* Device Select */
175#define DCP_MAXP_MASK (0x7F)
176#define PIPE_MAXP_MASK (0x7FF)
177
178/* PIPEBUF */
179#define BUFSIZE_SHIFT 10
180#define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT)
181#define BUFNMB_MASK (0xFF)
182
183/* PIPEnCTR */
184/* DCPCTR */
185#define BSTS (1 << 15) /* Buffer Status */
186#define CSSTS (1 << 12) /* CSSTS Status */
187#define SQCLR (1 << 8) /* Toggle Bit Clear */
188#define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */
189#define PBUSY (1 << 5) /* Pipe Busy */
190#define PID_MASK (0x3) /* Response PID */
191#define PID_NAK 0
192#define PID_BUF 1
193#define PID_STALL10 2
194#define PID_STALL11 3
195
196#define CCPL (1 << 2) /* Control Transfer End Enable */
197
198/* PIPEnTRE */
199#define TRENB (1 << 9) /* Transaction Counter Enable */
200#define TRCLR (1 << 8) /* Transaction Counter Clear */
201
202/* FRMNUM */
203#define FRNM_MASK (0x7FF)
204
205/*
206 * struct
207 */
208struct usbhs_priv {
209
210 void __iomem *base;
211 unsigned int irq;
212
213 struct renesas_usbhs_platform_callback *pfunc;
214 struct renesas_usbhs_driver_param *dparam;
215
216 struct delayed_work notify_hotplug_work;
217 struct platform_device *pdev;
218
219 spinlock_t lock;
220
221 u32 flags;
222
223 /*
224 * module control
225 */
226 struct usbhs_mod_info mod_info;
227
228 /*
229 * pipe control
230 */
231 struct usbhs_pipe_info pipe_info;
232
233 /*
234 * fifo control
235 */
236 struct usbhs_fifo_info fifo_info;
237};
238
239/*
240 * common
241 */
242u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
243void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
244void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
245
246int usbhsc_drvcllbck_notify_hotplug(struct platform_device *pdev);
247
248#define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
249#define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
250
251/*
252 * sysconfig
253 */
254void usbhs_sys_clock_ctrl(struct usbhs_priv *priv, int enable);
255void usbhs_sys_hispeed_ctrl(struct usbhs_priv *priv, int enable);
256void usbhs_sys_usb_ctrl(struct usbhs_priv *priv, int enable);
257void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
258void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
259
260/*
261 * frame
262 */
263int usbhs_frame_get_num(struct usbhs_priv *priv);
264
265/*
266 * data
267 */
268struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
269#define usbhs_get_dparam(priv, param) (priv->dparam->param)
270#define usbhs_priv_to_pdev(priv) (priv->pdev)
271#define usbhs_priv_to_dev(priv) (&priv->pdev->dev)
272#define usbhs_priv_to_lock(priv) (&priv->lock)
273
274#endif /* RENESAS_USB_DRIVER_H */
1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Renesas USB driver
4 *
5 * Copyright (C) 2011 Renesas Solutions Corp.
6 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 */
8#ifndef RENESAS_USB_DRIVER_H
9#define RENESAS_USB_DRIVER_H
10
11#include <linux/extcon.h>
12#include <linux/platform_device.h>
13#include <linux/usb/renesas_usbhs.h>
14
15struct usbhs_priv;
16
17#include "mod.h"
18#include "pipe.h"
19
20/*
21 *
22 * register define
23 *
24 */
25#define SYSCFG 0x0000
26#define BUSWAIT 0x0002
27#define DVSTCTR 0x0008
28#define TESTMODE 0x000C
29#define CFIFO 0x0014
30#define CFIFOSEL 0x0020
31#define CFIFOCTR 0x0022
32#define D0FIFO 0x0100
33#define D0FIFOSEL 0x0028
34#define D0FIFOCTR 0x002A
35#define D1FIFO 0x0120
36#define D1FIFOSEL 0x002C
37#define D1FIFOCTR 0x002E
38#define INTENB0 0x0030
39#define INTENB1 0x0032
40#define BRDYENB 0x0036
41#define NRDYENB 0x0038
42#define BEMPENB 0x003A
43#define INTSTS0 0x0040
44#define INTSTS1 0x0042
45#define BRDYSTS 0x0046
46#define NRDYSTS 0x0048
47#define BEMPSTS 0x004A
48#define FRMNUM 0x004C
49#define USBREQ 0x0054 /* USB request type register */
50#define USBVAL 0x0056 /* USB request value register */
51#define USBINDX 0x0058 /* USB request index register */
52#define USBLENG 0x005A /* USB request length register */
53#define DCPCFG 0x005C
54#define DCPMAXP 0x005E
55#define DCPCTR 0x0060
56#define PIPESEL 0x0064
57#define PIPECFG 0x0068
58#define PIPEBUF 0x006A
59#define PIPEMAXP 0x006C
60#define PIPEPERI 0x006E
61#define PIPEnCTR 0x0070
62#define PIPE1TRE 0x0090
63#define PIPE1TRN 0x0092
64#define PIPE2TRE 0x0094
65#define PIPE2TRN 0x0096
66#define PIPE3TRE 0x0098
67#define PIPE3TRN 0x009A
68#define PIPE4TRE 0x009C
69#define PIPE4TRN 0x009E
70#define PIPE5TRE 0x00A0
71#define PIPE5TRN 0x00A2
72#define PIPEBTRE 0x00A4
73#define PIPEBTRN 0x00A6
74#define PIPECTRE 0x00A8
75#define PIPECTRN 0x00AA
76#define PIPEDTRE 0x00AC
77#define PIPEDTRN 0x00AE
78#define PIPEETRE 0x00B0
79#define PIPEETRN 0x00B2
80#define PIPEFTRE 0x00B4
81#define PIPEFTRN 0x00B6
82#define PIPE9TRE 0x00B8
83#define PIPE9TRN 0x00BA
84#define PIPEATRE 0x00BC
85#define PIPEATRN 0x00BE
86#define DEVADD0 0x00D0 /* Device address n configuration */
87#define DEVADD1 0x00D2
88#define DEVADD2 0x00D4
89#define DEVADD3 0x00D6
90#define DEVADD4 0x00D8
91#define DEVADD5 0x00DA
92#define DEVADD6 0x00DC
93#define DEVADD7 0x00DE
94#define DEVADD8 0x00E0
95#define DEVADD9 0x00E2
96#define DEVADDA 0x00E4
97#define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
98#define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
99#define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
100#define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
101#define SUSPMODE 0x0102 /* for RZ/A */
102
103/* SYSCFG */
104#define SCKE (1 << 10) /* USB Module Clock Enable */
105#define HSE (1 << 7) /* High-Speed Operation Enable */
106#define DCFM (1 << 6) /* Controller Function Select */
107#define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
108#define DPRPU (1 << 4) /* D+ Line Resistance Control */
109#define USBE (1 << 0) /* USB Module Operation Enable */
110#define UCKSEL (1 << 2) /* Clock Select for RZ/A1 */
111#define UPLLE (1 << 1) /* USB PLL Enable for RZ/A1 */
112
113/* DVSTCTR */
114#define EXTLP (1 << 10) /* Controls the EXTLP pin output state */
115#define PWEN (1 << 9) /* Controls the PWEN pin output state */
116#define USBRST (1 << 6) /* Bus Reset Output */
117#define UACT (1 << 4) /* USB Bus Enable */
118#define RHST (0x7) /* Reset Handshake */
119#define RHST_LOW_SPEED 1 /* Low-speed connection */
120#define RHST_FULL_SPEED 2 /* Full-speed connection */
121#define RHST_HIGH_SPEED 3 /* High-speed connection */
122
123/* CFIFOSEL */
124#define DREQE (1 << 12) /* DMA Transfer Request Enable */
125#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */
126
127/* CFIFOCTR */
128#define BVAL (1 << 15) /* Buffer Memory Enable Flag */
129#define BCLR (1 << 14) /* CPU buffer clear */
130#define FRDY (1 << 13) /* FIFO Port Ready */
131#define DTLN_MASK (0x0FFF) /* Receive Data Length */
132
133/* INTENB0 */
134#define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */
135#define RSME (1 << 14) /* Enable IRQ Resume */
136#define SOFE (1 << 13) /* Enable IRQ Frame Number Update */
137#define DVSE (1 << 12) /* Enable IRQ Device State Transition */
138#define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
139#define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */
140#define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */
141#define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */
142
143/* INTENB1 */
144#define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */
145#define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */
146#define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */
147#define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */
148#define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */
149#define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */
150
151/* INTSTS0 */
152#define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */
153#define DVST (1 << 12) /* Device State Transition Interrupt Status */
154#define CTRT (1 << 11) /* Control Stage Interrupt Status */
155#define BEMP (1 << 10) /* Buffer Empty Interrupt Status */
156#define BRDY (1 << 8) /* Buffer Ready Interrupt Status */
157#define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */
158#define VALID (1 << 3) /* USB Request Receive */
159
160#define DVSQ_MASK (0x3 << 4) /* Device State */
161#define POWER_STATE (0 << 4)
162#define DEFAULT_STATE (1 << 4)
163#define ADDRESS_STATE (2 << 4)
164#define CONFIGURATION_STATE (3 << 4)
165
166#define CTSQ_MASK (0x7) /* Control Transfer Stage */
167#define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
168#define READ_DATA_STAGE 1 /* Control read data stage */
169#define READ_STATUS_STAGE 2 /* Control read status stage */
170#define WRITE_DATA_STAGE 3 /* Control write data stage */
171#define WRITE_STATUS_STAGE 4 /* Control write status stage */
172#define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
173#define SEQUENCE_ERROR 6 /* Control transfer sequence error */
174
175/* INTSTS1 */
176#define OVRCR (1 << 15) /* OVRCR Interrupt Status */
177#define BCHG (1 << 14) /* USB Bus Change Interrupt Status */
178#define DTCH (1 << 12) /* USB Disconnection Detect Interrupt Status */
179#define ATTCH (1 << 11) /* ATTCH Interrupt Status */
180#define EOFERR (1 << 6) /* EOF Error Detect Interrupt Status */
181#define SIGN (1 << 5) /* Setup Transaction Error Interrupt Status */
182#define SACK (1 << 4) /* Setup Transaction ACK Response Interrupt Status */
183
184/* PIPECFG */
185/* DCPCFG */
186#define TYPE_NONE (0 << 14) /* Transfer Type */
187#define TYPE_BULK (1 << 14)
188#define TYPE_INT (2 << 14)
189#define TYPE_ISO (3 << 14)
190#define BFRE (1 << 10) /* BRDY Interrupt Operation Spec. */
191#define DBLB (1 << 9) /* Double Buffer Mode */
192#define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */
193#define DIR_OUT (1 << 4) /* Transfer Direction */
194
195/* PIPEMAXP */
196/* DCPMAXP */
197#define DEVSEL_MASK (0xF << 12) /* Device Select */
198#define DCP_MAXP_MASK (0x7F)
199#define PIPE_MAXP_MASK (0x7FF)
200
201/* PIPEBUF */
202#define BUFSIZE_SHIFT 10
203#define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT)
204#define BUFNMB_MASK (0xFF)
205
206/* PIPEnCTR */
207/* DCPCTR */
208#define BSTS (1 << 15) /* Buffer Status */
209#define SUREQ (1 << 14) /* Sending SETUP Token */
210#define CSSTS (1 << 12) /* CSSTS Status */
211#define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */
212#define SQCLR (1 << 8) /* Toggle Bit Clear */
213#define SQSET (1 << 7) /* Toggle Bit Set */
214#define SQMON (1 << 6) /* Toggle Bit Check */
215#define PBUSY (1 << 5) /* Pipe Busy */
216#define PID_MASK (0x3) /* Response PID */
217#define PID_NAK 0
218#define PID_BUF 1
219#define PID_STALL10 2
220#define PID_STALL11 3
221
222#define CCPL (1 << 2) /* Control Transfer End Enable */
223
224/* PIPEnTRE */
225#define TRENB (1 << 9) /* Transaction Counter Enable */
226#define TRCLR (1 << 8) /* Transaction Counter Clear */
227
228/* FRMNUM */
229#define FRNM_MASK (0x7FF)
230
231/* DEVADDn */
232#define UPPHUB(x) (((x) & 0xF) << 11) /* HUB Register */
233#define HUBPORT(x) (((x) & 0x7) << 8) /* HUB Port for Target Device */
234#define USBSPD(x) (((x) & 0x3) << 6) /* Device Transfer Rate */
235#define USBSPD_SPEED_LOW 0x1
236#define USBSPD_SPEED_FULL 0x2
237#define USBSPD_SPEED_HIGH 0x3
238
239/* SUSPMODE */
240#define SUSPM (1 << 14) /* SuspendM Control */
241
242/*
243 * struct
244 */
245struct usbhs_priv {
246
247 void __iomem *base;
248 unsigned int irq;
249 unsigned long irqflags;
250
251 struct renesas_usbhs_platform_callback pfunc;
252 struct renesas_usbhs_driver_param dparam;
253
254 struct delayed_work notify_hotplug_work;
255 struct platform_device *pdev;
256
257 struct extcon_dev *edev;
258 struct notifier_block nb;
259
260 spinlock_t lock;
261
262 u32 flags;
263
264 /*
265 * module control
266 */
267 struct usbhs_mod_info mod_info;
268
269 /*
270 * pipe control
271 */
272 struct usbhs_pipe_info pipe_info;
273
274 /*
275 * fifo control
276 */
277 struct usbhs_fifo_info fifo_info;
278
279 struct usb_phy *usb_phy;
280 struct phy *phy;
281};
282
283/*
284 * common
285 */
286u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
287void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
288void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
289
290#define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
291#define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
292
293/*
294 * sysconfig
295 */
296void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
297void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
298void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
299void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode);
300
301/*
302 * usb request
303 */
304void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
305void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
306
307/*
308 * bus
309 */
310void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
311void usbhs_bus_send_reset(struct usbhs_priv *priv);
312int usbhs_bus_get_speed(struct usbhs_priv *priv);
313int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
314
315/*
316 * frame
317 */
318int usbhs_frame_get_num(struct usbhs_priv *priv);
319
320/*
321 * device config
322 */
323int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub,
324 u16 hubport, u16 speed);
325
326/*
327 * interrupt functions
328 */
329void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit);
330
331/*
332 * data
333 */
334struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
335#define usbhs_get_dparam(priv, param) (priv->dparam.param)
336#define usbhs_priv_to_pdev(priv) (priv->pdev)
337#define usbhs_priv_to_dev(priv) (&priv->pdev->dev)
338#define usbhs_priv_to_lock(priv) (&priv->lock)
339
340#endif /* RENESAS_USB_DRIVER_H */