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1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
58#define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
59
60/****** Kernel includes ******/
61
62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
75#include <linux/serial.h>
76#include <linux/string.h>
77#include <linux/fcntl.h>
78#include <linux/ptrace.h>
79#include <linux/mutex.h>
80#include <linux/ioport.h>
81#include <linux/delay.h>
82#include <linux/completion.h>
83#include <linux/wait.h>
84#include <linux/pci.h>
85#include <linux/uaccess.h>
86#include <linux/atomic.h>
87#include <asm/unaligned.h>
88#include <linux/bitops.h>
89#include <linux/spinlock.h>
90#include <linux/init.h>
91
92/****** RocketPort includes ******/
93
94#include "rocket_int.h"
95#include "rocket.h"
96
97#define ROCKET_VERSION "2.09"
98#define ROCKET_DATE "12-June-2003"
99
100/****** RocketPort Local Variables ******/
101
102static void rp_do_poll(unsigned long dummy);
103
104static struct tty_driver *rocket_driver;
105
106static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108};
109
110static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113static atomic_t rp_num_ports_open; /* Number of serial ports open */
114static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
115
116static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117static unsigned long board2;
118static unsigned long board3;
119static unsigned long board4;
120static unsigned long controller;
121static int support_low_speed;
122static unsigned long modem1;
123static unsigned long modem2;
124static unsigned long modem3;
125static unsigned long modem4;
126static unsigned long pc104_1[8];
127static unsigned long pc104_2[8];
128static unsigned long pc104_3[8];
129static unsigned long pc104_4[8];
130static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133static unsigned long rcktpt_io_addr[NUM_BOARDS];
134static int rcktpt_type[NUM_BOARDS];
135static int is_PCI[NUM_BOARDS];
136static rocketModel_t rocketModel[NUM_BOARDS];
137static int max_board;
138static const struct tty_port_operations rocket_port_ops;
139
140/*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151};
152
153static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
154 UPCI_AIOP_INTR_BIT_0,
155 UPCI_AIOP_INTR_BIT_1,
156 UPCI_AIOP_INTR_BIT_2,
157 UPCI_AIOP_INTR_BIT_3
158};
159
160static Byte_t RData[RDATASIZE] = {
161 0x00, 0x09, 0xf6, 0x82,
162 0x02, 0x09, 0x86, 0xfb,
163 0x04, 0x09, 0x00, 0x0a,
164 0x06, 0x09, 0x01, 0x0a,
165 0x08, 0x09, 0x8a, 0x13,
166 0x0a, 0x09, 0xc5, 0x11,
167 0x0c, 0x09, 0x86, 0x85,
168 0x0e, 0x09, 0x20, 0x0a,
169 0x10, 0x09, 0x21, 0x0a,
170 0x12, 0x09, 0x41, 0xff,
171 0x14, 0x09, 0x82, 0x00,
172 0x16, 0x09, 0x82, 0x7b,
173 0x18, 0x09, 0x8a, 0x7d,
174 0x1a, 0x09, 0x88, 0x81,
175 0x1c, 0x09, 0x86, 0x7a,
176 0x1e, 0x09, 0x84, 0x81,
177 0x20, 0x09, 0x82, 0x7c,
178 0x22, 0x09, 0x0a, 0x0a
179};
180
181static Byte_t RRegData[RREGDATASIZE] = {
182 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
183 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
184 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
185 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
186 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
187 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
188 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
189 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
190 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
191 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
192 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
193 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
194 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
195};
196
197static CONTROLLER_T sController[CTL_SIZE] = {
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
206};
207
208static Byte_t sBitMapClrTbl[8] = {
209 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
210};
211
212static Byte_t sBitMapSetTbl[8] = {
213 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
214};
215
216static int sClockPrescale = 0x14;
217
218/*
219 * Line number is the ttySIx number (x), the Minor number. We
220 * assign them sequentially, starting at zero. The following
221 * array keeps track of the line number assigned to a given board/aiop/channel.
222 */
223static unsigned char lineNumbers[MAX_RP_PORTS];
224static unsigned long nextLineNumber;
225
226/***** RocketPort Static Prototypes *********/
227static int __init init_ISA(int i);
228static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
229static void rp_flush_buffer(struct tty_struct *tty);
230static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
231static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
232static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
233static void rp_start(struct tty_struct *tty);
234static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
235 int ChanNum);
236static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237static void sFlushRxFIFO(CHANNEL_T * ChP);
238static void sFlushTxFIFO(CHANNEL_T * ChP);
239static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
241static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
242static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
243static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
244static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
245 ByteIO_t * AiopIOList, int AiopIOListSize,
246 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
247 int PeriodicOnly, int altChanRingIndicator,
248 int UPCIRingInd);
249static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
250 ByteIO_t * AiopIOList, int AiopIOListSize,
251 int IRQNum, Byte_t Frequency, int PeriodicOnly);
252static int sReadAiopID(ByteIO_t io);
253static int sReadAiopNumChan(WordIO_t io);
254
255MODULE_AUTHOR("Theodore Ts'o");
256MODULE_DESCRIPTION("Comtrol RocketPort driver");
257module_param(board1, ulong, 0);
258MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
259module_param(board2, ulong, 0);
260MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
261module_param(board3, ulong, 0);
262MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
263module_param(board4, ulong, 0);
264MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
265module_param(controller, ulong, 0);
266MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
267module_param(support_low_speed, bool, 0);
268MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
269module_param(modem1, ulong, 0);
270MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
271module_param(modem2, ulong, 0);
272MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
273module_param(modem3, ulong, 0);
274MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
275module_param(modem4, ulong, 0);
276MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
277module_param_array(pc104_1, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
279module_param_array(pc104_2, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
281module_param_array(pc104_3, ulong, NULL, 0);
282MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
283module_param_array(pc104_4, ulong, NULL, 0);
284MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
285
286static int rp_init(void);
287static void rp_cleanup_module(void);
288
289module_init(rp_init);
290module_exit(rp_cleanup_module);
291
292
293MODULE_LICENSE("Dual BSD/GPL");
294
295/*************************************************************************/
296/* Module code starts here */
297
298static inline int rocket_paranoia_check(struct r_port *info,
299 const char *routine)
300{
301#ifdef ROCKET_PARANOIA_CHECK
302 if (!info)
303 return 1;
304 if (info->magic != RPORT_MAGIC) {
305 printk(KERN_WARNING "Warning: bad magic number for rocketport "
306 "struct in %s\n", routine);
307 return 1;
308 }
309#endif
310 return 0;
311}
312
313
314/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
315 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
316 * tty layer.
317 */
318static void rp_do_receive(struct r_port *info,
319 struct tty_struct *tty,
320 CHANNEL_t * cp, unsigned int ChanStatus)
321{
322 unsigned int CharNStat;
323 int ToRecv, wRecv, space;
324 unsigned char *cbuf;
325
326 ToRecv = sGetRxCnt(cp);
327#ifdef ROCKET_DEBUG_INTR
328 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
329#endif
330 if (ToRecv == 0)
331 return;
332
333 /*
334 * if status indicates there are errored characters in the
335 * FIFO, then enter status mode (a word in FIFO holds
336 * character and status).
337 */
338 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
339 if (!(ChanStatus & STATMODE)) {
340#ifdef ROCKET_DEBUG_RECEIVE
341 printk(KERN_INFO "Entering STATMODE...\n");
342#endif
343 ChanStatus |= STATMODE;
344 sEnRxStatusMode(cp);
345 }
346 }
347
348 /*
349 * if we previously entered status mode, then read down the
350 * FIFO one word at a time, pulling apart the character and
351 * the status. Update error counters depending on status
352 */
353 if (ChanStatus & STATMODE) {
354#ifdef ROCKET_DEBUG_RECEIVE
355 printk(KERN_INFO "Ignore %x, read %x...\n",
356 info->ignore_status_mask, info->read_status_mask);
357#endif
358 while (ToRecv) {
359 char flag;
360
361 CharNStat = sInW(sGetTxRxDataIO(cp));
362#ifdef ROCKET_DEBUG_RECEIVE
363 printk(KERN_INFO "%x...\n", CharNStat);
364#endif
365 if (CharNStat & STMBREAKH)
366 CharNStat &= ~(STMFRAMEH | STMPARITYH);
367 if (CharNStat & info->ignore_status_mask) {
368 ToRecv--;
369 continue;
370 }
371 CharNStat &= info->read_status_mask;
372 if (CharNStat & STMBREAKH)
373 flag = TTY_BREAK;
374 else if (CharNStat & STMPARITYH)
375 flag = TTY_PARITY;
376 else if (CharNStat & STMFRAMEH)
377 flag = TTY_FRAME;
378 else if (CharNStat & STMRCVROVRH)
379 flag = TTY_OVERRUN;
380 else
381 flag = TTY_NORMAL;
382 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
383 ToRecv--;
384 }
385
386 /*
387 * after we've emptied the FIFO in status mode, turn
388 * status mode back off
389 */
390 if (sGetRxCnt(cp) == 0) {
391#ifdef ROCKET_DEBUG_RECEIVE
392 printk(KERN_INFO "Status mode off.\n");
393#endif
394 sDisRxStatusMode(cp);
395 }
396 } else {
397 /*
398 * we aren't in status mode, so read down the FIFO two
399 * characters at time by doing repeated word IO
400 * transfer.
401 */
402 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
403 if (space < ToRecv) {
404#ifdef ROCKET_DEBUG_RECEIVE
405 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
406#endif
407 if (space <= 0)
408 return;
409 ToRecv = space;
410 }
411 wRecv = ToRecv >> 1;
412 if (wRecv)
413 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
414 if (ToRecv & 1)
415 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
416 }
417 /* Push the data up to the tty layer */
418 tty_flip_buffer_push(tty);
419}
420
421/*
422 * Serial port transmit data function. Called from the timer polling loop as a
423 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
424 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
425 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
426 */
427static void rp_do_transmit(struct r_port *info)
428{
429 int c;
430 CHANNEL_t *cp = &info->channel;
431 struct tty_struct *tty;
432 unsigned long flags;
433
434#ifdef ROCKET_DEBUG_INTR
435 printk(KERN_DEBUG "%s\n", __func__);
436#endif
437 if (!info)
438 return;
439 tty = tty_port_tty_get(&info->port);
440
441 if (tty == NULL) {
442 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
444 return;
445 }
446
447 spin_lock_irqsave(&info->slock, flags);
448 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
449
450 /* Loop sending data to FIFO until done or FIFO full */
451 while (1) {
452 if (tty->stopped || tty->hw_stopped)
453 break;
454 c = min(info->xmit_fifo_room, info->xmit_cnt);
455 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
456 if (c <= 0 || info->xmit_fifo_room <= 0)
457 break;
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
459 if (c & 1)
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
463 info->xmit_cnt -= c;
464 info->xmit_fifo_room -= c;
465#ifdef ROCKET_DEBUG_INTR
466 printk(KERN_INFO "tx %d chars...\n", c);
467#endif
468 }
469
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
472
473 if (info->xmit_cnt < WAKEUP_CHARS) {
474 tty_wakeup(tty);
475#ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
477#endif
478 }
479
480 spin_unlock_irqrestore(&info->slock, flags);
481 tty_kref_put(tty);
482
483#ifdef ROCKET_DEBUG_INTR
484 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
485 info->xmit_tail, info->xmit_fifo_room);
486#endif
487}
488
489/*
490 * Called when a serial port signals it has read data in it's RX FIFO.
491 * It checks what interrupts are pending and services them, including
492 * receiving serial data.
493 */
494static void rp_handle_port(struct r_port *info)
495{
496 CHANNEL_t *cp;
497 struct tty_struct *tty;
498 unsigned int IntMask, ChanStatus;
499
500 if (!info)
501 return;
502
503 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
504 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
505 "info->flags & NOT_INIT\n");
506 return;
507 }
508 tty = tty_port_tty_get(&info->port);
509 if (!tty) {
510 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
511 "tty==NULL\n");
512 return;
513 }
514 cp = &info->channel;
515
516 IntMask = sGetChanIntID(cp) & info->intmask;
517#ifdef ROCKET_DEBUG_INTR
518 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
519#endif
520 ChanStatus = sGetChanStatus(cp);
521 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
522 rp_do_receive(info, tty, cp, ChanStatus);
523 }
524 if (IntMask & DELTA_CD) { /* CD change */
525#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
526 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
527 (ChanStatus & CD_ACT) ? "on" : "off");
528#endif
529 if (!(ChanStatus & CD_ACT) && info->cd_status) {
530#ifdef ROCKET_DEBUG_HANGUP
531 printk(KERN_INFO "CD drop, calling hangup.\n");
532#endif
533 tty_hangup(tty);
534 }
535 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
536 wake_up_interruptible(&info->port.open_wait);
537 }
538#ifdef ROCKET_DEBUG_INTR
539 if (IntMask & DELTA_CTS) { /* CTS change */
540 printk(KERN_INFO "CTS change...\n");
541 }
542 if (IntMask & DELTA_DSR) { /* DSR change */
543 printk(KERN_INFO "DSR change...\n");
544 }
545#endif
546 tty_kref_put(tty);
547}
548
549/*
550 * The top level polling routine. Repeats every 1/100 HZ (10ms).
551 */
552static void rp_do_poll(unsigned long dummy)
553{
554 CONTROLLER_t *ctlp;
555 int ctrl, aiop, ch, line;
556 unsigned int xmitmask, i;
557 unsigned int CtlMask;
558 unsigned char AiopMask;
559 Word_t bit;
560
561 /* Walk through all the boards (ctrl's) */
562 for (ctrl = 0; ctrl < max_board; ctrl++) {
563 if (rcktpt_io_addr[ctrl] <= 0)
564 continue;
565
566 /* Get a ptr to the board's control struct */
567 ctlp = sCtlNumToCtlPtr(ctrl);
568
569 /* Get the interrupt status from the board */
570#ifdef CONFIG_PCI
571 if (ctlp->BusType == isPCI)
572 CtlMask = sPCIGetControllerIntStatus(ctlp);
573 else
574#endif
575 CtlMask = sGetControllerIntStatus(ctlp);
576
577 /* Check if any AIOP read bits are set */
578 for (aiop = 0; CtlMask; aiop++) {
579 bit = ctlp->AiopIntrBits[aiop];
580 if (CtlMask & bit) {
581 CtlMask &= ~bit;
582 AiopMask = sGetAiopIntStatus(ctlp, aiop);
583
584 /* Check if any port read bits are set */
585 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
586 if (AiopMask & 1) {
587
588 /* Get the line number (/dev/ttyRx number). */
589 /* Read the data from the port. */
590 line = GetLineNumber(ctrl, aiop, ch);
591 rp_handle_port(rp_table[line]);
592 }
593 }
594 }
595 }
596
597 xmitmask = xmit_flags[ctrl];
598
599 /*
600 * xmit_flags contains bit-significant flags, indicating there is data
601 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
602 * 1, ... (32 total possible). The variable i has the aiop and ch
603 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
604 */
605 if (xmitmask) {
606 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
607 if (xmitmask & (1 << i)) {
608 aiop = (i & 0x18) >> 3;
609 ch = i & 0x07;
610 line = GetLineNumber(ctrl, aiop, ch);
611 rp_do_transmit(rp_table[line]);
612 }
613 }
614 }
615 }
616
617 /*
618 * Reset the timer so we get called at the next clock tick (10ms).
619 */
620 if (atomic_read(&rp_num_ports_open))
621 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
622}
623
624/*
625 * Initializes the r_port structure for a port, as well as enabling the port on
626 * the board.
627 * Inputs: board, aiop, chan numbers
628 */
629static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
630{
631 unsigned rocketMode;
632 struct r_port *info;
633 int line;
634 CONTROLLER_T *ctlp;
635
636 /* Get the next available line number */
637 line = SetLineNumber(board, aiop, chan);
638
639 ctlp = sCtlNumToCtlPtr(board);
640
641 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
642 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
643 if (!info) {
644 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
645 line);
646 return;
647 }
648
649 info->magic = RPORT_MAGIC;
650 info->line = line;
651 info->ctlp = ctlp;
652 info->board = board;
653 info->aiop = aiop;
654 info->chan = chan;
655 tty_port_init(&info->port);
656 info->port.ops = &rocket_port_ops;
657 init_completion(&info->close_wait);
658 info->flags &= ~ROCKET_MODE_MASK;
659 switch (pc104[board][line]) {
660 case 422:
661 info->flags |= ROCKET_MODE_RS422;
662 break;
663 case 485:
664 info->flags |= ROCKET_MODE_RS485;
665 break;
666 case 232:
667 default:
668 info->flags |= ROCKET_MODE_RS232;
669 break;
670 }
671
672 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
673 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
674 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
675 board, aiop, chan);
676 kfree(info);
677 return;
678 }
679
680 rocketMode = info->flags & ROCKET_MODE_MASK;
681
682 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
683 sEnRTSToggle(&info->channel);
684 else
685 sDisRTSToggle(&info->channel);
686
687 if (ctlp->boardType == ROCKET_TYPE_PC104) {
688 switch (rocketMode) {
689 case ROCKET_MODE_RS485:
690 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
691 break;
692 case ROCKET_MODE_RS422:
693 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
694 break;
695 case ROCKET_MODE_RS232:
696 default:
697 if (info->flags & ROCKET_RTS_TOGGLE)
698 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
699 else
700 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
701 break;
702 }
703 }
704 spin_lock_init(&info->slock);
705 mutex_init(&info->write_mtx);
706 rp_table[line] = info;
707 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
708 NULL);
709}
710
711/*
712 * Configures a rocketport port according to its termio settings. Called from
713 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
714 */
715static void configure_r_port(struct tty_struct *tty, struct r_port *info,
716 struct ktermios *old_termios)
717{
718 unsigned cflag;
719 unsigned long flags;
720 unsigned rocketMode;
721 int bits, baud, divisor;
722 CHANNEL_t *cp;
723 struct ktermios *t = tty->termios;
724
725 cp = &info->channel;
726 cflag = t->c_cflag;
727
728 /* Byte size and parity */
729 if ((cflag & CSIZE) == CS8) {
730 sSetData8(cp);
731 bits = 10;
732 } else {
733 sSetData7(cp);
734 bits = 9;
735 }
736 if (cflag & CSTOPB) {
737 sSetStop2(cp);
738 bits++;
739 } else {
740 sSetStop1(cp);
741 }
742
743 if (cflag & PARENB) {
744 sEnParity(cp);
745 bits++;
746 if (cflag & PARODD) {
747 sSetOddParity(cp);
748 } else {
749 sSetEvenParity(cp);
750 }
751 } else {
752 sDisParity(cp);
753 }
754
755 /* baud rate */
756 baud = tty_get_baud_rate(tty);
757 if (!baud)
758 baud = 9600;
759 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
760 if ((divisor >= 8192 || divisor < 0) && old_termios) {
761 baud = tty_termios_baud_rate(old_termios);
762 if (!baud)
763 baud = 9600;
764 divisor = (rp_baud_base[info->board] / baud) - 1;
765 }
766 if (divisor >= 8192 || divisor < 0) {
767 baud = 9600;
768 divisor = (rp_baud_base[info->board] / baud) - 1;
769 }
770 info->cps = baud / bits;
771 sSetBaud(cp, divisor);
772
773 /* FIXME: Should really back compute a baud rate from the divisor */
774 tty_encode_baud_rate(tty, baud, baud);
775
776 if (cflag & CRTSCTS) {
777 info->intmask |= DELTA_CTS;
778 sEnCTSFlowCtl(cp);
779 } else {
780 info->intmask &= ~DELTA_CTS;
781 sDisCTSFlowCtl(cp);
782 }
783 if (cflag & CLOCAL) {
784 info->intmask &= ~DELTA_CD;
785 } else {
786 spin_lock_irqsave(&info->slock, flags);
787 if (sGetChanStatus(cp) & CD_ACT)
788 info->cd_status = 1;
789 else
790 info->cd_status = 0;
791 info->intmask |= DELTA_CD;
792 spin_unlock_irqrestore(&info->slock, flags);
793 }
794
795 /*
796 * Handle software flow control in the board
797 */
798#ifdef ROCKET_SOFT_FLOW
799 if (I_IXON(tty)) {
800 sEnTxSoftFlowCtl(cp);
801 if (I_IXANY(tty)) {
802 sEnIXANY(cp);
803 } else {
804 sDisIXANY(cp);
805 }
806 sSetTxXONChar(cp, START_CHAR(tty));
807 sSetTxXOFFChar(cp, STOP_CHAR(tty));
808 } else {
809 sDisTxSoftFlowCtl(cp);
810 sDisIXANY(cp);
811 sClrTxXOFF(cp);
812 }
813#endif
814
815 /*
816 * Set up ignore/read mask words
817 */
818 info->read_status_mask = STMRCVROVRH | 0xFF;
819 if (I_INPCK(tty))
820 info->read_status_mask |= STMFRAMEH | STMPARITYH;
821 if (I_BRKINT(tty) || I_PARMRK(tty))
822 info->read_status_mask |= STMBREAKH;
823
824 /*
825 * Characters to ignore
826 */
827 info->ignore_status_mask = 0;
828 if (I_IGNPAR(tty))
829 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
830 if (I_IGNBRK(tty)) {
831 info->ignore_status_mask |= STMBREAKH;
832 /*
833 * If we're ignoring parity and break indicators,
834 * ignore overruns too. (For real raw support).
835 */
836 if (I_IGNPAR(tty))
837 info->ignore_status_mask |= STMRCVROVRH;
838 }
839
840 rocketMode = info->flags & ROCKET_MODE_MASK;
841
842 if ((info->flags & ROCKET_RTS_TOGGLE)
843 || (rocketMode == ROCKET_MODE_RS485))
844 sEnRTSToggle(cp);
845 else
846 sDisRTSToggle(cp);
847
848 sSetRTS(&info->channel);
849
850 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
851 switch (rocketMode) {
852 case ROCKET_MODE_RS485:
853 sSetInterfaceMode(cp, InterfaceModeRS485);
854 break;
855 case ROCKET_MODE_RS422:
856 sSetInterfaceMode(cp, InterfaceModeRS422);
857 break;
858 case ROCKET_MODE_RS232:
859 default:
860 if (info->flags & ROCKET_RTS_TOGGLE)
861 sSetInterfaceMode(cp, InterfaceModeRS232T);
862 else
863 sSetInterfaceMode(cp, InterfaceModeRS232);
864 break;
865 }
866 }
867}
868
869static int carrier_raised(struct tty_port *port)
870{
871 struct r_port *info = container_of(port, struct r_port, port);
872 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
873}
874
875static void dtr_rts(struct tty_port *port, int on)
876{
877 struct r_port *info = container_of(port, struct r_port, port);
878 if (on) {
879 sSetDTR(&info->channel);
880 sSetRTS(&info->channel);
881 } else {
882 sClrDTR(&info->channel);
883 sClrRTS(&info->channel);
884 }
885}
886
887/*
888 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
889 * port's r_port struct. Initializes the port hardware.
890 */
891static int rp_open(struct tty_struct *tty, struct file *filp)
892{
893 struct r_port *info;
894 struct tty_port *port;
895 int line = 0, retval;
896 CHANNEL_t *cp;
897 unsigned long page;
898
899 line = tty->index;
900 if (line < 0 || line >= MAX_RP_PORTS || ((info = rp_table[line]) == NULL))
901 return -ENXIO;
902 port = &info->port;
903
904 page = __get_free_page(GFP_KERNEL);
905 if (!page)
906 return -ENOMEM;
907
908 if (port->flags & ASYNC_CLOSING) {
909 retval = wait_for_completion_interruptible(&info->close_wait);
910 free_page(page);
911 if (retval)
912 return retval;
913 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
914 }
915
916 /*
917 * We must not sleep from here until the port is marked fully in use.
918 */
919 if (info->xmit_buf)
920 free_page(page);
921 else
922 info->xmit_buf = (unsigned char *) page;
923
924 tty->driver_data = info;
925 tty_port_tty_set(port, tty);
926
927 if (port->count++ == 0) {
928 atomic_inc(&rp_num_ports_open);
929
930#ifdef ROCKET_DEBUG_OPEN
931 printk(KERN_INFO "rocket mod++ = %d...\n",
932 atomic_read(&rp_num_ports_open));
933#endif
934 }
935#ifdef ROCKET_DEBUG_OPEN
936 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
937#endif
938
939 /*
940 * Info->count is now 1; so it's safe to sleep now.
941 */
942 if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
943 cp = &info->channel;
944 sSetRxTrigger(cp, TRIG_1);
945 if (sGetChanStatus(cp) & CD_ACT)
946 info->cd_status = 1;
947 else
948 info->cd_status = 0;
949 sDisRxStatusMode(cp);
950 sFlushRxFIFO(cp);
951 sFlushTxFIFO(cp);
952
953 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
954 sSetRxTrigger(cp, TRIG_1);
955
956 sGetChanStatus(cp);
957 sDisRxStatusMode(cp);
958 sClrTxXOFF(cp);
959
960 sDisCTSFlowCtl(cp);
961 sDisTxSoftFlowCtl(cp);
962
963 sEnRxFIFO(cp);
964 sEnTransmit(cp);
965
966 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
967
968 /*
969 * Set up the tty->alt_speed kludge
970 */
971 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
972 tty->alt_speed = 57600;
973 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
974 tty->alt_speed = 115200;
975 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
976 tty->alt_speed = 230400;
977 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
978 tty->alt_speed = 460800;
979
980 configure_r_port(tty, info, NULL);
981 if (tty->termios->c_cflag & CBAUD) {
982 sSetDTR(cp);
983 sSetRTS(cp);
984 }
985 }
986 /* Starts (or resets) the maint polling loop */
987 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
988
989 retval = tty_port_block_til_ready(port, tty, filp);
990 if (retval) {
991#ifdef ROCKET_DEBUG_OPEN
992 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
993#endif
994 return retval;
995 }
996 return 0;
997}
998
999/*
1000 * Exception handler that closes a serial port. info->port.count is considered critical.
1001 */
1002static void rp_close(struct tty_struct *tty, struct file *filp)
1003{
1004 struct r_port *info = tty->driver_data;
1005 struct tty_port *port = &info->port;
1006 int timeout;
1007 CHANNEL_t *cp;
1008
1009 if (rocket_paranoia_check(info, "rp_close"))
1010 return;
1011
1012#ifdef ROCKET_DEBUG_OPEN
1013 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1014#endif
1015
1016 if (tty_port_close_start(port, tty, filp) == 0)
1017 return;
1018
1019 mutex_lock(&port->mutex);
1020 cp = &info->channel;
1021 /*
1022 * Before we drop DTR, make sure the UART transmitter
1023 * has completely drained; this is especially
1024 * important if there is a transmit FIFO!
1025 */
1026 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1027 if (timeout == 0)
1028 timeout = 1;
1029 rp_wait_until_sent(tty, timeout);
1030 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1031
1032 sDisTransmit(cp);
1033 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1034 sDisCTSFlowCtl(cp);
1035 sDisTxSoftFlowCtl(cp);
1036 sClrTxXOFF(cp);
1037 sFlushRxFIFO(cp);
1038 sFlushTxFIFO(cp);
1039 sClrRTS(cp);
1040 if (C_HUPCL(tty))
1041 sClrDTR(cp);
1042
1043 rp_flush_buffer(tty);
1044
1045 tty_ldisc_flush(tty);
1046
1047 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1048
1049 /* We can't yet use tty_port_close_end as the buffer handling in this
1050 driver is a bit different to the usual */
1051
1052 if (port->blocked_open) {
1053 if (port->close_delay) {
1054 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1055 }
1056 wake_up_interruptible(&port->open_wait);
1057 } else {
1058 if (info->xmit_buf) {
1059 free_page((unsigned long) info->xmit_buf);
1060 info->xmit_buf = NULL;
1061 }
1062 }
1063 spin_lock_irq(&port->lock);
1064 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1065 tty->closing = 0;
1066 spin_unlock_irq(&port->lock);
1067 mutex_unlock(&port->mutex);
1068 tty_port_tty_set(port, NULL);
1069
1070 wake_up_interruptible(&port->close_wait);
1071 complete_all(&info->close_wait);
1072 atomic_dec(&rp_num_ports_open);
1073
1074#ifdef ROCKET_DEBUG_OPEN
1075 printk(KERN_INFO "rocket mod-- = %d...\n",
1076 atomic_read(&rp_num_ports_open));
1077 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1078#endif
1079
1080}
1081
1082static void rp_set_termios(struct tty_struct *tty,
1083 struct ktermios *old_termios)
1084{
1085 struct r_port *info = tty->driver_data;
1086 CHANNEL_t *cp;
1087 unsigned cflag;
1088
1089 if (rocket_paranoia_check(info, "rp_set_termios"))
1090 return;
1091
1092 cflag = tty->termios->c_cflag;
1093
1094 /*
1095 * This driver doesn't support CS5 or CS6
1096 */
1097 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1098 tty->termios->c_cflag =
1099 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1100 /* Or CMSPAR */
1101 tty->termios->c_cflag &= ~CMSPAR;
1102
1103 configure_r_port(tty, info, old_termios);
1104
1105 cp = &info->channel;
1106
1107 /* Handle transition to B0 status */
1108 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1109 sClrDTR(cp);
1110 sClrRTS(cp);
1111 }
1112
1113 /* Handle transition away from B0 status */
1114 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1115 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1116 sSetRTS(cp);
1117 sSetDTR(cp);
1118 }
1119
1120 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1121 tty->hw_stopped = 0;
1122 rp_start(tty);
1123 }
1124}
1125
1126static int rp_break(struct tty_struct *tty, int break_state)
1127{
1128 struct r_port *info = tty->driver_data;
1129 unsigned long flags;
1130
1131 if (rocket_paranoia_check(info, "rp_break"))
1132 return -EINVAL;
1133
1134 spin_lock_irqsave(&info->slock, flags);
1135 if (break_state == -1)
1136 sSendBreak(&info->channel);
1137 else
1138 sClrBreak(&info->channel);
1139 spin_unlock_irqrestore(&info->slock, flags);
1140 return 0;
1141}
1142
1143/*
1144 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1145 * the UPCI boards was added, it was decided to make this a function because
1146 * the macro was getting too complicated. All cases except the first one
1147 * (UPCIRingInd) are taken directly from the original macro.
1148 */
1149static int sGetChanRI(CHANNEL_T * ChP)
1150{
1151 CONTROLLER_t *CtlP = ChP->CtlP;
1152 int ChanNum = ChP->ChanNum;
1153 int RingInd = 0;
1154
1155 if (CtlP->UPCIRingInd)
1156 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1157 else if (CtlP->AltChanRingIndicator)
1158 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1159 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1160 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1161
1162 return RingInd;
1163}
1164
1165/********************************************************************************************/
1166/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1167
1168/*
1169 * Returns the state of the serial modem control lines. These next 2 functions
1170 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1171 */
1172static int rp_tiocmget(struct tty_struct *tty)
1173{
1174 struct r_port *info = tty->driver_data;
1175 unsigned int control, result, ChanStatus;
1176
1177 ChanStatus = sGetChanStatusLo(&info->channel);
1178 control = info->channel.TxControl[3];
1179 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1180 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1181 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1182 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1183 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1184 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1185
1186 return result;
1187}
1188
1189/*
1190 * Sets the modem control lines
1191 */
1192static int rp_tiocmset(struct tty_struct *tty,
1193 unsigned int set, unsigned int clear)
1194{
1195 struct r_port *info = tty->driver_data;
1196
1197 if (set & TIOCM_RTS)
1198 info->channel.TxControl[3] |= SET_RTS;
1199 if (set & TIOCM_DTR)
1200 info->channel.TxControl[3] |= SET_DTR;
1201 if (clear & TIOCM_RTS)
1202 info->channel.TxControl[3] &= ~SET_RTS;
1203 if (clear & TIOCM_DTR)
1204 info->channel.TxControl[3] &= ~SET_DTR;
1205
1206 out32(info->channel.IndexAddr, info->channel.TxControl);
1207 return 0;
1208}
1209
1210static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1211{
1212 struct rocket_config tmp;
1213
1214 if (!retinfo)
1215 return -EFAULT;
1216 memset(&tmp, 0, sizeof (tmp));
1217 mutex_lock(&info->port.mutex);
1218 tmp.line = info->line;
1219 tmp.flags = info->flags;
1220 tmp.close_delay = info->port.close_delay;
1221 tmp.closing_wait = info->port.closing_wait;
1222 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1223 mutex_unlock(&info->port.mutex);
1224
1225 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1226 return -EFAULT;
1227 return 0;
1228}
1229
1230static int set_config(struct tty_struct *tty, struct r_port *info,
1231 struct rocket_config __user *new_info)
1232{
1233 struct rocket_config new_serial;
1234
1235 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1236 return -EFAULT;
1237
1238 mutex_lock(&info->port.mutex);
1239 if (!capable(CAP_SYS_ADMIN))
1240 {
1241 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1242 mutex_unlock(&info->port.mutex);
1243 return -EPERM;
1244 }
1245 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1246 configure_r_port(tty, info, NULL);
1247 mutex_unlock(&info->port.mutex);
1248 return 0;
1249 }
1250
1251 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1252 info->port.close_delay = new_serial.close_delay;
1253 info->port.closing_wait = new_serial.closing_wait;
1254
1255 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1256 tty->alt_speed = 57600;
1257 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1258 tty->alt_speed = 115200;
1259 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1260 tty->alt_speed = 230400;
1261 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1262 tty->alt_speed = 460800;
1263 mutex_unlock(&info->port.mutex);
1264
1265 configure_r_port(tty, info, NULL);
1266 return 0;
1267}
1268
1269/*
1270 * This function fills in a rocket_ports struct with information
1271 * about what boards/ports are in the system. This info is passed
1272 * to user space. See setrocket.c where the info is used to create
1273 * the /dev/ttyRx ports.
1274 */
1275static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1276{
1277 struct rocket_ports tmp;
1278 int board;
1279
1280 if (!retports)
1281 return -EFAULT;
1282 memset(&tmp, 0, sizeof (tmp));
1283 tmp.tty_major = rocket_driver->major;
1284
1285 for (board = 0; board < 4; board++) {
1286 tmp.rocketModel[board].model = rocketModel[board].model;
1287 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1288 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1289 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1290 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1291 }
1292 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1293 return -EFAULT;
1294 return 0;
1295}
1296
1297static int reset_rm2(struct r_port *info, void __user *arg)
1298{
1299 int reset;
1300
1301 if (!capable(CAP_SYS_ADMIN))
1302 return -EPERM;
1303
1304 if (copy_from_user(&reset, arg, sizeof (int)))
1305 return -EFAULT;
1306 if (reset)
1307 reset = 1;
1308
1309 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1310 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1311 return -EINVAL;
1312
1313 if (info->ctlp->BusType == isISA)
1314 sModemReset(info->ctlp, info->chan, reset);
1315 else
1316 sPCIModemReset(info->ctlp, info->chan, reset);
1317
1318 return 0;
1319}
1320
1321static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1322{
1323 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1324 return -EFAULT;
1325 return 0;
1326}
1327
1328/* IOCTL call handler into the driver */
1329static int rp_ioctl(struct tty_struct *tty,
1330 unsigned int cmd, unsigned long arg)
1331{
1332 struct r_port *info = tty->driver_data;
1333 void __user *argp = (void __user *)arg;
1334 int ret = 0;
1335
1336 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1337 return -ENXIO;
1338
1339 switch (cmd) {
1340 case RCKP_GET_STRUCT:
1341 if (copy_to_user(argp, info, sizeof (struct r_port)))
1342 ret = -EFAULT;
1343 break;
1344 case RCKP_GET_CONFIG:
1345 ret = get_config(info, argp);
1346 break;
1347 case RCKP_SET_CONFIG:
1348 ret = set_config(tty, info, argp);
1349 break;
1350 case RCKP_GET_PORTS:
1351 ret = get_ports(info, argp);
1352 break;
1353 case RCKP_RESET_RM2:
1354 ret = reset_rm2(info, argp);
1355 break;
1356 case RCKP_GET_VERSION:
1357 ret = get_version(info, argp);
1358 break;
1359 default:
1360 ret = -ENOIOCTLCMD;
1361 }
1362 return ret;
1363}
1364
1365static void rp_send_xchar(struct tty_struct *tty, char ch)
1366{
1367 struct r_port *info = tty->driver_data;
1368 CHANNEL_t *cp;
1369
1370 if (rocket_paranoia_check(info, "rp_send_xchar"))
1371 return;
1372
1373 cp = &info->channel;
1374 if (sGetTxCnt(cp))
1375 sWriteTxPrioByte(cp, ch);
1376 else
1377 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1378}
1379
1380static void rp_throttle(struct tty_struct *tty)
1381{
1382 struct r_port *info = tty->driver_data;
1383
1384#ifdef ROCKET_DEBUG_THROTTLE
1385 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1386 tty->ldisc.chars_in_buffer(tty));
1387#endif
1388
1389 if (rocket_paranoia_check(info, "rp_throttle"))
1390 return;
1391
1392 if (I_IXOFF(tty))
1393 rp_send_xchar(tty, STOP_CHAR(tty));
1394
1395 sClrRTS(&info->channel);
1396}
1397
1398static void rp_unthrottle(struct tty_struct *tty)
1399{
1400 struct r_port *info = tty->driver_data;
1401#ifdef ROCKET_DEBUG_THROTTLE
1402 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1403 tty->ldisc.chars_in_buffer(tty));
1404#endif
1405
1406 if (rocket_paranoia_check(info, "rp_throttle"))
1407 return;
1408
1409 if (I_IXOFF(tty))
1410 rp_send_xchar(tty, START_CHAR(tty));
1411
1412 sSetRTS(&info->channel);
1413}
1414
1415/*
1416 * ------------------------------------------------------------
1417 * rp_stop() and rp_start()
1418 *
1419 * This routines are called before setting or resetting tty->stopped.
1420 * They enable or disable transmitter interrupts, as necessary.
1421 * ------------------------------------------------------------
1422 */
1423static void rp_stop(struct tty_struct *tty)
1424{
1425 struct r_port *info = tty->driver_data;
1426
1427#ifdef ROCKET_DEBUG_FLOW
1428 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1429 info->xmit_cnt, info->xmit_fifo_room);
1430#endif
1431
1432 if (rocket_paranoia_check(info, "rp_stop"))
1433 return;
1434
1435 if (sGetTxCnt(&info->channel))
1436 sDisTransmit(&info->channel);
1437}
1438
1439static void rp_start(struct tty_struct *tty)
1440{
1441 struct r_port *info = tty->driver_data;
1442
1443#ifdef ROCKET_DEBUG_FLOW
1444 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1445 info->xmit_cnt, info->xmit_fifo_room);
1446#endif
1447
1448 if (rocket_paranoia_check(info, "rp_stop"))
1449 return;
1450
1451 sEnTransmit(&info->channel);
1452 set_bit((info->aiop * 8) + info->chan,
1453 (void *) &xmit_flags[info->board]);
1454}
1455
1456/*
1457 * rp_wait_until_sent() --- wait until the transmitter is empty
1458 */
1459static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1460{
1461 struct r_port *info = tty->driver_data;
1462 CHANNEL_t *cp;
1463 unsigned long orig_jiffies;
1464 int check_time, exit_time;
1465 int txcnt;
1466
1467 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1468 return;
1469
1470 cp = &info->channel;
1471
1472 orig_jiffies = jiffies;
1473#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1474 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1475 jiffies);
1476 printk(KERN_INFO "cps=%d...\n", info->cps);
1477#endif
1478 while (1) {
1479 txcnt = sGetTxCnt(cp);
1480 if (!txcnt) {
1481 if (sGetChanStatusLo(cp) & TXSHRMT)
1482 break;
1483 check_time = (HZ / info->cps) / 5;
1484 } else {
1485 check_time = HZ * txcnt / info->cps;
1486 }
1487 if (timeout) {
1488 exit_time = orig_jiffies + timeout - jiffies;
1489 if (exit_time <= 0)
1490 break;
1491 if (exit_time < check_time)
1492 check_time = exit_time;
1493 }
1494 if (check_time == 0)
1495 check_time = 1;
1496#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1497 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1498 jiffies, check_time);
1499#endif
1500 msleep_interruptible(jiffies_to_msecs(check_time));
1501 if (signal_pending(current))
1502 break;
1503 }
1504 __set_current_state(TASK_RUNNING);
1505#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1506 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1507#endif
1508}
1509
1510/*
1511 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1512 */
1513static void rp_hangup(struct tty_struct *tty)
1514{
1515 CHANNEL_t *cp;
1516 struct r_port *info = tty->driver_data;
1517 unsigned long flags;
1518
1519 if (rocket_paranoia_check(info, "rp_hangup"))
1520 return;
1521
1522#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1523 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1524#endif
1525 rp_flush_buffer(tty);
1526 spin_lock_irqsave(&info->port.lock, flags);
1527 if (info->port.flags & ASYNC_CLOSING) {
1528 spin_unlock_irqrestore(&info->port.lock, flags);
1529 return;
1530 }
1531 if (info->port.count)
1532 atomic_dec(&rp_num_ports_open);
1533 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1534 spin_unlock_irqrestore(&info->port.lock, flags);
1535
1536 tty_port_hangup(&info->port);
1537
1538 cp = &info->channel;
1539 sDisRxFIFO(cp);
1540 sDisTransmit(cp);
1541 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1542 sDisCTSFlowCtl(cp);
1543 sDisTxSoftFlowCtl(cp);
1544 sClrTxXOFF(cp);
1545 clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1546
1547 wake_up_interruptible(&info->port.open_wait);
1548}
1549
1550/*
1551 * Exception handler - write char routine. The RocketPort driver uses a
1552 * double-buffering strategy, with the twist that if the in-memory CPU
1553 * buffer is empty, and there's space in the transmit FIFO, the
1554 * writing routines will write directly to transmit FIFO.
1555 * Write buffer and counters protected by spinlocks
1556 */
1557static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1558{
1559 struct r_port *info = tty->driver_data;
1560 CHANNEL_t *cp;
1561 unsigned long flags;
1562
1563 if (rocket_paranoia_check(info, "rp_put_char"))
1564 return 0;
1565
1566 /*
1567 * Grab the port write mutex, locking out other processes that try to
1568 * write to this port
1569 */
1570 mutex_lock(&info->write_mtx);
1571
1572#ifdef ROCKET_DEBUG_WRITE
1573 printk(KERN_INFO "rp_put_char %c...\n", ch);
1574#endif
1575
1576 spin_lock_irqsave(&info->slock, flags);
1577 cp = &info->channel;
1578
1579 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1580 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1581
1582 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1583 info->xmit_buf[info->xmit_head++] = ch;
1584 info->xmit_head &= XMIT_BUF_SIZE - 1;
1585 info->xmit_cnt++;
1586 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1587 } else {
1588 sOutB(sGetTxRxDataIO(cp), ch);
1589 info->xmit_fifo_room--;
1590 }
1591 spin_unlock_irqrestore(&info->slock, flags);
1592 mutex_unlock(&info->write_mtx);
1593 return 1;
1594}
1595
1596/*
1597 * Exception handler - write routine, called when user app writes to the device.
1598 * A per port write mutex is used to protect from another process writing to
1599 * this port at the same time. This other process could be running on the other CPU
1600 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1601 * Spinlocks protect the info xmit members.
1602 */
1603static int rp_write(struct tty_struct *tty,
1604 const unsigned char *buf, int count)
1605{
1606 struct r_port *info = tty->driver_data;
1607 CHANNEL_t *cp;
1608 const unsigned char *b;
1609 int c, retval = 0;
1610 unsigned long flags;
1611
1612 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1613 return 0;
1614
1615 if (mutex_lock_interruptible(&info->write_mtx))
1616 return -ERESTARTSYS;
1617
1618#ifdef ROCKET_DEBUG_WRITE
1619 printk(KERN_INFO "rp_write %d chars...\n", count);
1620#endif
1621 cp = &info->channel;
1622
1623 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1624 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1625
1626 /*
1627 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1628 * into FIFO. Use the write queue for temp storage.
1629 */
1630 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1631 c = min(count, info->xmit_fifo_room);
1632 b = buf;
1633
1634 /* Push data into FIFO, 2 bytes at a time */
1635 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1636
1637 /* If there is a byte remaining, write it */
1638 if (c & 1)
1639 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1640
1641 retval += c;
1642 buf += c;
1643 count -= c;
1644
1645 spin_lock_irqsave(&info->slock, flags);
1646 info->xmit_fifo_room -= c;
1647 spin_unlock_irqrestore(&info->slock, flags);
1648 }
1649
1650 /* If count is zero, we wrote it all and are done */
1651 if (!count)
1652 goto end;
1653
1654 /* Write remaining data into the port's xmit_buf */
1655 while (1) {
1656 /* Hung up ? */
1657 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1658 goto end;
1659 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1660 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1661 if (c <= 0)
1662 break;
1663
1664 b = buf;
1665 memcpy(info->xmit_buf + info->xmit_head, b, c);
1666
1667 spin_lock_irqsave(&info->slock, flags);
1668 info->xmit_head =
1669 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1670 info->xmit_cnt += c;
1671 spin_unlock_irqrestore(&info->slock, flags);
1672
1673 buf += c;
1674 count -= c;
1675 retval += c;
1676 }
1677
1678 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1679 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1680
1681end:
1682 if (info->xmit_cnt < WAKEUP_CHARS) {
1683 tty_wakeup(tty);
1684#ifdef ROCKETPORT_HAVE_POLL_WAIT
1685 wake_up_interruptible(&tty->poll_wait);
1686#endif
1687 }
1688 mutex_unlock(&info->write_mtx);
1689 return retval;
1690}
1691
1692/*
1693 * Return the number of characters that can be sent. We estimate
1694 * only using the in-memory transmit buffer only, and ignore the
1695 * potential space in the transmit FIFO.
1696 */
1697static int rp_write_room(struct tty_struct *tty)
1698{
1699 struct r_port *info = tty->driver_data;
1700 int ret;
1701
1702 if (rocket_paranoia_check(info, "rp_write_room"))
1703 return 0;
1704
1705 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1706 if (ret < 0)
1707 ret = 0;
1708#ifdef ROCKET_DEBUG_WRITE
1709 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1710#endif
1711 return ret;
1712}
1713
1714/*
1715 * Return the number of characters in the buffer. Again, this only
1716 * counts those characters in the in-memory transmit buffer.
1717 */
1718static int rp_chars_in_buffer(struct tty_struct *tty)
1719{
1720 struct r_port *info = tty->driver_data;
1721
1722 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1723 return 0;
1724
1725#ifdef ROCKET_DEBUG_WRITE
1726 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1727#endif
1728 return info->xmit_cnt;
1729}
1730
1731/*
1732 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1733 * r_port struct for the port. Note that spinlock are used to protect info members,
1734 * do not call this function if the spinlock is already held.
1735 */
1736static void rp_flush_buffer(struct tty_struct *tty)
1737{
1738 struct r_port *info = tty->driver_data;
1739 CHANNEL_t *cp;
1740 unsigned long flags;
1741
1742 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1743 return;
1744
1745 spin_lock_irqsave(&info->slock, flags);
1746 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1747 spin_unlock_irqrestore(&info->slock, flags);
1748
1749#ifdef ROCKETPORT_HAVE_POLL_WAIT
1750 wake_up_interruptible(&tty->poll_wait);
1751#endif
1752 tty_wakeup(tty);
1753
1754 cp = &info->channel;
1755 sFlushTxFIFO(cp);
1756}
1757
1758#ifdef CONFIG_PCI
1759
1760static struct pci_device_id __devinitdata __used rocket_pci_ids[] = {
1761 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1762 { }
1763};
1764MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1765
1766/*
1767 * Called when a PCI card is found. Retrieves and stores model information,
1768 * init's aiopic and serial port hardware.
1769 * Inputs: i is the board number (0-n)
1770 */
1771static __init int register_PCI(int i, struct pci_dev *dev)
1772{
1773 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1774 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1775 CONTROLLER_t *ctlp;
1776
1777 int fast_clock = 0;
1778 int altChanRingIndicator = 0;
1779 int ports_per_aiop = 8;
1780 WordIO_t ConfigIO = 0;
1781 ByteIO_t UPCIRingInd = 0;
1782
1783 if (!dev || pci_enable_device(dev))
1784 return 0;
1785
1786 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1787
1788 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1789 rocketModel[i].loadrm2 = 0;
1790 rocketModel[i].startingPortNumber = nextLineNumber;
1791
1792 /* Depending on the model, set up some config variables */
1793 switch (dev->device) {
1794 case PCI_DEVICE_ID_RP4QUAD:
1795 max_num_aiops = 1;
1796 ports_per_aiop = 4;
1797 rocketModel[i].model = MODEL_RP4QUAD;
1798 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1799 rocketModel[i].numPorts = 4;
1800 break;
1801 case PCI_DEVICE_ID_RP8OCTA:
1802 max_num_aiops = 1;
1803 rocketModel[i].model = MODEL_RP8OCTA;
1804 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1805 rocketModel[i].numPorts = 8;
1806 break;
1807 case PCI_DEVICE_ID_URP8OCTA:
1808 max_num_aiops = 1;
1809 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1810 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1811 rocketModel[i].numPorts = 8;
1812 break;
1813 case PCI_DEVICE_ID_RP8INTF:
1814 max_num_aiops = 1;
1815 rocketModel[i].model = MODEL_RP8INTF;
1816 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1817 rocketModel[i].numPorts = 8;
1818 break;
1819 case PCI_DEVICE_ID_URP8INTF:
1820 max_num_aiops = 1;
1821 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1822 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1823 rocketModel[i].numPorts = 8;
1824 break;
1825 case PCI_DEVICE_ID_RP8J:
1826 max_num_aiops = 1;
1827 rocketModel[i].model = MODEL_RP8J;
1828 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1829 rocketModel[i].numPorts = 8;
1830 break;
1831 case PCI_DEVICE_ID_RP4J:
1832 max_num_aiops = 1;
1833 ports_per_aiop = 4;
1834 rocketModel[i].model = MODEL_RP4J;
1835 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1836 rocketModel[i].numPorts = 4;
1837 break;
1838 case PCI_DEVICE_ID_RP8SNI:
1839 max_num_aiops = 1;
1840 rocketModel[i].model = MODEL_RP8SNI;
1841 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1842 rocketModel[i].numPorts = 8;
1843 break;
1844 case PCI_DEVICE_ID_RP16SNI:
1845 max_num_aiops = 2;
1846 rocketModel[i].model = MODEL_RP16SNI;
1847 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1848 rocketModel[i].numPorts = 16;
1849 break;
1850 case PCI_DEVICE_ID_RP16INTF:
1851 max_num_aiops = 2;
1852 rocketModel[i].model = MODEL_RP16INTF;
1853 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1854 rocketModel[i].numPorts = 16;
1855 break;
1856 case PCI_DEVICE_ID_URP16INTF:
1857 max_num_aiops = 2;
1858 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1859 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1860 rocketModel[i].numPorts = 16;
1861 break;
1862 case PCI_DEVICE_ID_CRP16INTF:
1863 max_num_aiops = 2;
1864 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1865 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1866 rocketModel[i].numPorts = 16;
1867 break;
1868 case PCI_DEVICE_ID_RP32INTF:
1869 max_num_aiops = 4;
1870 rocketModel[i].model = MODEL_RP32INTF;
1871 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1872 rocketModel[i].numPorts = 32;
1873 break;
1874 case PCI_DEVICE_ID_URP32INTF:
1875 max_num_aiops = 4;
1876 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1877 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1878 rocketModel[i].numPorts = 32;
1879 break;
1880 case PCI_DEVICE_ID_RPP4:
1881 max_num_aiops = 1;
1882 ports_per_aiop = 4;
1883 altChanRingIndicator++;
1884 fast_clock++;
1885 rocketModel[i].model = MODEL_RPP4;
1886 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1887 rocketModel[i].numPorts = 4;
1888 break;
1889 case PCI_DEVICE_ID_RPP8:
1890 max_num_aiops = 2;
1891 ports_per_aiop = 4;
1892 altChanRingIndicator++;
1893 fast_clock++;
1894 rocketModel[i].model = MODEL_RPP8;
1895 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1896 rocketModel[i].numPorts = 8;
1897 break;
1898 case PCI_DEVICE_ID_RP2_232:
1899 max_num_aiops = 1;
1900 ports_per_aiop = 2;
1901 altChanRingIndicator++;
1902 fast_clock++;
1903 rocketModel[i].model = MODEL_RP2_232;
1904 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1905 rocketModel[i].numPorts = 2;
1906 break;
1907 case PCI_DEVICE_ID_RP2_422:
1908 max_num_aiops = 1;
1909 ports_per_aiop = 2;
1910 altChanRingIndicator++;
1911 fast_clock++;
1912 rocketModel[i].model = MODEL_RP2_422;
1913 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1914 rocketModel[i].numPorts = 2;
1915 break;
1916 case PCI_DEVICE_ID_RP6M:
1917
1918 max_num_aiops = 1;
1919 ports_per_aiop = 6;
1920
1921 /* If revision is 1, the rocketmodem flash must be loaded.
1922 * If it is 2 it is a "socketed" version. */
1923 if (dev->revision == 1) {
1924 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1925 rocketModel[i].loadrm2 = 1;
1926 } else {
1927 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1928 }
1929
1930 rocketModel[i].model = MODEL_RP6M;
1931 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
1932 rocketModel[i].numPorts = 6;
1933 break;
1934 case PCI_DEVICE_ID_RP4M:
1935 max_num_aiops = 1;
1936 ports_per_aiop = 4;
1937 if (dev->revision == 1) {
1938 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1939 rocketModel[i].loadrm2 = 1;
1940 } else {
1941 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1942 }
1943
1944 rocketModel[i].model = MODEL_RP4M;
1945 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
1946 rocketModel[i].numPorts = 4;
1947 break;
1948 default:
1949 max_num_aiops = 0;
1950 break;
1951 }
1952
1953 /*
1954 * Check for UPCI boards.
1955 */
1956
1957 switch (dev->device) {
1958 case PCI_DEVICE_ID_URP32INTF:
1959 case PCI_DEVICE_ID_URP8INTF:
1960 case PCI_DEVICE_ID_URP16INTF:
1961 case PCI_DEVICE_ID_CRP16INTF:
1962 case PCI_DEVICE_ID_URP8OCTA:
1963 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1964 ConfigIO = pci_resource_start(dev, 1);
1965 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
1966 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1967
1968 /*
1969 * Check for octa or quad cable.
1970 */
1971 if (!
1972 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
1973 PCI_GPIO_CTRL_8PORT)) {
1974 ports_per_aiop = 4;
1975 rocketModel[i].numPorts = 4;
1976 }
1977 }
1978 break;
1979 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1980 max_num_aiops = 1;
1981 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
1982 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
1983 rocketModel[i].numPorts = 8;
1984 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1985 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1986 ConfigIO = pci_resource_start(dev, 1);
1987 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
1988 break;
1989 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
1990 max_num_aiops = 1;
1991 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
1992 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
1993 rocketModel[i].numPorts = 4;
1994 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1995 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1996 ConfigIO = pci_resource_start(dev, 1);
1997 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
1998 break;
1999 default:
2000 break;
2001 }
2002
2003 if (fast_clock) {
2004 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2005 rp_baud_base[i] = 921600;
2006 } else {
2007 /*
2008 * If support_low_speed is set, use the slow clock
2009 * prescale, which supports 50 bps
2010 */
2011 if (support_low_speed) {
2012 /* mod 9 (divide by 10) prescale */
2013 sClockPrescale = 0x19;
2014 rp_baud_base[i] = 230400;
2015 } else {
2016 /* mod 4 (divide by 5) prescale */
2017 sClockPrescale = 0x14;
2018 rp_baud_base[i] = 460800;
2019 }
2020 }
2021
2022 for (aiop = 0; aiop < max_num_aiops; aiop++)
2023 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2024 ctlp = sCtlNumToCtlPtr(i);
2025 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2026 for (aiop = 0; aiop < max_num_aiops; aiop++)
2027 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2028
2029 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2030 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2031 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2032 rocketModel[i].startingPortNumber,
2033 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2034
2035 if (num_aiops <= 0) {
2036 rcktpt_io_addr[i] = 0;
2037 return (0);
2038 }
2039 is_PCI[i] = 1;
2040
2041 /* Reset the AIOPIC, init the serial ports */
2042 for (aiop = 0; aiop < num_aiops; aiop++) {
2043 sResetAiopByNum(ctlp, aiop);
2044 num_chan = ports_per_aiop;
2045 for (chan = 0; chan < num_chan; chan++)
2046 init_r_port(i, aiop, chan, dev);
2047 }
2048
2049 /* Rocket modems must be reset */
2050 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2051 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2052 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2053 num_chan = ports_per_aiop;
2054 for (chan = 0; chan < num_chan; chan++)
2055 sPCIModemReset(ctlp, chan, 1);
2056 msleep(500);
2057 for (chan = 0; chan < num_chan; chan++)
2058 sPCIModemReset(ctlp, chan, 0);
2059 msleep(500);
2060 rmSpeakerReset(ctlp, rocketModel[i].model);
2061 }
2062 return (1);
2063}
2064
2065/*
2066 * Probes for PCI cards, inits them if found
2067 * Input: board_found = number of ISA boards already found, or the
2068 * starting board number
2069 * Returns: Number of PCI boards found
2070 */
2071static int __init init_PCI(int boards_found)
2072{
2073 struct pci_dev *dev = NULL;
2074 int count = 0;
2075
2076 /* Work through the PCI device list, pulling out ours */
2077 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2078 if (register_PCI(count + boards_found, dev))
2079 count++;
2080 }
2081 return (count);
2082}
2083
2084#endif /* CONFIG_PCI */
2085
2086/*
2087 * Probes for ISA cards
2088 * Input: i = the board number to look for
2089 * Returns: 1 if board found, 0 else
2090 */
2091static int __init init_ISA(int i)
2092{
2093 int num_aiops, num_chan = 0, total_num_chan = 0;
2094 int aiop, chan;
2095 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2096 CONTROLLER_t *ctlp;
2097 char *type_string;
2098
2099 /* If io_addr is zero, no board configured */
2100 if (rcktpt_io_addr[i] == 0)
2101 return (0);
2102
2103 /* Reserve the IO region */
2104 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2105 printk(KERN_ERR "Unable to reserve IO region for configured "
2106 "ISA RocketPort at address 0x%lx, board not "
2107 "installed...\n", rcktpt_io_addr[i]);
2108 rcktpt_io_addr[i] = 0;
2109 return (0);
2110 }
2111
2112 ctlp = sCtlNumToCtlPtr(i);
2113
2114 ctlp->boardType = rcktpt_type[i];
2115
2116 switch (rcktpt_type[i]) {
2117 case ROCKET_TYPE_PC104:
2118 type_string = "(PC104)";
2119 break;
2120 case ROCKET_TYPE_MODEM:
2121 type_string = "(RocketModem)";
2122 break;
2123 case ROCKET_TYPE_MODEMII:
2124 type_string = "(RocketModem II)";
2125 break;
2126 default:
2127 type_string = "";
2128 break;
2129 }
2130
2131 /*
2132 * If support_low_speed is set, use the slow clock prescale,
2133 * which supports 50 bps
2134 */
2135 if (support_low_speed) {
2136 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2137 rp_baud_base[i] = 230400;
2138 } else {
2139 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2140 rp_baud_base[i] = 460800;
2141 }
2142
2143 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2144 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2145
2146 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2147
2148 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2149 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2150 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2151 }
2152
2153 /* If something went wrong initing the AIOP's release the ISA IO memory */
2154 if (num_aiops <= 0) {
2155 release_region(rcktpt_io_addr[i], 64);
2156 rcktpt_io_addr[i] = 0;
2157 return (0);
2158 }
2159
2160 rocketModel[i].startingPortNumber = nextLineNumber;
2161
2162 for (aiop = 0; aiop < num_aiops; aiop++) {
2163 sResetAiopByNum(ctlp, aiop);
2164 sEnAiop(ctlp, aiop);
2165 num_chan = sGetAiopNumChan(ctlp, aiop);
2166 total_num_chan += num_chan;
2167 for (chan = 0; chan < num_chan; chan++)
2168 init_r_port(i, aiop, chan, NULL);
2169 }
2170 is_PCI[i] = 0;
2171 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2172 num_chan = sGetAiopNumChan(ctlp, 0);
2173 total_num_chan = num_chan;
2174 for (chan = 0; chan < num_chan; chan++)
2175 sModemReset(ctlp, chan, 1);
2176 msleep(500);
2177 for (chan = 0; chan < num_chan; chan++)
2178 sModemReset(ctlp, chan, 0);
2179 msleep(500);
2180 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2181 } else {
2182 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2183 }
2184 rocketModel[i].numPorts = total_num_chan;
2185 rocketModel[i].model = MODEL_ISA;
2186
2187 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2188 i, rcktpt_io_addr[i], num_aiops, type_string);
2189
2190 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2191 rocketModel[i].modelString,
2192 rocketModel[i].startingPortNumber,
2193 rocketModel[i].startingPortNumber +
2194 rocketModel[i].numPorts - 1);
2195
2196 return (1);
2197}
2198
2199static const struct tty_operations rocket_ops = {
2200 .open = rp_open,
2201 .close = rp_close,
2202 .write = rp_write,
2203 .put_char = rp_put_char,
2204 .write_room = rp_write_room,
2205 .chars_in_buffer = rp_chars_in_buffer,
2206 .flush_buffer = rp_flush_buffer,
2207 .ioctl = rp_ioctl,
2208 .throttle = rp_throttle,
2209 .unthrottle = rp_unthrottle,
2210 .set_termios = rp_set_termios,
2211 .stop = rp_stop,
2212 .start = rp_start,
2213 .hangup = rp_hangup,
2214 .break_ctl = rp_break,
2215 .send_xchar = rp_send_xchar,
2216 .wait_until_sent = rp_wait_until_sent,
2217 .tiocmget = rp_tiocmget,
2218 .tiocmset = rp_tiocmset,
2219};
2220
2221static const struct tty_port_operations rocket_port_ops = {
2222 .carrier_raised = carrier_raised,
2223 .dtr_rts = dtr_rts,
2224};
2225
2226/*
2227 * The module "startup" routine; it's run when the module is loaded.
2228 */
2229static int __init rp_init(void)
2230{
2231 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2232
2233 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2234 ROCKET_VERSION, ROCKET_DATE);
2235
2236 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2237 if (!rocket_driver)
2238 goto err;
2239
2240 /*
2241 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2242 * zero, use the default controller IO address of board1 + 0x40.
2243 */
2244 if (board1) {
2245 if (controller == 0)
2246 controller = board1 + 0x40;
2247 } else {
2248 controller = 0; /* Used as a flag, meaning no ISA boards */
2249 }
2250
2251 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2252 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2253 printk(KERN_ERR "Unable to reserve IO region for first "
2254 "configured ISA RocketPort controller 0x%lx. "
2255 "Driver exiting\n", controller);
2256 ret = -EBUSY;
2257 goto err_tty;
2258 }
2259
2260 /* Store ISA variable retrieved from command line or .conf file. */
2261 rcktpt_io_addr[0] = board1;
2262 rcktpt_io_addr[1] = board2;
2263 rcktpt_io_addr[2] = board3;
2264 rcktpt_io_addr[3] = board4;
2265
2266 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2267 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2268 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2269 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2270 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2271 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2272 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2273 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2274
2275 /*
2276 * Set up the tty driver structure and then register this
2277 * driver with the tty layer.
2278 */
2279
2280 rocket_driver->owner = THIS_MODULE;
2281 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2282 rocket_driver->name = "ttyR";
2283 rocket_driver->driver_name = "Comtrol RocketPort";
2284 rocket_driver->major = TTY_ROCKET_MAJOR;
2285 rocket_driver->minor_start = 0;
2286 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2287 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2288 rocket_driver->init_termios = tty_std_termios;
2289 rocket_driver->init_termios.c_cflag =
2290 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2291 rocket_driver->init_termios.c_ispeed = 9600;
2292 rocket_driver->init_termios.c_ospeed = 9600;
2293#ifdef ROCKET_SOFT_FLOW
2294 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2295#endif
2296 tty_set_operations(rocket_driver, &rocket_ops);
2297
2298 ret = tty_register_driver(rocket_driver);
2299 if (ret < 0) {
2300 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2301 goto err_controller;
2302 }
2303
2304#ifdef ROCKET_DEBUG_OPEN
2305 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2306#endif
2307
2308 /*
2309 * OK, let's probe each of the controllers looking for boards. Any boards found
2310 * will be initialized here.
2311 */
2312 isa_boards_found = 0;
2313 pci_boards_found = 0;
2314
2315 for (i = 0; i < NUM_BOARDS; i++) {
2316 if (init_ISA(i))
2317 isa_boards_found++;
2318 }
2319
2320#ifdef CONFIG_PCI
2321 if (isa_boards_found < NUM_BOARDS)
2322 pci_boards_found = init_PCI(isa_boards_found);
2323#endif
2324
2325 max_board = pci_boards_found + isa_boards_found;
2326
2327 if (max_board == 0) {
2328 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2329 ret = -ENXIO;
2330 goto err_ttyu;
2331 }
2332
2333 return 0;
2334err_ttyu:
2335 tty_unregister_driver(rocket_driver);
2336err_controller:
2337 if (controller)
2338 release_region(controller, 4);
2339err_tty:
2340 put_tty_driver(rocket_driver);
2341err:
2342 return ret;
2343}
2344
2345
2346static void rp_cleanup_module(void)
2347{
2348 int retval;
2349 int i;
2350
2351 del_timer_sync(&rocket_timer);
2352
2353 retval = tty_unregister_driver(rocket_driver);
2354 if (retval)
2355 printk(KERN_ERR "Error %d while trying to unregister "
2356 "rocketport driver\n", -retval);
2357
2358 for (i = 0; i < MAX_RP_PORTS; i++)
2359 if (rp_table[i]) {
2360 tty_unregister_device(rocket_driver, i);
2361 kfree(rp_table[i]);
2362 }
2363
2364 put_tty_driver(rocket_driver);
2365
2366 for (i = 0; i < NUM_BOARDS; i++) {
2367 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2368 continue;
2369 release_region(rcktpt_io_addr[i], 64);
2370 }
2371 if (controller)
2372 release_region(controller, 4);
2373}
2374
2375/***************************************************************************
2376Function: sInitController
2377Purpose: Initialization of controller global registers and controller
2378 structure.
2379Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2380 IRQNum,Frequency,PeriodicOnly)
2381 CONTROLLER_T *CtlP; Ptr to controller structure
2382 int CtlNum; Controller number
2383 ByteIO_t MudbacIO; Mudbac base I/O address.
2384 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2385 This list must be in the order the AIOPs will be found on the
2386 controller. Once an AIOP in the list is not found, it is
2387 assumed that there are no more AIOPs on the controller.
2388 int AiopIOListSize; Number of addresses in AiopIOList
2389 int IRQNum; Interrupt Request number. Can be any of the following:
2390 0: Disable global interrupts
2391 3: IRQ 3
2392 4: IRQ 4
2393 5: IRQ 5
2394 9: IRQ 9
2395 10: IRQ 10
2396 11: IRQ 11
2397 12: IRQ 12
2398 15: IRQ 15
2399 Byte_t Frequency: A flag identifying the frequency
2400 of the periodic interrupt, can be any one of the following:
2401 FREQ_DIS - periodic interrupt disabled
2402 FREQ_137HZ - 137 Hertz
2403 FREQ_69HZ - 69 Hertz
2404 FREQ_34HZ - 34 Hertz
2405 FREQ_17HZ - 17 Hertz
2406 FREQ_9HZ - 9 Hertz
2407 FREQ_4HZ - 4 Hertz
2408 If IRQNum is set to 0 the Frequency parameter is
2409 overidden, it is forced to a value of FREQ_DIS.
2410 int PeriodicOnly: 1 if all interrupts except the periodic
2411 interrupt are to be blocked.
2412 0 is both the periodic interrupt and
2413 other channel interrupts are allowed.
2414 If IRQNum is set to 0 the PeriodicOnly parameter is
2415 overidden, it is forced to a value of 0.
2416Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2417 initialization failed.
2418
2419Comments:
2420 If periodic interrupts are to be disabled but AIOP interrupts
2421 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2422
2423 If interrupts are to be completely disabled set IRQNum to 0.
2424
2425 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2426 invalid combination.
2427
2428 This function performs initialization of global interrupt modes,
2429 but it does not actually enable global interrupts. To enable
2430 and disable global interrupts use functions sEnGlobalInt() and
2431 sDisGlobalInt(). Enabling of global interrupts is normally not
2432 done until all other initializations are complete.
2433
2434 Even if interrupts are globally enabled, they must also be
2435 individually enabled for each channel that is to generate
2436 interrupts.
2437
2438Warnings: No range checking on any of the parameters is done.
2439
2440 No context switches are allowed while executing this function.
2441
2442 After this function all AIOPs on the controller are disabled,
2443 they can be enabled with sEnAiop().
2444*/
2445static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2446 ByteIO_t * AiopIOList, int AiopIOListSize,
2447 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2448{
2449 int i;
2450 ByteIO_t io;
2451 int done;
2452
2453 CtlP->AiopIntrBits = aiop_intr_bits;
2454 CtlP->AltChanRingIndicator = 0;
2455 CtlP->CtlNum = CtlNum;
2456 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2457 CtlP->BusType = isISA;
2458 CtlP->MBaseIO = MudbacIO;
2459 CtlP->MReg1IO = MudbacIO + 1;
2460 CtlP->MReg2IO = MudbacIO + 2;
2461 CtlP->MReg3IO = MudbacIO + 3;
2462#if 1
2463 CtlP->MReg2 = 0; /* interrupt disable */
2464 CtlP->MReg3 = 0; /* no periodic interrupts */
2465#else
2466 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2467 CtlP->MReg2 = 0; /* interrupt disable */
2468 CtlP->MReg3 = 0; /* no periodic interrupts */
2469 } else {
2470 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2471 CtlP->MReg3 = Frequency; /* set frequency */
2472 if (PeriodicOnly) { /* periodic interrupt only */
2473 CtlP->MReg3 |= PERIODIC_ONLY;
2474 }
2475 }
2476#endif
2477 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2478 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2479 sControllerEOI(CtlP); /* clear EOI if warm init */
2480 /* Init AIOPs */
2481 CtlP->NumAiop = 0;
2482 for (i = done = 0; i < AiopIOListSize; i++) {
2483 io = AiopIOList[i];
2484 CtlP->AiopIO[i] = (WordIO_t) io;
2485 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2486 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2487 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2488 if (done)
2489 continue;
2490 sEnAiop(CtlP, i); /* enable the AIOP */
2491 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2492 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2493 done = 1; /* done looking for AIOPs */
2494 else {
2495 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2496 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2497 sOutB(io + _INDX_DATA, sClockPrescale);
2498 CtlP->NumAiop++; /* bump count of AIOPs */
2499 }
2500 sDisAiop(CtlP, i); /* disable AIOP */
2501 }
2502
2503 if (CtlP->NumAiop == 0)
2504 return (-1);
2505 else
2506 return (CtlP->NumAiop);
2507}
2508
2509/***************************************************************************
2510Function: sPCIInitController
2511Purpose: Initialization of controller global registers and controller
2512 structure.
2513Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2514 IRQNum,Frequency,PeriodicOnly)
2515 CONTROLLER_T *CtlP; Ptr to controller structure
2516 int CtlNum; Controller number
2517 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2518 This list must be in the order the AIOPs will be found on the
2519 controller. Once an AIOP in the list is not found, it is
2520 assumed that there are no more AIOPs on the controller.
2521 int AiopIOListSize; Number of addresses in AiopIOList
2522 int IRQNum; Interrupt Request number. Can be any of the following:
2523 0: Disable global interrupts
2524 3: IRQ 3
2525 4: IRQ 4
2526 5: IRQ 5
2527 9: IRQ 9
2528 10: IRQ 10
2529 11: IRQ 11
2530 12: IRQ 12
2531 15: IRQ 15
2532 Byte_t Frequency: A flag identifying the frequency
2533 of the periodic interrupt, can be any one of the following:
2534 FREQ_DIS - periodic interrupt disabled
2535 FREQ_137HZ - 137 Hertz
2536 FREQ_69HZ - 69 Hertz
2537 FREQ_34HZ - 34 Hertz
2538 FREQ_17HZ - 17 Hertz
2539 FREQ_9HZ - 9 Hertz
2540 FREQ_4HZ - 4 Hertz
2541 If IRQNum is set to 0 the Frequency parameter is
2542 overidden, it is forced to a value of FREQ_DIS.
2543 int PeriodicOnly: 1 if all interrupts except the periodic
2544 interrupt are to be blocked.
2545 0 is both the periodic interrupt and
2546 other channel interrupts are allowed.
2547 If IRQNum is set to 0 the PeriodicOnly parameter is
2548 overidden, it is forced to a value of 0.
2549Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2550 initialization failed.
2551
2552Comments:
2553 If periodic interrupts are to be disabled but AIOP interrupts
2554 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2555
2556 If interrupts are to be completely disabled set IRQNum to 0.
2557
2558 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2559 invalid combination.
2560
2561 This function performs initialization of global interrupt modes,
2562 but it does not actually enable global interrupts. To enable
2563 and disable global interrupts use functions sEnGlobalInt() and
2564 sDisGlobalInt(). Enabling of global interrupts is normally not
2565 done until all other initializations are complete.
2566
2567 Even if interrupts are globally enabled, they must also be
2568 individually enabled for each channel that is to generate
2569 interrupts.
2570
2571Warnings: No range checking on any of the parameters is done.
2572
2573 No context switches are allowed while executing this function.
2574
2575 After this function all AIOPs on the controller are disabled,
2576 they can be enabled with sEnAiop().
2577*/
2578static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2579 ByteIO_t * AiopIOList, int AiopIOListSize,
2580 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2581 int PeriodicOnly, int altChanRingIndicator,
2582 int UPCIRingInd)
2583{
2584 int i;
2585 ByteIO_t io;
2586
2587 CtlP->AltChanRingIndicator = altChanRingIndicator;
2588 CtlP->UPCIRingInd = UPCIRingInd;
2589 CtlP->CtlNum = CtlNum;
2590 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2591 CtlP->BusType = isPCI; /* controller release 1 */
2592
2593 if (ConfigIO) {
2594 CtlP->isUPCI = 1;
2595 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2596 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2597 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2598 } else {
2599 CtlP->isUPCI = 0;
2600 CtlP->PCIIO =
2601 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2602 CtlP->AiopIntrBits = aiop_intr_bits;
2603 }
2604
2605 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2606 /* Init AIOPs */
2607 CtlP->NumAiop = 0;
2608 for (i = 0; i < AiopIOListSize; i++) {
2609 io = AiopIOList[i];
2610 CtlP->AiopIO[i] = (WordIO_t) io;
2611 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2612
2613 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2614 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2615 break; /* done looking for AIOPs */
2616
2617 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2618 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2619 sOutB(io + _INDX_DATA, sClockPrescale);
2620 CtlP->NumAiop++; /* bump count of AIOPs */
2621 }
2622
2623 if (CtlP->NumAiop == 0)
2624 return (-1);
2625 else
2626 return (CtlP->NumAiop);
2627}
2628
2629/***************************************************************************
2630Function: sReadAiopID
2631Purpose: Read the AIOP idenfication number directly from an AIOP.
2632Call: sReadAiopID(io)
2633 ByteIO_t io: AIOP base I/O address
2634Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2635 is replace by an identifying number.
2636 Flag AIOPID_NULL if no valid AIOP is found
2637Warnings: No context switches are allowed while executing this function.
2638
2639*/
2640static int sReadAiopID(ByteIO_t io)
2641{
2642 Byte_t AiopID; /* ID byte from AIOP */
2643
2644 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2645 sOutB(io + _CMD_REG, 0x0);
2646 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2647 if (AiopID == 0x06)
2648 return (1);
2649 else /* AIOP does not exist */
2650 return (-1);
2651}
2652
2653/***************************************************************************
2654Function: sReadAiopNumChan
2655Purpose: Read the number of channels available in an AIOP directly from
2656 an AIOP.
2657Call: sReadAiopNumChan(io)
2658 WordIO_t io: AIOP base I/O address
2659Return: int: The number of channels available
2660Comments: The number of channels is determined by write/reads from identical
2661 offsets within the SRAM address spaces for channels 0 and 4.
2662 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2663 AIOP, otherwise it is an 8 channel.
2664Warnings: No context switches are allowed while executing this function.
2665*/
2666static int sReadAiopNumChan(WordIO_t io)
2667{
2668 Word_t x;
2669 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2670
2671 /* write to chan 0 SRAM */
2672 out32((DWordIO_t) io + _INDX_ADDR, R);
2673 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2674 x = sInW(io + _INDX_DATA);
2675 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2676 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2677 return (8);
2678 else
2679 return (4);
2680}
2681
2682/***************************************************************************
2683Function: sInitChan
2684Purpose: Initialization of a channel and channel structure
2685Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2686 CONTROLLER_T *CtlP; Ptr to controller structure
2687 CHANNEL_T *ChP; Ptr to channel structure
2688 int AiopNum; AIOP number within controller
2689 int ChanNum; Channel number within AIOP
2690Return: int: 1 if initialization succeeded, 0 if it fails because channel
2691 number exceeds number of channels available in AIOP.
2692Comments: This function must be called before a channel can be used.
2693Warnings: No range checking on any of the parameters is done.
2694
2695 No context switches are allowed while executing this function.
2696*/
2697static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2698 int ChanNum)
2699{
2700 int i;
2701 WordIO_t AiopIO;
2702 WordIO_t ChIOOff;
2703 Byte_t *ChR;
2704 Word_t ChOff;
2705 static Byte_t R[4];
2706 int brd9600;
2707
2708 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2709 return 0; /* exceeds num chans in AIOP */
2710
2711 /* Channel, AIOP, and controller identifiers */
2712 ChP->CtlP = CtlP;
2713 ChP->ChanID = CtlP->AiopID[AiopNum];
2714 ChP->AiopNum = AiopNum;
2715 ChP->ChanNum = ChanNum;
2716
2717 /* Global direct addresses */
2718 AiopIO = CtlP->AiopIO[AiopNum];
2719 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2720 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2721 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2722 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2723 ChP->IndexData = AiopIO + _INDX_DATA;
2724
2725 /* Channel direct addresses */
2726 ChIOOff = AiopIO + ChP->ChanNum * 2;
2727 ChP->TxRxData = ChIOOff + _TD0;
2728 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2729 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2730 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2731
2732 /* Initialize the channel from the RData array */
2733 for (i = 0; i < RDATASIZE; i += 4) {
2734 R[0] = RData[i];
2735 R[1] = RData[i + 1] + 0x10 * ChanNum;
2736 R[2] = RData[i + 2];
2737 R[3] = RData[i + 3];
2738 out32(ChP->IndexAddr, R);
2739 }
2740
2741 ChR = ChP->R;
2742 for (i = 0; i < RREGDATASIZE; i += 4) {
2743 ChR[i] = RRegData[i];
2744 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2745 ChR[i + 2] = RRegData[i + 2];
2746 ChR[i + 3] = RRegData[i + 3];
2747 }
2748
2749 /* Indexed registers */
2750 ChOff = (Word_t) ChanNum *0x1000;
2751
2752 if (sClockPrescale == 0x14)
2753 brd9600 = 47;
2754 else
2755 brd9600 = 23;
2756
2757 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2758 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2759 ChP->BaudDiv[2] = (Byte_t) brd9600;
2760 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2761 out32(ChP->IndexAddr, ChP->BaudDiv);
2762
2763 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2764 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2765 ChP->TxControl[2] = 0;
2766 ChP->TxControl[3] = 0;
2767 out32(ChP->IndexAddr, ChP->TxControl);
2768
2769 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2770 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2771 ChP->RxControl[2] = 0;
2772 ChP->RxControl[3] = 0;
2773 out32(ChP->IndexAddr, ChP->RxControl);
2774
2775 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2776 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2777 ChP->TxEnables[2] = 0;
2778 ChP->TxEnables[3] = 0;
2779 out32(ChP->IndexAddr, ChP->TxEnables);
2780
2781 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2782 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2783 ChP->TxCompare[2] = 0;
2784 ChP->TxCompare[3] = 0;
2785 out32(ChP->IndexAddr, ChP->TxCompare);
2786
2787 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2788 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2789 ChP->TxReplace1[2] = 0;
2790 ChP->TxReplace1[3] = 0;
2791 out32(ChP->IndexAddr, ChP->TxReplace1);
2792
2793 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2794 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2795 ChP->TxReplace2[2] = 0;
2796 ChP->TxReplace2[3] = 0;
2797 out32(ChP->IndexAddr, ChP->TxReplace2);
2798
2799 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2800 ChP->TxFIFO = ChOff + _TX_FIFO;
2801
2802 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2803 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2804 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2805 sOutW(ChP->IndexData, 0);
2806 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2807 ChP->RxFIFO = ChOff + _RX_FIFO;
2808
2809 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2810 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2811 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2812 sOutW(ChP->IndexData, 0);
2813 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2814 sOutW(ChP->IndexData, 0);
2815 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2816 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2817 sOutB(ChP->IndexData, 0);
2818 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2819 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2820 sOutB(ChP->IndexData, 0);
2821 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2822 sEnRxProcessor(ChP); /* start the Rx processor */
2823
2824 return 1;
2825}
2826
2827/***************************************************************************
2828Function: sStopRxProcessor
2829Purpose: Stop the receive processor from processing a channel.
2830Call: sStopRxProcessor(ChP)
2831 CHANNEL_T *ChP; Ptr to channel structure
2832
2833Comments: The receive processor can be started again with sStartRxProcessor().
2834 This function causes the receive processor to skip over the
2835 stopped channel. It does not stop it from processing other channels.
2836
2837Warnings: No context switches are allowed while executing this function.
2838
2839 Do not leave the receive processor stopped for more than one
2840 character time.
2841
2842 After calling this function a delay of 4 uS is required to ensure
2843 that the receive processor is no longer processing this channel.
2844*/
2845static void sStopRxProcessor(CHANNEL_T * ChP)
2846{
2847 Byte_t R[4];
2848
2849 R[0] = ChP->R[0];
2850 R[1] = ChP->R[1];
2851 R[2] = 0x0a;
2852 R[3] = ChP->R[3];
2853 out32(ChP->IndexAddr, R);
2854}
2855
2856/***************************************************************************
2857Function: sFlushRxFIFO
2858Purpose: Flush the Rx FIFO
2859Call: sFlushRxFIFO(ChP)
2860 CHANNEL_T *ChP; Ptr to channel structure
2861Return: void
2862Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2863 while it is being flushed the receive processor is stopped
2864 and the transmitter is disabled. After these operations a
2865 4 uS delay is done before clearing the pointers to allow
2866 the receive processor to stop. These items are handled inside
2867 this function.
2868Warnings: No context switches are allowed while executing this function.
2869*/
2870static void sFlushRxFIFO(CHANNEL_T * ChP)
2871{
2872 int i;
2873 Byte_t Ch; /* channel number within AIOP */
2874 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2875
2876 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2877 return; /* don't need to flush */
2878
2879 RxFIFOEnabled = 0;
2880 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2881 RxFIFOEnabled = 1;
2882 sDisRxFIFO(ChP); /* disable it */
2883 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2884 sInB(ChP->IntChan); /* depends on bus i/o timing */
2885 }
2886 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2887 Ch = (Byte_t) sGetChanNum(ChP);
2888 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2889 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2890 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2891 sOutW(ChP->IndexData, 0);
2892 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2893 sOutW(ChP->IndexData, 0);
2894 if (RxFIFOEnabled)
2895 sEnRxFIFO(ChP); /* enable Rx FIFO */
2896}
2897
2898/***************************************************************************
2899Function: sFlushTxFIFO
2900Purpose: Flush the Tx FIFO
2901Call: sFlushTxFIFO(ChP)
2902 CHANNEL_T *ChP; Ptr to channel structure
2903Return: void
2904Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2905 while it is being flushed the receive processor is stopped
2906 and the transmitter is disabled. After these operations a
2907 4 uS delay is done before clearing the pointers to allow
2908 the receive processor to stop. These items are handled inside
2909 this function.
2910Warnings: No context switches are allowed while executing this function.
2911*/
2912static void sFlushTxFIFO(CHANNEL_T * ChP)
2913{
2914 int i;
2915 Byte_t Ch; /* channel number within AIOP */
2916 int TxEnabled; /* 1 if transmitter enabled */
2917
2918 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2919 return; /* don't need to flush */
2920
2921 TxEnabled = 0;
2922 if (ChP->TxControl[3] & TX_ENABLE) {
2923 TxEnabled = 1;
2924 sDisTransmit(ChP); /* disable transmitter */
2925 }
2926 sStopRxProcessor(ChP); /* stop Rx processor */
2927 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2928 sInB(ChP->IntChan); /* depends on bus i/o timing */
2929 Ch = (Byte_t) sGetChanNum(ChP);
2930 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2931 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2932 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2933 sOutW(ChP->IndexData, 0);
2934 if (TxEnabled)
2935 sEnTransmit(ChP); /* enable transmitter */
2936 sStartRxProcessor(ChP); /* restart Rx processor */
2937}
2938
2939/***************************************************************************
2940Function: sWriteTxPrioByte
2941Purpose: Write a byte of priority transmit data to a channel
2942Call: sWriteTxPrioByte(ChP,Data)
2943 CHANNEL_T *ChP; Ptr to channel structure
2944 Byte_t Data; The transmit data byte
2945
2946Return: int: 1 if the bytes is successfully written, otherwise 0.
2947
2948Comments: The priority byte is transmitted before any data in the Tx FIFO.
2949
2950Warnings: No context switches are allowed while executing this function.
2951*/
2952static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2953{
2954 Byte_t DWBuf[4]; /* buffer for double word writes */
2955 Word_t *WordPtr; /* must be far because Win SS != DS */
2956 register DWordIO_t IndexAddr;
2957
2958 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2959 IndexAddr = ChP->IndexAddr;
2960 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2961 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2962 return (0); /* nothing sent */
2963
2964 WordPtr = (Word_t *) (&DWBuf[0]);
2965 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2966
2967 DWBuf[2] = Data; /* data byte value */
2968 out32(IndexAddr, DWBuf); /* write it out */
2969
2970 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2971
2972 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2973 DWBuf[3] = 0; /* priority buffer pointer */
2974 out32(IndexAddr, DWBuf); /* write it out */
2975 } else { /* write it to Tx FIFO */
2976
2977 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2978 }
2979 return (1); /* 1 byte sent */
2980}
2981
2982/***************************************************************************
2983Function: sEnInterrupts
2984Purpose: Enable one or more interrupts for a channel
2985Call: sEnInterrupts(ChP,Flags)
2986 CHANNEL_T *ChP; Ptr to channel structure
2987 Word_t Flags: Interrupt enable flags, can be any combination
2988 of the following flags:
2989 TXINT_EN: Interrupt on Tx FIFO empty
2990 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
2991 sSetRxTrigger())
2992 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
2993 MCINT_EN: Interrupt on modem input change
2994 CHANINT_EN: Allow channel interrupt signal to the AIOP's
2995 Interrupt Channel Register.
2996Return: void
2997Comments: If an interrupt enable flag is set in Flags, that interrupt will be
2998 enabled. If an interrupt enable flag is not set in Flags, that
2999 interrupt will not be changed. Interrupts can be disabled with
3000 function sDisInterrupts().
3001
3002 This function sets the appropriate bit for the channel in the AIOP's
3003 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3004 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3005
3006 Interrupts must also be globally enabled before channel interrupts
3007 will be passed on to the host. This is done with function
3008 sEnGlobalInt().
3009
3010 In some cases it may be desirable to disable interrupts globally but
3011 enable channel interrupts. This would allow the global interrupt
3012 status register to be used to determine which AIOPs need service.
3013*/
3014static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3015{
3016 Byte_t Mask; /* Interrupt Mask Register */
3017
3018 ChP->RxControl[2] |=
3019 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3020
3021 out32(ChP->IndexAddr, ChP->RxControl);
3022
3023 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3024
3025 out32(ChP->IndexAddr, ChP->TxControl);
3026
3027 if (Flags & CHANINT_EN) {
3028 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3029 sOutB(ChP->IntMask, Mask);
3030 }
3031}
3032
3033/***************************************************************************
3034Function: sDisInterrupts
3035Purpose: Disable one or more interrupts for a channel
3036Call: sDisInterrupts(ChP,Flags)
3037 CHANNEL_T *ChP; Ptr to channel structure
3038 Word_t Flags: Interrupt flags, can be any combination
3039 of the following flags:
3040 TXINT_EN: Interrupt on Tx FIFO empty
3041 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3042 sSetRxTrigger())
3043 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3044 MCINT_EN: Interrupt on modem input change
3045 CHANINT_EN: Disable channel interrupt signal to the
3046 AIOP's Interrupt Channel Register.
3047Return: void
3048Comments: If an interrupt flag is set in Flags, that interrupt will be
3049 disabled. If an interrupt flag is not set in Flags, that
3050 interrupt will not be changed. Interrupts can be enabled with
3051 function sEnInterrupts().
3052
3053 This function clears the appropriate bit for the channel in the AIOP's
3054 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3055 this channel's bit from being set in the AIOP's Interrupt Channel
3056 Register.
3057*/
3058static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3059{
3060 Byte_t Mask; /* Interrupt Mask Register */
3061
3062 ChP->RxControl[2] &=
3063 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3064 out32(ChP->IndexAddr, ChP->RxControl);
3065 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3066 out32(ChP->IndexAddr, ChP->TxControl);
3067
3068 if (Flags & CHANINT_EN) {
3069 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3070 sOutB(ChP->IntMask, Mask);
3071 }
3072}
3073
3074static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3075{
3076 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3077}
3078
3079/*
3080 * Not an official SSCI function, but how to reset RocketModems.
3081 * ISA bus version
3082 */
3083static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3084{
3085 ByteIO_t addr;
3086 Byte_t val;
3087
3088 addr = CtlP->AiopIO[0] + 0x400;
3089 val = sInB(CtlP->MReg3IO);
3090 /* if AIOP[1] is not enabled, enable it */
3091 if ((val & 2) == 0) {
3092 val = sInB(CtlP->MReg2IO);
3093 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3094 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3095 }
3096
3097 sEnAiop(CtlP, 1);
3098 if (!on)
3099 addr += 8;
3100 sOutB(addr + chan, 0); /* apply or remove reset */
3101 sDisAiop(CtlP, 1);
3102}
3103
3104/*
3105 * Not an official SSCI function, but how to reset RocketModems.
3106 * PCI bus version
3107 */
3108static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3109{
3110 ByteIO_t addr;
3111
3112 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3113 if (!on)
3114 addr += 8;
3115 sOutB(addr + chan, 0); /* apply or remove reset */
3116}
3117
3118/* Resets the speaker controller on RocketModem II and III devices */
3119static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3120{
3121 ByteIO_t addr;
3122
3123 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3124 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3125 addr = CtlP->AiopIO[0] + 0x4F;
3126 sOutB(addr, 0);
3127 }
3128
3129 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3130 if ((model == MODEL_UPCI_RM3_8PORT)
3131 || (model == MODEL_UPCI_RM3_4PORT)) {
3132 addr = CtlP->AiopIO[0] + 0x88;
3133 sOutB(addr, 0);
3134 }
3135}
3136
3137/* Returns the line number given the controller (board), aiop and channel number */
3138static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3139{
3140 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3141}
3142
3143/*
3144 * Stores the line number associated with a given controller (board), aiop
3145 * and channel number.
3146 * Returns: The line number assigned
3147 */
3148static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3149{
3150 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3151 return (nextLineNumber - 1);
3152}
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * RocketPort device driver for Linux
4 *
5 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 *
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 */
9
10/*
11 * Kernel Synchronization:
12 *
13 * This driver has 2 kernel control paths - exception handlers (calls into the driver
14 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
15 * are not used.
16 *
17 * Critical data:
18 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
19 * serial port state information and the xmit_buf circular buffer. Protected by
20 * a per port spinlock.
21 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
22 * is data to be transmitted. Protected by atomic bit operations.
23 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
24 *
25 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
26 * simultaneous access to the same port by more than one process.
27 */
28
29/****** Defines ******/
30#define ROCKET_PARANOIA_CHECK
31#define ROCKET_DISABLE_SIMUSAGE
32
33#undef ROCKET_SOFT_FLOW
34#undef ROCKET_DEBUG_OPEN
35#undef ROCKET_DEBUG_INTR
36#undef ROCKET_DEBUG_WRITE
37#undef ROCKET_DEBUG_FLOW
38#undef ROCKET_DEBUG_THROTTLE
39#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
40#undef ROCKET_DEBUG_RECEIVE
41#undef ROCKET_DEBUG_HANGUP
42#undef REV_PCI_ORDER
43#undef ROCKET_DEBUG_IO
44
45#define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
46
47/****** Kernel includes ******/
48
49#include <linux/module.h>
50#include <linux/errno.h>
51#include <linux/major.h>
52#include <linux/kernel.h>
53#include <linux/signal.h>
54#include <linux/slab.h>
55#include <linux/mm.h>
56#include <linux/sched.h>
57#include <linux/timer.h>
58#include <linux/interrupt.h>
59#include <linux/tty.h>
60#include <linux/tty_driver.h>
61#include <linux/tty_flip.h>
62#include <linux/serial.h>
63#include <linux/string.h>
64#include <linux/fcntl.h>
65#include <linux/ptrace.h>
66#include <linux/mutex.h>
67#include <linux/ioport.h>
68#include <linux/delay.h>
69#include <linux/completion.h>
70#include <linux/wait.h>
71#include <linux/pci.h>
72#include <linux/uaccess.h>
73#include <linux/atomic.h>
74#include <asm/unaligned.h>
75#include <linux/bitops.h>
76#include <linux/spinlock.h>
77#include <linux/init.h>
78
79/****** RocketPort includes ******/
80
81#include "rocket_int.h"
82#include "rocket.h"
83
84#define ROCKET_VERSION "2.09"
85#define ROCKET_DATE "12-June-2003"
86
87/****** RocketPort Local Variables ******/
88
89static void rp_do_poll(struct timer_list *unused);
90
91static struct tty_driver *rocket_driver;
92
93static struct rocket_version driver_version = {
94 ROCKET_VERSION, ROCKET_DATE
95};
96
97static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
98static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
99 /* eg. Bit 0 indicates port 0 has xmit data, ... */
100static atomic_t rp_num_ports_open; /* Number of serial ports open */
101static DEFINE_TIMER(rocket_timer, rp_do_poll);
102
103static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
104static unsigned long board2;
105static unsigned long board3;
106static unsigned long board4;
107static unsigned long controller;
108static bool support_low_speed;
109static unsigned long modem1;
110static unsigned long modem2;
111static unsigned long modem3;
112static unsigned long modem4;
113static unsigned long pc104_1[8];
114static unsigned long pc104_2[8];
115static unsigned long pc104_3[8];
116static unsigned long pc104_4[8];
117static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
118
119static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
120static unsigned long rcktpt_io_addr[NUM_BOARDS];
121static int rcktpt_type[NUM_BOARDS];
122static int is_PCI[NUM_BOARDS];
123static rocketModel_t rocketModel[NUM_BOARDS];
124static int max_board;
125static const struct tty_port_operations rocket_port_ops;
126
127/*
128 * The following arrays define the interrupt bits corresponding to each AIOP.
129 * These bits are different between the ISA and regular PCI boards and the
130 * Universal PCI boards.
131 */
132
133static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
134 AIOP_INTR_BIT_0,
135 AIOP_INTR_BIT_1,
136 AIOP_INTR_BIT_2,
137 AIOP_INTR_BIT_3
138};
139
140#ifdef CONFIG_PCI
141static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
142 UPCI_AIOP_INTR_BIT_0,
143 UPCI_AIOP_INTR_BIT_1,
144 UPCI_AIOP_INTR_BIT_2,
145 UPCI_AIOP_INTR_BIT_3
146};
147#endif
148
149static Byte_t RData[RDATASIZE] = {
150 0x00, 0x09, 0xf6, 0x82,
151 0x02, 0x09, 0x86, 0xfb,
152 0x04, 0x09, 0x00, 0x0a,
153 0x06, 0x09, 0x01, 0x0a,
154 0x08, 0x09, 0x8a, 0x13,
155 0x0a, 0x09, 0xc5, 0x11,
156 0x0c, 0x09, 0x86, 0x85,
157 0x0e, 0x09, 0x20, 0x0a,
158 0x10, 0x09, 0x21, 0x0a,
159 0x12, 0x09, 0x41, 0xff,
160 0x14, 0x09, 0x82, 0x00,
161 0x16, 0x09, 0x82, 0x7b,
162 0x18, 0x09, 0x8a, 0x7d,
163 0x1a, 0x09, 0x88, 0x81,
164 0x1c, 0x09, 0x86, 0x7a,
165 0x1e, 0x09, 0x84, 0x81,
166 0x20, 0x09, 0x82, 0x7c,
167 0x22, 0x09, 0x0a, 0x0a
168};
169
170static Byte_t RRegData[RREGDATASIZE] = {
171 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
172 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
173 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
174 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
175 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
176 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
177 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
178 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
179 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
180 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
181 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
182 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
183 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
184};
185
186static CONTROLLER_T sController[CTL_SIZE] = {
187 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
188 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
189 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
190 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
191 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
192 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
193 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
194 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
195};
196
197static Byte_t sBitMapClrTbl[8] = {
198 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
199};
200
201static Byte_t sBitMapSetTbl[8] = {
202 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
203};
204
205static int sClockPrescale = 0x14;
206
207/*
208 * Line number is the ttySIx number (x), the Minor number. We
209 * assign them sequentially, starting at zero. The following
210 * array keeps track of the line number assigned to a given board/aiop/channel.
211 */
212static unsigned char lineNumbers[MAX_RP_PORTS];
213static unsigned long nextLineNumber;
214
215/***** RocketPort Static Prototypes *********/
216static int __init init_ISA(int i);
217static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
218static void rp_flush_buffer(struct tty_struct *tty);
219static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
220static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
221static void rp_start(struct tty_struct *tty);
222static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
223 int ChanNum);
224static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
225static void sFlushRxFIFO(CHANNEL_T * ChP);
226static void sFlushTxFIFO(CHANNEL_T * ChP);
227static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
228static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
229static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
230static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
231static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
232static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
233 ByteIO_t * AiopIOList, int AiopIOListSize,
234 int IRQNum, Byte_t Frequency, int PeriodicOnly);
235static int sReadAiopID(ByteIO_t io);
236static int sReadAiopNumChan(WordIO_t io);
237
238MODULE_AUTHOR("Theodore Ts'o");
239MODULE_DESCRIPTION("Comtrol RocketPort driver");
240module_param_hw(board1, ulong, ioport, 0);
241MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
242module_param_hw(board2, ulong, ioport, 0);
243MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
244module_param_hw(board3, ulong, ioport, 0);
245MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
246module_param_hw(board4, ulong, ioport, 0);
247MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
248module_param_hw(controller, ulong, ioport, 0);
249MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
250module_param(support_low_speed, bool, 0);
251MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
252module_param(modem1, ulong, 0);
253MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
254module_param(modem2, ulong, 0);
255MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
256module_param(modem3, ulong, 0);
257MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
258module_param(modem4, ulong, 0);
259MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
260module_param_array(pc104_1, ulong, NULL, 0);
261MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
262module_param_array(pc104_2, ulong, NULL, 0);
263MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
264module_param_array(pc104_3, ulong, NULL, 0);
265MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
266module_param_array(pc104_4, ulong, NULL, 0);
267MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
268
269static int rp_init(void);
270static void rp_cleanup_module(void);
271
272module_init(rp_init);
273module_exit(rp_cleanup_module);
274
275
276MODULE_LICENSE("Dual BSD/GPL");
277
278/*************************************************************************/
279/* Module code starts here */
280
281static inline int rocket_paranoia_check(struct r_port *info,
282 const char *routine)
283{
284#ifdef ROCKET_PARANOIA_CHECK
285 if (!info)
286 return 1;
287 if (info->magic != RPORT_MAGIC) {
288 printk(KERN_WARNING "Warning: bad magic number for rocketport "
289 "struct in %s\n", routine);
290 return 1;
291 }
292#endif
293 return 0;
294}
295
296
297/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
298 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
299 * tty layer.
300 */
301static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
302 unsigned int ChanStatus)
303{
304 unsigned int CharNStat;
305 int ToRecv, wRecv, space;
306 unsigned char *cbuf;
307
308 ToRecv = sGetRxCnt(cp);
309#ifdef ROCKET_DEBUG_INTR
310 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
311#endif
312 if (ToRecv == 0)
313 return;
314
315 /*
316 * if status indicates there are errored characters in the
317 * FIFO, then enter status mode (a word in FIFO holds
318 * character and status).
319 */
320 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
321 if (!(ChanStatus & STATMODE)) {
322#ifdef ROCKET_DEBUG_RECEIVE
323 printk(KERN_INFO "Entering STATMODE...\n");
324#endif
325 ChanStatus |= STATMODE;
326 sEnRxStatusMode(cp);
327 }
328 }
329
330 /*
331 * if we previously entered status mode, then read down the
332 * FIFO one word at a time, pulling apart the character and
333 * the status. Update error counters depending on status
334 */
335 if (ChanStatus & STATMODE) {
336#ifdef ROCKET_DEBUG_RECEIVE
337 printk(KERN_INFO "Ignore %x, read %x...\n",
338 info->ignore_status_mask, info->read_status_mask);
339#endif
340 while (ToRecv) {
341 char flag;
342
343 CharNStat = sInW(sGetTxRxDataIO(cp));
344#ifdef ROCKET_DEBUG_RECEIVE
345 printk(KERN_INFO "%x...\n", CharNStat);
346#endif
347 if (CharNStat & STMBREAKH)
348 CharNStat &= ~(STMFRAMEH | STMPARITYH);
349 if (CharNStat & info->ignore_status_mask) {
350 ToRecv--;
351 continue;
352 }
353 CharNStat &= info->read_status_mask;
354 if (CharNStat & STMBREAKH)
355 flag = TTY_BREAK;
356 else if (CharNStat & STMPARITYH)
357 flag = TTY_PARITY;
358 else if (CharNStat & STMFRAMEH)
359 flag = TTY_FRAME;
360 else if (CharNStat & STMRCVROVRH)
361 flag = TTY_OVERRUN;
362 else
363 flag = TTY_NORMAL;
364 tty_insert_flip_char(&info->port, CharNStat & 0xff,
365 flag);
366 ToRecv--;
367 }
368
369 /*
370 * after we've emptied the FIFO in status mode, turn
371 * status mode back off
372 */
373 if (sGetRxCnt(cp) == 0) {
374#ifdef ROCKET_DEBUG_RECEIVE
375 printk(KERN_INFO "Status mode off.\n");
376#endif
377 sDisRxStatusMode(cp);
378 }
379 } else {
380 /*
381 * we aren't in status mode, so read down the FIFO two
382 * characters at time by doing repeated word IO
383 * transfer.
384 */
385 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
386 if (space < ToRecv) {
387#ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
389#endif
390 if (space <= 0)
391 return;
392 ToRecv = space;
393 }
394 wRecv = ToRecv >> 1;
395 if (wRecv)
396 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
397 if (ToRecv & 1)
398 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
399 }
400 /* Push the data up to the tty layer */
401 tty_flip_buffer_push(&info->port);
402}
403
404/*
405 * Serial port transmit data function. Called from the timer polling loop as a
406 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
407 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
408 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
409 */
410static void rp_do_transmit(struct r_port *info)
411{
412 int c;
413 CHANNEL_t *cp = &info->channel;
414 struct tty_struct *tty;
415 unsigned long flags;
416
417#ifdef ROCKET_DEBUG_INTR
418 printk(KERN_DEBUG "%s\n", __func__);
419#endif
420 if (!info)
421 return;
422 tty = tty_port_tty_get(&info->port);
423
424 if (tty == NULL) {
425 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
426 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
427 return;
428 }
429
430 spin_lock_irqsave(&info->slock, flags);
431 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
432
433 /* Loop sending data to FIFO until done or FIFO full */
434 while (1) {
435 if (tty->stopped)
436 break;
437 c = min(info->xmit_fifo_room, info->xmit_cnt);
438 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
439 if (c <= 0 || info->xmit_fifo_room <= 0)
440 break;
441 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
442 if (c & 1)
443 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
444 info->xmit_tail += c;
445 info->xmit_tail &= XMIT_BUF_SIZE - 1;
446 info->xmit_cnt -= c;
447 info->xmit_fifo_room -= c;
448#ifdef ROCKET_DEBUG_INTR
449 printk(KERN_INFO "tx %d chars...\n", c);
450#endif
451 }
452
453 if (info->xmit_cnt == 0)
454 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
455
456 if (info->xmit_cnt < WAKEUP_CHARS) {
457 tty_wakeup(tty);
458#ifdef ROCKETPORT_HAVE_POLL_WAIT
459 wake_up_interruptible(&tty->poll_wait);
460#endif
461 }
462
463 spin_unlock_irqrestore(&info->slock, flags);
464 tty_kref_put(tty);
465
466#ifdef ROCKET_DEBUG_INTR
467 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
468 info->xmit_tail, info->xmit_fifo_room);
469#endif
470}
471
472/*
473 * Called when a serial port signals it has read data in it's RX FIFO.
474 * It checks what interrupts are pending and services them, including
475 * receiving serial data.
476 */
477static void rp_handle_port(struct r_port *info)
478{
479 CHANNEL_t *cp;
480 unsigned int IntMask, ChanStatus;
481
482 if (!info)
483 return;
484
485 if (!tty_port_initialized(&info->port)) {
486 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
487 "info->flags & NOT_INIT\n");
488 return;
489 }
490
491 cp = &info->channel;
492
493 IntMask = sGetChanIntID(cp) & info->intmask;
494#ifdef ROCKET_DEBUG_INTR
495 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
496#endif
497 ChanStatus = sGetChanStatus(cp);
498 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
499 rp_do_receive(info, cp, ChanStatus);
500 }
501 if (IntMask & DELTA_CD) { /* CD change */
502#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
503 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
504 (ChanStatus & CD_ACT) ? "on" : "off");
505#endif
506 if (!(ChanStatus & CD_ACT) && info->cd_status) {
507#ifdef ROCKET_DEBUG_HANGUP
508 printk(KERN_INFO "CD drop, calling hangup.\n");
509#endif
510 tty_port_tty_hangup(&info->port, false);
511 }
512 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
513 wake_up_interruptible(&info->port.open_wait);
514 }
515#ifdef ROCKET_DEBUG_INTR
516 if (IntMask & DELTA_CTS) { /* CTS change */
517 printk(KERN_INFO "CTS change...\n");
518 }
519 if (IntMask & DELTA_DSR) { /* DSR change */
520 printk(KERN_INFO "DSR change...\n");
521 }
522#endif
523}
524
525/*
526 * The top level polling routine. Repeats every 1/100 HZ (10ms).
527 */
528static void rp_do_poll(struct timer_list *unused)
529{
530 CONTROLLER_t *ctlp;
531 int ctrl, aiop, ch, line;
532 unsigned int xmitmask, i;
533 unsigned int CtlMask;
534 unsigned char AiopMask;
535 Word_t bit;
536
537 /* Walk through all the boards (ctrl's) */
538 for (ctrl = 0; ctrl < max_board; ctrl++) {
539 if (rcktpt_io_addr[ctrl] <= 0)
540 continue;
541
542 /* Get a ptr to the board's control struct */
543 ctlp = sCtlNumToCtlPtr(ctrl);
544
545 /* Get the interrupt status from the board */
546#ifdef CONFIG_PCI
547 if (ctlp->BusType == isPCI)
548 CtlMask = sPCIGetControllerIntStatus(ctlp);
549 else
550#endif
551 CtlMask = sGetControllerIntStatus(ctlp);
552
553 /* Check if any AIOP read bits are set */
554 for (aiop = 0; CtlMask; aiop++) {
555 bit = ctlp->AiopIntrBits[aiop];
556 if (CtlMask & bit) {
557 CtlMask &= ~bit;
558 AiopMask = sGetAiopIntStatus(ctlp, aiop);
559
560 /* Check if any port read bits are set */
561 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
562 if (AiopMask & 1) {
563
564 /* Get the line number (/dev/ttyRx number). */
565 /* Read the data from the port. */
566 line = GetLineNumber(ctrl, aiop, ch);
567 rp_handle_port(rp_table[line]);
568 }
569 }
570 }
571 }
572
573 xmitmask = xmit_flags[ctrl];
574
575 /*
576 * xmit_flags contains bit-significant flags, indicating there is data
577 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
578 * 1, ... (32 total possible). The variable i has the aiop and ch
579 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
580 */
581 if (xmitmask) {
582 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
583 if (xmitmask & (1 << i)) {
584 aiop = (i & 0x18) >> 3;
585 ch = i & 0x07;
586 line = GetLineNumber(ctrl, aiop, ch);
587 rp_do_transmit(rp_table[line]);
588 }
589 }
590 }
591 }
592
593 /*
594 * Reset the timer so we get called at the next clock tick (10ms).
595 */
596 if (atomic_read(&rp_num_ports_open))
597 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
598}
599
600/*
601 * Initializes the r_port structure for a port, as well as enabling the port on
602 * the board.
603 * Inputs: board, aiop, chan numbers
604 */
605static void __init
606init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
607{
608 unsigned rocketMode;
609 struct r_port *info;
610 int line;
611 CONTROLLER_T *ctlp;
612
613 /* Get the next available line number */
614 line = SetLineNumber(board, aiop, chan);
615
616 ctlp = sCtlNumToCtlPtr(board);
617
618 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
619 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
620 if (!info) {
621 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
622 line);
623 return;
624 }
625
626 info->magic = RPORT_MAGIC;
627 info->line = line;
628 info->ctlp = ctlp;
629 info->board = board;
630 info->aiop = aiop;
631 info->chan = chan;
632 tty_port_init(&info->port);
633 info->port.ops = &rocket_port_ops;
634 info->flags &= ~ROCKET_MODE_MASK;
635 switch (pc104[board][line]) {
636 case 422:
637 info->flags |= ROCKET_MODE_RS422;
638 break;
639 case 485:
640 info->flags |= ROCKET_MODE_RS485;
641 break;
642 case 232:
643 default:
644 info->flags |= ROCKET_MODE_RS232;
645 break;
646 }
647
648 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
649 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
650 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
651 board, aiop, chan);
652 tty_port_destroy(&info->port);
653 kfree(info);
654 return;
655 }
656
657 rocketMode = info->flags & ROCKET_MODE_MASK;
658
659 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
660 sEnRTSToggle(&info->channel);
661 else
662 sDisRTSToggle(&info->channel);
663
664 if (ctlp->boardType == ROCKET_TYPE_PC104) {
665 switch (rocketMode) {
666 case ROCKET_MODE_RS485:
667 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
668 break;
669 case ROCKET_MODE_RS422:
670 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
671 break;
672 case ROCKET_MODE_RS232:
673 default:
674 if (info->flags & ROCKET_RTS_TOGGLE)
675 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
676 else
677 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
678 break;
679 }
680 }
681 spin_lock_init(&info->slock);
682 mutex_init(&info->write_mtx);
683 rp_table[line] = info;
684 tty_port_register_device(&info->port, rocket_driver, line,
685 pci_dev ? &pci_dev->dev : NULL);
686}
687
688/*
689 * Configures a rocketport port according to its termio settings. Called from
690 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
691 */
692static void configure_r_port(struct tty_struct *tty, struct r_port *info,
693 struct ktermios *old_termios)
694{
695 unsigned cflag;
696 unsigned long flags;
697 unsigned rocketMode;
698 int bits, baud, divisor;
699 CHANNEL_t *cp;
700 struct ktermios *t = &tty->termios;
701
702 cp = &info->channel;
703 cflag = t->c_cflag;
704
705 /* Byte size and parity */
706 if ((cflag & CSIZE) == CS8) {
707 sSetData8(cp);
708 bits = 10;
709 } else {
710 sSetData7(cp);
711 bits = 9;
712 }
713 if (cflag & CSTOPB) {
714 sSetStop2(cp);
715 bits++;
716 } else {
717 sSetStop1(cp);
718 }
719
720 if (cflag & PARENB) {
721 sEnParity(cp);
722 bits++;
723 if (cflag & PARODD) {
724 sSetOddParity(cp);
725 } else {
726 sSetEvenParity(cp);
727 }
728 } else {
729 sDisParity(cp);
730 }
731
732 /* baud rate */
733 baud = tty_get_baud_rate(tty);
734 if (!baud)
735 baud = 9600;
736 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
737 if ((divisor >= 8192 || divisor < 0) && old_termios) {
738 baud = tty_termios_baud_rate(old_termios);
739 if (!baud)
740 baud = 9600;
741 divisor = (rp_baud_base[info->board] / baud) - 1;
742 }
743 if (divisor >= 8192 || divisor < 0) {
744 baud = 9600;
745 divisor = (rp_baud_base[info->board] / baud) - 1;
746 }
747 info->cps = baud / bits;
748 sSetBaud(cp, divisor);
749
750 /* FIXME: Should really back compute a baud rate from the divisor */
751 tty_encode_baud_rate(tty, baud, baud);
752
753 if (cflag & CRTSCTS) {
754 info->intmask |= DELTA_CTS;
755 sEnCTSFlowCtl(cp);
756 } else {
757 info->intmask &= ~DELTA_CTS;
758 sDisCTSFlowCtl(cp);
759 }
760 if (cflag & CLOCAL) {
761 info->intmask &= ~DELTA_CD;
762 } else {
763 spin_lock_irqsave(&info->slock, flags);
764 if (sGetChanStatus(cp) & CD_ACT)
765 info->cd_status = 1;
766 else
767 info->cd_status = 0;
768 info->intmask |= DELTA_CD;
769 spin_unlock_irqrestore(&info->slock, flags);
770 }
771
772 /*
773 * Handle software flow control in the board
774 */
775#ifdef ROCKET_SOFT_FLOW
776 if (I_IXON(tty)) {
777 sEnTxSoftFlowCtl(cp);
778 if (I_IXANY(tty)) {
779 sEnIXANY(cp);
780 } else {
781 sDisIXANY(cp);
782 }
783 sSetTxXONChar(cp, START_CHAR(tty));
784 sSetTxXOFFChar(cp, STOP_CHAR(tty));
785 } else {
786 sDisTxSoftFlowCtl(cp);
787 sDisIXANY(cp);
788 sClrTxXOFF(cp);
789 }
790#endif
791
792 /*
793 * Set up ignore/read mask words
794 */
795 info->read_status_mask = STMRCVROVRH | 0xFF;
796 if (I_INPCK(tty))
797 info->read_status_mask |= STMFRAMEH | STMPARITYH;
798 if (I_BRKINT(tty) || I_PARMRK(tty))
799 info->read_status_mask |= STMBREAKH;
800
801 /*
802 * Characters to ignore
803 */
804 info->ignore_status_mask = 0;
805 if (I_IGNPAR(tty))
806 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
807 if (I_IGNBRK(tty)) {
808 info->ignore_status_mask |= STMBREAKH;
809 /*
810 * If we're ignoring parity and break indicators,
811 * ignore overruns too. (For real raw support).
812 */
813 if (I_IGNPAR(tty))
814 info->ignore_status_mask |= STMRCVROVRH;
815 }
816
817 rocketMode = info->flags & ROCKET_MODE_MASK;
818
819 if ((info->flags & ROCKET_RTS_TOGGLE)
820 || (rocketMode == ROCKET_MODE_RS485))
821 sEnRTSToggle(cp);
822 else
823 sDisRTSToggle(cp);
824
825 sSetRTS(&info->channel);
826
827 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
828 switch (rocketMode) {
829 case ROCKET_MODE_RS485:
830 sSetInterfaceMode(cp, InterfaceModeRS485);
831 break;
832 case ROCKET_MODE_RS422:
833 sSetInterfaceMode(cp, InterfaceModeRS422);
834 break;
835 case ROCKET_MODE_RS232:
836 default:
837 if (info->flags & ROCKET_RTS_TOGGLE)
838 sSetInterfaceMode(cp, InterfaceModeRS232T);
839 else
840 sSetInterfaceMode(cp, InterfaceModeRS232);
841 break;
842 }
843 }
844}
845
846static int carrier_raised(struct tty_port *port)
847{
848 struct r_port *info = container_of(port, struct r_port, port);
849 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
850}
851
852static void dtr_rts(struct tty_port *port, int on)
853{
854 struct r_port *info = container_of(port, struct r_port, port);
855 if (on) {
856 sSetDTR(&info->channel);
857 sSetRTS(&info->channel);
858 } else {
859 sClrDTR(&info->channel);
860 sClrRTS(&info->channel);
861 }
862}
863
864/*
865 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
866 * port's r_port struct. Initializes the port hardware.
867 */
868static int rp_open(struct tty_struct *tty, struct file *filp)
869{
870 struct r_port *info;
871 struct tty_port *port;
872 int retval;
873 CHANNEL_t *cp;
874 unsigned long page;
875
876 info = rp_table[tty->index];
877 if (info == NULL)
878 return -ENXIO;
879 port = &info->port;
880
881 page = __get_free_page(GFP_KERNEL);
882 if (!page)
883 return -ENOMEM;
884
885 /*
886 * We must not sleep from here until the port is marked fully in use.
887 */
888 if (info->xmit_buf)
889 free_page(page);
890 else
891 info->xmit_buf = (unsigned char *) page;
892
893 tty->driver_data = info;
894 tty_port_tty_set(port, tty);
895
896 if (port->count++ == 0) {
897 atomic_inc(&rp_num_ports_open);
898
899#ifdef ROCKET_DEBUG_OPEN
900 printk(KERN_INFO "rocket mod++ = %d...\n",
901 atomic_read(&rp_num_ports_open));
902#endif
903 }
904#ifdef ROCKET_DEBUG_OPEN
905 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
906#endif
907
908 /*
909 * Info->count is now 1; so it's safe to sleep now.
910 */
911 if (!tty_port_initialized(port)) {
912 cp = &info->channel;
913 sSetRxTrigger(cp, TRIG_1);
914 if (sGetChanStatus(cp) & CD_ACT)
915 info->cd_status = 1;
916 else
917 info->cd_status = 0;
918 sDisRxStatusMode(cp);
919 sFlushRxFIFO(cp);
920 sFlushTxFIFO(cp);
921
922 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
923 sSetRxTrigger(cp, TRIG_1);
924
925 sGetChanStatus(cp);
926 sDisRxStatusMode(cp);
927 sClrTxXOFF(cp);
928
929 sDisCTSFlowCtl(cp);
930 sDisTxSoftFlowCtl(cp);
931
932 sEnRxFIFO(cp);
933 sEnTransmit(cp);
934
935 tty_port_set_initialized(&info->port, 1);
936
937 configure_r_port(tty, info, NULL);
938 if (C_BAUD(tty)) {
939 sSetDTR(cp);
940 sSetRTS(cp);
941 }
942 }
943 /* Starts (or resets) the maint polling loop */
944 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
945
946 retval = tty_port_block_til_ready(port, tty, filp);
947 if (retval) {
948#ifdef ROCKET_DEBUG_OPEN
949 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
950#endif
951 return retval;
952 }
953 return 0;
954}
955
956/*
957 * Exception handler that closes a serial port. info->port.count is considered critical.
958 */
959static void rp_close(struct tty_struct *tty, struct file *filp)
960{
961 struct r_port *info = tty->driver_data;
962 struct tty_port *port = &info->port;
963 int timeout;
964 CHANNEL_t *cp;
965
966 if (rocket_paranoia_check(info, "rp_close"))
967 return;
968
969#ifdef ROCKET_DEBUG_OPEN
970 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
971#endif
972
973 if (tty_port_close_start(port, tty, filp) == 0)
974 return;
975
976 mutex_lock(&port->mutex);
977 cp = &info->channel;
978 /*
979 * Before we drop DTR, make sure the UART transmitter
980 * has completely drained; this is especially
981 * important if there is a transmit FIFO!
982 */
983 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
984 if (timeout == 0)
985 timeout = 1;
986 rp_wait_until_sent(tty, timeout);
987 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
988
989 sDisTransmit(cp);
990 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
991 sDisCTSFlowCtl(cp);
992 sDisTxSoftFlowCtl(cp);
993 sClrTxXOFF(cp);
994 sFlushRxFIFO(cp);
995 sFlushTxFIFO(cp);
996 sClrRTS(cp);
997 if (C_HUPCL(tty))
998 sClrDTR(cp);
999
1000 rp_flush_buffer(tty);
1001
1002 tty_ldisc_flush(tty);
1003
1004 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1005
1006 /* We can't yet use tty_port_close_end as the buffer handling in this
1007 driver is a bit different to the usual */
1008
1009 if (port->blocked_open) {
1010 if (port->close_delay) {
1011 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1012 }
1013 wake_up_interruptible(&port->open_wait);
1014 } else {
1015 if (info->xmit_buf) {
1016 free_page((unsigned long) info->xmit_buf);
1017 info->xmit_buf = NULL;
1018 }
1019 }
1020 spin_lock_irq(&port->lock);
1021 tty->closing = 0;
1022 spin_unlock_irq(&port->lock);
1023 tty_port_set_initialized(port, 0);
1024 tty_port_set_active(port, 0);
1025 mutex_unlock(&port->mutex);
1026 tty_port_tty_set(port, NULL);
1027
1028 atomic_dec(&rp_num_ports_open);
1029
1030#ifdef ROCKET_DEBUG_OPEN
1031 printk(KERN_INFO "rocket mod-- = %d...\n",
1032 atomic_read(&rp_num_ports_open));
1033 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1034#endif
1035
1036}
1037
1038static void rp_set_termios(struct tty_struct *tty,
1039 struct ktermios *old_termios)
1040{
1041 struct r_port *info = tty->driver_data;
1042 CHANNEL_t *cp;
1043 unsigned cflag;
1044
1045 if (rocket_paranoia_check(info, "rp_set_termios"))
1046 return;
1047
1048 cflag = tty->termios.c_cflag;
1049
1050 /*
1051 * This driver doesn't support CS5 or CS6
1052 */
1053 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1054 tty->termios.c_cflag =
1055 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1056 /* Or CMSPAR */
1057 tty->termios.c_cflag &= ~CMSPAR;
1058
1059 configure_r_port(tty, info, old_termios);
1060
1061 cp = &info->channel;
1062
1063 /* Handle transition to B0 status */
1064 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
1065 sClrDTR(cp);
1066 sClrRTS(cp);
1067 }
1068
1069 /* Handle transition away from B0 status */
1070 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1071 sSetRTS(cp);
1072 sSetDTR(cp);
1073 }
1074
1075 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1076 rp_start(tty);
1077}
1078
1079static int rp_break(struct tty_struct *tty, int break_state)
1080{
1081 struct r_port *info = tty->driver_data;
1082 unsigned long flags;
1083
1084 if (rocket_paranoia_check(info, "rp_break"))
1085 return -EINVAL;
1086
1087 spin_lock_irqsave(&info->slock, flags);
1088 if (break_state == -1)
1089 sSendBreak(&info->channel);
1090 else
1091 sClrBreak(&info->channel);
1092 spin_unlock_irqrestore(&info->slock, flags);
1093 return 0;
1094}
1095
1096/*
1097 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1098 * the UPCI boards was added, it was decided to make this a function because
1099 * the macro was getting too complicated. All cases except the first one
1100 * (UPCIRingInd) are taken directly from the original macro.
1101 */
1102static int sGetChanRI(CHANNEL_T * ChP)
1103{
1104 CONTROLLER_t *CtlP = ChP->CtlP;
1105 int ChanNum = ChP->ChanNum;
1106 int RingInd = 0;
1107
1108 if (CtlP->UPCIRingInd)
1109 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1110 else if (CtlP->AltChanRingIndicator)
1111 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1112 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1113 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1114
1115 return RingInd;
1116}
1117
1118/********************************************************************************************/
1119/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1120
1121/*
1122 * Returns the state of the serial modem control lines. These next 2 functions
1123 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1124 */
1125static int rp_tiocmget(struct tty_struct *tty)
1126{
1127 struct r_port *info = tty->driver_data;
1128 unsigned int control, result, ChanStatus;
1129
1130 ChanStatus = sGetChanStatusLo(&info->channel);
1131 control = info->channel.TxControl[3];
1132 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1133 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1134 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1135 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1136 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1137 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1138
1139 return result;
1140}
1141
1142/*
1143 * Sets the modem control lines
1144 */
1145static int rp_tiocmset(struct tty_struct *tty,
1146 unsigned int set, unsigned int clear)
1147{
1148 struct r_port *info = tty->driver_data;
1149
1150 if (set & TIOCM_RTS)
1151 info->channel.TxControl[3] |= SET_RTS;
1152 if (set & TIOCM_DTR)
1153 info->channel.TxControl[3] |= SET_DTR;
1154 if (clear & TIOCM_RTS)
1155 info->channel.TxControl[3] &= ~SET_RTS;
1156 if (clear & TIOCM_DTR)
1157 info->channel.TxControl[3] &= ~SET_DTR;
1158
1159 out32(info->channel.IndexAddr, info->channel.TxControl);
1160 return 0;
1161}
1162
1163static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1164{
1165 struct rocket_config tmp;
1166
1167 memset(&tmp, 0, sizeof (tmp));
1168 mutex_lock(&info->port.mutex);
1169 tmp.line = info->line;
1170 tmp.flags = info->flags;
1171 tmp.close_delay = info->port.close_delay;
1172 tmp.closing_wait = info->port.closing_wait;
1173 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1174 mutex_unlock(&info->port.mutex);
1175
1176 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1177 return -EFAULT;
1178 return 0;
1179}
1180
1181static int set_config(struct tty_struct *tty, struct r_port *info,
1182 struct rocket_config __user *new_info)
1183{
1184 struct rocket_config new_serial;
1185
1186 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1187 return -EFAULT;
1188
1189 mutex_lock(&info->port.mutex);
1190 if (!capable(CAP_SYS_ADMIN))
1191 {
1192 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1193 mutex_unlock(&info->port.mutex);
1194 return -EPERM;
1195 }
1196 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1197 mutex_unlock(&info->port.mutex);
1198 return 0;
1199 }
1200
1201 if ((new_serial.flags ^ info->flags) & ROCKET_SPD_MASK) {
1202 /* warn about deprecation, unless clearing */
1203 if (new_serial.flags & ROCKET_SPD_MASK)
1204 dev_warn_ratelimited(tty->dev, "use of SPD flags is deprecated\n");
1205 }
1206
1207 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1208 info->port.close_delay = new_serial.close_delay;
1209 info->port.closing_wait = new_serial.closing_wait;
1210
1211 mutex_unlock(&info->port.mutex);
1212
1213 configure_r_port(tty, info, NULL);
1214 return 0;
1215}
1216
1217/*
1218 * This function fills in a rocket_ports struct with information
1219 * about what boards/ports are in the system. This info is passed
1220 * to user space. See setrocket.c where the info is used to create
1221 * the /dev/ttyRx ports.
1222 */
1223static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1224{
1225 struct rocket_ports tmp;
1226 int board;
1227
1228 memset(&tmp, 0, sizeof (tmp));
1229 tmp.tty_major = rocket_driver->major;
1230
1231 for (board = 0; board < 4; board++) {
1232 tmp.rocketModel[board].model = rocketModel[board].model;
1233 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1234 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1235 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1236 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1237 }
1238 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1239 return -EFAULT;
1240 return 0;
1241}
1242
1243static int reset_rm2(struct r_port *info, void __user *arg)
1244{
1245 int reset;
1246
1247 if (!capable(CAP_SYS_ADMIN))
1248 return -EPERM;
1249
1250 if (copy_from_user(&reset, arg, sizeof (int)))
1251 return -EFAULT;
1252 if (reset)
1253 reset = 1;
1254
1255 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1256 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1257 return -EINVAL;
1258
1259 if (info->ctlp->BusType == isISA)
1260 sModemReset(info->ctlp, info->chan, reset);
1261 else
1262 sPCIModemReset(info->ctlp, info->chan, reset);
1263
1264 return 0;
1265}
1266
1267static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1268{
1269 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1270 return -EFAULT;
1271 return 0;
1272}
1273
1274/* IOCTL call handler into the driver */
1275static int rp_ioctl(struct tty_struct *tty,
1276 unsigned int cmd, unsigned long arg)
1277{
1278 struct r_port *info = tty->driver_data;
1279 void __user *argp = (void __user *)arg;
1280 int ret = 0;
1281
1282 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1283 return -ENXIO;
1284
1285 switch (cmd) {
1286 case RCKP_GET_STRUCT:
1287 if (copy_to_user(argp, info, sizeof (struct r_port)))
1288 ret = -EFAULT;
1289 break;
1290 case RCKP_GET_CONFIG:
1291 ret = get_config(info, argp);
1292 break;
1293 case RCKP_SET_CONFIG:
1294 ret = set_config(tty, info, argp);
1295 break;
1296 case RCKP_GET_PORTS:
1297 ret = get_ports(info, argp);
1298 break;
1299 case RCKP_RESET_RM2:
1300 ret = reset_rm2(info, argp);
1301 break;
1302 case RCKP_GET_VERSION:
1303 ret = get_version(info, argp);
1304 break;
1305 default:
1306 ret = -ENOIOCTLCMD;
1307 }
1308 return ret;
1309}
1310
1311static void rp_send_xchar(struct tty_struct *tty, char ch)
1312{
1313 struct r_port *info = tty->driver_data;
1314 CHANNEL_t *cp;
1315
1316 if (rocket_paranoia_check(info, "rp_send_xchar"))
1317 return;
1318
1319 cp = &info->channel;
1320 if (sGetTxCnt(cp))
1321 sWriteTxPrioByte(cp, ch);
1322 else
1323 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1324}
1325
1326static void rp_throttle(struct tty_struct *tty)
1327{
1328 struct r_port *info = tty->driver_data;
1329
1330#ifdef ROCKET_DEBUG_THROTTLE
1331 printk(KERN_INFO "throttle %s ....\n", tty->name);
1332#endif
1333
1334 if (rocket_paranoia_check(info, "rp_throttle"))
1335 return;
1336
1337 if (I_IXOFF(tty))
1338 rp_send_xchar(tty, STOP_CHAR(tty));
1339
1340 sClrRTS(&info->channel);
1341}
1342
1343static void rp_unthrottle(struct tty_struct *tty)
1344{
1345 struct r_port *info = tty->driver_data;
1346#ifdef ROCKET_DEBUG_THROTTLE
1347 printk(KERN_INFO "unthrottle %s ....\n", tty->name);
1348#endif
1349
1350 if (rocket_paranoia_check(info, "rp_unthrottle"))
1351 return;
1352
1353 if (I_IXOFF(tty))
1354 rp_send_xchar(tty, START_CHAR(tty));
1355
1356 sSetRTS(&info->channel);
1357}
1358
1359/*
1360 * ------------------------------------------------------------
1361 * rp_stop() and rp_start()
1362 *
1363 * This routines are called before setting or resetting tty->stopped.
1364 * They enable or disable transmitter interrupts, as necessary.
1365 * ------------------------------------------------------------
1366 */
1367static void rp_stop(struct tty_struct *tty)
1368{
1369 struct r_port *info = tty->driver_data;
1370
1371#ifdef ROCKET_DEBUG_FLOW
1372 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1373 info->xmit_cnt, info->xmit_fifo_room);
1374#endif
1375
1376 if (rocket_paranoia_check(info, "rp_stop"))
1377 return;
1378
1379 if (sGetTxCnt(&info->channel))
1380 sDisTransmit(&info->channel);
1381}
1382
1383static void rp_start(struct tty_struct *tty)
1384{
1385 struct r_port *info = tty->driver_data;
1386
1387#ifdef ROCKET_DEBUG_FLOW
1388 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1389 info->xmit_cnt, info->xmit_fifo_room);
1390#endif
1391
1392 if (rocket_paranoia_check(info, "rp_stop"))
1393 return;
1394
1395 sEnTransmit(&info->channel);
1396 set_bit((info->aiop * 8) + info->chan,
1397 (void *) &xmit_flags[info->board]);
1398}
1399
1400/*
1401 * rp_wait_until_sent() --- wait until the transmitter is empty
1402 */
1403static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1404{
1405 struct r_port *info = tty->driver_data;
1406 CHANNEL_t *cp;
1407 unsigned long orig_jiffies;
1408 int check_time, exit_time;
1409 int txcnt;
1410
1411 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1412 return;
1413
1414 cp = &info->channel;
1415
1416 orig_jiffies = jiffies;
1417#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1418 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1419 jiffies);
1420 printk(KERN_INFO "cps=%d...\n", info->cps);
1421#endif
1422 while (1) {
1423 txcnt = sGetTxCnt(cp);
1424 if (!txcnt) {
1425 if (sGetChanStatusLo(cp) & TXSHRMT)
1426 break;
1427 check_time = (HZ / info->cps) / 5;
1428 } else {
1429 check_time = HZ * txcnt / info->cps;
1430 }
1431 if (timeout) {
1432 exit_time = orig_jiffies + timeout - jiffies;
1433 if (exit_time <= 0)
1434 break;
1435 if (exit_time < check_time)
1436 check_time = exit_time;
1437 }
1438 if (check_time == 0)
1439 check_time = 1;
1440#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1441 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1442 jiffies, check_time);
1443#endif
1444 msleep_interruptible(jiffies_to_msecs(check_time));
1445 if (signal_pending(current))
1446 break;
1447 }
1448 __set_current_state(TASK_RUNNING);
1449#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1450 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1451#endif
1452}
1453
1454/*
1455 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1456 */
1457static void rp_hangup(struct tty_struct *tty)
1458{
1459 CHANNEL_t *cp;
1460 struct r_port *info = tty->driver_data;
1461 unsigned long flags;
1462
1463 if (rocket_paranoia_check(info, "rp_hangup"))
1464 return;
1465
1466#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1467 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1468#endif
1469 rp_flush_buffer(tty);
1470 spin_lock_irqsave(&info->port.lock, flags);
1471 if (info->port.count)
1472 atomic_dec(&rp_num_ports_open);
1473 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1474 spin_unlock_irqrestore(&info->port.lock, flags);
1475
1476 tty_port_hangup(&info->port);
1477
1478 cp = &info->channel;
1479 sDisRxFIFO(cp);
1480 sDisTransmit(cp);
1481 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1482 sDisCTSFlowCtl(cp);
1483 sDisTxSoftFlowCtl(cp);
1484 sClrTxXOFF(cp);
1485 tty_port_set_initialized(&info->port, 0);
1486
1487 wake_up_interruptible(&info->port.open_wait);
1488}
1489
1490/*
1491 * Exception handler - write char routine. The RocketPort driver uses a
1492 * double-buffering strategy, with the twist that if the in-memory CPU
1493 * buffer is empty, and there's space in the transmit FIFO, the
1494 * writing routines will write directly to transmit FIFO.
1495 * Write buffer and counters protected by spinlocks
1496 */
1497static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1498{
1499 struct r_port *info = tty->driver_data;
1500 CHANNEL_t *cp;
1501 unsigned long flags;
1502
1503 if (rocket_paranoia_check(info, "rp_put_char"))
1504 return 0;
1505
1506 /*
1507 * Grab the port write mutex, locking out other processes that try to
1508 * write to this port
1509 */
1510 mutex_lock(&info->write_mtx);
1511
1512#ifdef ROCKET_DEBUG_WRITE
1513 printk(KERN_INFO "rp_put_char %c...\n", ch);
1514#endif
1515
1516 spin_lock_irqsave(&info->slock, flags);
1517 cp = &info->channel;
1518
1519 if (!tty->stopped && info->xmit_fifo_room == 0)
1520 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1521
1522 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1523 info->xmit_buf[info->xmit_head++] = ch;
1524 info->xmit_head &= XMIT_BUF_SIZE - 1;
1525 info->xmit_cnt++;
1526 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1527 } else {
1528 sOutB(sGetTxRxDataIO(cp), ch);
1529 info->xmit_fifo_room--;
1530 }
1531 spin_unlock_irqrestore(&info->slock, flags);
1532 mutex_unlock(&info->write_mtx);
1533 return 1;
1534}
1535
1536/*
1537 * Exception handler - write routine, called when user app writes to the device.
1538 * A per port write mutex is used to protect from another process writing to
1539 * this port at the same time. This other process could be running on the other CPU
1540 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1541 * Spinlocks protect the info xmit members.
1542 */
1543static int rp_write(struct tty_struct *tty,
1544 const unsigned char *buf, int count)
1545{
1546 struct r_port *info = tty->driver_data;
1547 CHANNEL_t *cp;
1548 const unsigned char *b;
1549 int c, retval = 0;
1550 unsigned long flags;
1551
1552 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1553 return 0;
1554
1555 if (mutex_lock_interruptible(&info->write_mtx))
1556 return -ERESTARTSYS;
1557
1558#ifdef ROCKET_DEBUG_WRITE
1559 printk(KERN_INFO "rp_write %d chars...\n", count);
1560#endif
1561 cp = &info->channel;
1562
1563 if (!tty->stopped && info->xmit_fifo_room < count)
1564 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1565
1566 /*
1567 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1568 * into FIFO. Use the write queue for temp storage.
1569 */
1570 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1571 c = min(count, info->xmit_fifo_room);
1572 b = buf;
1573
1574 /* Push data into FIFO, 2 bytes at a time */
1575 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1576
1577 /* If there is a byte remaining, write it */
1578 if (c & 1)
1579 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1580
1581 retval += c;
1582 buf += c;
1583 count -= c;
1584
1585 spin_lock_irqsave(&info->slock, flags);
1586 info->xmit_fifo_room -= c;
1587 spin_unlock_irqrestore(&info->slock, flags);
1588 }
1589
1590 /* If count is zero, we wrote it all and are done */
1591 if (!count)
1592 goto end;
1593
1594 /* Write remaining data into the port's xmit_buf */
1595 while (1) {
1596 /* Hung up ? */
1597 if (!tty_port_active(&info->port))
1598 goto end;
1599 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1600 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1601 if (c <= 0)
1602 break;
1603
1604 b = buf;
1605 memcpy(info->xmit_buf + info->xmit_head, b, c);
1606
1607 spin_lock_irqsave(&info->slock, flags);
1608 info->xmit_head =
1609 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1610 info->xmit_cnt += c;
1611 spin_unlock_irqrestore(&info->slock, flags);
1612
1613 buf += c;
1614 count -= c;
1615 retval += c;
1616 }
1617
1618 if ((retval > 0) && !tty->stopped)
1619 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1620
1621end:
1622 if (info->xmit_cnt < WAKEUP_CHARS) {
1623 tty_wakeup(tty);
1624#ifdef ROCKETPORT_HAVE_POLL_WAIT
1625 wake_up_interruptible(&tty->poll_wait);
1626#endif
1627 }
1628 mutex_unlock(&info->write_mtx);
1629 return retval;
1630}
1631
1632/*
1633 * Return the number of characters that can be sent. We estimate
1634 * only using the in-memory transmit buffer only, and ignore the
1635 * potential space in the transmit FIFO.
1636 */
1637static int rp_write_room(struct tty_struct *tty)
1638{
1639 struct r_port *info = tty->driver_data;
1640 int ret;
1641
1642 if (rocket_paranoia_check(info, "rp_write_room"))
1643 return 0;
1644
1645 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1646 if (ret < 0)
1647 ret = 0;
1648#ifdef ROCKET_DEBUG_WRITE
1649 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1650#endif
1651 return ret;
1652}
1653
1654/*
1655 * Return the number of characters in the buffer. Again, this only
1656 * counts those characters in the in-memory transmit buffer.
1657 */
1658static int rp_chars_in_buffer(struct tty_struct *tty)
1659{
1660 struct r_port *info = tty->driver_data;
1661
1662 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1663 return 0;
1664
1665#ifdef ROCKET_DEBUG_WRITE
1666 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1667#endif
1668 return info->xmit_cnt;
1669}
1670
1671/*
1672 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1673 * r_port struct for the port. Note that spinlock are used to protect info members,
1674 * do not call this function if the spinlock is already held.
1675 */
1676static void rp_flush_buffer(struct tty_struct *tty)
1677{
1678 struct r_port *info = tty->driver_data;
1679 CHANNEL_t *cp;
1680 unsigned long flags;
1681
1682 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1683 return;
1684
1685 spin_lock_irqsave(&info->slock, flags);
1686 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1687 spin_unlock_irqrestore(&info->slock, flags);
1688
1689#ifdef ROCKETPORT_HAVE_POLL_WAIT
1690 wake_up_interruptible(&tty->poll_wait);
1691#endif
1692 tty_wakeup(tty);
1693
1694 cp = &info->channel;
1695 sFlushTxFIFO(cp);
1696}
1697
1698#ifdef CONFIG_PCI
1699
1700static const struct pci_device_id rocket_pci_ids[] = {
1701 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1702 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1703 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1704 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1705 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1706 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1707 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1708 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1709 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1710 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1711 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1712 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1713 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1714 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1715 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1716 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1717 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1718 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1719 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1720 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1721 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1722 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1723 { }
1724};
1725MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1726
1727/* Resets the speaker controller on RocketModem II and III devices */
1728static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1729{
1730 ByteIO_t addr;
1731
1732 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1733 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1734 addr = CtlP->AiopIO[0] + 0x4F;
1735 sOutB(addr, 0);
1736 }
1737
1738 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1739 if ((model == MODEL_UPCI_RM3_8PORT)
1740 || (model == MODEL_UPCI_RM3_4PORT)) {
1741 addr = CtlP->AiopIO[0] + 0x88;
1742 sOutB(addr, 0);
1743 }
1744}
1745
1746/***************************************************************************
1747Function: sPCIInitController
1748Purpose: Initialization of controller global registers and controller
1749 structure.
1750Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1751 IRQNum,Frequency,PeriodicOnly)
1752 CONTROLLER_T *CtlP; Ptr to controller structure
1753 int CtlNum; Controller number
1754 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1755 This list must be in the order the AIOPs will be found on the
1756 controller. Once an AIOP in the list is not found, it is
1757 assumed that there are no more AIOPs on the controller.
1758 int AiopIOListSize; Number of addresses in AiopIOList
1759 int IRQNum; Interrupt Request number. Can be any of the following:
1760 0: Disable global interrupts
1761 3: IRQ 3
1762 4: IRQ 4
1763 5: IRQ 5
1764 9: IRQ 9
1765 10: IRQ 10
1766 11: IRQ 11
1767 12: IRQ 12
1768 15: IRQ 15
1769 Byte_t Frequency: A flag identifying the frequency
1770 of the periodic interrupt, can be any one of the following:
1771 FREQ_DIS - periodic interrupt disabled
1772 FREQ_137HZ - 137 Hertz
1773 FREQ_69HZ - 69 Hertz
1774 FREQ_34HZ - 34 Hertz
1775 FREQ_17HZ - 17 Hertz
1776 FREQ_9HZ - 9 Hertz
1777 FREQ_4HZ - 4 Hertz
1778 If IRQNum is set to 0 the Frequency parameter is
1779 overidden, it is forced to a value of FREQ_DIS.
1780 int PeriodicOnly: 1 if all interrupts except the periodic
1781 interrupt are to be blocked.
1782 0 is both the periodic interrupt and
1783 other channel interrupts are allowed.
1784 If IRQNum is set to 0 the PeriodicOnly parameter is
1785 overidden, it is forced to a value of 0.
1786Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1787 initialization failed.
1788
1789Comments:
1790 If periodic interrupts are to be disabled but AIOP interrupts
1791 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1792
1793 If interrupts are to be completely disabled set IRQNum to 0.
1794
1795 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1796 invalid combination.
1797
1798 This function performs initialization of global interrupt modes,
1799 but it does not actually enable global interrupts. To enable
1800 and disable global interrupts use functions sEnGlobalInt() and
1801 sDisGlobalInt(). Enabling of global interrupts is normally not
1802 done until all other initializations are complete.
1803
1804 Even if interrupts are globally enabled, they must also be
1805 individually enabled for each channel that is to generate
1806 interrupts.
1807
1808Warnings: No range checking on any of the parameters is done.
1809
1810 No context switches are allowed while executing this function.
1811
1812 After this function all AIOPs on the controller are disabled,
1813 they can be enabled with sEnAiop().
1814*/
1815static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1816 ByteIO_t * AiopIOList, int AiopIOListSize,
1817 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1818 int PeriodicOnly, int altChanRingIndicator,
1819 int UPCIRingInd)
1820{
1821 int i;
1822 ByteIO_t io;
1823
1824 CtlP->AltChanRingIndicator = altChanRingIndicator;
1825 CtlP->UPCIRingInd = UPCIRingInd;
1826 CtlP->CtlNum = CtlNum;
1827 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1828 CtlP->BusType = isPCI; /* controller release 1 */
1829
1830 if (ConfigIO) {
1831 CtlP->isUPCI = 1;
1832 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1833 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1834 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1835 } else {
1836 CtlP->isUPCI = 0;
1837 CtlP->PCIIO =
1838 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1839 CtlP->AiopIntrBits = aiop_intr_bits;
1840 }
1841
1842 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1843 /* Init AIOPs */
1844 CtlP->NumAiop = 0;
1845 for (i = 0; i < AiopIOListSize; i++) {
1846 io = AiopIOList[i];
1847 CtlP->AiopIO[i] = (WordIO_t) io;
1848 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1849
1850 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1851 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1852 break; /* done looking for AIOPs */
1853
1854 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1855 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1856 sOutB(io + _INDX_DATA, sClockPrescale);
1857 CtlP->NumAiop++; /* bump count of AIOPs */
1858 }
1859
1860 if (CtlP->NumAiop == 0)
1861 return (-1);
1862 else
1863 return (CtlP->NumAiop);
1864}
1865
1866/*
1867 * Called when a PCI card is found. Retrieves and stores model information,
1868 * init's aiopic and serial port hardware.
1869 * Inputs: i is the board number (0-n)
1870 */
1871static __init int register_PCI(int i, struct pci_dev *dev)
1872{
1873 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1874 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1875 CONTROLLER_t *ctlp;
1876
1877 int fast_clock = 0;
1878 int altChanRingIndicator = 0;
1879 int ports_per_aiop = 8;
1880 WordIO_t ConfigIO = 0;
1881 ByteIO_t UPCIRingInd = 0;
1882
1883 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1884 pci_enable_device(dev))
1885 return 0;
1886
1887 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1888
1889 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1890 rocketModel[i].loadrm2 = 0;
1891 rocketModel[i].startingPortNumber = nextLineNumber;
1892
1893 /* Depending on the model, set up some config variables */
1894 switch (dev->device) {
1895 case PCI_DEVICE_ID_RP4QUAD:
1896 max_num_aiops = 1;
1897 ports_per_aiop = 4;
1898 rocketModel[i].model = MODEL_RP4QUAD;
1899 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1900 rocketModel[i].numPorts = 4;
1901 break;
1902 case PCI_DEVICE_ID_RP8OCTA:
1903 max_num_aiops = 1;
1904 rocketModel[i].model = MODEL_RP8OCTA;
1905 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1906 rocketModel[i].numPorts = 8;
1907 break;
1908 case PCI_DEVICE_ID_URP8OCTA:
1909 max_num_aiops = 1;
1910 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1911 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1912 rocketModel[i].numPorts = 8;
1913 break;
1914 case PCI_DEVICE_ID_RP8INTF:
1915 max_num_aiops = 1;
1916 rocketModel[i].model = MODEL_RP8INTF;
1917 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1918 rocketModel[i].numPorts = 8;
1919 break;
1920 case PCI_DEVICE_ID_URP8INTF:
1921 max_num_aiops = 1;
1922 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1923 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1924 rocketModel[i].numPorts = 8;
1925 break;
1926 case PCI_DEVICE_ID_RP8J:
1927 max_num_aiops = 1;
1928 rocketModel[i].model = MODEL_RP8J;
1929 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1930 rocketModel[i].numPorts = 8;
1931 break;
1932 case PCI_DEVICE_ID_RP4J:
1933 max_num_aiops = 1;
1934 ports_per_aiop = 4;
1935 rocketModel[i].model = MODEL_RP4J;
1936 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1937 rocketModel[i].numPorts = 4;
1938 break;
1939 case PCI_DEVICE_ID_RP8SNI:
1940 max_num_aiops = 1;
1941 rocketModel[i].model = MODEL_RP8SNI;
1942 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1943 rocketModel[i].numPorts = 8;
1944 break;
1945 case PCI_DEVICE_ID_RP16SNI:
1946 max_num_aiops = 2;
1947 rocketModel[i].model = MODEL_RP16SNI;
1948 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1949 rocketModel[i].numPorts = 16;
1950 break;
1951 case PCI_DEVICE_ID_RP16INTF:
1952 max_num_aiops = 2;
1953 rocketModel[i].model = MODEL_RP16INTF;
1954 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1955 rocketModel[i].numPorts = 16;
1956 break;
1957 case PCI_DEVICE_ID_URP16INTF:
1958 max_num_aiops = 2;
1959 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1960 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1961 rocketModel[i].numPorts = 16;
1962 break;
1963 case PCI_DEVICE_ID_CRP16INTF:
1964 max_num_aiops = 2;
1965 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1966 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1967 rocketModel[i].numPorts = 16;
1968 break;
1969 case PCI_DEVICE_ID_RP32INTF:
1970 max_num_aiops = 4;
1971 rocketModel[i].model = MODEL_RP32INTF;
1972 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1973 rocketModel[i].numPorts = 32;
1974 break;
1975 case PCI_DEVICE_ID_URP32INTF:
1976 max_num_aiops = 4;
1977 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1978 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1979 rocketModel[i].numPorts = 32;
1980 break;
1981 case PCI_DEVICE_ID_RPP4:
1982 max_num_aiops = 1;
1983 ports_per_aiop = 4;
1984 altChanRingIndicator++;
1985 fast_clock++;
1986 rocketModel[i].model = MODEL_RPP4;
1987 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1988 rocketModel[i].numPorts = 4;
1989 break;
1990 case PCI_DEVICE_ID_RPP8:
1991 max_num_aiops = 2;
1992 ports_per_aiop = 4;
1993 altChanRingIndicator++;
1994 fast_clock++;
1995 rocketModel[i].model = MODEL_RPP8;
1996 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1997 rocketModel[i].numPorts = 8;
1998 break;
1999 case PCI_DEVICE_ID_RP2_232:
2000 max_num_aiops = 1;
2001 ports_per_aiop = 2;
2002 altChanRingIndicator++;
2003 fast_clock++;
2004 rocketModel[i].model = MODEL_RP2_232;
2005 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2006 rocketModel[i].numPorts = 2;
2007 break;
2008 case PCI_DEVICE_ID_RP2_422:
2009 max_num_aiops = 1;
2010 ports_per_aiop = 2;
2011 altChanRingIndicator++;
2012 fast_clock++;
2013 rocketModel[i].model = MODEL_RP2_422;
2014 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2015 rocketModel[i].numPorts = 2;
2016 break;
2017 case PCI_DEVICE_ID_RP6M:
2018
2019 max_num_aiops = 1;
2020 ports_per_aiop = 6;
2021
2022 /* If revision is 1, the rocketmodem flash must be loaded.
2023 * If it is 2 it is a "socketed" version. */
2024 if (dev->revision == 1) {
2025 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2026 rocketModel[i].loadrm2 = 1;
2027 } else {
2028 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2029 }
2030
2031 rocketModel[i].model = MODEL_RP6M;
2032 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2033 rocketModel[i].numPorts = 6;
2034 break;
2035 case PCI_DEVICE_ID_RP4M:
2036 max_num_aiops = 1;
2037 ports_per_aiop = 4;
2038 if (dev->revision == 1) {
2039 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2040 rocketModel[i].loadrm2 = 1;
2041 } else {
2042 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2043 }
2044
2045 rocketModel[i].model = MODEL_RP4M;
2046 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2047 rocketModel[i].numPorts = 4;
2048 break;
2049 default:
2050 max_num_aiops = 0;
2051 break;
2052 }
2053
2054 /*
2055 * Check for UPCI boards.
2056 */
2057
2058 switch (dev->device) {
2059 case PCI_DEVICE_ID_URP32INTF:
2060 case PCI_DEVICE_ID_URP8INTF:
2061 case PCI_DEVICE_ID_URP16INTF:
2062 case PCI_DEVICE_ID_CRP16INTF:
2063 case PCI_DEVICE_ID_URP8OCTA:
2064 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2065 ConfigIO = pci_resource_start(dev, 1);
2066 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2067 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2068
2069 /*
2070 * Check for octa or quad cable.
2071 */
2072 if (!
2073 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2074 PCI_GPIO_CTRL_8PORT)) {
2075 ports_per_aiop = 4;
2076 rocketModel[i].numPorts = 4;
2077 }
2078 }
2079 break;
2080 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2081 max_num_aiops = 1;
2082 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2083 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2084 rocketModel[i].numPorts = 8;
2085 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2086 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2087 ConfigIO = pci_resource_start(dev, 1);
2088 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2089 break;
2090 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2091 max_num_aiops = 1;
2092 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2093 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2094 rocketModel[i].numPorts = 4;
2095 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2096 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2097 ConfigIO = pci_resource_start(dev, 1);
2098 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2099 break;
2100 default:
2101 break;
2102 }
2103
2104 if (fast_clock) {
2105 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2106 rp_baud_base[i] = 921600;
2107 } else {
2108 /*
2109 * If support_low_speed is set, use the slow clock
2110 * prescale, which supports 50 bps
2111 */
2112 if (support_low_speed) {
2113 /* mod 9 (divide by 10) prescale */
2114 sClockPrescale = 0x19;
2115 rp_baud_base[i] = 230400;
2116 } else {
2117 /* mod 4 (divide by 5) prescale */
2118 sClockPrescale = 0x14;
2119 rp_baud_base[i] = 460800;
2120 }
2121 }
2122
2123 for (aiop = 0; aiop < max_num_aiops; aiop++)
2124 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2125 ctlp = sCtlNumToCtlPtr(i);
2126 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2127 for (aiop = 0; aiop < max_num_aiops; aiop++)
2128 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2129
2130 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2131 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2132 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2133 rocketModel[i].startingPortNumber,
2134 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2135
2136 if (num_aiops <= 0) {
2137 rcktpt_io_addr[i] = 0;
2138 return (0);
2139 }
2140 is_PCI[i] = 1;
2141
2142 /* Reset the AIOPIC, init the serial ports */
2143 for (aiop = 0; aiop < num_aiops; aiop++) {
2144 sResetAiopByNum(ctlp, aiop);
2145 num_chan = ports_per_aiop;
2146 for (chan = 0; chan < num_chan; chan++)
2147 init_r_port(i, aiop, chan, dev);
2148 }
2149
2150 /* Rocket modems must be reset */
2151 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2152 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2153 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2154 num_chan = ports_per_aiop;
2155 for (chan = 0; chan < num_chan; chan++)
2156 sPCIModemReset(ctlp, chan, 1);
2157 msleep(500);
2158 for (chan = 0; chan < num_chan; chan++)
2159 sPCIModemReset(ctlp, chan, 0);
2160 msleep(500);
2161 rmSpeakerReset(ctlp, rocketModel[i].model);
2162 }
2163 return (1);
2164}
2165
2166/*
2167 * Probes for PCI cards, inits them if found
2168 * Input: board_found = number of ISA boards already found, or the
2169 * starting board number
2170 * Returns: Number of PCI boards found
2171 */
2172static int __init init_PCI(int boards_found)
2173{
2174 struct pci_dev *dev = NULL;
2175 int count = 0;
2176
2177 /* Work through the PCI device list, pulling out ours */
2178 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2179 if (register_PCI(count + boards_found, dev))
2180 count++;
2181 }
2182 return (count);
2183}
2184
2185#endif /* CONFIG_PCI */
2186
2187/*
2188 * Probes for ISA cards
2189 * Input: i = the board number to look for
2190 * Returns: 1 if board found, 0 else
2191 */
2192static int __init init_ISA(int i)
2193{
2194 int num_aiops, num_chan = 0, total_num_chan = 0;
2195 int aiop, chan;
2196 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2197 CONTROLLER_t *ctlp;
2198 char *type_string;
2199
2200 /* If io_addr is zero, no board configured */
2201 if (rcktpt_io_addr[i] == 0)
2202 return (0);
2203
2204 /* Reserve the IO region */
2205 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2206 printk(KERN_ERR "Unable to reserve IO region for configured "
2207 "ISA RocketPort at address 0x%lx, board not "
2208 "installed...\n", rcktpt_io_addr[i]);
2209 rcktpt_io_addr[i] = 0;
2210 return (0);
2211 }
2212
2213 ctlp = sCtlNumToCtlPtr(i);
2214
2215 ctlp->boardType = rcktpt_type[i];
2216
2217 switch (rcktpt_type[i]) {
2218 case ROCKET_TYPE_PC104:
2219 type_string = "(PC104)";
2220 break;
2221 case ROCKET_TYPE_MODEM:
2222 type_string = "(RocketModem)";
2223 break;
2224 case ROCKET_TYPE_MODEMII:
2225 type_string = "(RocketModem II)";
2226 break;
2227 default:
2228 type_string = "";
2229 break;
2230 }
2231
2232 /*
2233 * If support_low_speed is set, use the slow clock prescale,
2234 * which supports 50 bps
2235 */
2236 if (support_low_speed) {
2237 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2238 rp_baud_base[i] = 230400;
2239 } else {
2240 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2241 rp_baud_base[i] = 460800;
2242 }
2243
2244 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2245 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2246
2247 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2248
2249 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2250 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2251 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2252 }
2253
2254 /* If something went wrong initing the AIOP's release the ISA IO memory */
2255 if (num_aiops <= 0) {
2256 release_region(rcktpt_io_addr[i], 64);
2257 rcktpt_io_addr[i] = 0;
2258 return (0);
2259 }
2260
2261 rocketModel[i].startingPortNumber = nextLineNumber;
2262
2263 for (aiop = 0; aiop < num_aiops; aiop++) {
2264 sResetAiopByNum(ctlp, aiop);
2265 sEnAiop(ctlp, aiop);
2266 num_chan = sGetAiopNumChan(ctlp, aiop);
2267 total_num_chan += num_chan;
2268 for (chan = 0; chan < num_chan; chan++)
2269 init_r_port(i, aiop, chan, NULL);
2270 }
2271 is_PCI[i] = 0;
2272 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2273 num_chan = sGetAiopNumChan(ctlp, 0);
2274 total_num_chan = num_chan;
2275 for (chan = 0; chan < num_chan; chan++)
2276 sModemReset(ctlp, chan, 1);
2277 msleep(500);
2278 for (chan = 0; chan < num_chan; chan++)
2279 sModemReset(ctlp, chan, 0);
2280 msleep(500);
2281 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2282 } else {
2283 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2284 }
2285 rocketModel[i].numPorts = total_num_chan;
2286 rocketModel[i].model = MODEL_ISA;
2287
2288 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2289 i, rcktpt_io_addr[i], num_aiops, type_string);
2290
2291 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2292 rocketModel[i].modelString,
2293 rocketModel[i].startingPortNumber,
2294 rocketModel[i].startingPortNumber +
2295 rocketModel[i].numPorts - 1);
2296
2297 return (1);
2298}
2299
2300static const struct tty_operations rocket_ops = {
2301 .open = rp_open,
2302 .close = rp_close,
2303 .write = rp_write,
2304 .put_char = rp_put_char,
2305 .write_room = rp_write_room,
2306 .chars_in_buffer = rp_chars_in_buffer,
2307 .flush_buffer = rp_flush_buffer,
2308 .ioctl = rp_ioctl,
2309 .throttle = rp_throttle,
2310 .unthrottle = rp_unthrottle,
2311 .set_termios = rp_set_termios,
2312 .stop = rp_stop,
2313 .start = rp_start,
2314 .hangup = rp_hangup,
2315 .break_ctl = rp_break,
2316 .send_xchar = rp_send_xchar,
2317 .wait_until_sent = rp_wait_until_sent,
2318 .tiocmget = rp_tiocmget,
2319 .tiocmset = rp_tiocmset,
2320};
2321
2322static const struct tty_port_operations rocket_port_ops = {
2323 .carrier_raised = carrier_raised,
2324 .dtr_rts = dtr_rts,
2325};
2326
2327/*
2328 * The module "startup" routine; it's run when the module is loaded.
2329 */
2330static int __init rp_init(void)
2331{
2332 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2333
2334 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2335 ROCKET_VERSION, ROCKET_DATE);
2336
2337 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2338 if (!rocket_driver)
2339 goto err;
2340
2341 /*
2342 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2343 * zero, use the default controller IO address of board1 + 0x40.
2344 */
2345 if (board1) {
2346 if (controller == 0)
2347 controller = board1 + 0x40;
2348 } else {
2349 controller = 0; /* Used as a flag, meaning no ISA boards */
2350 }
2351
2352 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2353 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2354 printk(KERN_ERR "Unable to reserve IO region for first "
2355 "configured ISA RocketPort controller 0x%lx. "
2356 "Driver exiting\n", controller);
2357 ret = -EBUSY;
2358 goto err_tty;
2359 }
2360
2361 /* Store ISA variable retrieved from command line or .conf file. */
2362 rcktpt_io_addr[0] = board1;
2363 rcktpt_io_addr[1] = board2;
2364 rcktpt_io_addr[2] = board3;
2365 rcktpt_io_addr[3] = board4;
2366
2367 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2368 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2369 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2370 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2371 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2372 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2373 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2374 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2375
2376 /*
2377 * Set up the tty driver structure and then register this
2378 * driver with the tty layer.
2379 */
2380
2381 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2382 rocket_driver->name = "ttyR";
2383 rocket_driver->driver_name = "Comtrol RocketPort";
2384 rocket_driver->major = TTY_ROCKET_MAJOR;
2385 rocket_driver->minor_start = 0;
2386 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2387 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2388 rocket_driver->init_termios = tty_std_termios;
2389 rocket_driver->init_termios.c_cflag =
2390 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2391 rocket_driver->init_termios.c_ispeed = 9600;
2392 rocket_driver->init_termios.c_ospeed = 9600;
2393#ifdef ROCKET_SOFT_FLOW
2394 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2395#endif
2396 tty_set_operations(rocket_driver, &rocket_ops);
2397
2398 ret = tty_register_driver(rocket_driver);
2399 if (ret < 0) {
2400 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2401 goto err_controller;
2402 }
2403
2404#ifdef ROCKET_DEBUG_OPEN
2405 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2406#endif
2407
2408 /*
2409 * OK, let's probe each of the controllers looking for boards. Any boards found
2410 * will be initialized here.
2411 */
2412 isa_boards_found = 0;
2413 pci_boards_found = 0;
2414
2415 for (i = 0; i < NUM_BOARDS; i++) {
2416 if (init_ISA(i))
2417 isa_boards_found++;
2418 }
2419
2420#ifdef CONFIG_PCI
2421 if (isa_boards_found < NUM_BOARDS)
2422 pci_boards_found = init_PCI(isa_boards_found);
2423#endif
2424
2425 max_board = pci_boards_found + isa_boards_found;
2426
2427 if (max_board == 0) {
2428 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2429 ret = -ENXIO;
2430 goto err_ttyu;
2431 }
2432
2433 return 0;
2434err_ttyu:
2435 tty_unregister_driver(rocket_driver);
2436err_controller:
2437 if (controller)
2438 release_region(controller, 4);
2439err_tty:
2440 put_tty_driver(rocket_driver);
2441err:
2442 return ret;
2443}
2444
2445
2446static void rp_cleanup_module(void)
2447{
2448 int retval;
2449 int i;
2450
2451 del_timer_sync(&rocket_timer);
2452
2453 retval = tty_unregister_driver(rocket_driver);
2454 if (retval)
2455 printk(KERN_ERR "Error %d while trying to unregister "
2456 "rocketport driver\n", -retval);
2457
2458 for (i = 0; i < MAX_RP_PORTS; i++)
2459 if (rp_table[i]) {
2460 tty_unregister_device(rocket_driver, i);
2461 tty_port_destroy(&rp_table[i]->port);
2462 kfree(rp_table[i]);
2463 }
2464
2465 put_tty_driver(rocket_driver);
2466
2467 for (i = 0; i < NUM_BOARDS; i++) {
2468 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2469 continue;
2470 release_region(rcktpt_io_addr[i], 64);
2471 }
2472 if (controller)
2473 release_region(controller, 4);
2474}
2475
2476/***************************************************************************
2477Function: sInitController
2478Purpose: Initialization of controller global registers and controller
2479 structure.
2480Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2481 IRQNum,Frequency,PeriodicOnly)
2482 CONTROLLER_T *CtlP; Ptr to controller structure
2483 int CtlNum; Controller number
2484 ByteIO_t MudbacIO; Mudbac base I/O address.
2485 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2486 This list must be in the order the AIOPs will be found on the
2487 controller. Once an AIOP in the list is not found, it is
2488 assumed that there are no more AIOPs on the controller.
2489 int AiopIOListSize; Number of addresses in AiopIOList
2490 int IRQNum; Interrupt Request number. Can be any of the following:
2491 0: Disable global interrupts
2492 3: IRQ 3
2493 4: IRQ 4
2494 5: IRQ 5
2495 9: IRQ 9
2496 10: IRQ 10
2497 11: IRQ 11
2498 12: IRQ 12
2499 15: IRQ 15
2500 Byte_t Frequency: A flag identifying the frequency
2501 of the periodic interrupt, can be any one of the following:
2502 FREQ_DIS - periodic interrupt disabled
2503 FREQ_137HZ - 137 Hertz
2504 FREQ_69HZ - 69 Hertz
2505 FREQ_34HZ - 34 Hertz
2506 FREQ_17HZ - 17 Hertz
2507 FREQ_9HZ - 9 Hertz
2508 FREQ_4HZ - 4 Hertz
2509 If IRQNum is set to 0 the Frequency parameter is
2510 overidden, it is forced to a value of FREQ_DIS.
2511 int PeriodicOnly: 1 if all interrupts except the periodic
2512 interrupt are to be blocked.
2513 0 is both the periodic interrupt and
2514 other channel interrupts are allowed.
2515 If IRQNum is set to 0 the PeriodicOnly parameter is
2516 overidden, it is forced to a value of 0.
2517Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2518 initialization failed.
2519
2520Comments:
2521 If periodic interrupts are to be disabled but AIOP interrupts
2522 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2523
2524 If interrupts are to be completely disabled set IRQNum to 0.
2525
2526 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2527 invalid combination.
2528
2529 This function performs initialization of global interrupt modes,
2530 but it does not actually enable global interrupts. To enable
2531 and disable global interrupts use functions sEnGlobalInt() and
2532 sDisGlobalInt(). Enabling of global interrupts is normally not
2533 done until all other initializations are complete.
2534
2535 Even if interrupts are globally enabled, they must also be
2536 individually enabled for each channel that is to generate
2537 interrupts.
2538
2539Warnings: No range checking on any of the parameters is done.
2540
2541 No context switches are allowed while executing this function.
2542
2543 After this function all AIOPs on the controller are disabled,
2544 they can be enabled with sEnAiop().
2545*/
2546static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2547 ByteIO_t * AiopIOList, int AiopIOListSize,
2548 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2549{
2550 int i;
2551 ByteIO_t io;
2552 int done;
2553
2554 CtlP->AiopIntrBits = aiop_intr_bits;
2555 CtlP->AltChanRingIndicator = 0;
2556 CtlP->CtlNum = CtlNum;
2557 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2558 CtlP->BusType = isISA;
2559 CtlP->MBaseIO = MudbacIO;
2560 CtlP->MReg1IO = MudbacIO + 1;
2561 CtlP->MReg2IO = MudbacIO + 2;
2562 CtlP->MReg3IO = MudbacIO + 3;
2563#if 1
2564 CtlP->MReg2 = 0; /* interrupt disable */
2565 CtlP->MReg3 = 0; /* no periodic interrupts */
2566#else
2567 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2568 CtlP->MReg2 = 0; /* interrupt disable */
2569 CtlP->MReg3 = 0; /* no periodic interrupts */
2570 } else {
2571 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2572 CtlP->MReg3 = Frequency; /* set frequency */
2573 if (PeriodicOnly) { /* periodic interrupt only */
2574 CtlP->MReg3 |= PERIODIC_ONLY;
2575 }
2576 }
2577#endif
2578 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2579 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2580 sControllerEOI(CtlP); /* clear EOI if warm init */
2581 /* Init AIOPs */
2582 CtlP->NumAiop = 0;
2583 for (i = done = 0; i < AiopIOListSize; i++) {
2584 io = AiopIOList[i];
2585 CtlP->AiopIO[i] = (WordIO_t) io;
2586 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2587 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2588 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2589 if (done)
2590 continue;
2591 sEnAiop(CtlP, i); /* enable the AIOP */
2592 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2593 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2594 done = 1; /* done looking for AIOPs */
2595 else {
2596 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2597 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2598 sOutB(io + _INDX_DATA, sClockPrescale);
2599 CtlP->NumAiop++; /* bump count of AIOPs */
2600 }
2601 sDisAiop(CtlP, i); /* disable AIOP */
2602 }
2603
2604 if (CtlP->NumAiop == 0)
2605 return (-1);
2606 else
2607 return (CtlP->NumAiop);
2608}
2609
2610/***************************************************************************
2611Function: sReadAiopID
2612Purpose: Read the AIOP idenfication number directly from an AIOP.
2613Call: sReadAiopID(io)
2614 ByteIO_t io: AIOP base I/O address
2615Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2616 is replace by an identifying number.
2617 Flag AIOPID_NULL if no valid AIOP is found
2618Warnings: No context switches are allowed while executing this function.
2619
2620*/
2621static int sReadAiopID(ByteIO_t io)
2622{
2623 Byte_t AiopID; /* ID byte from AIOP */
2624
2625 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2626 sOutB(io + _CMD_REG, 0x0);
2627 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2628 if (AiopID == 0x06)
2629 return (1);
2630 else /* AIOP does not exist */
2631 return (-1);
2632}
2633
2634/***************************************************************************
2635Function: sReadAiopNumChan
2636Purpose: Read the number of channels available in an AIOP directly from
2637 an AIOP.
2638Call: sReadAiopNumChan(io)
2639 WordIO_t io: AIOP base I/O address
2640Return: int: The number of channels available
2641Comments: The number of channels is determined by write/reads from identical
2642 offsets within the SRAM address spaces for channels 0 and 4.
2643 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2644 AIOP, otherwise it is an 8 channel.
2645Warnings: No context switches are allowed while executing this function.
2646*/
2647static int sReadAiopNumChan(WordIO_t io)
2648{
2649 Word_t x;
2650 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2651
2652 /* write to chan 0 SRAM */
2653 out32((DWordIO_t) io + _INDX_ADDR, R);
2654 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2655 x = sInW(io + _INDX_DATA);
2656 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2657 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2658 return (8);
2659 else
2660 return (4);
2661}
2662
2663/***************************************************************************
2664Function: sInitChan
2665Purpose: Initialization of a channel and channel structure
2666Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2667 CONTROLLER_T *CtlP; Ptr to controller structure
2668 CHANNEL_T *ChP; Ptr to channel structure
2669 int AiopNum; AIOP number within controller
2670 int ChanNum; Channel number within AIOP
2671Return: int: 1 if initialization succeeded, 0 if it fails because channel
2672 number exceeds number of channels available in AIOP.
2673Comments: This function must be called before a channel can be used.
2674Warnings: No range checking on any of the parameters is done.
2675
2676 No context switches are allowed while executing this function.
2677*/
2678static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2679 int ChanNum)
2680{
2681 int i;
2682 WordIO_t AiopIO;
2683 WordIO_t ChIOOff;
2684 Byte_t *ChR;
2685 Word_t ChOff;
2686 static Byte_t R[4];
2687 int brd9600;
2688
2689 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2690 return 0; /* exceeds num chans in AIOP */
2691
2692 /* Channel, AIOP, and controller identifiers */
2693 ChP->CtlP = CtlP;
2694 ChP->ChanID = CtlP->AiopID[AiopNum];
2695 ChP->AiopNum = AiopNum;
2696 ChP->ChanNum = ChanNum;
2697
2698 /* Global direct addresses */
2699 AiopIO = CtlP->AiopIO[AiopNum];
2700 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2701 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2702 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2703 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2704 ChP->IndexData = AiopIO + _INDX_DATA;
2705
2706 /* Channel direct addresses */
2707 ChIOOff = AiopIO + ChP->ChanNum * 2;
2708 ChP->TxRxData = ChIOOff + _TD0;
2709 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2710 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2711 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2712
2713 /* Initialize the channel from the RData array */
2714 for (i = 0; i < RDATASIZE; i += 4) {
2715 R[0] = RData[i];
2716 R[1] = RData[i + 1] + 0x10 * ChanNum;
2717 R[2] = RData[i + 2];
2718 R[3] = RData[i + 3];
2719 out32(ChP->IndexAddr, R);
2720 }
2721
2722 ChR = ChP->R;
2723 for (i = 0; i < RREGDATASIZE; i += 4) {
2724 ChR[i] = RRegData[i];
2725 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2726 ChR[i + 2] = RRegData[i + 2];
2727 ChR[i + 3] = RRegData[i + 3];
2728 }
2729
2730 /* Indexed registers */
2731 ChOff = (Word_t) ChanNum *0x1000;
2732
2733 if (sClockPrescale == 0x14)
2734 brd9600 = 47;
2735 else
2736 brd9600 = 23;
2737
2738 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2739 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2740 ChP->BaudDiv[2] = (Byte_t) brd9600;
2741 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2742 out32(ChP->IndexAddr, ChP->BaudDiv);
2743
2744 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2745 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2746 ChP->TxControl[2] = 0;
2747 ChP->TxControl[3] = 0;
2748 out32(ChP->IndexAddr, ChP->TxControl);
2749
2750 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2751 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2752 ChP->RxControl[2] = 0;
2753 ChP->RxControl[3] = 0;
2754 out32(ChP->IndexAddr, ChP->RxControl);
2755
2756 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2757 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2758 ChP->TxEnables[2] = 0;
2759 ChP->TxEnables[3] = 0;
2760 out32(ChP->IndexAddr, ChP->TxEnables);
2761
2762 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2763 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2764 ChP->TxCompare[2] = 0;
2765 ChP->TxCompare[3] = 0;
2766 out32(ChP->IndexAddr, ChP->TxCompare);
2767
2768 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2769 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2770 ChP->TxReplace1[2] = 0;
2771 ChP->TxReplace1[3] = 0;
2772 out32(ChP->IndexAddr, ChP->TxReplace1);
2773
2774 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2775 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2776 ChP->TxReplace2[2] = 0;
2777 ChP->TxReplace2[3] = 0;
2778 out32(ChP->IndexAddr, ChP->TxReplace2);
2779
2780 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2781 ChP->TxFIFO = ChOff + _TX_FIFO;
2782
2783 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2784 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2785 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2786 sOutW(ChP->IndexData, 0);
2787 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2788 ChP->RxFIFO = ChOff + _RX_FIFO;
2789
2790 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2791 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2792 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2793 sOutW(ChP->IndexData, 0);
2794 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2795 sOutW(ChP->IndexData, 0);
2796 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2797 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2798 sOutB(ChP->IndexData, 0);
2799 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2800 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2801 sOutB(ChP->IndexData, 0);
2802 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2803 sEnRxProcessor(ChP); /* start the Rx processor */
2804
2805 return 1;
2806}
2807
2808/***************************************************************************
2809Function: sStopRxProcessor
2810Purpose: Stop the receive processor from processing a channel.
2811Call: sStopRxProcessor(ChP)
2812 CHANNEL_T *ChP; Ptr to channel structure
2813
2814Comments: The receive processor can be started again with sStartRxProcessor().
2815 This function causes the receive processor to skip over the
2816 stopped channel. It does not stop it from processing other channels.
2817
2818Warnings: No context switches are allowed while executing this function.
2819
2820 Do not leave the receive processor stopped for more than one
2821 character time.
2822
2823 After calling this function a delay of 4 uS is required to ensure
2824 that the receive processor is no longer processing this channel.
2825*/
2826static void sStopRxProcessor(CHANNEL_T * ChP)
2827{
2828 Byte_t R[4];
2829
2830 R[0] = ChP->R[0];
2831 R[1] = ChP->R[1];
2832 R[2] = 0x0a;
2833 R[3] = ChP->R[3];
2834 out32(ChP->IndexAddr, R);
2835}
2836
2837/***************************************************************************
2838Function: sFlushRxFIFO
2839Purpose: Flush the Rx FIFO
2840Call: sFlushRxFIFO(ChP)
2841 CHANNEL_T *ChP; Ptr to channel structure
2842Return: void
2843Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2844 while it is being flushed the receive processor is stopped
2845 and the transmitter is disabled. After these operations a
2846 4 uS delay is done before clearing the pointers to allow
2847 the receive processor to stop. These items are handled inside
2848 this function.
2849Warnings: No context switches are allowed while executing this function.
2850*/
2851static void sFlushRxFIFO(CHANNEL_T * ChP)
2852{
2853 int i;
2854 Byte_t Ch; /* channel number within AIOP */
2855 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2856
2857 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2858 return; /* don't need to flush */
2859
2860 RxFIFOEnabled = 0;
2861 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2862 RxFIFOEnabled = 1;
2863 sDisRxFIFO(ChP); /* disable it */
2864 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2865 sInB(ChP->IntChan); /* depends on bus i/o timing */
2866 }
2867 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2868 Ch = (Byte_t) sGetChanNum(ChP);
2869 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2870 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2871 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2872 sOutW(ChP->IndexData, 0);
2873 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2874 sOutW(ChP->IndexData, 0);
2875 if (RxFIFOEnabled)
2876 sEnRxFIFO(ChP); /* enable Rx FIFO */
2877}
2878
2879/***************************************************************************
2880Function: sFlushTxFIFO
2881Purpose: Flush the Tx FIFO
2882Call: sFlushTxFIFO(ChP)
2883 CHANNEL_T *ChP; Ptr to channel structure
2884Return: void
2885Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2886 while it is being flushed the receive processor is stopped
2887 and the transmitter is disabled. After these operations a
2888 4 uS delay is done before clearing the pointers to allow
2889 the receive processor to stop. These items are handled inside
2890 this function.
2891Warnings: No context switches are allowed while executing this function.
2892*/
2893static void sFlushTxFIFO(CHANNEL_T * ChP)
2894{
2895 int i;
2896 Byte_t Ch; /* channel number within AIOP */
2897 int TxEnabled; /* 1 if transmitter enabled */
2898
2899 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2900 return; /* don't need to flush */
2901
2902 TxEnabled = 0;
2903 if (ChP->TxControl[3] & TX_ENABLE) {
2904 TxEnabled = 1;
2905 sDisTransmit(ChP); /* disable transmitter */
2906 }
2907 sStopRxProcessor(ChP); /* stop Rx processor */
2908 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2909 sInB(ChP->IntChan); /* depends on bus i/o timing */
2910 Ch = (Byte_t) sGetChanNum(ChP);
2911 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2912 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2913 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2914 sOutW(ChP->IndexData, 0);
2915 if (TxEnabled)
2916 sEnTransmit(ChP); /* enable transmitter */
2917 sStartRxProcessor(ChP); /* restart Rx processor */
2918}
2919
2920/***************************************************************************
2921Function: sWriteTxPrioByte
2922Purpose: Write a byte of priority transmit data to a channel
2923Call: sWriteTxPrioByte(ChP,Data)
2924 CHANNEL_T *ChP; Ptr to channel structure
2925 Byte_t Data; The transmit data byte
2926
2927Return: int: 1 if the bytes is successfully written, otherwise 0.
2928
2929Comments: The priority byte is transmitted before any data in the Tx FIFO.
2930
2931Warnings: No context switches are allowed while executing this function.
2932*/
2933static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2934{
2935 Byte_t DWBuf[4]; /* buffer for double word writes */
2936 Word_t *WordPtr; /* must be far because Win SS != DS */
2937 register DWordIO_t IndexAddr;
2938
2939 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2940 IndexAddr = ChP->IndexAddr;
2941 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2942 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2943 return (0); /* nothing sent */
2944
2945 WordPtr = (Word_t *) (&DWBuf[0]);
2946 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2947
2948 DWBuf[2] = Data; /* data byte value */
2949 out32(IndexAddr, DWBuf); /* write it out */
2950
2951 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2952
2953 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2954 DWBuf[3] = 0; /* priority buffer pointer */
2955 out32(IndexAddr, DWBuf); /* write it out */
2956 } else { /* write it to Tx FIFO */
2957
2958 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2959 }
2960 return (1); /* 1 byte sent */
2961}
2962
2963/***************************************************************************
2964Function: sEnInterrupts
2965Purpose: Enable one or more interrupts for a channel
2966Call: sEnInterrupts(ChP,Flags)
2967 CHANNEL_T *ChP; Ptr to channel structure
2968 Word_t Flags: Interrupt enable flags, can be any combination
2969 of the following flags:
2970 TXINT_EN: Interrupt on Tx FIFO empty
2971 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
2972 sSetRxTrigger())
2973 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
2974 MCINT_EN: Interrupt on modem input change
2975 CHANINT_EN: Allow channel interrupt signal to the AIOP's
2976 Interrupt Channel Register.
2977Return: void
2978Comments: If an interrupt enable flag is set in Flags, that interrupt will be
2979 enabled. If an interrupt enable flag is not set in Flags, that
2980 interrupt will not be changed. Interrupts can be disabled with
2981 function sDisInterrupts().
2982
2983 This function sets the appropriate bit for the channel in the AIOP's
2984 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
2985 this channel's bit to be set in the AIOP's Interrupt Channel Register.
2986
2987 Interrupts must also be globally enabled before channel interrupts
2988 will be passed on to the host. This is done with function
2989 sEnGlobalInt().
2990
2991 In some cases it may be desirable to disable interrupts globally but
2992 enable channel interrupts. This would allow the global interrupt
2993 status register to be used to determine which AIOPs need service.
2994*/
2995static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
2996{
2997 Byte_t Mask; /* Interrupt Mask Register */
2998
2999 ChP->RxControl[2] |=
3000 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3001
3002 out32(ChP->IndexAddr, ChP->RxControl);
3003
3004 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3005
3006 out32(ChP->IndexAddr, ChP->TxControl);
3007
3008 if (Flags & CHANINT_EN) {
3009 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3010 sOutB(ChP->IntMask, Mask);
3011 }
3012}
3013
3014/***************************************************************************
3015Function: sDisInterrupts
3016Purpose: Disable one or more interrupts for a channel
3017Call: sDisInterrupts(ChP,Flags)
3018 CHANNEL_T *ChP; Ptr to channel structure
3019 Word_t Flags: Interrupt flags, can be any combination
3020 of the following flags:
3021 TXINT_EN: Interrupt on Tx FIFO empty
3022 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3023 sSetRxTrigger())
3024 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3025 MCINT_EN: Interrupt on modem input change
3026 CHANINT_EN: Disable channel interrupt signal to the
3027 AIOP's Interrupt Channel Register.
3028Return: void
3029Comments: If an interrupt flag is set in Flags, that interrupt will be
3030 disabled. If an interrupt flag is not set in Flags, that
3031 interrupt will not be changed. Interrupts can be enabled with
3032 function sEnInterrupts().
3033
3034 This function clears the appropriate bit for the channel in the AIOP's
3035 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3036 this channel's bit from being set in the AIOP's Interrupt Channel
3037 Register.
3038*/
3039static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3040{
3041 Byte_t Mask; /* Interrupt Mask Register */
3042
3043 ChP->RxControl[2] &=
3044 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3045 out32(ChP->IndexAddr, ChP->RxControl);
3046 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3047 out32(ChP->IndexAddr, ChP->TxControl);
3048
3049 if (Flags & CHANINT_EN) {
3050 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3051 sOutB(ChP->IntMask, Mask);
3052 }
3053}
3054
3055static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3056{
3057 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3058}
3059
3060/*
3061 * Not an official SSCI function, but how to reset RocketModems.
3062 * ISA bus version
3063 */
3064static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3065{
3066 ByteIO_t addr;
3067 Byte_t val;
3068
3069 addr = CtlP->AiopIO[0] + 0x400;
3070 val = sInB(CtlP->MReg3IO);
3071 /* if AIOP[1] is not enabled, enable it */
3072 if ((val & 2) == 0) {
3073 val = sInB(CtlP->MReg2IO);
3074 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3075 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3076 }
3077
3078 sEnAiop(CtlP, 1);
3079 if (!on)
3080 addr += 8;
3081 sOutB(addr + chan, 0); /* apply or remove reset */
3082 sDisAiop(CtlP, 1);
3083}
3084
3085/*
3086 * Not an official SSCI function, but how to reset RocketModems.
3087 * PCI bus version
3088 */
3089static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3090{
3091 ByteIO_t addr;
3092
3093 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3094 if (!on)
3095 addr += 8;
3096 sOutB(addr + chan, 0); /* apply or remove reset */
3097}
3098
3099/* Returns the line number given the controller (board), aiop and channel number */
3100static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3101{
3102 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3103}
3104
3105/*
3106 * Stores the line number associated with a given controller (board), aiop
3107 * and channel number.
3108 * Returns: The line number assigned
3109 */
3110static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3111{
3112 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3113 return (nextLineNumber - 1);
3114}