1/*
  2 * SPI Driver for Microchip MCP795 RTC
  3 *
  4 * Copyright (C) Josef Gajdusek <atx@atx.name>
  5 *
  6 * based on other Linux RTC drivers
  7 *
  8 * Device datasheet:
  9 * http://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
 10 *
 11 * This program is free software; you can redistribute it and/or modify
 12 * it under the terms of the GNU General Public License version 2 as
 13 * published by the Free Software Foundation.
 14 *
 15 */
 16
 17#include <linux/module.h>
 18#include <linux/kernel.h>
 19#include <linux/device.h>
 20#include <linux/printk.h>
 21#include <linux/spi/spi.h>
 22#include <linux/rtc.h>
 23#include <linux/of.h>
 24#include <linux/bcd.h>
 25#include <linux/delay.h>
 26
 27/* MCP795 Instructions, see datasheet table 3-1 */
 28#define MCP795_EEREAD	0x03
 29#define MCP795_EEWRITE	0x02
 30#define MCP795_EEWRDI	0x04
 31#define MCP795_EEWREN	0x06
 32#define MCP795_SRREAD	0x05
 33#define MCP795_SRWRITE	0x01
 34#define MCP795_READ	0x13
 35#define MCP795_WRITE	0x12
 36#define MCP795_UNLOCK	0x14
 37#define MCP795_IDWRITE	0x32
 38#define MCP795_IDREAD	0x33
 39#define MCP795_CLRWDT	0x44
 40#define MCP795_CLRRAM	0x54
 41
 42/* MCP795 RTCC registers, see datasheet table 4-1 */
 43#define MCP795_REG_SECONDS	0x01
 44#define MCP795_REG_DAY		0x04
 45#define MCP795_REG_MONTH	0x06
 46#define MCP795_REG_CONTROL	0x08
 47#define MCP795_REG_ALM0_SECONDS	0x0C
 48#define MCP795_REG_ALM0_DAY	0x0F
 49
 50#define MCP795_ST_BIT		BIT(7)
 51#define MCP795_24_BIT		BIT(6)
 52#define MCP795_LP_BIT		BIT(5)
 53#define MCP795_EXTOSC_BIT	BIT(3)
 54#define MCP795_OSCON_BIT	BIT(5)
 55#define MCP795_ALM0_BIT		BIT(4)
 56#define MCP795_ALM1_BIT		BIT(5)
 57#define MCP795_ALM0IF_BIT	BIT(3)
 58#define MCP795_ALM0C0_BIT	BIT(4)
 59#define MCP795_ALM0C1_BIT	BIT(5)
 60#define MCP795_ALM0C2_BIT	BIT(6)
 61
 62#define SEC_PER_DAY		(24 * 60 * 60)
 63
 64static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
 65{
 66	struct spi_device *spi = to_spi_device(dev);
 67	int ret;
 68	u8 tx[2];
 69
 70	tx[0] = MCP795_READ;
 71	tx[1] = addr;
 72	ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
 73
 74	if (ret)
 75		dev_err(dev, "Failed reading %d bytes from address %x.\n",
 76					count, addr);
 77
 78	return ret;
 79}
 80
 81static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
 82{
 83	struct spi_device *spi = to_spi_device(dev);
 84	int ret;
 85	u8 tx[257];
 86
 87	tx[0] = MCP795_WRITE;
 88	tx[1] = addr;
 89	memcpy(&tx[2], data, count);
 90
 91	ret = spi_write(spi, tx, 2 + count);
 92
 93	if (ret)
 94		dev_err(dev, "Failed to write %d bytes to address %x.\n",
 95					count, addr);
 96
 97	return ret;
 98}
 99
100static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
101{
102	int ret;
103	u8 tmp;
104
105	ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
106	if (ret)
107		return ret;
108
109	if ((tmp & mask) != state) {
110		tmp = (tmp & ~mask) | state;
111		ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
112	}
113
114	return ret;
115}
116
117static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
118{
119	int retries = 5;
120	int ret;
121	u8 data;
122
123	ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
124	if (ret)
125		return ret;
126	ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
127	if (ret)
128		return ret;
129	*extosc = !!(data & MCP795_EXTOSC_BIT);
130	ret = mcp795_rtcc_set_bits(
131				dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
132	if (ret)
133		return ret;
134	/* wait for the OSCON bit to clear */
135	do {
136		usleep_range(700, 800);
137		ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
138		if (ret)
139			break;
140		if (!(data & MCP795_OSCON_BIT))
141			break;
142
143	} while (--retries);
144
145	return !retries ? -EIO : ret;
146}
147
148static int mcp795_start_oscillator(struct device *dev, bool *extosc)
149{
150	if (extosc) {
151		u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
152		int ret;
153
154		ret = mcp795_rtcc_set_bits(
155			dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
156		if (ret)
157			return ret;
158	}
159	return mcp795_rtcc_set_bits(
160			dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
161}
162
163/* Enable or disable Alarm 0 in RTC */
164static int mcp795_update_alarm(struct device *dev, bool enable)
165{
166	int ret;
167
168	dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
169
170	if (enable) {
171		/* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
172		ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
173					MCP795_ALM0IF_BIT, 0);
174		if (ret)
175			return ret;
176		/* enable alarm 0 */
177		ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
178					MCP795_ALM0_BIT, MCP795_ALM0_BIT);
179	} else {
180		/* disable alarm 0 and alarm 1 */
181		ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
182					MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
183	}
184	return ret;
185}
186
187static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
188{
189	int ret;
190	u8 data[7];
191	bool extosc;
192
193	/* Stop RTC and store current value of EXTOSC bit */
194	ret = mcp795_stop_oscillator(dev, &extosc);
195	if (ret)
196		return ret;
197
198	/* Read first, so we can leave config bits untouched */
199	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
200
201	if (ret)
202		return ret;
203
204	data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
205	data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
206	data[2] = bin2bcd(tim->tm_hour);
207	data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
208	data[4] = bin2bcd(tim->tm_mday);
209	data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);
210
211	if (tim->tm_year > 100)
212		tim->tm_year -= 100;
213
214	data[6] = bin2bcd(tim->tm_year);
215
216	/* Always write the date and month using a separate Write command.
217	 * This is a workaround for a know silicon issue that some combinations
218	 * of date and month values may result in the date being reset to 1.
219	 */
220	ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
221	if (ret)
222		return ret;
223
224	ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
225	if (ret)
226		return ret;
227
228	/* Start back RTC and restore previous value of EXTOSC bit.
229	 * There is no need to clear EXTOSC bit when the previous value was 0
230	 * because it was already cleared when stopping the RTC oscillator.
231	 */
232	ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
233	if (ret)
234		return ret;
235
236	dev_dbg(dev, "Set mcp795: %04d-%02d-%02d(%d) %02d:%02d:%02d\n",
237			tim->tm_year + 1900, tim->tm_mon, tim->tm_mday,
238			tim->tm_wday, tim->tm_hour, tim->tm_min, tim->tm_sec);
239
240	return 0;
241}
242
243static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
244{
245	int ret;
246	u8 data[7];
247
248	ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
249
250	if (ret)
251		return ret;
252
253	tim->tm_sec	= bcd2bin(data[0] & 0x7F);
254	tim->tm_min	= bcd2bin(data[1] & 0x7F);
255	tim->tm_hour	= bcd2bin(data[2] & 0x3F);
256	tim->tm_wday	= bcd2bin(data[3] & 0x07) - 1;
257	tim->tm_mday	= bcd2bin(data[4] & 0x3F);
258	tim->tm_mon	= bcd2bin(data[5] & 0x1F) - 1;
259	tim->tm_year	= bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
260
261	dev_dbg(dev, "Read from mcp795: %04d-%02d-%02d(%d) %02d:%02d:%02d\n",
262			tim->tm_year + 1900, tim->tm_mon, tim->tm_mday,
263			tim->tm_wday, tim->tm_hour, tim->tm_min, tim->tm_sec);
264
265	return 0;
266}
267
268static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
269{
270	struct rtc_time now_tm;
271	time64_t now;
272	time64_t later;
273	u8 tmp[6];
274	int ret;
275
276	/* Read current time from RTC hardware */
277	ret = mcp795_read_time(dev, &now_tm);
278	if (ret)
279		return ret;
280	/* Get the number of seconds since 1970 */
281	now = rtc_tm_to_time64(&now_tm);
282	later = rtc_tm_to_time64(&alm->time);
283	if (later <= now)
284		return -EINVAL;
285	/* make sure alarm fires within the next one year */
286	if ((later - now) >=
287		(SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
288		return -EDOM;
289	/* disable alarm */
290	ret = mcp795_update_alarm(dev, false);
291	if (ret)
292		return ret;
293	/* Read registers, so we can leave configuration bits untouched */
294	ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
295	if (ret)
296		return ret;
297
298	alm->time.tm_year	= -1;
299	alm->time.tm_isdst	= -1;
300	alm->time.tm_yday	= -1;
301
302	tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
303	tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
304	tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
305	tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
306	/* set alarm match: seconds, minutes, hour, day, date and month */
307	tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
308	tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
309	tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);
310
311	ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
312	if (ret)
313		return ret;
314
315	/* enable alarm if requested */
316	if (alm->enabled) {
317		ret = mcp795_update_alarm(dev, true);
318		if (ret)
319			return ret;
320		dev_dbg(dev, "Alarm IRQ armed\n");
321	}
322	dev_dbg(dev, "Set alarm: %02d-%02d(%d) %02d:%02d:%02d\n",
323			alm->time.tm_mon, alm->time.tm_mday, alm->time.tm_wday,
324			alm->time.tm_hour, alm->time.tm_min, alm->time.tm_sec);
325	return 0;
326}
327
328static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
329{
330	u8 data[6];
331	int ret;
332
333	ret = mcp795_rtcc_read(
334			dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
335	if (ret)
336		return ret;
337
338	alm->time.tm_sec	= bcd2bin(data[0] & 0x7F);
339	alm->time.tm_min	= bcd2bin(data[1] & 0x7F);
340	alm->time.tm_hour	= bcd2bin(data[2] & 0x1F);
341	alm->time.tm_wday	= bcd2bin(data[3] & 0x07) - 1;
342	alm->time.tm_mday	= bcd2bin(data[4] & 0x3F);
343	alm->time.tm_mon	= bcd2bin(data[5] & 0x1F) - 1;
344	alm->time.tm_year	= -1;
345	alm->time.tm_isdst	= -1;
346	alm->time.tm_yday	= -1;
347
348	dev_dbg(dev, "Read alarm: %02d-%02d(%d) %02d:%02d:%02d\n",
349			alm->time.tm_mon, alm->time.tm_mday, alm->time.tm_wday,
350			alm->time.tm_hour, alm->time.tm_min, alm->time.tm_sec);
351	return 0;
352}
353
354static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
355{
356	return mcp795_update_alarm(dev, !!enabled);
357}
358
359static irqreturn_t mcp795_irq(int irq, void *data)
360{
361	struct spi_device *spi = data;
362	struct rtc_device *rtc = spi_get_drvdata(spi);
363	struct mutex *lock = &rtc->ops_lock;
364	int ret;
365
366	mutex_lock(lock);
367
368	/* Disable alarm.
369	 * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
370	 * because it is done every time when alarm is enabled.
371	 */
372	ret = mcp795_update_alarm(&spi->dev, false);
373	if (ret)
374		dev_err(&spi->dev,
375			"Failed to disable alarm in IRQ (ret=%d)\n", ret);
376	rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
377
378	mutex_unlock(lock);
379
380	return IRQ_HANDLED;
381}
382
383static const struct rtc_class_ops mcp795_rtc_ops = {
384		.read_time = mcp795_read_time,
385		.set_time = mcp795_set_time,
386		.read_alarm = mcp795_read_alarm,
387		.set_alarm = mcp795_set_alarm,
388		.alarm_irq_enable = mcp795_alarm_irq_enable
389};
390
391static int mcp795_probe(struct spi_device *spi)
392{
393	struct rtc_device *rtc;
394	int ret;
395
396	spi->mode = SPI_MODE_0;
397	spi->bits_per_word = 8;
398	ret = spi_setup(spi);
399	if (ret) {
400		dev_err(&spi->dev, "Unable to setup SPI\n");
401		return ret;
402	}
403
404	/* Start the oscillator but don't set the value of EXTOSC bit */
405	mcp795_start_oscillator(&spi->dev, NULL);
406	/* Clear the 12 hour mode flag*/
407	mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
408
409	rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
410					&mcp795_rtc_ops, THIS_MODULE);
411	if (IS_ERR(rtc))
412		return PTR_ERR(rtc);
413
414	spi_set_drvdata(spi, rtc);
415
416	if (spi->irq > 0) {
417		dev_dbg(&spi->dev, "Alarm support enabled\n");
418
419		/* Clear any pending alarm (ALM0IF bit) before requesting
420		 * the interrupt.
421		 */
422		mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
423					MCP795_ALM0IF_BIT, 0);
424		ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
425				mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
426				dev_name(&rtc->dev), spi);
427		if (ret)
428			dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
429						spi->irq, ret);
430		else
431			device_init_wakeup(&spi->dev, true);
432	}
433	return 0;
434}
435
436#ifdef CONFIG_OF
437static const struct of_device_id mcp795_of_match[] = {
438	{ .compatible = "maxim,mcp795" },
439	{ }
440};
441MODULE_DEVICE_TABLE(of, mcp795_of_match);
442#endif
443
444static struct spi_driver mcp795_driver = {
445		.driver = {
446				.name = "rtc-mcp795",
447				.of_match_table = of_match_ptr(mcp795_of_match),
448		},
449		.probe = mcp795_probe,
450};
451
452module_spi_driver(mcp795_driver);
453
454MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
455MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
456MODULE_LICENSE("GPL");
457MODULE_ALIAS("spi:mcp795");