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1/*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, see <http://www.gnu.org/licenses/>.
22 .
23 . Information contained in this file was obtained from the LAN91C111
24 . manual from SMC. To get a copy, if you really want one, you can find
25 . information under www.smsc.com.
26 .
27 . Authors
28 . Erik Stahlman <erik@vt.edu>
29 . Daris A Nevil <dnevil@snmc.com>
30 . Nicolas Pitre <nico@fluxnic.net>
31 .
32 ---------------------------------------------------------------------------*/
33#ifndef _SMC91X_H_
34#define _SMC91X_H_
35
36#include <linux/dmaengine.h>
37#include <linux/smc91x.h>
38
39/*
40 * Any 16-bit access is performed with two 8-bit accesses if the hardware
41 * can't do it directly. Most registers are 16-bit so those are mandatory.
42 */
43#define SMC_outw_b(x, a, r) \
44 do { \
45 unsigned int __val16 = (x); \
46 unsigned int __reg = (r); \
47 SMC_outb(__val16, a, __reg); \
48 SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
49 } while (0)
50
51#define SMC_inw_b(a, r) \
52 ({ \
53 unsigned int __val16; \
54 unsigned int __reg = r; \
55 __val16 = SMC_inb(a, __reg); \
56 __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
57 __val16; \
58 })
59
60/*
61 * Define your architecture specific bus configuration parameters here.
62 */
63
64#if defined(CONFIG_ARM)
65
66#include <asm/mach-types.h>
67
68/* Now the bus width is specified in the platform data
69 * pretend here to support all I/O access types
70 */
71#define SMC_CAN_USE_8BIT 1
72#define SMC_CAN_USE_16BIT 1
73#define SMC_CAN_USE_32BIT 1
74#define SMC_NOWAIT 1
75
76#define SMC_IO_SHIFT (lp->io_shift)
77
78#define SMC_inb(a, r) readb((a) + (r))
79#define SMC_inw(a, r) \
80 ({ \
81 unsigned int __smc_r = r; \
82 SMC_16BIT(lp) ? readw((a) + __smc_r) : \
83 SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) : \
84 ({ BUG(); 0; }); \
85 })
86
87#define SMC_inl(a, r) readl((a) + (r))
88#define SMC_outb(v, a, r) writeb(v, (a) + (r))
89#define SMC_outw(lp, v, a, r) \
90 do { \
91 unsigned int __v = v, __smc_r = r; \
92 if (SMC_16BIT(lp)) \
93 __SMC_outw(lp, __v, a, __smc_r); \
94 else if (SMC_8BIT(lp)) \
95 SMC_outw_b(__v, a, __smc_r); \
96 else \
97 BUG(); \
98 } while (0)
99
100#define SMC_outl(v, a, r) writel(v, (a) + (r))
101#define SMC_insb(a, r, p, l) readsb((a) + (r), p, l)
102#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, l)
103#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
104#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
105#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
106#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
107#define SMC_IRQ_FLAGS (-1) /* from resource */
108
109/* We actually can't write halfwords properly if not word aligned */
110static inline void _SMC_outw_align4(u16 val, void __iomem *ioaddr, int reg,
111 bool use_align4_workaround)
112{
113 if (use_align4_workaround) {
114 unsigned int v = val << 16;
115 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
116 writel(v, ioaddr + (reg & ~2));
117 } else {
118 writew(val, ioaddr + reg);
119 }
120}
121
122#define __SMC_outw(lp, v, a, r) \
123 _SMC_outw_align4((v), (a), (r), \
124 IS_BUILTIN(CONFIG_ARCH_PXA) && ((r) & 2) && \
125 (lp)->cfg.pxa_u16_align4)
126
127
128#elif defined(CONFIG_SH_SH4202_MICRODEV)
129
130#define SMC_CAN_USE_8BIT 0
131#define SMC_CAN_USE_16BIT 1
132#define SMC_CAN_USE_32BIT 0
133
134#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
135#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
136#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
137#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
138#define SMC_outw(lp, v, a, r) outw(v, (a) + (r) - 0xa0000000)
139#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
140#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
141#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
142#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
143#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
144
145#define SMC_IRQ_FLAGS (0)
146
147#elif defined(CONFIG_ATARI)
148
149#define SMC_CAN_USE_8BIT 1
150#define SMC_CAN_USE_16BIT 1
151#define SMC_CAN_USE_32BIT 1
152#define SMC_NOWAIT 1
153
154#define SMC_inb(a, r) readb((a) + (r))
155#define SMC_inw(a, r) readw((a) + (r))
156#define SMC_inl(a, r) readl((a) + (r))
157#define SMC_outb(v, a, r) writeb(v, (a) + (r))
158#define SMC_outw(lp, v, a, r) writew(v, (a) + (r))
159#define SMC_outl(v, a, r) writel(v, (a) + (r))
160#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
161#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
162#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
163#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
164
165#define RPC_LSA_DEFAULT RPC_LED_100_10
166#define RPC_LSB_DEFAULT RPC_LED_TX_RX
167
168#elif defined(CONFIG_COLDFIRE)
169
170#define SMC_CAN_USE_8BIT 0
171#define SMC_CAN_USE_16BIT 1
172#define SMC_CAN_USE_32BIT 0
173#define SMC_NOWAIT 1
174
175static inline void mcf_insw(void *a, unsigned char *p, int l)
176{
177 u16 *wp = (u16 *) p;
178 while (l-- > 0)
179 *wp++ = readw(a);
180}
181
182static inline void mcf_outsw(void *a, unsigned char *p, int l)
183{
184 u16 *wp = (u16 *) p;
185 while (l-- > 0)
186 writew(*wp++, a);
187}
188
189#define SMC_inw(a, r) _swapw(readw((a) + (r)))
190#define SMC_outw(lp, v, a, r) writew(_swapw(v), (a) + (r))
191#define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l)
192#define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l)
193
194#define SMC_IRQ_FLAGS 0
195
196#elif defined(CONFIG_H8300)
197#define SMC_CAN_USE_8BIT 1
198#define SMC_CAN_USE_16BIT 0
199#define SMC_CAN_USE_32BIT 0
200#define SMC_NOWAIT 0
201
202#define SMC_inb(a, r) ioread8((a) + (r))
203#define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
204#define SMC_insb(a, r, p, l) ioread8_rep((a) + (r), p, l)
205#define SMC_outsb(a, r, p, l) iowrite8_rep((a) + (r), p, l)
206
207#else
208
209/*
210 * Default configuration
211 */
212
213#define SMC_CAN_USE_8BIT 1
214#define SMC_CAN_USE_16BIT 1
215#define SMC_CAN_USE_32BIT 1
216#define SMC_NOWAIT 1
217
218#define SMC_IO_SHIFT (lp->io_shift)
219
220#define SMC_inb(a, r) ioread8((a) + (r))
221#define SMC_inw(a, r) ioread16((a) + (r))
222#define SMC_inl(a, r) ioread32((a) + (r))
223#define SMC_outb(v, a, r) iowrite8(v, (a) + (r))
224#define SMC_outw(lp, v, a, r) iowrite16(v, (a) + (r))
225#define SMC_outl(v, a, r) iowrite32(v, (a) + (r))
226#define SMC_insw(a, r, p, l) ioread16_rep((a) + (r), p, l)
227#define SMC_outsw(a, r, p, l) iowrite16_rep((a) + (r), p, l)
228#define SMC_insl(a, r, p, l) ioread32_rep((a) + (r), p, l)
229#define SMC_outsl(a, r, p, l) iowrite32_rep((a) + (r), p, l)
230
231#define RPC_LSA_DEFAULT RPC_LED_100_10
232#define RPC_LSB_DEFAULT RPC_LED_TX_RX
233
234#endif
235
236
237/* store this information for the driver.. */
238struct smc_local {
239 /*
240 * If I have to wait until memory is available to send a
241 * packet, I will store the skbuff here, until I get the
242 * desired memory. Then, I'll send it out and free it.
243 */
244 struct sk_buff *pending_tx_skb;
245 struct tasklet_struct tx_task;
246
247 struct gpio_desc *power_gpio;
248 struct gpio_desc *reset_gpio;
249
250 /* version/revision of the SMC91x chip */
251 int version;
252
253 /* Contains the current active transmission mode */
254 int tcr_cur_mode;
255
256 /* Contains the current active receive mode */
257 int rcr_cur_mode;
258
259 /* Contains the current active receive/phy mode */
260 int rpc_cur_mode;
261 int ctl_rfduplx;
262 int ctl_rspeed;
263
264 u32 msg_enable;
265 u32 phy_type;
266 struct mii_if_info mii;
267
268 /* work queue */
269 struct work_struct phy_configure;
270 struct net_device *dev;
271 int work_pending;
272
273 spinlock_t lock;
274
275#ifdef CONFIG_ARCH_PXA
276 /* DMA needs the physical address of the chip */
277 u_long physaddr;
278 struct device *device;
279#endif
280 struct dma_chan *dma_chan;
281 void __iomem *base;
282 void __iomem *datacs;
283
284 /* the low address lines on some platforms aren't connected... */
285 int io_shift;
286 /* on some platforms a u16 write must be 4-bytes aligned */
287 bool half_word_align4;
288
289 struct smc91x_platdata cfg;
290};
291
292#define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
293#define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
294#define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
295
296#ifdef CONFIG_ARCH_PXA
297/*
298 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
299 * always happening in irq context so no need to worry about races. TX is
300 * different and probably not worth it for that reason, and not as critical
301 * as RX which can overrun memory and lose packets.
302 */
303#include <linux/dma-mapping.h>
304#include <linux/dma/pxa-dma.h>
305
306#ifdef SMC_insl
307#undef SMC_insl
308#define SMC_insl(a, r, p, l) \
309 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
310static inline void
311smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)
312{
313 dma_addr_t dmabuf;
314 struct dma_async_tx_descriptor *tx;
315 dma_cookie_t cookie;
316 enum dma_status status;
317 struct dma_tx_state state;
318
319 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
320 tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,
321 DMA_DEV_TO_MEM, 0);
322 if (tx) {
323 cookie = dmaengine_submit(tx);
324 dma_async_issue_pending(lp->dma_chan);
325 do {
326 status = dmaengine_tx_status(lp->dma_chan, cookie,
327 &state);
328 cpu_relax();
329 } while (status != DMA_COMPLETE && status != DMA_ERROR &&
330 state.residue);
331 dmaengine_terminate_all(lp->dma_chan);
332 }
333 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
334}
335
336static inline void
337smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
338 u_char *buf, int len)
339{
340 struct dma_slave_config config;
341 int ret;
342
343 /* fallback if no DMA available */
344 if (!lp->dma_chan) {
345 readsl(ioaddr + reg, buf, len);
346 return;
347 }
348
349 /* 64 bit alignment is required for memory to memory DMA */
350 if ((long)buf & 4) {
351 *((u32 *)buf) = SMC_inl(ioaddr, reg);
352 buf += 4;
353 len--;
354 }
355
356 memset(&config, 0, sizeof(config));
357 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
358 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
359 config.src_addr = lp->physaddr + reg;
360 config.dst_addr = lp->physaddr + reg;
361 config.src_maxburst = 32;
362 config.dst_maxburst = 32;
363 ret = dmaengine_slave_config(lp->dma_chan, &config);
364 if (ret) {
365 dev_err(lp->device, "dma channel configuration failed: %d\n",
366 ret);
367 return;
368 }
369
370 len *= 4;
371 smc_pxa_dma_inpump(lp, buf, len);
372}
373#endif
374
375#ifdef SMC_insw
376#undef SMC_insw
377#define SMC_insw(a, r, p, l) \
378 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
379static inline void
380smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
381 u_char *buf, int len)
382{
383 struct dma_slave_config config;
384 int ret;
385
386 /* fallback if no DMA available */
387 if (!lp->dma_chan) {
388 readsw(ioaddr + reg, buf, len);
389 return;
390 }
391
392 /* 64 bit alignment is required for memory to memory DMA */
393 while ((long)buf & 6) {
394 *((u16 *)buf) = SMC_inw(ioaddr, reg);
395 buf += 2;
396 len--;
397 }
398
399 memset(&config, 0, sizeof(config));
400 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
401 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
402 config.src_addr = lp->physaddr + reg;
403 config.dst_addr = lp->physaddr + reg;
404 config.src_maxburst = 32;
405 config.dst_maxburst = 32;
406 ret = dmaengine_slave_config(lp->dma_chan, &config);
407 if (ret) {
408 dev_err(lp->device, "dma channel configuration failed: %d\n",
409 ret);
410 return;
411 }
412
413 len *= 2;
414 smc_pxa_dma_inpump(lp, buf, len);
415}
416#endif
417
418#endif /* CONFIG_ARCH_PXA */
419
420
421/*
422 * Everything a particular hardware setup needs should have been defined
423 * at this point. Add stubs for the undefined cases, mainly to avoid
424 * compilation warnings since they'll be optimized away, or to prevent buggy
425 * use of them.
426 */
427
428#if ! SMC_CAN_USE_32BIT
429#define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
430#define SMC_outl(x, ioaddr, reg) BUG()
431#define SMC_insl(a, r, p, l) BUG()
432#define SMC_outsl(a, r, p, l) BUG()
433#endif
434
435#if !defined(SMC_insl) || !defined(SMC_outsl)
436#define SMC_insl(a, r, p, l) BUG()
437#define SMC_outsl(a, r, p, l) BUG()
438#endif
439
440#if ! SMC_CAN_USE_16BIT
441
442#define SMC_outw(lp, x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg)
443#define SMC_inw(ioaddr, reg) SMC_inw_b(ioaddr, reg)
444#define SMC_insw(a, r, p, l) BUG()
445#define SMC_outsw(a, r, p, l) BUG()
446
447#endif
448
449#if !defined(SMC_insw) || !defined(SMC_outsw)
450#define SMC_insw(a, r, p, l) BUG()
451#define SMC_outsw(a, r, p, l) BUG()
452#endif
453
454#if ! SMC_CAN_USE_8BIT
455#undef SMC_inb
456#define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
457#undef SMC_outb
458#define SMC_outb(x, ioaddr, reg) BUG()
459#define SMC_insb(a, r, p, l) BUG()
460#define SMC_outsb(a, r, p, l) BUG()
461#endif
462
463#if !defined(SMC_insb) || !defined(SMC_outsb)
464#define SMC_insb(a, r, p, l) BUG()
465#define SMC_outsb(a, r, p, l) BUG()
466#endif
467
468#ifndef SMC_CAN_USE_DATACS
469#define SMC_CAN_USE_DATACS 0
470#endif
471
472#ifndef SMC_IO_SHIFT
473#define SMC_IO_SHIFT 0
474#endif
475
476#ifndef SMC_IRQ_FLAGS
477#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
478#endif
479
480#ifndef SMC_INTERRUPT_PREAMBLE
481#define SMC_INTERRUPT_PREAMBLE
482#endif
483
484
485/* Because of bank switching, the LAN91x uses only 16 I/O ports */
486#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
487#define SMC_DATA_EXTENT (4)
488
489/*
490 . Bank Select Register:
491 .
492 . yyyy yyyy 0000 00xx
493 . xx = bank number
494 . yyyy yyyy = 0x33, for identification purposes.
495*/
496#define BANK_SELECT (14 << SMC_IO_SHIFT)
497
498
499// Transmit Control Register
500/* BANK 0 */
501#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
502#define TCR_ENABLE 0x0001 // When 1 we can transmit
503#define TCR_LOOP 0x0002 // Controls output pin LBK
504#define TCR_FORCOL 0x0004 // When 1 will force a collision
505#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
506#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
507#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
508#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
509#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
510#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
511#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
512
513#define TCR_CLEAR 0 /* do NOTHING */
514/* the default settings for the TCR register : */
515#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
516
517
518// EPH Status Register
519/* BANK 0 */
520#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
521#define ES_TX_SUC 0x0001 // Last TX was successful
522#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
523#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
524#define ES_LTX_MULT 0x0008 // Last tx was a multicast
525#define ES_16COL 0x0010 // 16 Collisions Reached
526#define ES_SQET 0x0020 // Signal Quality Error Test
527#define ES_LTXBRD 0x0040 // Last tx was a broadcast
528#define ES_TXDEFR 0x0080 // Transmit Deferred
529#define ES_LATCOL 0x0200 // Late collision detected on last tx
530#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
531#define ES_EXC_DEF 0x0800 // Excessive Deferral
532#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
533#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
534#define ES_TXUNRN 0x8000 // Tx Underrun
535
536
537// Receive Control Register
538/* BANK 0 */
539#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
540#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
541#define RCR_PRMS 0x0002 // Enable promiscuous mode
542#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
543#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
544#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
545#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
546#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
547#define RCR_SOFTRST 0x8000 // resets the chip
548
549/* the normal settings for the RCR register : */
550#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
551#define RCR_CLEAR 0x0 // set it to a base state
552
553
554// Counter Register
555/* BANK 0 */
556#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
557
558
559// Memory Information Register
560/* BANK 0 */
561#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
562
563
564// Receive/Phy Control Register
565/* BANK 0 */
566#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
567#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
568#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
569#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
570#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
571#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
572
573#ifndef RPC_LSA_DEFAULT
574#define RPC_LSA_DEFAULT RPC_LED_100
575#endif
576#ifndef RPC_LSB_DEFAULT
577#define RPC_LSB_DEFAULT RPC_LED_FD
578#endif
579
580#define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
581
582
583/* Bank 0 0x0C is reserved */
584
585// Bank Select Register
586/* All Banks */
587#define BSR_REG 0x000E
588
589
590// Configuration Reg
591/* BANK 1 */
592#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
593#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
594#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
595#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
596#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
597
598// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
599#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
600
601
602// Base Address Register
603/* BANK 1 */
604#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
605
606
607// Individual Address Registers
608/* BANK 1 */
609#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
610#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
611#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
612
613
614// General Purpose Register
615/* BANK 1 */
616#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
617
618
619// Control Register
620/* BANK 1 */
621#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
622#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
623#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
624#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
625#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
626#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
627#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
628#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
629#define CTL_STORE 0x0001 // When set stores registers into EEPROM
630
631
632// MMU Command Register
633/* BANK 2 */
634#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
635#define MC_BUSY 1 // When 1 the last release has not completed
636#define MC_NOP (0<<5) // No Op
637#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
638#define MC_RESET (2<<5) // Reset MMU to initial state
639#define MC_REMOVE (3<<5) // Remove the current rx packet
640#define MC_RELEASE (4<<5) // Remove and release the current rx packet
641#define MC_FREEPKT (5<<5) // Release packet in PNR register
642#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
643#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
644
645
646// Packet Number Register
647/* BANK 2 */
648#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
649
650
651// Allocation Result Register
652/* BANK 2 */
653#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
654#define AR_FAILED 0x80 // Alocation Failed
655
656
657// TX FIFO Ports Register
658/* BANK 2 */
659#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
660#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
661
662// RX FIFO Ports Register
663/* BANK 2 */
664#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
665#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
666
667#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
668
669// Pointer Register
670/* BANK 2 */
671#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
672#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
673#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
674#define PTR_READ 0x2000 // When 1 the operation is a read
675
676
677// Data Register
678/* BANK 2 */
679#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
680
681
682// Interrupt Status/Acknowledge Register
683/* BANK 2 */
684#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
685
686
687// Interrupt Mask Register
688/* BANK 2 */
689#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
690#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
691#define IM_ERCV_INT 0x40 // Early Receive Interrupt
692#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
693#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
694#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
695#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
696#define IM_TX_INT 0x02 // Transmit Interrupt
697#define IM_RCV_INT 0x01 // Receive Interrupt
698
699
700// Multicast Table Registers
701/* BANK 3 */
702#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
703#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
704#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
705#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
706
707
708// Management Interface Register (MII)
709/* BANK 3 */
710#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
711#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
712#define MII_MDOE 0x0008 // MII Output Enable
713#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
714#define MII_MDI 0x0002 // MII Input, pin MDI
715#define MII_MDO 0x0001 // MII Output, pin MDO
716
717
718// Revision Register
719/* BANK 3 */
720/* ( hi: chip id low: rev # ) */
721#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
722
723
724// Early RCV Register
725/* BANK 3 */
726/* this is NOT on SMC9192 */
727#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
728#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
729#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
730
731
732// External Register
733/* BANK 7 */
734#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
735
736
737#define CHIP_9192 3
738#define CHIP_9194 4
739#define CHIP_9195 5
740#define CHIP_9196 6
741#define CHIP_91100 7
742#define CHIP_91100FD 8
743#define CHIP_91111FD 9
744
745static const char * chip_ids[ 16 ] = {
746 NULL, NULL, NULL,
747 /* 3 */ "SMC91C90/91C92",
748 /* 4 */ "SMC91C94",
749 /* 5 */ "SMC91C95",
750 /* 6 */ "SMC91C96",
751 /* 7 */ "SMC91C100",
752 /* 8 */ "SMC91C100FD",
753 /* 9 */ "SMC91C11xFD",
754 NULL, NULL, NULL,
755 NULL, NULL, NULL};
756
757
758/*
759 . Receive status bits
760*/
761#define RS_ALGNERR 0x8000
762#define RS_BRODCAST 0x4000
763#define RS_BADCRC 0x2000
764#define RS_ODDFRAME 0x1000
765#define RS_TOOLONG 0x0800
766#define RS_TOOSHORT 0x0400
767#define RS_MULTICAST 0x0001
768#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
769
770
771/*
772 * PHY IDs
773 * LAN83C183 == LAN91C111 Internal PHY
774 */
775#define PHY_LAN83C183 0x0016f840
776#define PHY_LAN83C180 0x02821c50
777
778/*
779 * PHY Register Addresses (LAN91C111 Internal PHY)
780 *
781 * Generic PHY registers can be found in <linux/mii.h>
782 *
783 * These phy registers are specific to our on-board phy.
784 */
785
786// PHY Configuration Register 1
787#define PHY_CFG1_REG 0x10
788#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
789#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
790#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
791#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
792#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
793#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
794#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
795#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
796#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
797#define PHY_CFG1_TLVL_MASK 0x003C
798#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
799
800
801// PHY Configuration Register 2
802#define PHY_CFG2_REG 0x11
803#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
804#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
805#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
806#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
807
808// PHY Status Output (and Interrupt status) Register
809#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
810#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
811#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
812#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
813#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
814#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
815#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
816#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
817#define PHY_INT_JAB 0x0100 // 1=Jabber detected
818#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
819#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
820
821// PHY Interrupt/Status Mask Register
822#define PHY_MASK_REG 0x13 // Interrupt Mask
823// Uses the same bit definitions as PHY_INT_REG
824
825
826/*
827 * SMC91C96 ethernet config and status registers.
828 * These are in the "attribute" space.
829 */
830#define ECOR 0x8000
831#define ECOR_RESET 0x80
832#define ECOR_LEVEL_IRQ 0x40
833#define ECOR_WR_ATTRIB 0x04
834#define ECOR_ENABLE 0x01
835
836#define ECSR 0x8002
837#define ECSR_IOIS8 0x20
838#define ECSR_PWRDWN 0x04
839#define ECSR_INT 0x02
840
841#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
842
843
844/*
845 * Macros to abstract register access according to the data bus
846 * capabilities. Please use those and not the in/out primitives.
847 * Note: the following macros do *not* select the bank -- this must
848 * be done separately as needed in the main code. The SMC_REG() macro
849 * only uses the bank argument for debugging purposes (when enabled).
850 *
851 * Note: despite inline functions being safer, everything leading to this
852 * should preferably be macros to let BUG() display the line number in
853 * the core source code since we're interested in the top call site
854 * not in any inline function location.
855 */
856
857#if SMC_DEBUG > 0
858#define SMC_REG(lp, reg, bank) \
859 ({ \
860 int __b = SMC_CURRENT_BANK(lp); \
861 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
862 pr_err("%s: bank reg screwed (0x%04x)\n", \
863 CARDNAME, __b); \
864 BUG(); \
865 } \
866 reg<<SMC_IO_SHIFT; \
867 })
868#else
869#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
870#endif
871
872/*
873 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
874 * aligned to a 32 bit boundary. I tell you that does exist!
875 * Fortunately the affected register accesses can be easily worked around
876 * since we can write zeroes to the preceding 16 bits without adverse
877 * effects and use a 32-bit access.
878 *
879 * Enforce it on any 32-bit capable setup for now.
880 */
881#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
882
883#define SMC_GET_PN(lp) \
884 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
885 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
886
887#define SMC_SET_PN(lp, x) \
888 do { \
889 if (SMC_MUST_ALIGN_WRITE(lp)) \
890 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
891 else if (SMC_8BIT(lp)) \
892 SMC_outb(x, ioaddr, PN_REG(lp)); \
893 else \
894 SMC_outw(lp, x, ioaddr, PN_REG(lp)); \
895 } while (0)
896
897#define SMC_GET_AR(lp) \
898 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
899 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
900
901#define SMC_GET_TXFIFO(lp) \
902 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
903 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
904
905#define SMC_GET_RXFIFO(lp) \
906 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
907 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
908
909#define SMC_GET_INT(lp) \
910 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
911 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
912
913#define SMC_ACK_INT(lp, x) \
914 do { \
915 if (SMC_8BIT(lp)) \
916 SMC_outb(x, ioaddr, INT_REG(lp)); \
917 else { \
918 unsigned long __flags; \
919 int __mask; \
920 local_irq_save(__flags); \
921 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
922 SMC_outw(lp, __mask | (x), ioaddr, INT_REG(lp)); \
923 local_irq_restore(__flags); \
924 } \
925 } while (0)
926
927#define SMC_GET_INT_MASK(lp) \
928 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
929 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
930
931#define SMC_SET_INT_MASK(lp, x) \
932 do { \
933 if (SMC_8BIT(lp)) \
934 SMC_outb(x, ioaddr, IM_REG(lp)); \
935 else \
936 SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp)); \
937 } while (0)
938
939#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
940
941#define SMC_SELECT_BANK(lp, x) \
942 do { \
943 if (SMC_MUST_ALIGN_WRITE(lp)) \
944 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
945 else \
946 SMC_outw(lp, x, ioaddr, BANK_SELECT); \
947 } while (0)
948
949#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
950
951#define SMC_SET_BASE(lp, x) SMC_outw(lp, x, ioaddr, BASE_REG(lp))
952
953#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
954
955#define SMC_SET_CONFIG(lp, x) SMC_outw(lp, x, ioaddr, CONFIG_REG(lp))
956
957#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
958
959#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
960
961#define SMC_SET_CTL(lp, x) SMC_outw(lp, x, ioaddr, CTL_REG(lp))
962
963#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
964
965#define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
966
967#define SMC_SET_GP(lp, x) \
968 do { \
969 if (SMC_MUST_ALIGN_WRITE(lp)) \
970 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
971 else \
972 SMC_outw(lp, x, ioaddr, GP_REG(lp)); \
973 } while (0)
974
975#define SMC_SET_MII(lp, x) SMC_outw(lp, x, ioaddr, MII_REG(lp))
976
977#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
978
979#define SMC_SET_MIR(lp, x) SMC_outw(lp, x, ioaddr, MIR_REG(lp))
980
981#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
982
983#define SMC_SET_MMU_CMD(lp, x) SMC_outw(lp, x, ioaddr, MMU_CMD_REG(lp))
984
985#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
986
987#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
988
989#define SMC_SET_PTR(lp, x) \
990 do { \
991 if (SMC_MUST_ALIGN_WRITE(lp)) \
992 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
993 else \
994 SMC_outw(lp, x, ioaddr, PTR_REG(lp)); \
995 } while (0)
996
997#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
998
999#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1000
1001#define SMC_SET_RCR(lp, x) SMC_outw(lp, x, ioaddr, RCR_REG(lp))
1002
1003#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1004
1005#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1006
1007#define SMC_SET_RPC(lp, x) \
1008 do { \
1009 if (SMC_MUST_ALIGN_WRITE(lp)) \
1010 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1011 else \
1012 SMC_outw(lp, x, ioaddr, RPC_REG(lp)); \
1013 } while (0)
1014
1015#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1016
1017#define SMC_SET_TCR(lp, x) SMC_outw(lp, x, ioaddr, TCR_REG(lp))
1018
1019#ifndef SMC_GET_MAC_ADDR
1020#define SMC_GET_MAC_ADDR(lp, addr) \
1021 do { \
1022 unsigned int __v; \
1023 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1024 addr[0] = __v; addr[1] = __v >> 8; \
1025 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1026 addr[2] = __v; addr[3] = __v >> 8; \
1027 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1028 addr[4] = __v; addr[5] = __v >> 8; \
1029 } while (0)
1030#endif
1031
1032#define SMC_SET_MAC_ADDR(lp, addr) \
1033 do { \
1034 SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1035 SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1036 SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1037 } while (0)
1038
1039#define SMC_SET_MCAST(lp, x) \
1040 do { \
1041 const unsigned char *mt = (x); \
1042 SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1043 SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1044 SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1045 SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1046 } while (0)
1047
1048#define SMC_PUT_PKT_HDR(lp, status, length) \
1049 do { \
1050 if (SMC_32BIT(lp)) \
1051 SMC_outl((status) | (length)<<16, ioaddr, \
1052 DATA_REG(lp)); \
1053 else { \
1054 SMC_outw(lp, status, ioaddr, DATA_REG(lp)); \
1055 SMC_outw(lp, length, ioaddr, DATA_REG(lp)); \
1056 } \
1057 } while (0)
1058
1059#define SMC_GET_PKT_HDR(lp, status, length) \
1060 do { \
1061 if (SMC_32BIT(lp)) { \
1062 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1063 (status) = __val & 0xffff; \
1064 (length) = __val >> 16; \
1065 } else { \
1066 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1067 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1068 } \
1069 } while (0)
1070
1071#define SMC_PUSH_DATA(lp, p, l) \
1072 do { \
1073 if (SMC_32BIT(lp)) { \
1074 void *__ptr = (p); \
1075 int __len = (l); \
1076 void __iomem *__ioaddr = ioaddr; \
1077 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1078 __len -= 2; \
1079 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1080 __ptr += 2; \
1081 } \
1082 if (SMC_CAN_USE_DATACS && lp->datacs) \
1083 __ioaddr = lp->datacs; \
1084 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1085 if (__len & 2) { \
1086 __ptr += (__len & ~3); \
1087 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1088 } \
1089 } else if (SMC_16BIT(lp)) \
1090 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1091 else if (SMC_8BIT(lp)) \
1092 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1093 } while (0)
1094
1095#define SMC_PULL_DATA(lp, p, l) \
1096 do { \
1097 if (SMC_32BIT(lp)) { \
1098 void *__ptr = (p); \
1099 int __len = (l); \
1100 void __iomem *__ioaddr = ioaddr; \
1101 if ((unsigned long)__ptr & 2) { \
1102 /* \
1103 * We want 32bit alignment here. \
1104 * Since some buses perform a full \
1105 * 32bit fetch even for 16bit data \
1106 * we can't use SMC_inw() here. \
1107 * Back both source (on-chip) and \
1108 * destination pointers of 2 bytes. \
1109 * This is possible since the call to \
1110 * SMC_GET_PKT_HDR() already advanced \
1111 * the source pointer of 4 bytes, and \
1112 * the skb_reserve(skb, 2) advanced \
1113 * the destination pointer of 2 bytes. \
1114 */ \
1115 __ptr -= 2; \
1116 __len += 2; \
1117 SMC_SET_PTR(lp, \
1118 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1119 } \
1120 if (SMC_CAN_USE_DATACS && lp->datacs) \
1121 __ioaddr = lp->datacs; \
1122 __len += 2; \
1123 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1124 } else if (SMC_16BIT(lp)) \
1125 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1126 else if (SMC_8BIT(lp)) \
1127 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1128 } while (0)
1129
1130#endif /* _SMC91X_H_ */