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1/* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#include <linux/types.h>
33#include <asm/byteorder.h>
34#include <linux/bitops.h>
35#include <linux/delay.h>
36#include <linux/dma-mapping.h>
37#include <linux/errno.h>
38#include <linux/io.h>
39#include <linux/kernel.h>
40#include <linux/list.h>
41#include <linux/module.h>
42#include <linux/mutex.h>
43#include <linux/pci.h>
44#include <linux/slab.h>
45#include <linux/spinlock.h>
46#include <linux/string.h>
47#include "qed.h"
48#include "qed_cxt.h"
49#include "qed_hsi.h"
50#include "qed_hw.h"
51#include "qed_init_ops.h"
52#include "qed_int.h"
53#include "qed_ll2.h"
54#include "qed_mcp.h"
55#include "qed_reg_addr.h"
56#include <linux/qed/qed_rdma_if.h>
57#include "qed_rdma.h"
58#include "qed_roce.h"
59#include "qed_sp.h"
60
61
62int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn,
63 struct qed_bmap *bmap, u32 max_count, char *name)
64{
65 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count);
66
67 bmap->max_count = max_count;
68
69 bmap->bitmap = kcalloc(BITS_TO_LONGS(max_count), sizeof(long),
70 GFP_KERNEL);
71 if (!bmap->bitmap)
72 return -ENOMEM;
73
74 snprintf(bmap->name, QED_RDMA_MAX_BMAP_NAME, "%s", name);
75
76 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n");
77 return 0;
78}
79
80int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn,
81 struct qed_bmap *bmap, u32 *id_num)
82{
83 *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count);
84 if (*id_num >= bmap->max_count)
85 return -EINVAL;
86
87 __set_bit(*id_num, bmap->bitmap);
88
89 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: allocated id %d\n",
90 bmap->name, *id_num);
91
92 return 0;
93}
94
95void qed_bmap_set_id(struct qed_hwfn *p_hwfn,
96 struct qed_bmap *bmap, u32 id_num)
97{
98 if (id_num >= bmap->max_count)
99 return;
100
101 __set_bit(id_num, bmap->bitmap);
102}
103
104void qed_bmap_release_id(struct qed_hwfn *p_hwfn,
105 struct qed_bmap *bmap, u32 id_num)
106{
107 bool b_acquired;
108
109 if (id_num >= bmap->max_count)
110 return;
111
112 b_acquired = test_and_clear_bit(id_num, bmap->bitmap);
113 if (!b_acquired) {
114 DP_NOTICE(p_hwfn, "%s bitmap: id %d already released\n",
115 bmap->name, id_num);
116 return;
117 }
118
119 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: released id %d\n",
120 bmap->name, id_num);
121}
122
123int qed_bmap_test_id(struct qed_hwfn *p_hwfn,
124 struct qed_bmap *bmap, u32 id_num)
125{
126 if (id_num >= bmap->max_count)
127 return -1;
128
129 return test_bit(id_num, bmap->bitmap);
130}
131
132static bool qed_bmap_is_empty(struct qed_bmap *bmap)
133{
134 return bmap->max_count == find_first_bit(bmap->bitmap, bmap->max_count);
135}
136
137u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id)
138{
139 /* First sb id for RoCE is after all the l2 sb */
140 return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id;
141}
142
143static int qed_rdma_alloc(struct qed_hwfn *p_hwfn,
144 struct qed_ptt *p_ptt,
145 struct qed_rdma_start_in_params *params)
146{
147 struct qed_rdma_info *p_rdma_info;
148 u32 num_cons, num_tasks;
149 int rc = -ENOMEM;
150
151 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n");
152
153 /* Allocate a struct with current pf rdma info */
154 p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL);
155 if (!p_rdma_info)
156 return rc;
157
158 p_hwfn->p_rdma_info = p_rdma_info;
159 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
160 p_rdma_info->proto = PROTOCOLID_IWARP;
161 else
162 p_rdma_info->proto = PROTOCOLID_ROCE;
163
164 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto,
165 NULL);
166
167 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
168 p_rdma_info->num_qps = num_cons;
169 else
170 p_rdma_info->num_qps = num_cons / 2; /* 2 cids per qp */
171
172 num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE);
173
174 /* Each MR uses a single task */
175 p_rdma_info->num_mrs = num_tasks;
176
177 /* Queue zone lines are shared between RoCE and L2 in such a way that
178 * they can be used by each without obstructing the other.
179 */
180 p_rdma_info->queue_zone_base = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
181 p_rdma_info->max_queue_zones = (u16)RESC_NUM(p_hwfn, QED_L2_QUEUE);
182
183 /* Allocate a struct with device params and fill it */
184 p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL);
185 if (!p_rdma_info->dev)
186 goto free_rdma_info;
187
188 /* Allocate a struct with port params and fill it */
189 p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL);
190 if (!p_rdma_info->port)
191 goto free_rdma_dev;
192
193 /* Allocate bit map for pd's */
194 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS,
195 "PD");
196 if (rc) {
197 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
198 "Failed to allocate pd_map, rc = %d\n",
199 rc);
200 goto free_rdma_port;
201 }
202
203 /* Allocate DPI bitmap */
204 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map,
205 p_hwfn->dpi_count, "DPI");
206 if (rc) {
207 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
208 "Failed to allocate DPI bitmap, rc = %d\n", rc);
209 goto free_pd_map;
210 }
211
212 /* Allocate bitmap for cq's. The maximum number of CQs is bound to
213 * the number of connections we support. (num_qps in iWARP or
214 * num_qps/2 in RoCE).
215 */
216 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map, num_cons, "CQ");
217 if (rc) {
218 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
219 "Failed to allocate cq bitmap, rc = %d\n", rc);
220 goto free_dpi_map;
221 }
222
223 /* Allocate bitmap for toggle bit for cq icids
224 * We toggle the bit every time we create or resize cq for a given icid.
225 * Size needs to equal the size of the cq bmap.
226 */
227 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits,
228 num_cons, "Toggle");
229 if (rc) {
230 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
231 "Failed to allocate toogle bits, rc = %d\n", rc);
232 goto free_cq_map;
233 }
234
235 /* Allocate bitmap for itids */
236 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map,
237 p_rdma_info->num_mrs, "MR");
238 if (rc) {
239 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
240 "Failed to allocate itids bitmaps, rc = %d\n", rc);
241 goto free_toggle_map;
242 }
243
244 /* Allocate bitmap for cids used for qps. */
245 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons,
246 "CID");
247 if (rc) {
248 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
249 "Failed to allocate cid bitmap, rc = %d\n", rc);
250 goto free_tid_map;
251 }
252
253 /* Allocate bitmap for cids used for responders/requesters. */
254 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->real_cid_map, num_cons,
255 "REAL_CID");
256 if (rc) {
257 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
258 "Failed to allocate real cid bitmap, rc = %d\n", rc);
259 goto free_cid_map;
260 }
261
262 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
263 rc = qed_iwarp_alloc(p_hwfn);
264
265 if (rc)
266 goto free_cid_map;
267
268 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n");
269 return 0;
270
271free_cid_map:
272 kfree(p_rdma_info->cid_map.bitmap);
273free_tid_map:
274 kfree(p_rdma_info->tid_map.bitmap);
275free_toggle_map:
276 kfree(p_rdma_info->toggle_bits.bitmap);
277free_cq_map:
278 kfree(p_rdma_info->cq_map.bitmap);
279free_dpi_map:
280 kfree(p_rdma_info->dpi_map.bitmap);
281free_pd_map:
282 kfree(p_rdma_info->pd_map.bitmap);
283free_rdma_port:
284 kfree(p_rdma_info->port);
285free_rdma_dev:
286 kfree(p_rdma_info->dev);
287free_rdma_info:
288 kfree(p_rdma_info);
289
290 return rc;
291}
292
293void qed_rdma_bmap_free(struct qed_hwfn *p_hwfn,
294 struct qed_bmap *bmap, bool check)
295{
296 int weight = bitmap_weight(bmap->bitmap, bmap->max_count);
297 int last_line = bmap->max_count / (64 * 8);
298 int last_item = last_line * 8 +
299 DIV_ROUND_UP(bmap->max_count % (64 * 8), 64);
300 u64 *pmap = (u64 *)bmap->bitmap;
301 int line, item, offset;
302 u8 str_last_line[200] = { 0 };
303
304 if (!weight || !check)
305 goto end;
306
307 DP_NOTICE(p_hwfn,
308 "%s bitmap not free - size=%d, weight=%d, 512 bits per line\n",
309 bmap->name, bmap->max_count, weight);
310
311 /* print aligned non-zero lines, if any */
312 for (item = 0, line = 0; line < last_line; line++, item += 8)
313 if (bitmap_weight((unsigned long *)&pmap[item], 64 * 8))
314 DP_NOTICE(p_hwfn,
315 "line 0x%04x: 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx\n",
316 line,
317 pmap[item],
318 pmap[item + 1],
319 pmap[item + 2],
320 pmap[item + 3],
321 pmap[item + 4],
322 pmap[item + 5],
323 pmap[item + 6], pmap[item + 7]);
324
325 /* print last unaligned non-zero line, if any */
326 if ((bmap->max_count % (64 * 8)) &&
327 (bitmap_weight((unsigned long *)&pmap[item],
328 bmap->max_count - item * 64))) {
329 offset = sprintf(str_last_line, "line 0x%04x: ", line);
330 for (; item < last_item; item++)
331 offset += sprintf(str_last_line + offset,
332 "0x%016llx ", pmap[item]);
333 DP_NOTICE(p_hwfn, "%s\n", str_last_line);
334 }
335
336end:
337 kfree(bmap->bitmap);
338 bmap->bitmap = NULL;
339}
340
341static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn)
342{
343 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info;
344
345 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
346 qed_iwarp_resc_free(p_hwfn);
347
348 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cid_map, 1);
349 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->pd_map, 1);
350 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 1);
351 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cq_map, 1);
352 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->toggle_bits, 0);
353 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->tid_map, 1);
354
355 kfree(p_rdma_info->port);
356 kfree(p_rdma_info->dev);
357
358 kfree(p_rdma_info);
359}
360
361static void qed_rdma_free_tid(void *rdma_cxt, u32 itid)
362{
363 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
364
365 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
366
367 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
368 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid);
369 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
370}
371
372static void qed_rdma_free_reserved_lkey(struct qed_hwfn *p_hwfn)
373{
374 qed_rdma_free_tid(p_hwfn, p_hwfn->p_rdma_info->dev->reserved_lkey);
375}
376
377static void qed_rdma_free(struct qed_hwfn *p_hwfn)
378{
379 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n");
380
381 qed_rdma_free_reserved_lkey(p_hwfn);
382 qed_cxt_free_proto_ilt(p_hwfn, p_hwfn->p_rdma_info->proto);
383 qed_rdma_resc_free(p_hwfn);
384}
385
386static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid)
387{
388 guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2;
389 guid[1] = p_hwfn->hw_info.hw_mac_addr[1];
390 guid[2] = p_hwfn->hw_info.hw_mac_addr[2];
391 guid[3] = 0xff;
392 guid[4] = 0xfe;
393 guid[5] = p_hwfn->hw_info.hw_mac_addr[3];
394 guid[6] = p_hwfn->hw_info.hw_mac_addr[4];
395 guid[7] = p_hwfn->hw_info.hw_mac_addr[5];
396}
397
398static void qed_rdma_init_events(struct qed_hwfn *p_hwfn,
399 struct qed_rdma_start_in_params *params)
400{
401 struct qed_rdma_events *events;
402
403 events = &p_hwfn->p_rdma_info->events;
404
405 events->unaffiliated_event = params->events->unaffiliated_event;
406 events->affiliated_event = params->events->affiliated_event;
407 events->context = params->events->context;
408}
409
410static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn,
411 struct qed_rdma_start_in_params *params)
412{
413 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
414 struct qed_dev *cdev = p_hwfn->cdev;
415 u32 pci_status_control;
416 u32 num_qps;
417
418 /* Vendor specific information */
419 dev->vendor_id = cdev->vendor_id;
420 dev->vendor_part_id = cdev->device_id;
421 dev->hw_ver = 0;
422 dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) |
423 (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION);
424
425 qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid);
426 dev->node_guid = dev->sys_image_guid;
427
428 dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE,
429 RDMA_MAX_SGE_PER_RQ_WQE);
430
431 if (cdev->rdma_max_sge)
432 dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge);
433
434 dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE;
435
436 dev->max_inline = (cdev->rdma_max_inline) ?
437 min_t(u32, cdev->rdma_max_inline, dev->max_inline) :
438 dev->max_inline;
439
440 dev->max_wqe = QED_RDMA_MAX_WQE;
441 dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ);
442
443 /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because
444 * it is up-aligned to 16 and then to ILT page size within qed cxt.
445 * This is OK in terms of ILT but we don't want to configure the FW
446 * above its abilities
447 */
448 num_qps = ROCE_MAX_QPS;
449 num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps);
450 dev->max_qp = num_qps;
451
452 /* CQs uses the same icids that QPs use hence they are limited by the
453 * number of icids. There are two icids per QP.
454 */
455 dev->max_cq = num_qps * 2;
456
457 /* The number of mrs is smaller by 1 since the first is reserved */
458 dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1;
459 dev->max_mr_size = QED_RDMA_MAX_MR_SIZE;
460
461 /* The maximum CQE capacity per CQ supported.
462 * max number of cqes will be in two layer pbl,
463 * 8 is the pointer size in bytes
464 * 32 is the size of cq element in bytes
465 */
466 if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS)
467 dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT;
468 else
469 dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT;
470
471 dev->max_mw = 0;
472 dev->max_fmr = QED_RDMA_MAX_FMR;
473 dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8);
474 dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE;
475 dev->max_pkey = QED_RDMA_MAX_P_KEY;
476
477 dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
478 (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2);
479 dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE /
480 RDMA_REQ_RD_ATOMIC_ELM_SIZE;
481 dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc *
482 p_hwfn->p_rdma_info->num_qps;
483 dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS;
484 dev->dev_ack_delay = QED_RDMA_ACK_DELAY;
485 dev->max_pd = RDMA_MAX_PDS;
486 dev->max_ah = p_hwfn->p_rdma_info->num_qps;
487 dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE);
488
489 /* Set capablities */
490 dev->dev_caps = 0;
491 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1);
492 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1);
493 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1);
494 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1);
495 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1);
496 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1);
497 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1);
498 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1);
499
500 /* Check atomic operations support in PCI configuration space. */
501 pci_read_config_dword(cdev->pdev,
502 cdev->pdev->pcie_cap + PCI_EXP_DEVCTL2,
503 &pci_status_control);
504
505 if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN)
506 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1);
507
508 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
509 qed_iwarp_init_devinfo(p_hwfn);
510}
511
512static void qed_rdma_init_port(struct qed_hwfn *p_hwfn)
513{
514 struct qed_rdma_port *port = p_hwfn->p_rdma_info->port;
515 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
516
517 port->port_state = p_hwfn->mcp_info->link_output.link_up ?
518 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
519
520 port->max_msg_size = min_t(u64,
521 (dev->max_mr_mw_fmr_size *
522 p_hwfn->cdev->rdma_max_sge),
523 BIT(31));
524
525 port->pkey_bad_counter = 0;
526}
527
528static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
529{
530 int rc = 0;
531
532 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n");
533 p_hwfn->b_rdma_enabled_in_prs = false;
534
535 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
536 qed_iwarp_init_hw(p_hwfn, p_ptt);
537 else
538 rc = qed_roce_init_hw(p_hwfn, p_ptt);
539
540 return rc;
541}
542
543static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn,
544 struct qed_rdma_start_in_params *params,
545 struct qed_ptt *p_ptt)
546{
547 struct rdma_init_func_ramrod_data *p_ramrod;
548 struct qed_rdma_cnq_params *p_cnq_pbl_list;
549 struct rdma_init_func_hdr *p_params_header;
550 struct rdma_cnq_params *p_cnq_params;
551 struct qed_sp_init_data init_data;
552 struct qed_spq_entry *p_ent;
553 u32 cnq_id, sb_id;
554 u16 igu_sb_id;
555 int rc;
556
557 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n");
558
559 /* Save the number of cnqs for the function close ramrod */
560 p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq;
561
562 /* Get SPQ entry */
563 memset(&init_data, 0, sizeof(init_data));
564 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
565 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
566
567 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT,
568 p_hwfn->p_rdma_info->proto, &init_data);
569 if (rc)
570 return rc;
571
572 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
573 qed_iwarp_init_fw_ramrod(p_hwfn,
574 &p_ent->ramrod.iwarp_init_func);
575 p_ramrod = &p_ent->ramrod.iwarp_init_func.rdma;
576 } else {
577 p_ramrod = &p_ent->ramrod.roce_init_func.rdma;
578 }
579
580 p_params_header = &p_ramrod->params_header;
581 p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn,
582 QED_RDMA_CNQ_RAM);
583 p_params_header->num_cnqs = params->desired_cnq;
584
585 if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS)
586 p_params_header->cq_ring_mode = 1;
587 else
588 p_params_header->cq_ring_mode = 0;
589
590 for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) {
591 sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id);
592 igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
593 p_ramrod->cnq_params[cnq_id].sb_num = cpu_to_le16(igu_sb_id);
594 p_cnq_params = &p_ramrod->cnq_params[cnq_id];
595 p_cnq_pbl_list = ¶ms->cnq_pbl_list[cnq_id];
596
597 p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi;
598 p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages;
599
600 DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr,
601 p_cnq_pbl_list->pbl_ptr);
602
603 /* we assume here that cnq_id and qz_offset are the same */
604 p_cnq_params->queue_zone_num =
605 cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base +
606 cnq_id);
607 }
608
609 return qed_spq_post(p_hwfn, p_ent, NULL);
610}
611
612static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid)
613{
614 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
615 int rc;
616
617 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n");
618
619 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
620 rc = qed_rdma_bmap_alloc_id(p_hwfn,
621 &p_hwfn->p_rdma_info->tid_map, itid);
622 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
623 if (rc)
624 goto out;
625
626 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid);
627out:
628 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc);
629 return rc;
630}
631
632static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn)
633{
634 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev;
635
636 /* Tid 0 will be used as the key for "reserved MR".
637 * The driver should allocate memory for it so it can be loaded but no
638 * ramrod should be passed on it.
639 */
640 qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey);
641 if (dev->reserved_lkey != RDMA_RESERVED_LKEY) {
642 DP_NOTICE(p_hwfn,
643 "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n");
644 return -EINVAL;
645 }
646
647 return 0;
648}
649
650static int qed_rdma_setup(struct qed_hwfn *p_hwfn,
651 struct qed_ptt *p_ptt,
652 struct qed_rdma_start_in_params *params)
653{
654 int rc;
655
656 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n");
657
658 spin_lock_init(&p_hwfn->p_rdma_info->lock);
659
660 qed_rdma_init_devinfo(p_hwfn, params);
661 qed_rdma_init_port(p_hwfn);
662 qed_rdma_init_events(p_hwfn, params);
663
664 rc = qed_rdma_reserve_lkey(p_hwfn);
665 if (rc)
666 return rc;
667
668 rc = qed_rdma_init_hw(p_hwfn, p_ptt);
669 if (rc)
670 return rc;
671
672 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
673 rc = qed_iwarp_setup(p_hwfn, p_ptt, params);
674 if (rc)
675 return rc;
676 } else {
677 rc = qed_roce_setup(p_hwfn);
678 if (rc)
679 return rc;
680 }
681
682 return qed_rdma_start_fw(p_hwfn, params, p_ptt);
683}
684
685int qed_rdma_stop(void *rdma_cxt)
686{
687 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
688 struct rdma_close_func_ramrod_data *p_ramrod;
689 struct qed_sp_init_data init_data;
690 struct qed_spq_entry *p_ent;
691 struct qed_ptt *p_ptt;
692 u32 ll2_ethertype_en;
693 int rc = -EBUSY;
694
695 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n");
696
697 p_ptt = qed_ptt_acquire(p_hwfn);
698 if (!p_ptt) {
699 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n");
700 return rc;
701 }
702
703 /* Disable RoCE search */
704 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0);
705 p_hwfn->b_rdma_enabled_in_prs = false;
706
707 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0);
708
709 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
710
711 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN,
712 (ll2_ethertype_en & 0xFFFE));
713
714 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
715 rc = qed_iwarp_stop(p_hwfn, p_ptt);
716 if (rc) {
717 qed_ptt_release(p_hwfn, p_ptt);
718 return rc;
719 }
720 } else {
721 qed_roce_stop(p_hwfn);
722 }
723
724 qed_ptt_release(p_hwfn, p_ptt);
725
726 /* Get SPQ entry */
727 memset(&init_data, 0, sizeof(init_data));
728 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
729 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
730
731 /* Stop RoCE */
732 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE,
733 p_hwfn->p_rdma_info->proto, &init_data);
734 if (rc)
735 goto out;
736
737 p_ramrod = &p_ent->ramrod.rdma_close_func;
738
739 p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs;
740 p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM);
741
742 rc = qed_spq_post(p_hwfn, p_ent, NULL);
743
744out:
745 qed_rdma_free(p_hwfn);
746
747 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc);
748 return rc;
749}
750
751static int qed_rdma_add_user(void *rdma_cxt,
752 struct qed_rdma_add_user_out_params *out_params)
753{
754 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
755 u32 dpi_start_offset;
756 u32 returned_id = 0;
757 int rc;
758
759 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n");
760
761 /* Allocate DPI */
762 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
763 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map,
764 &returned_id);
765 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
766
767 out_params->dpi = (u16)returned_id;
768
769 /* Calculate the corresponding DPI address */
770 dpi_start_offset = p_hwfn->dpi_start_offset;
771
772 out_params->dpi_addr = (u64)((u8 __iomem *)p_hwfn->doorbells +
773 dpi_start_offset +
774 ((out_params->dpi) * p_hwfn->dpi_size));
775
776 out_params->dpi_phys_addr = p_hwfn->cdev->db_phys_addr +
777 dpi_start_offset +
778 ((out_params->dpi) * p_hwfn->dpi_size);
779
780 out_params->dpi_size = p_hwfn->dpi_size;
781 out_params->wid_count = p_hwfn->wid_count;
782
783 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc);
784 return rc;
785}
786
787static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt)
788{
789 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
790 struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port;
791
792 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n");
793
794 /* Link may have changed */
795 p_port->port_state = p_hwfn->mcp_info->link_output.link_up ?
796 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN;
797
798 p_port->link_speed = p_hwfn->mcp_info->link_output.speed;
799
800 p_port->max_msg_size = RDMA_MAX_DATA_SIZE_IN_WQE;
801
802 return p_port;
803}
804
805static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt)
806{
807 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
808
809 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n");
810
811 /* Return struct with device parameters */
812 return p_hwfn->p_rdma_info->dev;
813}
814
815static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod)
816{
817 struct qed_hwfn *p_hwfn;
818 u16 qz_num;
819 u32 addr;
820
821 p_hwfn = (struct qed_hwfn *)rdma_cxt;
822
823 if (qz_offset > p_hwfn->p_rdma_info->max_queue_zones) {
824 DP_NOTICE(p_hwfn,
825 "queue zone offset %d is too large (max is %d)\n",
826 qz_offset, p_hwfn->p_rdma_info->max_queue_zones);
827 return;
828 }
829
830 qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset;
831 addr = GTT_BAR0_MAP_REG_USDM_RAM +
832 USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num);
833
834 REG_WR16(p_hwfn, addr, prod);
835
836 /* keep prod updates ordered */
837 wmb();
838}
839
840static int qed_fill_rdma_dev_info(struct qed_dev *cdev,
841 struct qed_dev_rdma_info *info)
842{
843 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
844
845 memset(info, 0, sizeof(*info));
846
847 info->rdma_type = QED_IS_ROCE_PERSONALITY(p_hwfn) ?
848 QED_RDMA_TYPE_ROCE : QED_RDMA_TYPE_IWARP;
849
850 info->user_dpm_enabled = (p_hwfn->db_bar_no_edpm == 0);
851
852 qed_fill_dev_info(cdev, &info->common);
853
854 return 0;
855}
856
857static int qed_rdma_get_sb_start(struct qed_dev *cdev)
858{
859 int feat_num;
860
861 if (cdev->num_hwfns > 1)
862 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE);
863 else
864 feat_num = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_PF_L2_QUE) *
865 cdev->num_hwfns;
866
867 return feat_num;
868}
869
870static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev)
871{
872 int n_cnq = FEAT_NUM(QED_LEADING_HWFN(cdev), QED_RDMA_CNQ);
873 int n_msix = cdev->int_params.rdma_msix_cnt;
874
875 return min_t(int, n_cnq, n_msix);
876}
877
878static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt)
879{
880 int limit = 0;
881
882 /* Mark the fastpath as free/used */
883 cdev->int_params.fp_initialized = cnt ? true : false;
884
885 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) {
886 DP_ERR(cdev,
887 "qed roce supports only MSI-X interrupts (detected %d).\n",
888 cdev->int_params.out.int_mode);
889 return -EINVAL;
890 } else if (cdev->int_params.fp_msix_cnt) {
891 limit = cdev->int_params.rdma_msix_cnt;
892 }
893
894 if (!limit)
895 return -ENOMEM;
896
897 return min_t(int, cnt, limit);
898}
899
900static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info)
901{
902 memset(info, 0, sizeof(*info));
903
904 if (!cdev->int_params.fp_initialized) {
905 DP_INFO(cdev,
906 "Protocol driver requested interrupt information, but its support is not yet configured\n");
907 return -EINVAL;
908 }
909
910 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
911 int msix_base = cdev->int_params.rdma_msix_base;
912
913 info->msix_cnt = cdev->int_params.rdma_msix_cnt;
914 info->msix = &cdev->int_params.msix_table[msix_base];
915
916 DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n",
917 info->msix_cnt, msix_base);
918 }
919
920 return 0;
921}
922
923static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd)
924{
925 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
926 u32 returned_id;
927 int rc;
928
929 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n");
930
931 /* Allocates an unused protection domain */
932 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
933 rc = qed_rdma_bmap_alloc_id(p_hwfn,
934 &p_hwfn->p_rdma_info->pd_map, &returned_id);
935 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
936
937 *pd = (u16)returned_id;
938
939 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc);
940 return rc;
941}
942
943static void qed_rdma_free_pd(void *rdma_cxt, u16 pd)
944{
945 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
946
947 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd);
948
949 /* Returns a previously allocated protection domain for reuse */
950 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
951 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd);
952 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
953}
954
955static enum qed_rdma_toggle_bit
956qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid)
957{
958 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
959 enum qed_rdma_toggle_bit toggle_bit;
960 u32 bmap_id;
961
962 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid);
963
964 /* the function toggle the bit that is related to a given icid
965 * and returns the new toggle bit's value
966 */
967 bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto);
968
969 spin_lock_bh(&p_info->lock);
970 toggle_bit = !test_and_change_bit(bmap_id,
971 p_info->toggle_bits.bitmap);
972 spin_unlock_bh(&p_info->lock);
973
974 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n",
975 toggle_bit);
976
977 return toggle_bit;
978}
979
980static int qed_rdma_create_cq(void *rdma_cxt,
981 struct qed_rdma_create_cq_in_params *params,
982 u16 *icid)
983{
984 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
985 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info;
986 struct rdma_create_cq_ramrod_data *p_ramrod;
987 enum qed_rdma_toggle_bit toggle_bit;
988 struct qed_sp_init_data init_data;
989 struct qed_spq_entry *p_ent;
990 u32 returned_id, start_cid;
991 int rc;
992
993 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n",
994 params->cq_handle_hi, params->cq_handle_lo);
995
996 /* Allocate icid */
997 spin_lock_bh(&p_info->lock);
998 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_info->cq_map, &returned_id);
999 spin_unlock_bh(&p_info->lock);
1000
1001 if (rc) {
1002 DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc);
1003 return rc;
1004 }
1005
1006 start_cid = qed_cxt_get_proto_cid_start(p_hwfn,
1007 p_info->proto);
1008 *icid = returned_id + start_cid;
1009
1010 /* Check if icid requires a page allocation */
1011 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid);
1012 if (rc)
1013 goto err;
1014
1015 /* Get SPQ entry */
1016 memset(&init_data, 0, sizeof(init_data));
1017 init_data.cid = *icid;
1018 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1019 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1020
1021 /* Send create CQ ramrod */
1022 rc = qed_sp_init_request(p_hwfn, &p_ent,
1023 RDMA_RAMROD_CREATE_CQ,
1024 p_info->proto, &init_data);
1025 if (rc)
1026 goto err;
1027
1028 p_ramrod = &p_ent->ramrod.rdma_create_cq;
1029
1030 p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi);
1031 p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo);
1032 p_ramrod->dpi = cpu_to_le16(params->dpi);
1033 p_ramrod->is_two_level_pbl = params->pbl_two_level;
1034 p_ramrod->max_cqes = cpu_to_le32(params->cq_size);
1035 DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr);
1036 p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages);
1037 p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) +
1038 params->cnq_id;
1039 p_ramrod->int_timeout = params->int_timeout;
1040
1041 /* toggle the bit for every resize or create cq for a given icid */
1042 toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
1043
1044 p_ramrod->toggle_bit = toggle_bit;
1045
1046 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1047 if (rc) {
1048 /* restore toggle bit */
1049 qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid);
1050 goto err;
1051 }
1052
1053 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc);
1054 return rc;
1055
1056err:
1057 /* release allocated icid */
1058 spin_lock_bh(&p_info->lock);
1059 qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id);
1060 spin_unlock_bh(&p_info->lock);
1061 DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc);
1062
1063 return rc;
1064}
1065
1066static int
1067qed_rdma_destroy_cq(void *rdma_cxt,
1068 struct qed_rdma_destroy_cq_in_params *in_params,
1069 struct qed_rdma_destroy_cq_out_params *out_params)
1070{
1071 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1072 struct rdma_destroy_cq_output_params *p_ramrod_res;
1073 struct rdma_destroy_cq_ramrod_data *p_ramrod;
1074 struct qed_sp_init_data init_data;
1075 struct qed_spq_entry *p_ent;
1076 dma_addr_t ramrod_res_phys;
1077 enum protocol_type proto;
1078 int rc = -ENOMEM;
1079
1080 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid);
1081
1082 p_ramrod_res =
1083 (struct rdma_destroy_cq_output_params *)
1084 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1085 sizeof(struct rdma_destroy_cq_output_params),
1086 &ramrod_res_phys, GFP_KERNEL);
1087 if (!p_ramrod_res) {
1088 DP_NOTICE(p_hwfn,
1089 "qed destroy cq failed: cannot allocate memory (ramrod)\n");
1090 return rc;
1091 }
1092
1093 /* Get SPQ entry */
1094 memset(&init_data, 0, sizeof(init_data));
1095 init_data.cid = in_params->icid;
1096 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1097 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1098 proto = p_hwfn->p_rdma_info->proto;
1099 /* Send destroy CQ ramrod */
1100 rc = qed_sp_init_request(p_hwfn, &p_ent,
1101 RDMA_RAMROD_DESTROY_CQ,
1102 proto, &init_data);
1103 if (rc)
1104 goto err;
1105
1106 p_ramrod = &p_ent->ramrod.rdma_destroy_cq;
1107 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys);
1108
1109 rc = qed_spq_post(p_hwfn, p_ent, NULL);
1110 if (rc)
1111 goto err;
1112
1113 out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num);
1114
1115 dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1116 sizeof(struct rdma_destroy_cq_output_params),
1117 p_ramrod_res, ramrod_res_phys);
1118
1119 /* Free icid */
1120 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1121
1122 qed_bmap_release_id(p_hwfn,
1123 &p_hwfn->p_rdma_info->cq_map,
1124 (in_params->icid -
1125 qed_cxt_get_proto_cid_start(p_hwfn, proto)));
1126
1127 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1128
1129 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc);
1130 return rc;
1131
1132err: dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1133 sizeof(struct rdma_destroy_cq_output_params),
1134 p_ramrod_res, ramrod_res_phys);
1135
1136 return rc;
1137}
1138
1139void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac)
1140{
1141 p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]);
1142 p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]);
1143 p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]);
1144}
1145
1146static int qed_rdma_query_qp(void *rdma_cxt,
1147 struct qed_rdma_qp *qp,
1148 struct qed_rdma_query_qp_out_params *out_params)
1149{
1150 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1151 int rc = 0;
1152
1153 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1154
1155 /* The following fields are filled in from qp and not FW as they can't
1156 * be modified by FW
1157 */
1158 out_params->mtu = qp->mtu;
1159 out_params->dest_qp = qp->dest_qp;
1160 out_params->incoming_atomic_en = qp->incoming_atomic_en;
1161 out_params->e2e_flow_control_en = qp->e2e_flow_control_en;
1162 out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en;
1163 out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en;
1164 out_params->dgid = qp->dgid;
1165 out_params->flow_label = qp->flow_label;
1166 out_params->hop_limit_ttl = qp->hop_limit_ttl;
1167 out_params->traffic_class_tos = qp->traffic_class_tos;
1168 out_params->timeout = qp->ack_timeout;
1169 out_params->rnr_retry = qp->rnr_retry_cnt;
1170 out_params->retry_cnt = qp->retry_cnt;
1171 out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer;
1172 out_params->pkey_index = 0;
1173 out_params->max_rd_atomic = qp->max_rd_atomic_req;
1174 out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp;
1175 out_params->sqd_async = qp->sqd_async;
1176
1177 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
1178 qed_iwarp_query_qp(qp, out_params);
1179 else
1180 rc = qed_roce_query_qp(p_hwfn, qp, out_params);
1181
1182 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc);
1183 return rc;
1184}
1185
1186static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp)
1187{
1188 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1189 int rc = 0;
1190
1191 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid);
1192
1193 if (QED_IS_IWARP_PERSONALITY(p_hwfn))
1194 rc = qed_iwarp_destroy_qp(p_hwfn, qp);
1195 else
1196 rc = qed_roce_destroy_qp(p_hwfn, qp);
1197
1198 /* free qp params struct */
1199 kfree(qp);
1200
1201 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n");
1202 return rc;
1203}
1204
1205static struct qed_rdma_qp *
1206qed_rdma_create_qp(void *rdma_cxt,
1207 struct qed_rdma_create_qp_in_params *in_params,
1208 struct qed_rdma_create_qp_out_params *out_params)
1209{
1210 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1211 struct qed_rdma_qp *qp;
1212 u8 max_stats_queues;
1213 int rc;
1214
1215 if (!rdma_cxt || !in_params || !out_params || !p_hwfn->p_rdma_info) {
1216 DP_ERR(p_hwfn->cdev,
1217 "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n",
1218 rdma_cxt, in_params, out_params);
1219 return NULL;
1220 }
1221
1222 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1223 "qed rdma create qp called with qp_handle = %08x%08x\n",
1224 in_params->qp_handle_hi, in_params->qp_handle_lo);
1225
1226 /* Some sanity checks... */
1227 max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues;
1228 if (in_params->stats_queue >= max_stats_queues) {
1229 DP_ERR(p_hwfn->cdev,
1230 "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n",
1231 in_params->stats_queue, max_stats_queues);
1232 return NULL;
1233 }
1234
1235 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
1236 if (in_params->sq_num_pages * sizeof(struct regpair) >
1237 IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE) {
1238 DP_NOTICE(p_hwfn->cdev,
1239 "Sq num pages: %d exceeds maximum\n",
1240 in_params->sq_num_pages);
1241 return NULL;
1242 }
1243 if (in_params->rq_num_pages * sizeof(struct regpair) >
1244 IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE) {
1245 DP_NOTICE(p_hwfn->cdev,
1246 "Rq num pages: %d exceeds maximum\n",
1247 in_params->rq_num_pages);
1248 return NULL;
1249 }
1250 }
1251
1252 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1253 if (!qp)
1254 return NULL;
1255
1256 qp->cur_state = QED_ROCE_QP_STATE_RESET;
1257 qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi);
1258 qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo);
1259 qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi);
1260 qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo);
1261 qp->use_srq = in_params->use_srq;
1262 qp->signal_all = in_params->signal_all;
1263 qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey;
1264 qp->pd = in_params->pd;
1265 qp->dpi = in_params->dpi;
1266 qp->sq_cq_id = in_params->sq_cq_id;
1267 qp->sq_num_pages = in_params->sq_num_pages;
1268 qp->sq_pbl_ptr = in_params->sq_pbl_ptr;
1269 qp->rq_cq_id = in_params->rq_cq_id;
1270 qp->rq_num_pages = in_params->rq_num_pages;
1271 qp->rq_pbl_ptr = in_params->rq_pbl_ptr;
1272 qp->srq_id = in_params->srq_id;
1273 qp->req_offloaded = false;
1274 qp->resp_offloaded = false;
1275 qp->e2e_flow_control_en = qp->use_srq ? false : true;
1276 qp->stats_queue = in_params->stats_queue;
1277
1278 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
1279 rc = qed_iwarp_create_qp(p_hwfn, qp, out_params);
1280 qp->qpid = qp->icid;
1281 } else {
1282 rc = qed_roce_alloc_cid(p_hwfn, &qp->icid);
1283 qp->qpid = ((0xFF << 16) | qp->icid);
1284 }
1285
1286 if (rc) {
1287 kfree(qp);
1288 return NULL;
1289 }
1290
1291 out_params->icid = qp->icid;
1292 out_params->qp_id = qp->qpid;
1293
1294 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc);
1295 return qp;
1296}
1297
1298static int qed_rdma_modify_qp(void *rdma_cxt,
1299 struct qed_rdma_qp *qp,
1300 struct qed_rdma_modify_qp_in_params *params)
1301{
1302 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1303 enum qed_roce_qp_state prev_state;
1304 int rc = 0;
1305
1306 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n",
1307 qp->icid, params->new_state);
1308
1309 if (rc) {
1310 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1311 return rc;
1312 }
1313
1314 if (GET_FIELD(params->modify_flags,
1315 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) {
1316 qp->incoming_rdma_read_en = params->incoming_rdma_read_en;
1317 qp->incoming_rdma_write_en = params->incoming_rdma_write_en;
1318 qp->incoming_atomic_en = params->incoming_atomic_en;
1319 }
1320
1321 /* Update QP structure with the updated values */
1322 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE))
1323 qp->roce_mode = params->roce_mode;
1324 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY))
1325 qp->pkey = params->pkey;
1326 if (GET_FIELD(params->modify_flags,
1327 QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN))
1328 qp->e2e_flow_control_en = params->e2e_flow_control_en;
1329 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP))
1330 qp->dest_qp = params->dest_qp;
1331 if (GET_FIELD(params->modify_flags,
1332 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) {
1333 /* Indicates that the following parameters have changed:
1334 * Traffic class, flow label, hop limit, source GID,
1335 * destination GID, loopback indicator
1336 */
1337 qp->traffic_class_tos = params->traffic_class_tos;
1338 qp->flow_label = params->flow_label;
1339 qp->hop_limit_ttl = params->hop_limit_ttl;
1340
1341 qp->sgid = params->sgid;
1342 qp->dgid = params->dgid;
1343 qp->udp_src_port = 0;
1344 qp->vlan_id = params->vlan_id;
1345 qp->mtu = params->mtu;
1346 qp->lb_indication = params->lb_indication;
1347 memcpy((u8 *)&qp->remote_mac_addr[0],
1348 (u8 *)¶ms->remote_mac_addr[0], ETH_ALEN);
1349 if (params->use_local_mac) {
1350 memcpy((u8 *)&qp->local_mac_addr[0],
1351 (u8 *)¶ms->local_mac_addr[0], ETH_ALEN);
1352 } else {
1353 memcpy((u8 *)&qp->local_mac_addr[0],
1354 (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
1355 }
1356 }
1357 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN))
1358 qp->rq_psn = params->rq_psn;
1359 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN))
1360 qp->sq_psn = params->sq_psn;
1361 if (GET_FIELD(params->modify_flags,
1362 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ))
1363 qp->max_rd_atomic_req = params->max_rd_atomic_req;
1364 if (GET_FIELD(params->modify_flags,
1365 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP))
1366 qp->max_rd_atomic_resp = params->max_rd_atomic_resp;
1367 if (GET_FIELD(params->modify_flags,
1368 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT))
1369 qp->ack_timeout = params->ack_timeout;
1370 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT))
1371 qp->retry_cnt = params->retry_cnt;
1372 if (GET_FIELD(params->modify_flags,
1373 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT))
1374 qp->rnr_retry_cnt = params->rnr_retry_cnt;
1375 if (GET_FIELD(params->modify_flags,
1376 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER))
1377 qp->min_rnr_nak_timer = params->min_rnr_nak_timer;
1378
1379 qp->sqd_async = params->sqd_async;
1380
1381 prev_state = qp->cur_state;
1382 if (GET_FIELD(params->modify_flags,
1383 QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) {
1384 qp->cur_state = params->new_state;
1385 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n",
1386 qp->cur_state);
1387 }
1388
1389 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) {
1390 enum qed_iwarp_qp_state new_state =
1391 qed_roce2iwarp_state(qp->cur_state);
1392
1393 rc = qed_iwarp_modify_qp(p_hwfn, qp, new_state, 0);
1394 } else {
1395 rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params);
1396 }
1397
1398 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc);
1399 return rc;
1400}
1401
1402static int
1403qed_rdma_register_tid(void *rdma_cxt,
1404 struct qed_rdma_register_tid_in_params *params)
1405{
1406 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1407 struct rdma_register_tid_ramrod_data *p_ramrod;
1408 struct qed_sp_init_data init_data;
1409 struct qed_spq_entry *p_ent;
1410 enum rdma_tid_type tid_type;
1411 u8 fw_return_code;
1412 int rc;
1413
1414 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid);
1415
1416 /* Get SPQ entry */
1417 memset(&init_data, 0, sizeof(init_data));
1418 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1419 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1420
1421 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR,
1422 p_hwfn->p_rdma_info->proto, &init_data);
1423 if (rc) {
1424 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1425 return rc;
1426 }
1427
1428 if (p_hwfn->p_rdma_info->last_tid < params->itid)
1429 p_hwfn->p_rdma_info->last_tid = params->itid;
1430
1431 p_ramrod = &p_ent->ramrod.rdma_register_tid;
1432
1433 p_ramrod->flags = 0;
1434 SET_FIELD(p_ramrod->flags,
1435 RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL,
1436 params->pbl_two_level);
1437
1438 SET_FIELD(p_ramrod->flags,
1439 RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva);
1440
1441 SET_FIELD(p_ramrod->flags,
1442 RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr);
1443
1444 /* Don't initialize D/C field, as it may override other bits. */
1445 if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr))
1446 SET_FIELD(p_ramrod->flags,
1447 RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG,
1448 params->page_size_log - 12);
1449
1450 SET_FIELD(p_ramrod->flags,
1451 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ,
1452 params->remote_read);
1453
1454 SET_FIELD(p_ramrod->flags,
1455 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE,
1456 params->remote_write);
1457
1458 SET_FIELD(p_ramrod->flags,
1459 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC,
1460 params->remote_atomic);
1461
1462 SET_FIELD(p_ramrod->flags,
1463 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE,
1464 params->local_write);
1465
1466 SET_FIELD(p_ramrod->flags,
1467 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read);
1468
1469 SET_FIELD(p_ramrod->flags,
1470 RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND,
1471 params->mw_bind);
1472
1473 SET_FIELD(p_ramrod->flags1,
1474 RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG,
1475 params->pbl_page_size_log - 12);
1476
1477 SET_FIELD(p_ramrod->flags2,
1478 RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr);
1479
1480 switch (params->tid_type) {
1481 case QED_RDMA_TID_REGISTERED_MR:
1482 tid_type = RDMA_TID_REGISTERED_MR;
1483 break;
1484 case QED_RDMA_TID_FMR:
1485 tid_type = RDMA_TID_FMR;
1486 break;
1487 case QED_RDMA_TID_MW_TYPE1:
1488 tid_type = RDMA_TID_MW_TYPE1;
1489 break;
1490 case QED_RDMA_TID_MW_TYPE2A:
1491 tid_type = RDMA_TID_MW_TYPE2A;
1492 break;
1493 default:
1494 rc = -EINVAL;
1495 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1496 return rc;
1497 }
1498 SET_FIELD(p_ramrod->flags1,
1499 RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type);
1500
1501 p_ramrod->itid = cpu_to_le32(params->itid);
1502 p_ramrod->key = params->key;
1503 p_ramrod->pd = cpu_to_le16(params->pd);
1504 p_ramrod->length_hi = (u8)(params->length >> 32);
1505 p_ramrod->length_lo = DMA_LO_LE(params->length);
1506 if (params->zbva) {
1507 /* Lower 32 bits of the registered MR address.
1508 * In case of zero based MR, will hold FBO
1509 */
1510 p_ramrod->va.hi = 0;
1511 p_ramrod->va.lo = cpu_to_le32(params->fbo);
1512 } else {
1513 DMA_REGPAIR_LE(p_ramrod->va, params->vaddr);
1514 }
1515 DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr);
1516
1517 /* DIF */
1518 if (params->dif_enabled) {
1519 SET_FIELD(p_ramrod->flags2,
1520 RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1);
1521 DMA_REGPAIR_LE(p_ramrod->dif_error_addr,
1522 params->dif_error_addr);
1523 DMA_REGPAIR_LE(p_ramrod->dif_runt_addr, params->dif_runt_addr);
1524 }
1525
1526 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1527 if (rc)
1528 return rc;
1529
1530 if (fw_return_code != RDMA_RETURN_OK) {
1531 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
1532 return -EINVAL;
1533 }
1534
1535 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc);
1536 return rc;
1537}
1538
1539static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid)
1540{
1541 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1542 struct rdma_deregister_tid_ramrod_data *p_ramrod;
1543 struct qed_sp_init_data init_data;
1544 struct qed_spq_entry *p_ent;
1545 struct qed_ptt *p_ptt;
1546 u8 fw_return_code;
1547 int rc;
1548
1549 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid);
1550
1551 /* Get SPQ entry */
1552 memset(&init_data, 0, sizeof(init_data));
1553 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
1554 init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
1555
1556 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR,
1557 p_hwfn->p_rdma_info->proto, &init_data);
1558 if (rc) {
1559 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1560 return rc;
1561 }
1562
1563 p_ramrod = &p_ent->ramrod.rdma_deregister_tid;
1564 p_ramrod->itid = cpu_to_le32(itid);
1565
1566 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1567 if (rc) {
1568 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc);
1569 return rc;
1570 }
1571
1572 if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) {
1573 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code);
1574 return -EINVAL;
1575 } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) {
1576 /* Bit indicating that the TID is in use and a nig drain is
1577 * required before sending the ramrod again
1578 */
1579 p_ptt = qed_ptt_acquire(p_hwfn);
1580 if (!p_ptt) {
1581 rc = -EBUSY;
1582 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1583 "Failed to acquire PTT\n");
1584 return rc;
1585 }
1586
1587 rc = qed_mcp_drain(p_hwfn, p_ptt);
1588 if (rc) {
1589 qed_ptt_release(p_hwfn, p_ptt);
1590 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1591 "Drain failed\n");
1592 return rc;
1593 }
1594
1595 qed_ptt_release(p_hwfn, p_ptt);
1596
1597 /* Resend the ramrod */
1598 rc = qed_sp_init_request(p_hwfn, &p_ent,
1599 RDMA_RAMROD_DEREGISTER_MR,
1600 p_hwfn->p_rdma_info->proto,
1601 &init_data);
1602 if (rc) {
1603 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1604 "Failed to init sp-element\n");
1605 return rc;
1606 }
1607
1608 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code);
1609 if (rc) {
1610 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1611 "Ramrod failed\n");
1612 return rc;
1613 }
1614
1615 if (fw_return_code != RDMA_RETURN_OK) {
1616 DP_NOTICE(p_hwfn, "fw_return_code = %d\n",
1617 fw_return_code);
1618 return rc;
1619 }
1620 }
1621
1622 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc);
1623 return rc;
1624}
1625
1626static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev)
1627{
1628 return QED_LEADING_HWFN(cdev);
1629}
1630
1631bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn)
1632{
1633 bool result;
1634
1635 /* if rdma info has not been allocated, naturally there are no qps */
1636 if (!p_hwfn->p_rdma_info)
1637 return false;
1638
1639 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1640 if (!p_hwfn->p_rdma_info->cid_map.bitmap)
1641 result = false;
1642 else
1643 result = !qed_bmap_is_empty(&p_hwfn->p_rdma_info->cid_map);
1644 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1645 return result;
1646}
1647
1648void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1649{
1650 u32 val;
1651
1652 val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1;
1653
1654 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val);
1655 DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA),
1656 "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n",
1657 val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm);
1658}
1659
1660
1661void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1662{
1663 p_hwfn->db_bar_no_edpm = true;
1664
1665 qed_rdma_dpm_conf(p_hwfn, p_ptt);
1666}
1667
1668static int qed_rdma_start(void *rdma_cxt,
1669 struct qed_rdma_start_in_params *params)
1670{
1671 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1672 struct qed_ptt *p_ptt;
1673 int rc = -EBUSY;
1674
1675 DP_VERBOSE(p_hwfn, QED_MSG_RDMA,
1676 "desired_cnq = %08x\n", params->desired_cnq);
1677
1678 p_ptt = qed_ptt_acquire(p_hwfn);
1679 if (!p_ptt)
1680 goto err;
1681
1682 rc = qed_rdma_alloc(p_hwfn, p_ptt, params);
1683 if (rc)
1684 goto err1;
1685
1686 rc = qed_rdma_setup(p_hwfn, p_ptt, params);
1687 if (rc)
1688 goto err2;
1689
1690 qed_ptt_release(p_hwfn, p_ptt);
1691
1692 return rc;
1693
1694err2:
1695 qed_rdma_free(p_hwfn);
1696err1:
1697 qed_ptt_release(p_hwfn, p_ptt);
1698err:
1699 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc);
1700 return rc;
1701}
1702
1703static int qed_rdma_init(struct qed_dev *cdev,
1704 struct qed_rdma_start_in_params *params)
1705{
1706 return qed_rdma_start(QED_LEADING_HWFN(cdev), params);
1707}
1708
1709static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi)
1710{
1711 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt;
1712
1713 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi);
1714
1715 spin_lock_bh(&p_hwfn->p_rdma_info->lock);
1716 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi);
1717 spin_unlock_bh(&p_hwfn->p_rdma_info->lock);
1718}
1719
1720static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev,
1721 u8 *old_mac_address,
1722 u8 *new_mac_address)
1723{
1724 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1725 struct qed_ptt *p_ptt;
1726 int rc = 0;
1727
1728 p_ptt = qed_ptt_acquire(p_hwfn);
1729 if (!p_ptt) {
1730 DP_ERR(cdev,
1731 "qed roce ll2 mac filter set: failed to acquire PTT\n");
1732 return -EINVAL;
1733 }
1734
1735 if (old_mac_address)
1736 qed_llh_remove_mac_filter(p_hwfn, p_ptt, old_mac_address);
1737 if (new_mac_address)
1738 rc = qed_llh_add_mac_filter(p_hwfn, p_ptt, new_mac_address);
1739
1740 qed_ptt_release(p_hwfn, p_ptt);
1741
1742 if (rc)
1743 DP_ERR(cdev,
1744 "qed roce ll2 mac filter set: failed to add MAC filter\n");
1745
1746 return rc;
1747}
1748
1749static const struct qed_rdma_ops qed_rdma_ops_pass = {
1750 .common = &qed_common_ops_pass,
1751 .fill_dev_info = &qed_fill_rdma_dev_info,
1752 .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx,
1753 .rdma_init = &qed_rdma_init,
1754 .rdma_add_user = &qed_rdma_add_user,
1755 .rdma_remove_user = &qed_rdma_remove_user,
1756 .rdma_stop = &qed_rdma_stop,
1757 .rdma_query_port = &qed_rdma_query_port,
1758 .rdma_query_device = &qed_rdma_query_device,
1759 .rdma_get_start_sb = &qed_rdma_get_sb_start,
1760 .rdma_get_rdma_int = &qed_rdma_get_int,
1761 .rdma_set_rdma_int = &qed_rdma_set_int,
1762 .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix,
1763 .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update,
1764 .rdma_alloc_pd = &qed_rdma_alloc_pd,
1765 .rdma_dealloc_pd = &qed_rdma_free_pd,
1766 .rdma_create_cq = &qed_rdma_create_cq,
1767 .rdma_destroy_cq = &qed_rdma_destroy_cq,
1768 .rdma_create_qp = &qed_rdma_create_qp,
1769 .rdma_modify_qp = &qed_rdma_modify_qp,
1770 .rdma_query_qp = &qed_rdma_query_qp,
1771 .rdma_destroy_qp = &qed_rdma_destroy_qp,
1772 .rdma_alloc_tid = &qed_rdma_alloc_tid,
1773 .rdma_free_tid = &qed_rdma_free_tid,
1774 .rdma_register_tid = &qed_rdma_register_tid,
1775 .rdma_deregister_tid = &qed_rdma_deregister_tid,
1776 .ll2_acquire_connection = &qed_ll2_acquire_connection,
1777 .ll2_establish_connection = &qed_ll2_establish_connection,
1778 .ll2_terminate_connection = &qed_ll2_terminate_connection,
1779 .ll2_release_connection = &qed_ll2_release_connection,
1780 .ll2_post_rx_buffer = &qed_ll2_post_rx_buffer,
1781 .ll2_prepare_tx_packet = &qed_ll2_prepare_tx_packet,
1782 .ll2_set_fragment_of_tx_packet = &qed_ll2_set_fragment_of_tx_packet,
1783 .ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter,
1784 .ll2_get_stats = &qed_ll2_get_stats,
1785 .iwarp_connect = &qed_iwarp_connect,
1786 .iwarp_create_listen = &qed_iwarp_create_listen,
1787 .iwarp_destroy_listen = &qed_iwarp_destroy_listen,
1788 .iwarp_accept = &qed_iwarp_accept,
1789 .iwarp_reject = &qed_iwarp_reject,
1790 .iwarp_send_rtr = &qed_iwarp_send_rtr,
1791};
1792
1793const struct qed_rdma_ops *qed_get_rdma_ops(void)
1794{
1795 return &qed_rdma_ops_pass;
1796}
1797EXPORT_SYMBOL(qed_get_rdma_ops);