1// SPDX-License-Identifier: GPL-2.0
  2/* Copyright (c) 2018, Intel Corporation. */
  3
  4#include "ice_common.h"
  5
  6/**
  7 * ice_aq_read_nvm
  8 * @hw: pointer to the hw struct
  9 * @module_typeid: module pointer location in words from the NVM beginning
 10 * @offset: byte offset from the module beginning
 11 * @length: length of the section to be read (in bytes from the offset)
 12 * @data: command buffer (size [bytes] = length)
 13 * @last_command: tells if this is the last command in a series
 14 * @cd: pointer to command details structure or NULL
 15 *
 16 * Read the NVM using the admin queue commands (0x0701)
 17 */
 18static enum ice_status
 19ice_aq_read_nvm(struct ice_hw *hw, u8 module_typeid, u32 offset, u16 length,
 20		void *data, bool last_command, struct ice_sq_cd *cd)
 21{
 22	struct ice_aq_desc desc;
 23	struct ice_aqc_nvm *cmd;
 24
 25	cmd = &desc.params.nvm;
 26
 27	/* In offset the highest byte must be zeroed. */
 28	if (offset & 0xFF000000)
 29		return ICE_ERR_PARAM;
 30
 31	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
 32
 33	/* If this is the last command in a series, set the proper flag. */
 34	if (last_command)
 35		cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
 36	cmd->module_typeid = module_typeid;
 37	cmd->offset = cpu_to_le32(offset);
 38	cmd->length = cpu_to_le16(length);
 39
 40	return ice_aq_send_cmd(hw, &desc, data, length, cd);
 41}
 42
 43/**
 44 * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.
 45 * @hw: pointer to the HW structure
 46 * @offset: offset in words from module start
 47 * @words: number of words to access
 48 */
 49static enum ice_status
 50ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)
 51{
 52	if ((offset + words) > hw->nvm.sr_words) {
 53		ice_debug(hw, ICE_DBG_NVM,
 54			  "NVM error: offset beyond SR lmt.\n");
 55		return ICE_ERR_PARAM;
 56	}
 57
 58	if (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {
 59		/* We can access only up to 4KB (one sector), in one AQ write */
 60		ice_debug(hw, ICE_DBG_NVM,
 61			  "NVM error: tried to access %d words, limit is %d.\n",
 62			  words, ICE_SR_SECTOR_SIZE_IN_WORDS);
 63		return ICE_ERR_PARAM;
 64	}
 65
 66	if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=
 67	    (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {
 68		/* A single access cannot spread over two sectors */
 69		ice_debug(hw, ICE_DBG_NVM,
 70			  "NVM error: cannot spread over two sectors.\n");
 71		return ICE_ERR_PARAM;
 72	}
 73
 74	return 0;
 75}
 76
 77/**
 78 * ice_read_sr_aq - Read Shadow RAM.
 79 * @hw: pointer to the HW structure
 80 * @offset: offset in words from module start
 81 * @words: number of words to read
 82 * @data: buffer for words reads from Shadow RAM
 83 * @last_command: tells the AdminQ that this is the last command
 84 *
 85 * Reads 16-bit word buffers from the Shadow RAM using the admin command.
 86 */
 87static enum ice_status
 88ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,
 89	       bool last_command)
 90{
 91	enum ice_status status;
 92
 93	status = ice_check_sr_access_params(hw, offset, words);
 94
 95	/* values in "offset" and "words" parameters are sized as words
 96	 * (16 bits) but ice_aq_read_nvm expects these values in bytes.
 97	 * So do this conversion while calling ice_aq_read_nvm.
 98	 */
 99	if (!status)
100		status = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,
101					 last_command, NULL);
102
103	return status;
104}
105
106/**
107 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
108 * @hw: pointer to the HW structure
109 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
110 * @data: word read from the Shadow RAM
111 *
112 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.
113 */
114static enum ice_status
115ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
116{
117	enum ice_status status;
118
119	status = ice_read_sr_aq(hw, offset, 1, data, true);
120	if (!status)
121		*data = le16_to_cpu(*(__le16 *)data);
122
123	return status;
124}
125
126/**
127 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
128 * @hw: pointer to the HW structure
129 * @access: NVM access type (read or write)
130 *
131 * This function will request NVM ownership.
132 */
133static enum
134ice_status ice_acquire_nvm(struct ice_hw *hw,
135			   enum ice_aq_res_access_type access)
136{
137	if (hw->nvm.blank_nvm_mode)
138		return 0;
139
140	return ice_acquire_res(hw, ICE_NVM_RES_ID, access);
141}
142
143/**
144 * ice_release_nvm - Generic request for releasing the NVM ownership
145 * @hw: pointer to the HW structure
146 *
147 * This function will release NVM ownership.
148 */
149static void ice_release_nvm(struct ice_hw *hw)
150{
151	if (hw->nvm.blank_nvm_mode)
152		return;
153
154	ice_release_res(hw, ICE_NVM_RES_ID);
155}
156
157/**
158 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
159 * @hw: pointer to the HW structure
160 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
161 * @data: word read from the Shadow RAM
162 *
163 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
164 */
165static enum ice_status
166ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
167{
168	enum ice_status status;
169
170	status = ice_acquire_nvm(hw, ICE_RES_READ);
171	if (!status) {
172		status = ice_read_sr_word_aq(hw, offset, data);
173		ice_release_nvm(hw);
174	}
175
176	return status;
177}
178
179/**
180 * ice_init_nvm - initializes NVM setting
181 * @hw: pointer to the hw struct
182 *
183 * This function reads and populates NVM settings such as Shadow RAM size,
184 * max_timeout, and blank_nvm_mode
185 */
186enum ice_status ice_init_nvm(struct ice_hw *hw)
187{
188	struct ice_nvm_info *nvm = &hw->nvm;
189	u16 eetrack_lo, eetrack_hi;
190	enum ice_status status = 0;
191	u32 fla, gens_stat;
192	u8 sr_size;
193
194	/* The SR size is stored regardless of the nvm programming mode
195	 * as the blank mode may be used in the factory line.
196	 */
197	gens_stat = rd32(hw, GLNVM_GENS);
198	sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
199
200	/* Switching to words (sr_size contains power of 2) */
201	nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
202
203	/* Check if we are in the normal or blank NVM programming mode */
204	fla = rd32(hw, GLNVM_FLA);
205	if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
206		nvm->blank_nvm_mode = false;
207	} else { /* Blank programming mode */
208		nvm->blank_nvm_mode = true;
209		status = ICE_ERR_NVM_BLANK_MODE;
210		ice_debug(hw, ICE_DBG_NVM,
211			  "NVM init error: unsupported blank mode.\n");
212		return status;
213	}
214
215	status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);
216	if (status) {
217		ice_debug(hw, ICE_DBG_INIT,
218			  "Failed to read DEV starter version.\n");
219		return status;
220	}
221
222	status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
223	if (status) {
224		ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n");
225		return status;
226	}
227	status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
228	if (status) {
229		ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n");
230		return status;
231	}
232
233	hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
234
235	return status;
236}