Linux Audio

Check our new training course

Real-Time Linux with PREEMPT_RT training

Feb 18-20, 2025
Register
Loading...
Note: File does not exist in v3.1.
   1/*
   2 * linux/drivers/net/ethernet/ethoc.c
   3 *
   4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
   5 * Copyright (C) 2008-2009 Avionic Design GmbH
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
  12 */
  13
  14#include <linux/dma-mapping.h>
  15#include <linux/etherdevice.h>
  16#include <linux/clk.h>
  17#include <linux/crc32.h>
  18#include <linux/interrupt.h>
  19#include <linux/io.h>
  20#include <linux/mii.h>
  21#include <linux/phy.h>
  22#include <linux/platform_device.h>
  23#include <linux/sched.h>
  24#include <linux/slab.h>
  25#include <linux/of.h>
  26#include <linux/of_net.h>
  27#include <linux/module.h>
  28#include <net/ethoc.h>
  29
  30static int buffer_size = 0x8000; /* 32 KBytes */
  31module_param(buffer_size, int, 0);
  32MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
  33
  34/* register offsets */
  35#define	MODER		0x00
  36#define	INT_SOURCE	0x04
  37#define	INT_MASK	0x08
  38#define	IPGT		0x0c
  39#define	IPGR1		0x10
  40#define	IPGR2		0x14
  41#define	PACKETLEN	0x18
  42#define	COLLCONF	0x1c
  43#define	TX_BD_NUM	0x20
  44#define	CTRLMODER	0x24
  45#define	MIIMODER	0x28
  46#define	MIICOMMAND	0x2c
  47#define	MIIADDRESS	0x30
  48#define	MIITX_DATA	0x34
  49#define	MIIRX_DATA	0x38
  50#define	MIISTATUS	0x3c
  51#define	MAC_ADDR0	0x40
  52#define	MAC_ADDR1	0x44
  53#define	ETH_HASH0	0x48
  54#define	ETH_HASH1	0x4c
  55#define	ETH_TXCTRL	0x50
  56#define	ETH_END		0x54
  57
  58/* mode register */
  59#define	MODER_RXEN	(1 <<  0) /* receive enable */
  60#define	MODER_TXEN	(1 <<  1) /* transmit enable */
  61#define	MODER_NOPRE	(1 <<  2) /* no preamble */
  62#define	MODER_BRO	(1 <<  3) /* broadcast address */
  63#define	MODER_IAM	(1 <<  4) /* individual address mode */
  64#define	MODER_PRO	(1 <<  5) /* promiscuous mode */
  65#define	MODER_IFG	(1 <<  6) /* interframe gap for incoming frames */
  66#define	MODER_LOOP	(1 <<  7) /* loopback */
  67#define	MODER_NBO	(1 <<  8) /* no back-off */
  68#define	MODER_EDE	(1 <<  9) /* excess defer enable */
  69#define	MODER_FULLD	(1 << 10) /* full duplex */
  70#define	MODER_RESET	(1 << 11) /* FIXME: reset (undocumented) */
  71#define	MODER_DCRC	(1 << 12) /* delayed CRC enable */
  72#define	MODER_CRC	(1 << 13) /* CRC enable */
  73#define	MODER_HUGE	(1 << 14) /* huge packets enable */
  74#define	MODER_PAD	(1 << 15) /* padding enabled */
  75#define	MODER_RSM	(1 << 16) /* receive small packets */
  76
  77/* interrupt source and mask registers */
  78#define	INT_MASK_TXF	(1 << 0) /* transmit frame */
  79#define	INT_MASK_TXE	(1 << 1) /* transmit error */
  80#define	INT_MASK_RXF	(1 << 2) /* receive frame */
  81#define	INT_MASK_RXE	(1 << 3) /* receive error */
  82#define	INT_MASK_BUSY	(1 << 4)
  83#define	INT_MASK_TXC	(1 << 5) /* transmit control frame */
  84#define	INT_MASK_RXC	(1 << 6) /* receive control frame */
  85
  86#define	INT_MASK_TX	(INT_MASK_TXF | INT_MASK_TXE)
  87#define	INT_MASK_RX	(INT_MASK_RXF | INT_MASK_RXE)
  88
  89#define	INT_MASK_ALL ( \
  90		INT_MASK_TXF | INT_MASK_TXE | \
  91		INT_MASK_RXF | INT_MASK_RXE | \
  92		INT_MASK_TXC | INT_MASK_RXC | \
  93		INT_MASK_BUSY \
  94	)
  95
  96/* packet length register */
  97#define	PACKETLEN_MIN(min)		(((min) & 0xffff) << 16)
  98#define	PACKETLEN_MAX(max)		(((max) & 0xffff) <<  0)
  99#define	PACKETLEN_MIN_MAX(min, max)	(PACKETLEN_MIN(min) | \
 100					PACKETLEN_MAX(max))
 101
 102/* transmit buffer number register */
 103#define	TX_BD_NUM_VAL(x)	(((x) <= 0x80) ? (x) : 0x80)
 104
 105/* control module mode register */
 106#define	CTRLMODER_PASSALL	(1 << 0) /* pass all receive frames */
 107#define	CTRLMODER_RXFLOW	(1 << 1) /* receive control flow */
 108#define	CTRLMODER_TXFLOW	(1 << 2) /* transmit control flow */
 109
 110/* MII mode register */
 111#define	MIIMODER_CLKDIV(x)	((x) & 0xfe) /* needs to be an even number */
 112#define	MIIMODER_NOPRE		(1 << 8) /* no preamble */
 113
 114/* MII command register */
 115#define	MIICOMMAND_SCAN		(1 << 0) /* scan status */
 116#define	MIICOMMAND_READ		(1 << 1) /* read status */
 117#define	MIICOMMAND_WRITE	(1 << 2) /* write control data */
 118
 119/* MII address register */
 120#define	MIIADDRESS_FIAD(x)		(((x) & 0x1f) << 0)
 121#define	MIIADDRESS_RGAD(x)		(((x) & 0x1f) << 8)
 122#define	MIIADDRESS_ADDR(phy, reg)	(MIIADDRESS_FIAD(phy) | \
 123					MIIADDRESS_RGAD(reg))
 124
 125/* MII transmit data register */
 126#define	MIITX_DATA_VAL(x)	((x) & 0xffff)
 127
 128/* MII receive data register */
 129#define	MIIRX_DATA_VAL(x)	((x) & 0xffff)
 130
 131/* MII status register */
 132#define	MIISTATUS_LINKFAIL	(1 << 0)
 133#define	MIISTATUS_BUSY		(1 << 1)
 134#define	MIISTATUS_INVALID	(1 << 2)
 135
 136/* TX buffer descriptor */
 137#define	TX_BD_CS		(1 <<  0) /* carrier sense lost */
 138#define	TX_BD_DF		(1 <<  1) /* defer indication */
 139#define	TX_BD_LC		(1 <<  2) /* late collision */
 140#define	TX_BD_RL		(1 <<  3) /* retransmission limit */
 141#define	TX_BD_RETRY_MASK	(0x00f0)
 142#define	TX_BD_RETRY(x)		(((x) & 0x00f0) >>  4)
 143#define	TX_BD_UR		(1 <<  8) /* transmitter underrun */
 144#define	TX_BD_CRC		(1 << 11) /* TX CRC enable */
 145#define	TX_BD_PAD		(1 << 12) /* pad enable for short packets */
 146#define	TX_BD_WRAP		(1 << 13)
 147#define	TX_BD_IRQ		(1 << 14) /* interrupt request enable */
 148#define	TX_BD_READY		(1 << 15) /* TX buffer ready */
 149#define	TX_BD_LEN(x)		(((x) & 0xffff) << 16)
 150#define	TX_BD_LEN_MASK		(0xffff << 16)
 151
 152#define	TX_BD_STATS		(TX_BD_CS | TX_BD_DF | TX_BD_LC | \
 153				TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
 154
 155/* RX buffer descriptor */
 156#define	RX_BD_LC	(1 <<  0) /* late collision */
 157#define	RX_BD_CRC	(1 <<  1) /* RX CRC error */
 158#define	RX_BD_SF	(1 <<  2) /* short frame */
 159#define	RX_BD_TL	(1 <<  3) /* too long */
 160#define	RX_BD_DN	(1 <<  4) /* dribble nibble */
 161#define	RX_BD_IS	(1 <<  5) /* invalid symbol */
 162#define	RX_BD_OR	(1 <<  6) /* receiver overrun */
 163#define	RX_BD_MISS	(1 <<  7)
 164#define	RX_BD_CF	(1 <<  8) /* control frame */
 165#define	RX_BD_WRAP	(1 << 13)
 166#define	RX_BD_IRQ	(1 << 14) /* interrupt request enable */
 167#define	RX_BD_EMPTY	(1 << 15)
 168#define	RX_BD_LEN(x)	(((x) & 0xffff) << 16)
 169
 170#define	RX_BD_STATS	(RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
 171			RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
 172
 173#define	ETHOC_BUFSIZ		1536
 174#define	ETHOC_ZLEN		64
 175#define	ETHOC_BD_BASE		0x400
 176#define	ETHOC_TIMEOUT		(HZ / 2)
 177#define	ETHOC_MII_TIMEOUT	(1 + (HZ / 5))
 178
 179/**
 180 * struct ethoc - driver-private device structure
 181 * @iobase:	pointer to I/O memory region
 182 * @membase:	pointer to buffer memory region
 183 * @num_bd:	number of buffer descriptors
 184 * @num_tx:	number of send buffers
 185 * @cur_tx:	last send buffer written
 186 * @dty_tx:	last buffer actually sent
 187 * @num_rx:	number of receive buffers
 188 * @cur_rx:	current receive buffer
 189 * @vma:        pointer to array of virtual memory addresses for buffers
 190 * @netdev:	pointer to network device structure
 191 * @napi:	NAPI structure
 192 * @msg_enable:	device state flags
 193 * @lock:	device lock
 194 * @mdio:	MDIO bus for PHY access
 195 * @phy_id:	address of attached PHY
 196 */
 197struct ethoc {
 198	void __iomem *iobase;
 199	void __iomem *membase;
 200	bool big_endian;
 201
 202	unsigned int num_bd;
 203	unsigned int num_tx;
 204	unsigned int cur_tx;
 205	unsigned int dty_tx;
 206
 207	unsigned int num_rx;
 208	unsigned int cur_rx;
 209
 210	void **vma;
 211
 212	struct net_device *netdev;
 213	struct napi_struct napi;
 214	u32 msg_enable;
 215
 216	spinlock_t lock;
 217
 218	struct mii_bus *mdio;
 219	struct clk *clk;
 220	s8 phy_id;
 221
 222	int old_link;
 223	int old_duplex;
 224};
 225
 226/**
 227 * struct ethoc_bd - buffer descriptor
 228 * @stat:	buffer statistics
 229 * @addr:	physical memory address
 230 */
 231struct ethoc_bd {
 232	u32 stat;
 233	u32 addr;
 234};
 235
 236static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
 237{
 238	if (dev->big_endian)
 239		return ioread32be(dev->iobase + offset);
 240	else
 241		return ioread32(dev->iobase + offset);
 242}
 243
 244static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
 245{
 246	if (dev->big_endian)
 247		iowrite32be(data, dev->iobase + offset);
 248	else
 249		iowrite32(data, dev->iobase + offset);
 250}
 251
 252static inline void ethoc_read_bd(struct ethoc *dev, int index,
 253		struct ethoc_bd *bd)
 254{
 255	loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
 256	bd->stat = ethoc_read(dev, offset + 0);
 257	bd->addr = ethoc_read(dev, offset + 4);
 258}
 259
 260static inline void ethoc_write_bd(struct ethoc *dev, int index,
 261		const struct ethoc_bd *bd)
 262{
 263	loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
 264	ethoc_write(dev, offset + 0, bd->stat);
 265	ethoc_write(dev, offset + 4, bd->addr);
 266}
 267
 268static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
 269{
 270	u32 imask = ethoc_read(dev, INT_MASK);
 271	imask |= mask;
 272	ethoc_write(dev, INT_MASK, imask);
 273}
 274
 275static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
 276{
 277	u32 imask = ethoc_read(dev, INT_MASK);
 278	imask &= ~mask;
 279	ethoc_write(dev, INT_MASK, imask);
 280}
 281
 282static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
 283{
 284	ethoc_write(dev, INT_SOURCE, mask);
 285}
 286
 287static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
 288{
 289	u32 mode = ethoc_read(dev, MODER);
 290	mode |= MODER_RXEN | MODER_TXEN;
 291	ethoc_write(dev, MODER, mode);
 292}
 293
 294static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
 295{
 296	u32 mode = ethoc_read(dev, MODER);
 297	mode &= ~(MODER_RXEN | MODER_TXEN);
 298	ethoc_write(dev, MODER, mode);
 299}
 300
 301static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
 302{
 303	struct ethoc_bd bd;
 304	int i;
 305	void *vma;
 306
 307	dev->cur_tx = 0;
 308	dev->dty_tx = 0;
 309	dev->cur_rx = 0;
 310
 311	ethoc_write(dev, TX_BD_NUM, dev->num_tx);
 312
 313	/* setup transmission buffers */
 314	bd.addr = mem_start;
 315	bd.stat = TX_BD_IRQ | TX_BD_CRC;
 316	vma = dev->membase;
 317
 318	for (i = 0; i < dev->num_tx; i++) {
 319		if (i == dev->num_tx - 1)
 320			bd.stat |= TX_BD_WRAP;
 321
 322		ethoc_write_bd(dev, i, &bd);
 323		bd.addr += ETHOC_BUFSIZ;
 324
 325		dev->vma[i] = vma;
 326		vma += ETHOC_BUFSIZ;
 327	}
 328
 329	bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
 330
 331	for (i = 0; i < dev->num_rx; i++) {
 332		if (i == dev->num_rx - 1)
 333			bd.stat |= RX_BD_WRAP;
 334
 335		ethoc_write_bd(dev, dev->num_tx + i, &bd);
 336		bd.addr += ETHOC_BUFSIZ;
 337
 338		dev->vma[dev->num_tx + i] = vma;
 339		vma += ETHOC_BUFSIZ;
 340	}
 341
 342	return 0;
 343}
 344
 345static int ethoc_reset(struct ethoc *dev)
 346{
 347	u32 mode;
 348
 349	/* TODO: reset controller? */
 350
 351	ethoc_disable_rx_and_tx(dev);
 352
 353	/* TODO: setup registers */
 354
 355	/* enable FCS generation and automatic padding */
 356	mode = ethoc_read(dev, MODER);
 357	mode |= MODER_CRC | MODER_PAD;
 358	ethoc_write(dev, MODER, mode);
 359
 360	/* set full-duplex mode */
 361	mode = ethoc_read(dev, MODER);
 362	mode |= MODER_FULLD;
 363	ethoc_write(dev, MODER, mode);
 364	ethoc_write(dev, IPGT, 0x15);
 365
 366	ethoc_ack_irq(dev, INT_MASK_ALL);
 367	ethoc_enable_irq(dev, INT_MASK_ALL);
 368	ethoc_enable_rx_and_tx(dev);
 369	return 0;
 370}
 371
 372static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
 373		struct ethoc_bd *bd)
 374{
 375	struct net_device *netdev = dev->netdev;
 376	unsigned int ret = 0;
 377
 378	if (bd->stat & RX_BD_TL) {
 379		dev_err(&netdev->dev, "RX: frame too long\n");
 380		netdev->stats.rx_length_errors++;
 381		ret++;
 382	}
 383
 384	if (bd->stat & RX_BD_SF) {
 385		dev_err(&netdev->dev, "RX: frame too short\n");
 386		netdev->stats.rx_length_errors++;
 387		ret++;
 388	}
 389
 390	if (bd->stat & RX_BD_DN) {
 391		dev_err(&netdev->dev, "RX: dribble nibble\n");
 392		netdev->stats.rx_frame_errors++;
 393	}
 394
 395	if (bd->stat & RX_BD_CRC) {
 396		dev_err(&netdev->dev, "RX: wrong CRC\n");
 397		netdev->stats.rx_crc_errors++;
 398		ret++;
 399	}
 400
 401	if (bd->stat & RX_BD_OR) {
 402		dev_err(&netdev->dev, "RX: overrun\n");
 403		netdev->stats.rx_over_errors++;
 404		ret++;
 405	}
 406
 407	if (bd->stat & RX_BD_MISS)
 408		netdev->stats.rx_missed_errors++;
 409
 410	if (bd->stat & RX_BD_LC) {
 411		dev_err(&netdev->dev, "RX: late collision\n");
 412		netdev->stats.collisions++;
 413		ret++;
 414	}
 415
 416	return ret;
 417}
 418
 419static int ethoc_rx(struct net_device *dev, int limit)
 420{
 421	struct ethoc *priv = netdev_priv(dev);
 422	int count;
 423
 424	for (count = 0; count < limit; ++count) {
 425		unsigned int entry;
 426		struct ethoc_bd bd;
 427
 428		entry = priv->num_tx + priv->cur_rx;
 429		ethoc_read_bd(priv, entry, &bd);
 430		if (bd.stat & RX_BD_EMPTY) {
 431			ethoc_ack_irq(priv, INT_MASK_RX);
 432			/* If packet (interrupt) came in between checking
 433			 * BD_EMTPY and clearing the interrupt source, then we
 434			 * risk missing the packet as the RX interrupt won't
 435			 * trigger right away when we reenable it; hence, check
 436			 * BD_EMTPY here again to make sure there isn't such a
 437			 * packet waiting for us...
 438			 */
 439			ethoc_read_bd(priv, entry, &bd);
 440			if (bd.stat & RX_BD_EMPTY)
 441				break;
 442		}
 443
 444		if (ethoc_update_rx_stats(priv, &bd) == 0) {
 445			int size = bd.stat >> 16;
 446			struct sk_buff *skb;
 447
 448			size -= 4; /* strip the CRC */
 449			skb = netdev_alloc_skb_ip_align(dev, size);
 450
 451			if (likely(skb)) {
 452				void *src = priv->vma[entry];
 453				memcpy_fromio(skb_put(skb, size), src, size);
 454				skb->protocol = eth_type_trans(skb, dev);
 455				dev->stats.rx_packets++;
 456				dev->stats.rx_bytes += size;
 457				netif_receive_skb(skb);
 458			} else {
 459				if (net_ratelimit())
 460					dev_warn(&dev->dev,
 461					    "low on memory - packet dropped\n");
 462
 463				dev->stats.rx_dropped++;
 464				break;
 465			}
 466		}
 467
 468		/* clear the buffer descriptor so it can be reused */
 469		bd.stat &= ~RX_BD_STATS;
 470		bd.stat |=  RX_BD_EMPTY;
 471		ethoc_write_bd(priv, entry, &bd);
 472		if (++priv->cur_rx == priv->num_rx)
 473			priv->cur_rx = 0;
 474	}
 475
 476	return count;
 477}
 478
 479static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
 480{
 481	struct net_device *netdev = dev->netdev;
 482
 483	if (bd->stat & TX_BD_LC) {
 484		dev_err(&netdev->dev, "TX: late collision\n");
 485		netdev->stats.tx_window_errors++;
 486	}
 487
 488	if (bd->stat & TX_BD_RL) {
 489		dev_err(&netdev->dev, "TX: retransmit limit\n");
 490		netdev->stats.tx_aborted_errors++;
 491	}
 492
 493	if (bd->stat & TX_BD_UR) {
 494		dev_err(&netdev->dev, "TX: underrun\n");
 495		netdev->stats.tx_fifo_errors++;
 496	}
 497
 498	if (bd->stat & TX_BD_CS) {
 499		dev_err(&netdev->dev, "TX: carrier sense lost\n");
 500		netdev->stats.tx_carrier_errors++;
 501	}
 502
 503	if (bd->stat & TX_BD_STATS)
 504		netdev->stats.tx_errors++;
 505
 506	netdev->stats.collisions += (bd->stat >> 4) & 0xf;
 507	netdev->stats.tx_bytes += bd->stat >> 16;
 508	netdev->stats.tx_packets++;
 509}
 510
 511static int ethoc_tx(struct net_device *dev, int limit)
 512{
 513	struct ethoc *priv = netdev_priv(dev);
 514	int count;
 515	struct ethoc_bd bd;
 516
 517	for (count = 0; count < limit; ++count) {
 518		unsigned int entry;
 519
 520		entry = priv->dty_tx & (priv->num_tx-1);
 521
 522		ethoc_read_bd(priv, entry, &bd);
 523
 524		if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
 525			ethoc_ack_irq(priv, INT_MASK_TX);
 526			/* If interrupt came in between reading in the BD
 527			 * and clearing the interrupt source, then we risk
 528			 * missing the event as the TX interrupt won't trigger
 529			 * right away when we reenable it; hence, check
 530			 * BD_EMPTY here again to make sure there isn't such an
 531			 * event pending...
 532			 */
 533			ethoc_read_bd(priv, entry, &bd);
 534			if (bd.stat & TX_BD_READY ||
 535			    (priv->dty_tx == priv->cur_tx))
 536				break;
 537		}
 538
 539		ethoc_update_tx_stats(priv, &bd);
 540		priv->dty_tx++;
 541	}
 542
 543	if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
 544		netif_wake_queue(dev);
 545
 546	return count;
 547}
 548
 549static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
 550{
 551	struct net_device *dev = dev_id;
 552	struct ethoc *priv = netdev_priv(dev);
 553	u32 pending;
 554	u32 mask;
 555
 556	/* Figure out what triggered the interrupt...
 557	 * The tricky bit here is that the interrupt source bits get
 558	 * set in INT_SOURCE for an event regardless of whether that
 559	 * event is masked or not.  Thus, in order to figure out what
 560	 * triggered the interrupt, we need to remove the sources
 561	 * for all events that are currently masked.  This behaviour
 562	 * is not particularly well documented but reasonable...
 563	 */
 564	mask = ethoc_read(priv, INT_MASK);
 565	pending = ethoc_read(priv, INT_SOURCE);
 566	pending &= mask;
 567
 568	if (unlikely(pending == 0))
 569		return IRQ_NONE;
 570
 571	ethoc_ack_irq(priv, pending);
 572
 573	/* We always handle the dropped packet interrupt */
 574	if (pending & INT_MASK_BUSY) {
 575		dev_dbg(&dev->dev, "packet dropped\n");
 576		dev->stats.rx_dropped++;
 577	}
 578
 579	/* Handle receive/transmit event by switching to polling */
 580	if (pending & (INT_MASK_TX | INT_MASK_RX)) {
 581		ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 582		napi_schedule(&priv->napi);
 583	}
 584
 585	return IRQ_HANDLED;
 586}
 587
 588static int ethoc_get_mac_address(struct net_device *dev, void *addr)
 589{
 590	struct ethoc *priv = netdev_priv(dev);
 591	u8 *mac = (u8 *)addr;
 592	u32 reg;
 593
 594	reg = ethoc_read(priv, MAC_ADDR0);
 595	mac[2] = (reg >> 24) & 0xff;
 596	mac[3] = (reg >> 16) & 0xff;
 597	mac[4] = (reg >>  8) & 0xff;
 598	mac[5] = (reg >>  0) & 0xff;
 599
 600	reg = ethoc_read(priv, MAC_ADDR1);
 601	mac[0] = (reg >>  8) & 0xff;
 602	mac[1] = (reg >>  0) & 0xff;
 603
 604	return 0;
 605}
 606
 607static int ethoc_poll(struct napi_struct *napi, int budget)
 608{
 609	struct ethoc *priv = container_of(napi, struct ethoc, napi);
 610	int rx_work_done = 0;
 611	int tx_work_done = 0;
 612
 613	rx_work_done = ethoc_rx(priv->netdev, budget);
 614	tx_work_done = ethoc_tx(priv->netdev, budget);
 615
 616	if (rx_work_done < budget && tx_work_done < budget) {
 617		napi_complete_done(napi, rx_work_done);
 618		ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 619	}
 620
 621	return rx_work_done;
 622}
 623
 624static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
 625{
 626	struct ethoc *priv = bus->priv;
 627	int i;
 628
 629	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
 630	ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
 631
 632	for (i = 0; i < 5; i++) {
 633		u32 status = ethoc_read(priv, MIISTATUS);
 634		if (!(status & MIISTATUS_BUSY)) {
 635			u32 data = ethoc_read(priv, MIIRX_DATA);
 636			/* reset MII command register */
 637			ethoc_write(priv, MIICOMMAND, 0);
 638			return data;
 639		}
 640		usleep_range(100, 200);
 641	}
 642
 643	return -EBUSY;
 644}
 645
 646static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
 647{
 648	struct ethoc *priv = bus->priv;
 649	int i;
 650
 651	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
 652	ethoc_write(priv, MIITX_DATA, val);
 653	ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
 654
 655	for (i = 0; i < 5; i++) {
 656		u32 stat = ethoc_read(priv, MIISTATUS);
 657		if (!(stat & MIISTATUS_BUSY)) {
 658			/* reset MII command register */
 659			ethoc_write(priv, MIICOMMAND, 0);
 660			return 0;
 661		}
 662		usleep_range(100, 200);
 663	}
 664
 665	return -EBUSY;
 666}
 667
 668static void ethoc_mdio_poll(struct net_device *dev)
 669{
 670	struct ethoc *priv = netdev_priv(dev);
 671	struct phy_device *phydev = dev->phydev;
 672	bool changed = false;
 673	u32 mode;
 674
 675	if (priv->old_link != phydev->link) {
 676		changed = true;
 677		priv->old_link = phydev->link;
 678	}
 679
 680	if (priv->old_duplex != phydev->duplex) {
 681		changed = true;
 682		priv->old_duplex = phydev->duplex;
 683	}
 684
 685	if (!changed)
 686		return;
 687
 688	mode = ethoc_read(priv, MODER);
 689	if (phydev->duplex == DUPLEX_FULL)
 690		mode |= MODER_FULLD;
 691	else
 692		mode &= ~MODER_FULLD;
 693	ethoc_write(priv, MODER, mode);
 694
 695	phy_print_status(phydev);
 696}
 697
 698static int ethoc_mdio_probe(struct net_device *dev)
 699{
 700	struct ethoc *priv = netdev_priv(dev);
 701	struct phy_device *phy;
 702	int err;
 703
 704	if (priv->phy_id != -1)
 705		phy = mdiobus_get_phy(priv->mdio, priv->phy_id);
 706	else
 707		phy = phy_find_first(priv->mdio);
 708
 709	if (!phy) {
 710		dev_err(&dev->dev, "no PHY found\n");
 711		return -ENXIO;
 712	}
 713
 714	priv->old_duplex = -1;
 715	priv->old_link = -1;
 716
 717	err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
 718				 PHY_INTERFACE_MODE_GMII);
 719	if (err) {
 720		dev_err(&dev->dev, "could not attach to PHY\n");
 721		return err;
 722	}
 723
 724	phy->advertising &= ~(ADVERTISED_1000baseT_Full |
 725			      ADVERTISED_1000baseT_Half);
 726	phy->supported &= ~(SUPPORTED_1000baseT_Full |
 727			    SUPPORTED_1000baseT_Half);
 728
 729	return 0;
 730}
 731
 732static int ethoc_open(struct net_device *dev)
 733{
 734	struct ethoc *priv = netdev_priv(dev);
 735	int ret;
 736
 737	ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
 738			dev->name, dev);
 739	if (ret)
 740		return ret;
 741
 742	napi_enable(&priv->napi);
 743
 744	ethoc_init_ring(priv, dev->mem_start);
 745	ethoc_reset(priv);
 746
 747	if (netif_queue_stopped(dev)) {
 748		dev_dbg(&dev->dev, " resuming queue\n");
 749		netif_wake_queue(dev);
 750	} else {
 751		dev_dbg(&dev->dev, " starting queue\n");
 752		netif_start_queue(dev);
 753	}
 754
 755	priv->old_link = -1;
 756	priv->old_duplex = -1;
 757
 758	phy_start(dev->phydev);
 759
 760	if (netif_msg_ifup(priv)) {
 761		dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
 762				dev->base_addr, dev->mem_start, dev->mem_end);
 763	}
 764
 765	return 0;
 766}
 767
 768static int ethoc_stop(struct net_device *dev)
 769{
 770	struct ethoc *priv = netdev_priv(dev);
 771
 772	napi_disable(&priv->napi);
 773
 774	if (dev->phydev)
 775		phy_stop(dev->phydev);
 776
 777	ethoc_disable_rx_and_tx(priv);
 778	free_irq(dev->irq, dev);
 779
 780	if (!netif_queue_stopped(dev))
 781		netif_stop_queue(dev);
 782
 783	return 0;
 784}
 785
 786static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 787{
 788	struct ethoc *priv = netdev_priv(dev);
 789	struct mii_ioctl_data *mdio = if_mii(ifr);
 790	struct phy_device *phy = NULL;
 791
 792	if (!netif_running(dev))
 793		return -EINVAL;
 794
 795	if (cmd != SIOCGMIIPHY) {
 796		if (mdio->phy_id >= PHY_MAX_ADDR)
 797			return -ERANGE;
 798
 799		phy = mdiobus_get_phy(priv->mdio, mdio->phy_id);
 800		if (!phy)
 801			return -ENODEV;
 802	} else {
 803		phy = dev->phydev;
 804	}
 805
 806	return phy_mii_ioctl(phy, ifr, cmd);
 807}
 808
 809static void ethoc_do_set_mac_address(struct net_device *dev)
 810{
 811	struct ethoc *priv = netdev_priv(dev);
 812	unsigned char *mac = dev->dev_addr;
 813
 814	ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
 815				     (mac[4] <<  8) | (mac[5] <<  0));
 816	ethoc_write(priv, MAC_ADDR1, (mac[0] <<  8) | (mac[1] <<  0));
 817}
 818
 819static int ethoc_set_mac_address(struct net_device *dev, void *p)
 820{
 821	const struct sockaddr *addr = p;
 822
 823	if (!is_valid_ether_addr(addr->sa_data))
 824		return -EADDRNOTAVAIL;
 825	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 826	ethoc_do_set_mac_address(dev);
 827	return 0;
 828}
 829
 830static void ethoc_set_multicast_list(struct net_device *dev)
 831{
 832	struct ethoc *priv = netdev_priv(dev);
 833	u32 mode = ethoc_read(priv, MODER);
 834	struct netdev_hw_addr *ha;
 835	u32 hash[2] = { 0, 0 };
 836
 837	/* set loopback mode if requested */
 838	if (dev->flags & IFF_LOOPBACK)
 839		mode |=  MODER_LOOP;
 840	else
 841		mode &= ~MODER_LOOP;
 842
 843	/* receive broadcast frames if requested */
 844	if (dev->flags & IFF_BROADCAST)
 845		mode &= ~MODER_BRO;
 846	else
 847		mode |=  MODER_BRO;
 848
 849	/* enable promiscuous mode if requested */
 850	if (dev->flags & IFF_PROMISC)
 851		mode |=  MODER_PRO;
 852	else
 853		mode &= ~MODER_PRO;
 854
 855	ethoc_write(priv, MODER, mode);
 856
 857	/* receive multicast frames */
 858	if (dev->flags & IFF_ALLMULTI) {
 859		hash[0] = 0xffffffff;
 860		hash[1] = 0xffffffff;
 861	} else {
 862		netdev_for_each_mc_addr(ha, dev) {
 863			u32 crc = ether_crc(ETH_ALEN, ha->addr);
 864			int bit = (crc >> 26) & 0x3f;
 865			hash[bit >> 5] |= 1 << (bit & 0x1f);
 866		}
 867	}
 868
 869	ethoc_write(priv, ETH_HASH0, hash[0]);
 870	ethoc_write(priv, ETH_HASH1, hash[1]);
 871}
 872
 873static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
 874{
 875	return -ENOSYS;
 876}
 877
 878static void ethoc_tx_timeout(struct net_device *dev)
 879{
 880	struct ethoc *priv = netdev_priv(dev);
 881	u32 pending = ethoc_read(priv, INT_SOURCE);
 882	if (likely(pending))
 883		ethoc_interrupt(dev->irq, dev);
 884}
 885
 886static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
 887{
 888	struct ethoc *priv = netdev_priv(dev);
 889	struct ethoc_bd bd;
 890	unsigned int entry;
 891	void *dest;
 892
 893	if (skb_put_padto(skb, ETHOC_ZLEN)) {
 894		dev->stats.tx_errors++;
 895		goto out_no_free;
 896	}
 897
 898	if (unlikely(skb->len > ETHOC_BUFSIZ)) {
 899		dev->stats.tx_errors++;
 900		goto out;
 901	}
 902
 903	entry = priv->cur_tx % priv->num_tx;
 904	spin_lock_irq(&priv->lock);
 905	priv->cur_tx++;
 906
 907	ethoc_read_bd(priv, entry, &bd);
 908	if (unlikely(skb->len < ETHOC_ZLEN))
 909		bd.stat |=  TX_BD_PAD;
 910	else
 911		bd.stat &= ~TX_BD_PAD;
 912
 913	dest = priv->vma[entry];
 914	memcpy_toio(dest, skb->data, skb->len);
 915
 916	bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
 917	bd.stat |= TX_BD_LEN(skb->len);
 918	ethoc_write_bd(priv, entry, &bd);
 919
 920	bd.stat |= TX_BD_READY;
 921	ethoc_write_bd(priv, entry, &bd);
 922
 923	if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
 924		dev_dbg(&dev->dev, "stopping queue\n");
 925		netif_stop_queue(dev);
 926	}
 927
 928	spin_unlock_irq(&priv->lock);
 929	skb_tx_timestamp(skb);
 930out:
 931	dev_kfree_skb(skb);
 932out_no_free:
 933	return NETDEV_TX_OK;
 934}
 935
 936static int ethoc_get_regs_len(struct net_device *netdev)
 937{
 938	return ETH_END;
 939}
 940
 941static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 942			   void *p)
 943{
 944	struct ethoc *priv = netdev_priv(dev);
 945	u32 *regs_buff = p;
 946	unsigned i;
 947
 948	regs->version = 0;
 949	for (i = 0; i < ETH_END / sizeof(u32); ++i)
 950		regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
 951}
 952
 953static void ethoc_get_ringparam(struct net_device *dev,
 954				struct ethtool_ringparam *ring)
 955{
 956	struct ethoc *priv = netdev_priv(dev);
 957
 958	ring->rx_max_pending = priv->num_bd - 1;
 959	ring->rx_mini_max_pending = 0;
 960	ring->rx_jumbo_max_pending = 0;
 961	ring->tx_max_pending = priv->num_bd - 1;
 962
 963	ring->rx_pending = priv->num_rx;
 964	ring->rx_mini_pending = 0;
 965	ring->rx_jumbo_pending = 0;
 966	ring->tx_pending = priv->num_tx;
 967}
 968
 969static int ethoc_set_ringparam(struct net_device *dev,
 970			       struct ethtool_ringparam *ring)
 971{
 972	struct ethoc *priv = netdev_priv(dev);
 973
 974	if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
 975	    ring->tx_pending + ring->rx_pending > priv->num_bd)
 976		return -EINVAL;
 977	if (ring->rx_mini_pending || ring->rx_jumbo_pending)
 978		return -EINVAL;
 979
 980	if (netif_running(dev)) {
 981		netif_tx_disable(dev);
 982		ethoc_disable_rx_and_tx(priv);
 983		ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 984		synchronize_irq(dev->irq);
 985	}
 986
 987	priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
 988	priv->num_rx = ring->rx_pending;
 989	ethoc_init_ring(priv, dev->mem_start);
 990
 991	if (netif_running(dev)) {
 992		ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 993		ethoc_enable_rx_and_tx(priv);
 994		netif_wake_queue(dev);
 995	}
 996	return 0;
 997}
 998
 999static const struct ethtool_ops ethoc_ethtool_ops = {
1000	.get_regs_len = ethoc_get_regs_len,
1001	.get_regs = ethoc_get_regs,
1002	.nway_reset = phy_ethtool_nway_reset,
1003	.get_link = ethtool_op_get_link,
1004	.get_ringparam = ethoc_get_ringparam,
1005	.set_ringparam = ethoc_set_ringparam,
1006	.get_ts_info = ethtool_op_get_ts_info,
1007	.get_link_ksettings = phy_ethtool_get_link_ksettings,
1008	.set_link_ksettings = phy_ethtool_set_link_ksettings,
1009};
1010
1011static const struct net_device_ops ethoc_netdev_ops = {
1012	.ndo_open = ethoc_open,
1013	.ndo_stop = ethoc_stop,
1014	.ndo_do_ioctl = ethoc_ioctl,
1015	.ndo_set_mac_address = ethoc_set_mac_address,
1016	.ndo_set_rx_mode = ethoc_set_multicast_list,
1017	.ndo_change_mtu = ethoc_change_mtu,
1018	.ndo_tx_timeout = ethoc_tx_timeout,
1019	.ndo_start_xmit = ethoc_start_xmit,
1020};
1021
1022/**
1023 * ethoc_probe - initialize OpenCores ethernet MAC
1024 * pdev:	platform device
1025 */
1026static int ethoc_probe(struct platform_device *pdev)
1027{
1028	struct net_device *netdev = NULL;
1029	struct resource *res = NULL;
1030	struct resource *mmio = NULL;
1031	struct resource *mem = NULL;
1032	struct ethoc *priv = NULL;
1033	int num_bd;
1034	int ret = 0;
1035	struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1036	u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
1037
1038	/* allocate networking device */
1039	netdev = alloc_etherdev(sizeof(struct ethoc));
1040	if (!netdev) {
1041		ret = -ENOMEM;
1042		goto out;
1043	}
1044
1045	SET_NETDEV_DEV(netdev, &pdev->dev);
1046	platform_set_drvdata(pdev, netdev);
1047
1048	/* obtain I/O memory space */
1049	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1050	if (!res) {
1051		dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
1052		ret = -ENXIO;
1053		goto free;
1054	}
1055
1056	mmio = devm_request_mem_region(&pdev->dev, res->start,
1057			resource_size(res), res->name);
1058	if (!mmio) {
1059		dev_err(&pdev->dev, "cannot request I/O memory space\n");
1060		ret = -ENXIO;
1061		goto free;
1062	}
1063
1064	netdev->base_addr = mmio->start;
1065
1066	/* obtain buffer memory space */
1067	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1068	if (res) {
1069		mem = devm_request_mem_region(&pdev->dev, res->start,
1070			resource_size(res), res->name);
1071		if (!mem) {
1072			dev_err(&pdev->dev, "cannot request memory space\n");
1073			ret = -ENXIO;
1074			goto free;
1075		}
1076
1077		netdev->mem_start = mem->start;
1078		netdev->mem_end   = mem->end;
1079	}
1080
1081
1082	/* obtain device IRQ number */
1083	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1084	if (!res) {
1085		dev_err(&pdev->dev, "cannot obtain IRQ\n");
1086		ret = -ENXIO;
1087		goto free;
1088	}
1089
1090	netdev->irq = res->start;
1091
1092	/* setup driver-private data */
1093	priv = netdev_priv(netdev);
1094	priv->netdev = netdev;
1095
1096	priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
1097			resource_size(mmio));
1098	if (!priv->iobase) {
1099		dev_err(&pdev->dev, "cannot remap I/O memory space\n");
1100		ret = -ENXIO;
1101		goto free;
1102	}
1103
1104	if (netdev->mem_end) {
1105		priv->membase = devm_ioremap_nocache(&pdev->dev,
1106			netdev->mem_start, resource_size(mem));
1107		if (!priv->membase) {
1108			dev_err(&pdev->dev, "cannot remap memory space\n");
1109			ret = -ENXIO;
1110			goto free;
1111		}
1112	} else {
1113		/* Allocate buffer memory */
1114		priv->membase = dmam_alloc_coherent(&pdev->dev,
1115			buffer_size, (void *)&netdev->mem_start,
1116			GFP_KERNEL);
1117		if (!priv->membase) {
1118			dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
1119				buffer_size);
1120			ret = -ENOMEM;
1121			goto free;
1122		}
1123		netdev->mem_end = netdev->mem_start + buffer_size;
1124	}
1125
1126	priv->big_endian = pdata ? pdata->big_endian :
1127		of_device_is_big_endian(pdev->dev.of_node);
1128
1129	/* calculate the number of TX/RX buffers, maximum 128 supported */
1130	num_bd = min_t(unsigned int,
1131		128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
1132	if (num_bd < 4) {
1133		ret = -ENODEV;
1134		goto free;
1135	}
1136	priv->num_bd = num_bd;
1137	/* num_tx must be a power of two */
1138	priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
1139	priv->num_rx = num_bd - priv->num_tx;
1140
1141	dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
1142		priv->num_tx, priv->num_rx);
1143
1144	priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void *), GFP_KERNEL);
1145	if (!priv->vma) {
1146		ret = -ENOMEM;
1147		goto free;
1148	}
1149
1150	/* Allow the platform setup code to pass in a MAC address. */
1151	if (pdata) {
1152		ether_addr_copy(netdev->dev_addr, pdata->hwaddr);
1153		priv->phy_id = pdata->phy_id;
1154	} else {
1155		const void *mac;
1156
1157		mac = of_get_mac_address(pdev->dev.of_node);
1158		if (mac)
1159			ether_addr_copy(netdev->dev_addr, mac);
1160		priv->phy_id = -1;
1161	}
1162
1163	/* Check that the given MAC address is valid. If it isn't, read the
1164	 * current MAC from the controller.
1165	 */
1166	if (!is_valid_ether_addr(netdev->dev_addr))
1167		ethoc_get_mac_address(netdev, netdev->dev_addr);
1168
1169	/* Check the MAC again for validity, if it still isn't choose and
1170	 * program a random one.
1171	 */
1172	if (!is_valid_ether_addr(netdev->dev_addr))
1173		eth_hw_addr_random(netdev);
1174
1175	ethoc_do_set_mac_address(netdev);
1176
1177	/* Allow the platform setup code to adjust MII management bus clock. */
1178	if (!eth_clkfreq) {
1179		struct clk *clk = devm_clk_get(&pdev->dev, NULL);
1180
1181		if (!IS_ERR(clk)) {
1182			priv->clk = clk;
1183			clk_prepare_enable(clk);
1184			eth_clkfreq = clk_get_rate(clk);
1185		}
1186	}
1187	if (eth_clkfreq) {
1188		u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);
1189
1190		if (!clkdiv)
1191			clkdiv = 2;
1192		dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
1193		ethoc_write(priv, MIIMODER,
1194			    (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
1195			    clkdiv);
1196	}
1197
1198	/* register MII bus */
1199	priv->mdio = mdiobus_alloc();
1200	if (!priv->mdio) {
1201		ret = -ENOMEM;
1202		goto free2;
1203	}
1204
1205	priv->mdio->name = "ethoc-mdio";
1206	snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1207			priv->mdio->name, pdev->id);
1208	priv->mdio->read = ethoc_mdio_read;
1209	priv->mdio->write = ethoc_mdio_write;
1210	priv->mdio->priv = priv;
1211
1212	ret = mdiobus_register(priv->mdio);
1213	if (ret) {
1214		dev_err(&netdev->dev, "failed to register MDIO bus\n");
1215		goto free2;
1216	}
1217
1218	ret = ethoc_mdio_probe(netdev);
1219	if (ret) {
1220		dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1221		goto error;
1222	}
1223
1224	/* setup the net_device structure */
1225	netdev->netdev_ops = &ethoc_netdev_ops;
1226	netdev->watchdog_timeo = ETHOC_TIMEOUT;
1227	netdev->features |= 0;
1228	netdev->ethtool_ops = &ethoc_ethtool_ops;
1229
1230	/* setup NAPI */
1231	netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1232
1233	spin_lock_init(&priv->lock);
1234
1235	ret = register_netdev(netdev);
1236	if (ret < 0) {
1237		dev_err(&netdev->dev, "failed to register interface\n");
1238		goto error2;
1239	}
1240
1241	goto out;
1242
1243error2:
1244	netif_napi_del(&priv->napi);
1245error:
1246	mdiobus_unregister(priv->mdio);
1247	mdiobus_free(priv->mdio);
1248free2:
1249	if (priv->clk)
1250		clk_disable_unprepare(priv->clk);
1251free:
1252	free_netdev(netdev);
1253out:
1254	return ret;
1255}
1256
1257/**
1258 * ethoc_remove - shutdown OpenCores ethernet MAC
1259 * @pdev:	platform device
1260 */
1261static int ethoc_remove(struct platform_device *pdev)
1262{
1263	struct net_device *netdev = platform_get_drvdata(pdev);
1264	struct ethoc *priv = netdev_priv(netdev);
1265
1266	if (netdev) {
1267		netif_napi_del(&priv->napi);
1268		phy_disconnect(netdev->phydev);
1269
1270		if (priv->mdio) {
1271			mdiobus_unregister(priv->mdio);
1272			mdiobus_free(priv->mdio);
1273		}
1274		if (priv->clk)
1275			clk_disable_unprepare(priv->clk);
1276		unregister_netdev(netdev);
1277		free_netdev(netdev);
1278	}
1279
1280	return 0;
1281}
1282
1283#ifdef CONFIG_PM
1284static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1285{
1286	return -ENOSYS;
1287}
1288
1289static int ethoc_resume(struct platform_device *pdev)
1290{
1291	return -ENOSYS;
1292}
1293#else
1294# define ethoc_suspend NULL
1295# define ethoc_resume  NULL
1296#endif
1297
1298static const struct of_device_id ethoc_match[] = {
1299	{ .compatible = "opencores,ethoc", },
1300	{},
1301};
1302MODULE_DEVICE_TABLE(of, ethoc_match);
1303
1304static struct platform_driver ethoc_driver = {
1305	.probe   = ethoc_probe,
1306	.remove  = ethoc_remove,
1307	.suspend = ethoc_suspend,
1308	.resume  = ethoc_resume,
1309	.driver  = {
1310		.name = "ethoc",
1311		.of_match_table = ethoc_match,
1312	},
1313};
1314
1315module_platform_driver(ethoc_driver);
1316
1317MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1318MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1319MODULE_LICENSE("GPL v2");
1320