1/*
  2 * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
  3 * Copyright (c) 2008-2009 Marvell Semiconductor
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License as published by
  7 * the Free Software Foundation; either version 2 of the License, or
  8 * (at your option) any later version.
  9 */
 10
 11#include <linux/delay.h>
 12#include <linux/etherdevice.h>
 13#include <linux/jiffies.h>
 14#include <linux/list.h>
 15#include <linux/module.h>
 16#include <linux/netdevice.h>
 17#include <linux/phy.h>
 18#include <net/dsa.h>
 19#include "mv88e6060.h"
 20
 21static int reg_read(struct dsa_switch *ds, int addr, int reg)
 22{
 23	struct mv88e6060_priv *priv = ds->priv;
 24
 25	return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
 26}
 27
 28#define REG_READ(addr, reg)					\
 29	({							\
 30		int __ret;					\
 31								\
 32		__ret = reg_read(ds, addr, reg);		\
 33		if (__ret < 0)					\
 34			return __ret;				\
 35		__ret;						\
 36	})
 37
 38
 39static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
 40{
 41	struct mv88e6060_priv *priv = ds->priv;
 42
 43	return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
 44}
 45
 46#define REG_WRITE(addr, reg, val)				\
 47	({							\
 48		int __ret;					\
 49								\
 50		__ret = reg_write(ds, addr, reg, val);		\
 51		if (__ret < 0)					\
 52			return __ret;				\
 53	})
 54
 55static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
 56{
 57	int ret;
 58
 59	ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
 60	if (ret >= 0) {
 61		if (ret == PORT_SWITCH_ID_6060)
 62			return "Marvell 88E6060 (A0)";
 63		if (ret == PORT_SWITCH_ID_6060_R1 ||
 64		    ret == PORT_SWITCH_ID_6060_R2)
 65			return "Marvell 88E6060 (B0)";
 66		if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
 67			return "Marvell 88E6060";
 68	}
 69
 70	return NULL;
 71}
 72
 73static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds,
 74							int port)
 75{
 76	return DSA_TAG_PROTO_TRAILER;
 77}
 78
 79static const char *mv88e6060_drv_probe(struct device *dsa_dev,
 80				       struct device *host_dev, int sw_addr,
 81				       void **_priv)
 82{
 83	struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
 84	struct mv88e6060_priv *priv;
 85	const char *name;
 86
 87	name = mv88e6060_get_name(bus, sw_addr);
 88	if (name) {
 89		priv = devm_kzalloc(dsa_dev, sizeof(*priv), GFP_KERNEL);
 90		if (!priv)
 91			return NULL;
 92		*_priv = priv;
 93		priv->bus = bus;
 94		priv->sw_addr = sw_addr;
 95	}
 96
 97	return name;
 98}
 99
100static int mv88e6060_switch_reset(struct dsa_switch *ds)
101{
102	int i;
103	int ret;
104	unsigned long timeout;
105
106	/* Set all ports to the disabled state. */
107	for (i = 0; i < MV88E6060_PORTS; i++) {
108		ret = REG_READ(REG_PORT(i), PORT_CONTROL);
109		REG_WRITE(REG_PORT(i), PORT_CONTROL,
110			  ret & ~PORT_CONTROL_STATE_MASK);
111	}
112
113	/* Wait for transmit queues to drain. */
114	usleep_range(2000, 4000);
115
116	/* Reset the switch. */
117	REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
118		  GLOBAL_ATU_CONTROL_SWRESET |
119		  GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
120		  GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
121
122	/* Wait up to one second for reset to complete. */
123	timeout = jiffies + 1 * HZ;
124	while (time_before(jiffies, timeout)) {
125		ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
126		if (ret & GLOBAL_STATUS_INIT_READY)
127			break;
128
129		usleep_range(1000, 2000);
130	}
131	if (time_after(jiffies, timeout))
132		return -ETIMEDOUT;
133
134	return 0;
135}
136
137static int mv88e6060_setup_global(struct dsa_switch *ds)
138{
139	/* Disable discarding of frames with excessive collisions,
140	 * set the maximum frame size to 1536 bytes, and mask all
141	 * interrupt sources.
142	 */
143	REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536);
144
145	/* Enable automatic address learning, set the address
146	 * database size to 1024 entries, and set the default aging
147	 * time to 5 minutes.
148	 */
149	REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
150		  GLOBAL_ATU_CONTROL_ATUSIZE_1024 |
151		  GLOBAL_ATU_CONTROL_ATE_AGE_5MIN);
152
153	return 0;
154}
155
156static int mv88e6060_setup_port(struct dsa_switch *ds, int p)
157{
158	int addr = REG_PORT(p);
159
160	/* Do not force flow control, disable Ingress and Egress
161	 * Header tagging, disable VLAN tunneling, and set the port
162	 * state to Forwarding.  Additionally, if this is the CPU
163	 * port, enable Ingress and Egress Trailer tagging mode.
164	 */
165	REG_WRITE(addr, PORT_CONTROL,
166		  dsa_is_cpu_port(ds, p) ?
167			PORT_CONTROL_TRAILER |
168			PORT_CONTROL_INGRESS_MODE |
169			PORT_CONTROL_STATE_FORWARDING :
170			PORT_CONTROL_STATE_FORWARDING);
171
172	/* Port based VLAN map: give each port its own address
173	 * database, allow the CPU port to talk to each of the 'real'
174	 * ports, and allow each of the 'real' ports to only talk to
175	 * the CPU port.
176	 */
177	REG_WRITE(addr, PORT_VLAN_MAP,
178		  ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
179		   (dsa_is_cpu_port(ds, p) ? dsa_user_ports(ds) :
180		    BIT(dsa_to_port(ds, p)->cpu_dp->index)));
181
182	/* Port Association Vector: when learning source addresses
183	 * of packets, add the address to the address database using
184	 * a port bitmap that has only the bit for this port set and
185	 * the other bits clear.
186	 */
187	REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p));
188
189	return 0;
190}
191
192static int mv88e6060_setup_addr(struct dsa_switch *ds)
193{
194	u8 addr[ETH_ALEN];
195	u16 val;
196
197	eth_random_addr(addr);
198
199	val = addr[0] << 8 | addr[1];
200
201	/* The multicast bit is always transmitted as a zero, so the switch uses
202	 * bit 8 for "DiffAddr", where 0 means all ports transmit the same SA.
203	 */
204	val &= 0xfeff;
205
206	REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, val);
207	REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
208	REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
209
210	return 0;
211}
212
213static int mv88e6060_setup(struct dsa_switch *ds)
214{
215	int ret;
216	int i;
217
218	ret = mv88e6060_switch_reset(ds);
219	if (ret < 0)
220		return ret;
221
222	/* @@@ initialise atu */
223
224	ret = mv88e6060_setup_global(ds);
225	if (ret < 0)
226		return ret;
227
228	ret = mv88e6060_setup_addr(ds);
229	if (ret < 0)
230		return ret;
231
232	for (i = 0; i < MV88E6060_PORTS; i++) {
233		ret = mv88e6060_setup_port(ds, i);
234		if (ret < 0)
235			return ret;
236	}
237
238	return 0;
239}
240
241static int mv88e6060_port_to_phy_addr(int port)
242{
243	if (port >= 0 && port < MV88E6060_PORTS)
244		return port;
245	return -1;
246}
247
248static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
249{
250	int addr;
251
252	addr = mv88e6060_port_to_phy_addr(port);
253	if (addr == -1)
254		return 0xffff;
255
256	return reg_read(ds, addr, regnum);
257}
258
259static int
260mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
261{
262	int addr;
263
264	addr = mv88e6060_port_to_phy_addr(port);
265	if (addr == -1)
266		return 0xffff;
267
268	return reg_write(ds, addr, regnum, val);
269}
270
271static const struct dsa_switch_ops mv88e6060_switch_ops = {
272	.get_tag_protocol = mv88e6060_get_tag_protocol,
273	.probe		= mv88e6060_drv_probe,
274	.setup		= mv88e6060_setup,
275	.phy_read	= mv88e6060_phy_read,
276	.phy_write	= mv88e6060_phy_write,
277};
278
279static struct dsa_switch_driver mv88e6060_switch_drv = {
280	.ops		= &mv88e6060_switch_ops,
281};
282
283static int __init mv88e6060_init(void)
284{
285	register_switch_driver(&mv88e6060_switch_drv);
286	return 0;
287}
288module_init(mv88e6060_init);
289
290static void __exit mv88e6060_cleanup(void)
291{
292	unregister_switch_driver(&mv88e6060_switch_drv);
293}
294module_exit(mv88e6060_cleanup);
295
296MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
297MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
298MODULE_LICENSE("GPL");
299MODULE_ALIAS("platform:mv88e6060");