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1/*
2 * Marvell MMC/SD/SDIO driver
3 *
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/mbus.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/scatterlist.h>
21#include <linux/irq.h>
22#include <linux/gpio.h>
23#include <linux/mmc/host.h>
24
25#include <asm/sizes.h>
26#include <asm/unaligned.h>
27#include <plat/mvsdio.h>
28
29#include "mvsdio.h"
30
31#define DRIVER_NAME "mvsdio"
32
33static int maxfreq = MVSD_CLOCKRATE_MAX;
34static int nodma;
35
36struct mvsd_host {
37 void __iomem *base;
38 struct mmc_request *mrq;
39 spinlock_t lock;
40 unsigned int xfer_mode;
41 unsigned int intr_en;
42 unsigned int ctrl;
43 unsigned int pio_size;
44 void *pio_ptr;
45 unsigned int sg_frags;
46 unsigned int ns_per_clk;
47 unsigned int clock;
48 unsigned int base_clock;
49 struct timer_list timer;
50 struct mmc_host *mmc;
51 struct device *dev;
52 struct resource *res;
53 int irq;
54 int gpio_card_detect;
55 int gpio_write_protect;
56};
57
58#define mvsd_write(offs, val) writel(val, iobase + (offs))
59#define mvsd_read(offs) readl(iobase + (offs))
60
61static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
62{
63 void __iomem *iobase = host->base;
64 unsigned int tmout;
65 int tmout_index;
66
67 /*
68 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
69 * register is sometimes not set before a while when some
70 * "unusual" data block sizes are used (such as with the SWITCH
71 * command), even despite the fact that the XFER_DONE interrupt
72 * was raised. And if another data transfer starts before
73 * this bit comes to good sense (which eventually happens by
74 * itself) then the new transfer simply fails with a timeout.
75 */
76 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
77 unsigned long t = jiffies + HZ;
78 unsigned int hw_state, count = 0;
79 do {
80 if (time_after(jiffies, t)) {
81 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
82 break;
83 }
84 hw_state = mvsd_read(MVSD_HW_STATE);
85 count++;
86 } while (!(hw_state & (1 << 13)));
87 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
88 "(hw=0x%04x, count=%d, jiffies=%ld)\n",
89 hw_state, count, jiffies - (t - HZ));
90 }
91
92 /* If timeout=0 then maximum timeout index is used. */
93 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
94 tmout += data->timeout_clks;
95 tmout_index = fls(tmout - 1) - 12;
96 if (tmout_index < 0)
97 tmout_index = 0;
98 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
99 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
100
101 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
102 (data->flags & MMC_DATA_READ) ? "read" : "write",
103 (u32)sg_virt(data->sg), data->blocks, data->blksz,
104 tmout, tmout_index);
105
106 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
107 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
108 mvsd_write(MVSD_HOST_CTRL, host->ctrl);
109 mvsd_write(MVSD_BLK_COUNT, data->blocks);
110 mvsd_write(MVSD_BLK_SIZE, data->blksz);
111
112 if (nodma || (data->blksz | data->sg->offset) & 3) {
113 /*
114 * We cannot do DMA on a buffer which offset or size
115 * is not aligned on a 4-byte boundary.
116 */
117 host->pio_size = data->blocks * data->blksz;
118 host->pio_ptr = sg_virt(data->sg);
119 if (!nodma)
120 printk(KERN_DEBUG "%s: fallback to PIO for data "
121 "at 0x%p size %d\n",
122 mmc_hostname(host->mmc),
123 host->pio_ptr, host->pio_size);
124 return 1;
125 } else {
126 dma_addr_t phys_addr;
127 int dma_dir = (data->flags & MMC_DATA_READ) ?
128 DMA_FROM_DEVICE : DMA_TO_DEVICE;
129 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
130 data->sg_len, dma_dir);
131 phys_addr = sg_dma_address(data->sg);
132 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
133 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
134 return 0;
135 }
136}
137
138static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
139{
140 struct mvsd_host *host = mmc_priv(mmc);
141 void __iomem *iobase = host->base;
142 struct mmc_command *cmd = mrq->cmd;
143 u32 cmdreg = 0, xfer = 0, intr = 0;
144 unsigned long flags;
145
146 BUG_ON(host->mrq != NULL);
147 host->mrq = mrq;
148
149 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
150 cmd->opcode, mvsd_read(MVSD_HW_STATE));
151
152 cmdreg = MVSD_CMD_INDEX(cmd->opcode);
153
154 if (cmd->flags & MMC_RSP_BUSY)
155 cmdreg |= MVSD_CMD_RSP_48BUSY;
156 else if (cmd->flags & MMC_RSP_136)
157 cmdreg |= MVSD_CMD_RSP_136;
158 else if (cmd->flags & MMC_RSP_PRESENT)
159 cmdreg |= MVSD_CMD_RSP_48;
160 else
161 cmdreg |= MVSD_CMD_RSP_NONE;
162
163 if (cmd->flags & MMC_RSP_CRC)
164 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
165
166 if (cmd->flags & MMC_RSP_OPCODE)
167 cmdreg |= MVSD_CMD_INDX_CHECK;
168
169 if (cmd->flags & MMC_RSP_PRESENT) {
170 cmdreg |= MVSD_UNEXPECTED_RESP;
171 intr |= MVSD_NOR_UNEXP_RSP;
172 }
173
174 if (mrq->data) {
175 struct mmc_data *data = mrq->data;
176 int pio;
177
178 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
179 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
180 if (data->flags & MMC_DATA_READ)
181 xfer |= MVSD_XFER_MODE_TO_HOST;
182
183 pio = mvsd_setup_data(host, data);
184 if (pio) {
185 xfer |= MVSD_XFER_MODE_PIO;
186 /* PIO section of mvsd_irq has comments on those bits */
187 if (data->flags & MMC_DATA_WRITE)
188 intr |= MVSD_NOR_TX_AVAIL;
189 else if (host->pio_size > 32)
190 intr |= MVSD_NOR_RX_FIFO_8W;
191 else
192 intr |= MVSD_NOR_RX_READY;
193 }
194
195 if (data->stop) {
196 struct mmc_command *stop = data->stop;
197 u32 cmd12reg = 0;
198
199 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
200 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
201
202 if (stop->flags & MMC_RSP_BUSY)
203 cmd12reg |= MVSD_AUTOCMD12_BUSY;
204 if (stop->flags & MMC_RSP_OPCODE)
205 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
206 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
207 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
208
209 xfer |= MVSD_XFER_MODE_AUTO_CMD12;
210 intr |= MVSD_NOR_AUTOCMD12_DONE;
211 } else {
212 intr |= MVSD_NOR_XFER_DONE;
213 }
214 } else {
215 intr |= MVSD_NOR_CMD_DONE;
216 }
217
218 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
219 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
220
221 spin_lock_irqsave(&host->lock, flags);
222
223 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
224 host->xfer_mode |= xfer;
225 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
226
227 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
228 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
229 mvsd_write(MVSD_CMD, cmdreg);
230
231 host->intr_en &= MVSD_NOR_CARD_INT;
232 host->intr_en |= intr | MVSD_NOR_ERROR;
233 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
234 mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
235
236 mod_timer(&host->timer, jiffies + 5 * HZ);
237
238 spin_unlock_irqrestore(&host->lock, flags);
239}
240
241static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
242 u32 err_status)
243{
244 void __iomem *iobase = host->base;
245
246 if (cmd->flags & MMC_RSP_136) {
247 unsigned int response[8], i;
248 for (i = 0; i < 8; i++)
249 response[i] = mvsd_read(MVSD_RSP(i));
250 cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
251 ((response[1] & 0xffff) << 6) |
252 ((response[2] & 0xfc00) >> 10);
253 cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
254 ((response[3] & 0xffff) << 6) |
255 ((response[4] & 0xfc00) >> 10);
256 cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
257 ((response[5] & 0xffff) << 6) |
258 ((response[6] & 0xfc00) >> 10);
259 cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
260 ((response[7] & 0x3fff) << 8);
261 } else if (cmd->flags & MMC_RSP_PRESENT) {
262 unsigned int response[3], i;
263 for (i = 0; i < 3; i++)
264 response[i] = mvsd_read(MVSD_RSP(i));
265 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
266 ((response[1] & 0xffff) << (14 - 8)) |
267 ((response[0] & 0x03ff) << (30 - 8));
268 cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
269 cmd->resp[2] = 0;
270 cmd->resp[3] = 0;
271 }
272
273 if (err_status & MVSD_ERR_CMD_TIMEOUT) {
274 cmd->error = -ETIMEDOUT;
275 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
276 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
277 cmd->error = -EILSEQ;
278 }
279 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
280 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
281 MVSD_ERR_CMD_STARTBIT);
282
283 return err_status;
284}
285
286static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
287 u32 err_status)
288{
289 void __iomem *iobase = host->base;
290
291 if (host->pio_ptr) {
292 host->pio_ptr = NULL;
293 host->pio_size = 0;
294 } else {
295 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
296 (data->flags & MMC_DATA_READ) ?
297 DMA_FROM_DEVICE : DMA_TO_DEVICE);
298 }
299
300 if (err_status & MVSD_ERR_DATA_TIMEOUT)
301 data->error = -ETIMEDOUT;
302 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
303 data->error = -EILSEQ;
304 else if (err_status & MVSD_ERR_XFER_SIZE)
305 data->error = -EBADE;
306 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
307 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
308
309 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
310 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
311 data->bytes_xfered =
312 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
313 /* We can't be sure about the last block when errors are detected */
314 if (data->bytes_xfered && data->error)
315 data->bytes_xfered -= data->blksz;
316
317 /* Handle Auto cmd 12 response */
318 if (data->stop) {
319 unsigned int response[3], i;
320 for (i = 0; i < 3; i++)
321 response[i] = mvsd_read(MVSD_AUTO_RSP(i));
322 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
323 ((response[1] & 0xffff) << (14 - 8)) |
324 ((response[0] & 0x03ff) << (30 - 8));
325 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
326 data->stop->resp[2] = 0;
327 data->stop->resp[3] = 0;
328
329 if (err_status & MVSD_ERR_AUTOCMD12) {
330 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
331 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
332 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
333 data->stop->error = -ENOEXEC;
334 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
335 data->stop->error = -ETIMEDOUT;
336 else if (err_cmd12)
337 data->stop->error = -EILSEQ;
338 err_status &= ~MVSD_ERR_AUTOCMD12;
339 }
340 }
341
342 return err_status;
343}
344
345static irqreturn_t mvsd_irq(int irq, void *dev)
346{
347 struct mvsd_host *host = dev;
348 void __iomem *iobase = host->base;
349 u32 intr_status, intr_done_mask;
350 int irq_handled = 0;
351
352 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
353 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
354 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
355 mvsd_read(MVSD_HW_STATE));
356
357 spin_lock(&host->lock);
358
359 /* PIO handling, if needed. Messy business... */
360 if (host->pio_size &&
361 (intr_status & host->intr_en &
362 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
363 u16 *p = host->pio_ptr;
364 int s = host->pio_size;
365 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
366 readsw(iobase + MVSD_FIFO, p, 16);
367 p += 16;
368 s -= 32;
369 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
370 }
371 /*
372 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
373 * doesn't appear to assert when there is exactly 32 bytes
374 * (8 words) left to fetch in a transfer.
375 */
376 if (s <= 32) {
377 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
378 put_unaligned(mvsd_read(MVSD_FIFO), p++);
379 put_unaligned(mvsd_read(MVSD_FIFO), p++);
380 s -= 4;
381 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
382 }
383 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
384 u16 val[2] = {0, 0};
385 val[0] = mvsd_read(MVSD_FIFO);
386 val[1] = mvsd_read(MVSD_FIFO);
387 memcpy(p, ((void *)&val) + 4 - s, s);
388 s = 0;
389 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
390 }
391 if (s == 0) {
392 host->intr_en &=
393 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
394 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
395 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
396 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
397 host->intr_en |= MVSD_NOR_RX_READY;
398 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
399 }
400 }
401 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
402 s, intr_status, mvsd_read(MVSD_HW_STATE));
403 host->pio_ptr = p;
404 host->pio_size = s;
405 irq_handled = 1;
406 } else if (host->pio_size &&
407 (intr_status & host->intr_en &
408 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
409 u16 *p = host->pio_ptr;
410 int s = host->pio_size;
411 /*
412 * The TX_FIFO_8W bit is unreliable. When set, bursting
413 * 16 halfwords all at once in the FIFO drops data. Actually
414 * TX_AVAIL does go off after only one word is pushed even if
415 * TX_FIFO_8W remains set.
416 */
417 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
418 mvsd_write(MVSD_FIFO, get_unaligned(p++));
419 mvsd_write(MVSD_FIFO, get_unaligned(p++));
420 s -= 4;
421 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
422 }
423 if (s < 4) {
424 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
425 u16 val[2] = {0, 0};
426 memcpy(((void *)&val) + 4 - s, p, s);
427 mvsd_write(MVSD_FIFO, val[0]);
428 mvsd_write(MVSD_FIFO, val[1]);
429 s = 0;
430 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
431 }
432 if (s == 0) {
433 host->intr_en &=
434 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
435 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
436 }
437 }
438 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
439 s, intr_status, mvsd_read(MVSD_HW_STATE));
440 host->pio_ptr = p;
441 host->pio_size = s;
442 irq_handled = 1;
443 }
444
445 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
446
447 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
448 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
449 if (intr_status & host->intr_en & ~intr_done_mask) {
450 struct mmc_request *mrq = host->mrq;
451 struct mmc_command *cmd = mrq->cmd;
452 u32 err_status = 0;
453
454 del_timer(&host->timer);
455 host->mrq = NULL;
456
457 host->intr_en &= MVSD_NOR_CARD_INT;
458 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
459 mvsd_write(MVSD_ERR_INTR_EN, 0);
460
461 spin_unlock(&host->lock);
462
463 if (intr_status & MVSD_NOR_UNEXP_RSP) {
464 cmd->error = -EPROTO;
465 } else if (intr_status & MVSD_NOR_ERROR) {
466 err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
467 dev_dbg(host->dev, "err 0x%04x\n", err_status);
468 }
469
470 err_status = mvsd_finish_cmd(host, cmd, err_status);
471 if (mrq->data)
472 err_status = mvsd_finish_data(host, mrq->data, err_status);
473 if (err_status) {
474 printk(KERN_ERR "%s: unhandled error status %#04x\n",
475 mmc_hostname(host->mmc), err_status);
476 cmd->error = -ENOMSG;
477 }
478
479 mmc_request_done(host->mmc, mrq);
480 irq_handled = 1;
481 } else
482 spin_unlock(&host->lock);
483
484 if (intr_status & MVSD_NOR_CARD_INT) {
485 mmc_signal_sdio_irq(host->mmc);
486 irq_handled = 1;
487 }
488
489 if (irq_handled)
490 return IRQ_HANDLED;
491
492 printk(KERN_ERR "%s: unhandled interrupt status=0x%04x en=0x%04x "
493 "pio=%d\n", mmc_hostname(host->mmc), intr_status,
494 host->intr_en, host->pio_size);
495 return IRQ_NONE;
496}
497
498static void mvsd_timeout_timer(unsigned long data)
499{
500 struct mvsd_host *host = (struct mvsd_host *)data;
501 void __iomem *iobase = host->base;
502 struct mmc_request *mrq;
503 unsigned long flags;
504
505 spin_lock_irqsave(&host->lock, flags);
506 mrq = host->mrq;
507 if (mrq) {
508 printk(KERN_ERR "%s: Timeout waiting for hardware interrupt.\n",
509 mmc_hostname(host->mmc));
510 printk(KERN_ERR "%s: hw_state=0x%04x, intr_status=0x%04x "
511 "intr_en=0x%04x\n", mmc_hostname(host->mmc),
512 mvsd_read(MVSD_HW_STATE),
513 mvsd_read(MVSD_NOR_INTR_STATUS),
514 mvsd_read(MVSD_NOR_INTR_EN));
515
516 host->mrq = NULL;
517
518 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
519
520 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
521 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
522
523 host->intr_en &= MVSD_NOR_CARD_INT;
524 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
525 mvsd_write(MVSD_ERR_INTR_EN, 0);
526 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
527
528 mrq->cmd->error = -ETIMEDOUT;
529 mvsd_finish_cmd(host, mrq->cmd, 0);
530 if (mrq->data) {
531 mrq->data->error = -ETIMEDOUT;
532 mvsd_finish_data(host, mrq->data, 0);
533 }
534 }
535 spin_unlock_irqrestore(&host->lock, flags);
536
537 if (mrq)
538 mmc_request_done(host->mmc, mrq);
539}
540
541static irqreturn_t mvsd_card_detect_irq(int irq, void *dev)
542{
543 struct mvsd_host *host = dev;
544 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
545 return IRQ_HANDLED;
546}
547
548static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
549{
550 struct mvsd_host *host = mmc_priv(mmc);
551 void __iomem *iobase = host->base;
552 unsigned long flags;
553
554 spin_lock_irqsave(&host->lock, flags);
555 if (enable) {
556 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
557 host->intr_en |= MVSD_NOR_CARD_INT;
558 } else {
559 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
560 host->intr_en &= ~MVSD_NOR_CARD_INT;
561 }
562 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
563 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
564 spin_unlock_irqrestore(&host->lock, flags);
565}
566
567static int mvsd_get_ro(struct mmc_host *mmc)
568{
569 struct mvsd_host *host = mmc_priv(mmc);
570
571 if (host->gpio_write_protect)
572 return gpio_get_value(host->gpio_write_protect);
573
574 /*
575 * Board doesn't support read only detection; let the mmc core
576 * decide what to do.
577 */
578 return -ENOSYS;
579}
580
581static void mvsd_power_up(struct mvsd_host *host)
582{
583 void __iomem *iobase = host->base;
584 dev_dbg(host->dev, "power up\n");
585 mvsd_write(MVSD_NOR_INTR_EN, 0);
586 mvsd_write(MVSD_ERR_INTR_EN, 0);
587 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
588 mvsd_write(MVSD_XFER_MODE, 0);
589 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
590 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
591 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
592 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
593}
594
595static void mvsd_power_down(struct mvsd_host *host)
596{
597 void __iomem *iobase = host->base;
598 dev_dbg(host->dev, "power down\n");
599 mvsd_write(MVSD_NOR_INTR_EN, 0);
600 mvsd_write(MVSD_ERR_INTR_EN, 0);
601 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
602 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
603 mvsd_write(MVSD_NOR_STATUS_EN, 0);
604 mvsd_write(MVSD_ERR_STATUS_EN, 0);
605 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
606 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
607}
608
609static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
610{
611 struct mvsd_host *host = mmc_priv(mmc);
612 void __iomem *iobase = host->base;
613 u32 ctrl_reg = 0;
614
615 if (ios->power_mode == MMC_POWER_UP)
616 mvsd_power_up(host);
617
618 if (ios->clock == 0) {
619 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
620 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
621 host->clock = 0;
622 dev_dbg(host->dev, "clock off\n");
623 } else if (ios->clock != host->clock) {
624 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
625 if (m > MVSD_BASE_DIV_MAX)
626 m = MVSD_BASE_DIV_MAX;
627 mvsd_write(MVSD_CLK_DIV, m);
628 host->clock = ios->clock;
629 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
630 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
631 ios->clock, host->base_clock / (m+1), m);
632 }
633
634 /* default transfer mode */
635 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
636 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
637
638 /* default to maximum timeout */
639 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
640 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
641
642 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
643 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
644
645 if (ios->bus_width == MMC_BUS_WIDTH_4)
646 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
647
648 /*
649 * The HI_SPEED_EN bit is causing trouble with many (but not all)
650 * high speed SD, SDHC and SDIO cards. Not enabling that bit
651 * makes all cards work. So let's just ignore that bit for now
652 * and revisit this issue if problems for not enabling this bit
653 * are ever reported.
654 */
655#if 0
656 if (ios->timing == MMC_TIMING_MMC_HS ||
657 ios->timing == MMC_TIMING_SD_HS)
658 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
659#endif
660
661 host->ctrl = ctrl_reg;
662 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
663 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
664 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
665 "push-pull" : "open-drain",
666 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
667 "4bit-width" : "1bit-width",
668 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
669 "high-speed" : "");
670
671 if (ios->power_mode == MMC_POWER_OFF)
672 mvsd_power_down(host);
673}
674
675static const struct mmc_host_ops mvsd_ops = {
676 .request = mvsd_request,
677 .get_ro = mvsd_get_ro,
678 .set_ios = mvsd_set_ios,
679 .enable_sdio_irq = mvsd_enable_sdio_irq,
680};
681
682static void __init mv_conf_mbus_windows(struct mvsd_host *host,
683 struct mbus_dram_target_info *dram)
684{
685 void __iomem *iobase = host->base;
686 int i;
687
688 for (i = 0; i < 4; i++) {
689 writel(0, iobase + MVSD_WINDOW_CTRL(i));
690 writel(0, iobase + MVSD_WINDOW_BASE(i));
691 }
692
693 for (i = 0; i < dram->num_cs; i++) {
694 struct mbus_dram_window *cs = dram->cs + i;
695 writel(((cs->size - 1) & 0xffff0000) |
696 (cs->mbus_attr << 8) |
697 (dram->mbus_dram_target_id << 4) | 1,
698 iobase + MVSD_WINDOW_CTRL(i));
699 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
700 }
701}
702
703static int __init mvsd_probe(struct platform_device *pdev)
704{
705 struct mmc_host *mmc = NULL;
706 struct mvsd_host *host = NULL;
707 const struct mvsdio_platform_data *mvsd_data;
708 struct resource *r;
709 int ret, irq;
710
711 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
712 irq = platform_get_irq(pdev, 0);
713 mvsd_data = pdev->dev.platform_data;
714 if (!r || irq < 0 || !mvsd_data)
715 return -ENXIO;
716
717 r = request_mem_region(r->start, SZ_1K, DRIVER_NAME);
718 if (!r)
719 return -EBUSY;
720
721 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
722 if (!mmc) {
723 ret = -ENOMEM;
724 goto out;
725 }
726
727 host = mmc_priv(mmc);
728 host->mmc = mmc;
729 host->dev = &pdev->dev;
730 host->res = r;
731 host->base_clock = mvsd_data->clock / 2;
732
733 mmc->ops = &mvsd_ops;
734
735 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
736 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
737 MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
738
739 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
740 mmc->f_max = maxfreq;
741
742 mmc->max_blk_size = 2048;
743 mmc->max_blk_count = 65535;
744
745 mmc->max_segs = 1;
746 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
747 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
748
749 spin_lock_init(&host->lock);
750
751 host->base = ioremap(r->start, SZ_4K);
752 if (!host->base) {
753 ret = -ENOMEM;
754 goto out;
755 }
756
757 /* (Re-)program MBUS remapping windows if we are asked to. */
758 if (mvsd_data->dram != NULL)
759 mv_conf_mbus_windows(host, mvsd_data->dram);
760
761 mvsd_power_down(host);
762
763 ret = request_irq(irq, mvsd_irq, 0, DRIVER_NAME, host);
764 if (ret) {
765 printk(KERN_ERR "%s: cannot assign irq %d\n", DRIVER_NAME, irq);
766 goto out;
767 } else
768 host->irq = irq;
769
770 if (mvsd_data->gpio_card_detect) {
771 ret = gpio_request(mvsd_data->gpio_card_detect,
772 DRIVER_NAME " cd");
773 if (ret == 0) {
774 gpio_direction_input(mvsd_data->gpio_card_detect);
775 irq = gpio_to_irq(mvsd_data->gpio_card_detect);
776 ret = request_irq(irq, mvsd_card_detect_irq,
777 IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING,
778 DRIVER_NAME " cd", host);
779 if (ret == 0)
780 host->gpio_card_detect =
781 mvsd_data->gpio_card_detect;
782 else
783 gpio_free(mvsd_data->gpio_card_detect);
784 }
785 }
786 if (!host->gpio_card_detect)
787 mmc->caps |= MMC_CAP_NEEDS_POLL;
788
789 if (mvsd_data->gpio_write_protect) {
790 ret = gpio_request(mvsd_data->gpio_write_protect,
791 DRIVER_NAME " wp");
792 if (ret == 0) {
793 gpio_direction_input(mvsd_data->gpio_write_protect);
794 host->gpio_write_protect =
795 mvsd_data->gpio_write_protect;
796 }
797 }
798
799 setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
800 platform_set_drvdata(pdev, mmc);
801 ret = mmc_add_host(mmc);
802 if (ret)
803 goto out;
804
805 printk(KERN_NOTICE "%s: %s driver initialized, ",
806 mmc_hostname(mmc), DRIVER_NAME);
807 if (host->gpio_card_detect)
808 printk("using GPIO %d for card detection\n",
809 host->gpio_card_detect);
810 else
811 printk("lacking card detect (fall back to polling)\n");
812 return 0;
813
814out:
815 if (host) {
816 if (host->irq)
817 free_irq(host->irq, host);
818 if (host->gpio_card_detect) {
819 free_irq(gpio_to_irq(host->gpio_card_detect), host);
820 gpio_free(host->gpio_card_detect);
821 }
822 if (host->gpio_write_protect)
823 gpio_free(host->gpio_write_protect);
824 if (host->base)
825 iounmap(host->base);
826 }
827 if (r)
828 release_resource(r);
829 if (mmc)
830 mmc_free_host(mmc);
831
832 return ret;
833}
834
835static int __exit mvsd_remove(struct platform_device *pdev)
836{
837 struct mmc_host *mmc = platform_get_drvdata(pdev);
838
839 if (mmc) {
840 struct mvsd_host *host = mmc_priv(mmc);
841
842 if (host->gpio_card_detect) {
843 free_irq(gpio_to_irq(host->gpio_card_detect), host);
844 gpio_free(host->gpio_card_detect);
845 }
846 mmc_remove_host(mmc);
847 free_irq(host->irq, host);
848 if (host->gpio_write_protect)
849 gpio_free(host->gpio_write_protect);
850 del_timer_sync(&host->timer);
851 mvsd_power_down(host);
852 iounmap(host->base);
853 release_resource(host->res);
854 mmc_free_host(mmc);
855 }
856 platform_set_drvdata(pdev, NULL);
857 return 0;
858}
859
860#ifdef CONFIG_PM
861static int mvsd_suspend(struct platform_device *dev, pm_message_t state)
862{
863 struct mmc_host *mmc = platform_get_drvdata(dev);
864 int ret = 0;
865
866 if (mmc)
867 ret = mmc_suspend_host(mmc);
868
869 return ret;
870}
871
872static int mvsd_resume(struct platform_device *dev)
873{
874 struct mmc_host *mmc = platform_get_drvdata(dev);
875 int ret = 0;
876
877 if (mmc)
878 ret = mmc_resume_host(mmc);
879
880 return ret;
881}
882#else
883#define mvsd_suspend NULL
884#define mvsd_resume NULL
885#endif
886
887static struct platform_driver mvsd_driver = {
888 .remove = __exit_p(mvsd_remove),
889 .suspend = mvsd_suspend,
890 .resume = mvsd_resume,
891 .driver = {
892 .name = DRIVER_NAME,
893 },
894};
895
896static int __init mvsd_init(void)
897{
898 return platform_driver_probe(&mvsd_driver, mvsd_probe);
899}
900
901static void __exit mvsd_exit(void)
902{
903 platform_driver_unregister(&mvsd_driver);
904}
905
906module_init(mvsd_init);
907module_exit(mvsd_exit);
908
909/* maximum card clock frequency (default 50MHz) */
910module_param(maxfreq, int, 0);
911
912/* force PIO transfers all the time */
913module_param(nodma, int, 0);
914
915MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
916MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
917MODULE_LICENSE("GPL");
918MODULE_ALIAS("platform:mvsdio");
1/*
2 * Marvell MMC/SD/SDIO driver
3 *
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/mbus.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/scatterlist.h>
21#include <linux/irq.h>
22#include <linux/clk.h>
23#include <linux/of_irq.h>
24#include <linux/mmc/host.h>
25#include <linux/mmc/slot-gpio.h>
26
27#include <asm/sizes.h>
28#include <asm/unaligned.h>
29
30#include "mvsdio.h"
31
32#define DRIVER_NAME "mvsdio"
33
34static int maxfreq;
35static int nodma;
36
37struct mvsd_host {
38 void __iomem *base;
39 struct mmc_request *mrq;
40 spinlock_t lock;
41 unsigned int xfer_mode;
42 unsigned int intr_en;
43 unsigned int ctrl;
44 unsigned int pio_size;
45 void *pio_ptr;
46 unsigned int sg_frags;
47 unsigned int ns_per_clk;
48 unsigned int clock;
49 unsigned int base_clock;
50 struct timer_list timer;
51 struct mmc_host *mmc;
52 struct device *dev;
53 struct clk *clk;
54};
55
56#define mvsd_write(offs, val) writel(val, iobase + (offs))
57#define mvsd_read(offs) readl(iobase + (offs))
58
59static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
60{
61 void __iomem *iobase = host->base;
62 unsigned int tmout;
63 int tmout_index;
64
65 /*
66 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
67 * register is sometimes not set before a while when some
68 * "unusual" data block sizes are used (such as with the SWITCH
69 * command), even despite the fact that the XFER_DONE interrupt
70 * was raised. And if another data transfer starts before
71 * this bit comes to good sense (which eventually happens by
72 * itself) then the new transfer simply fails with a timeout.
73 */
74 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
75 unsigned long t = jiffies + HZ;
76 unsigned int hw_state, count = 0;
77 do {
78 hw_state = mvsd_read(MVSD_HW_STATE);
79 if (time_after(jiffies, t)) {
80 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
81 break;
82 }
83 count++;
84 } while (!(hw_state & (1 << 13)));
85 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
86 "(hw=0x%04x, count=%d, jiffies=%ld)\n",
87 hw_state, count, jiffies - (t - HZ));
88 }
89
90 /* If timeout=0 then maximum timeout index is used. */
91 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
92 tmout += data->timeout_clks;
93 tmout_index = fls(tmout - 1) - 12;
94 if (tmout_index < 0)
95 tmout_index = 0;
96 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
97 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
98
99 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
100 (data->flags & MMC_DATA_READ) ? "read" : "write",
101 (u32)sg_virt(data->sg), data->blocks, data->blksz,
102 tmout, tmout_index);
103
104 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
105 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
106 mvsd_write(MVSD_HOST_CTRL, host->ctrl);
107 mvsd_write(MVSD_BLK_COUNT, data->blocks);
108 mvsd_write(MVSD_BLK_SIZE, data->blksz);
109
110 if (nodma || (data->blksz | data->sg->offset) & 3 ||
111 ((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) {
112 /*
113 * We cannot do DMA on a buffer which offset or size
114 * is not aligned on a 4-byte boundary.
115 *
116 * It also appears the host to card DMA can corrupt
117 * data when the buffer is not aligned on a 64 byte
118 * boundary.
119 */
120 host->pio_size = data->blocks * data->blksz;
121 host->pio_ptr = sg_virt(data->sg);
122 if (!nodma)
123 dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n",
124 host->pio_ptr, host->pio_size);
125 return 1;
126 } else {
127 dma_addr_t phys_addr;
128
129 host->sg_frags = dma_map_sg(mmc_dev(host->mmc),
130 data->sg, data->sg_len,
131 mmc_get_dma_dir(data));
132 phys_addr = sg_dma_address(data->sg);
133 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
134 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
135 return 0;
136 }
137}
138
139static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
140{
141 struct mvsd_host *host = mmc_priv(mmc);
142 void __iomem *iobase = host->base;
143 struct mmc_command *cmd = mrq->cmd;
144 u32 cmdreg = 0, xfer = 0, intr = 0;
145 unsigned long flags;
146
147 BUG_ON(host->mrq != NULL);
148 host->mrq = mrq;
149
150 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
151 cmd->opcode, mvsd_read(MVSD_HW_STATE));
152
153 cmdreg = MVSD_CMD_INDEX(cmd->opcode);
154
155 if (cmd->flags & MMC_RSP_BUSY)
156 cmdreg |= MVSD_CMD_RSP_48BUSY;
157 else if (cmd->flags & MMC_RSP_136)
158 cmdreg |= MVSD_CMD_RSP_136;
159 else if (cmd->flags & MMC_RSP_PRESENT)
160 cmdreg |= MVSD_CMD_RSP_48;
161 else
162 cmdreg |= MVSD_CMD_RSP_NONE;
163
164 if (cmd->flags & MMC_RSP_CRC)
165 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
166
167 if (cmd->flags & MMC_RSP_OPCODE)
168 cmdreg |= MVSD_CMD_INDX_CHECK;
169
170 if (cmd->flags & MMC_RSP_PRESENT) {
171 cmdreg |= MVSD_UNEXPECTED_RESP;
172 intr |= MVSD_NOR_UNEXP_RSP;
173 }
174
175 if (mrq->data) {
176 struct mmc_data *data = mrq->data;
177 int pio;
178
179 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
180 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
181 if (data->flags & MMC_DATA_READ)
182 xfer |= MVSD_XFER_MODE_TO_HOST;
183
184 pio = mvsd_setup_data(host, data);
185 if (pio) {
186 xfer |= MVSD_XFER_MODE_PIO;
187 /* PIO section of mvsd_irq has comments on those bits */
188 if (data->flags & MMC_DATA_WRITE)
189 intr |= MVSD_NOR_TX_AVAIL;
190 else if (host->pio_size > 32)
191 intr |= MVSD_NOR_RX_FIFO_8W;
192 else
193 intr |= MVSD_NOR_RX_READY;
194 }
195
196 if (data->stop) {
197 struct mmc_command *stop = data->stop;
198 u32 cmd12reg = 0;
199
200 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
201 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
202
203 if (stop->flags & MMC_RSP_BUSY)
204 cmd12reg |= MVSD_AUTOCMD12_BUSY;
205 if (stop->flags & MMC_RSP_OPCODE)
206 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
207 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
208 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
209
210 xfer |= MVSD_XFER_MODE_AUTO_CMD12;
211 intr |= MVSD_NOR_AUTOCMD12_DONE;
212 } else {
213 intr |= MVSD_NOR_XFER_DONE;
214 }
215 } else {
216 intr |= MVSD_NOR_CMD_DONE;
217 }
218
219 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
220 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
221
222 spin_lock_irqsave(&host->lock, flags);
223
224 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
225 host->xfer_mode |= xfer;
226 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
227
228 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
229 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
230 mvsd_write(MVSD_CMD, cmdreg);
231
232 host->intr_en &= MVSD_NOR_CARD_INT;
233 host->intr_en |= intr | MVSD_NOR_ERROR;
234 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
235 mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
236
237 mod_timer(&host->timer, jiffies + 5 * HZ);
238
239 spin_unlock_irqrestore(&host->lock, flags);
240}
241
242static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
243 u32 err_status)
244{
245 void __iomem *iobase = host->base;
246
247 if (cmd->flags & MMC_RSP_136) {
248 unsigned int response[8], i;
249 for (i = 0; i < 8; i++)
250 response[i] = mvsd_read(MVSD_RSP(i));
251 cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
252 ((response[1] & 0xffff) << 6) |
253 ((response[2] & 0xfc00) >> 10);
254 cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
255 ((response[3] & 0xffff) << 6) |
256 ((response[4] & 0xfc00) >> 10);
257 cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
258 ((response[5] & 0xffff) << 6) |
259 ((response[6] & 0xfc00) >> 10);
260 cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
261 ((response[7] & 0x3fff) << 8);
262 } else if (cmd->flags & MMC_RSP_PRESENT) {
263 unsigned int response[3], i;
264 for (i = 0; i < 3; i++)
265 response[i] = mvsd_read(MVSD_RSP(i));
266 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
267 ((response[1] & 0xffff) << (14 - 8)) |
268 ((response[0] & 0x03ff) << (30 - 8));
269 cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
270 cmd->resp[2] = 0;
271 cmd->resp[3] = 0;
272 }
273
274 if (err_status & MVSD_ERR_CMD_TIMEOUT) {
275 cmd->error = -ETIMEDOUT;
276 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
277 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
278 cmd->error = -EILSEQ;
279 }
280 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
281 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
282 MVSD_ERR_CMD_STARTBIT);
283
284 return err_status;
285}
286
287static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
288 u32 err_status)
289{
290 void __iomem *iobase = host->base;
291
292 if (host->pio_ptr) {
293 host->pio_ptr = NULL;
294 host->pio_size = 0;
295 } else {
296 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
297 mmc_get_dma_dir(data));
298 }
299
300 if (err_status & MVSD_ERR_DATA_TIMEOUT)
301 data->error = -ETIMEDOUT;
302 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
303 data->error = -EILSEQ;
304 else if (err_status & MVSD_ERR_XFER_SIZE)
305 data->error = -EBADE;
306 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
307 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
308
309 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
310 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
311 data->bytes_xfered =
312 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
313 /* We can't be sure about the last block when errors are detected */
314 if (data->bytes_xfered && data->error)
315 data->bytes_xfered -= data->blksz;
316
317 /* Handle Auto cmd 12 response */
318 if (data->stop) {
319 unsigned int response[3], i;
320 for (i = 0; i < 3; i++)
321 response[i] = mvsd_read(MVSD_AUTO_RSP(i));
322 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
323 ((response[1] & 0xffff) << (14 - 8)) |
324 ((response[0] & 0x03ff) << (30 - 8));
325 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
326 data->stop->resp[2] = 0;
327 data->stop->resp[3] = 0;
328
329 if (err_status & MVSD_ERR_AUTOCMD12) {
330 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
331 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
332 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
333 data->stop->error = -ENOEXEC;
334 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
335 data->stop->error = -ETIMEDOUT;
336 else if (err_cmd12)
337 data->stop->error = -EILSEQ;
338 err_status &= ~MVSD_ERR_AUTOCMD12;
339 }
340 }
341
342 return err_status;
343}
344
345static irqreturn_t mvsd_irq(int irq, void *dev)
346{
347 struct mvsd_host *host = dev;
348 void __iomem *iobase = host->base;
349 u32 intr_status, intr_done_mask;
350 int irq_handled = 0;
351
352 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
353 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
354 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
355 mvsd_read(MVSD_HW_STATE));
356
357 /*
358 * It looks like, SDIO IP can issue one late, spurious irq
359 * although all irqs should be disabled. To work around this,
360 * bail out early, if we didn't expect any irqs to occur.
361 */
362 if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) {
363 dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n",
364 mvsd_read(MVSD_NOR_INTR_STATUS),
365 mvsd_read(MVSD_NOR_INTR_EN),
366 mvsd_read(MVSD_ERR_INTR_STATUS),
367 mvsd_read(MVSD_ERR_INTR_EN));
368 return IRQ_HANDLED;
369 }
370
371 spin_lock(&host->lock);
372
373 /* PIO handling, if needed. Messy business... */
374 if (host->pio_size &&
375 (intr_status & host->intr_en &
376 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
377 u16 *p = host->pio_ptr;
378 int s = host->pio_size;
379 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
380 readsw(iobase + MVSD_FIFO, p, 16);
381 p += 16;
382 s -= 32;
383 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
384 }
385 /*
386 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
387 * doesn't appear to assert when there is exactly 32 bytes
388 * (8 words) left to fetch in a transfer.
389 */
390 if (s <= 32) {
391 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
392 put_unaligned(mvsd_read(MVSD_FIFO), p++);
393 put_unaligned(mvsd_read(MVSD_FIFO), p++);
394 s -= 4;
395 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
396 }
397 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
398 u16 val[2] = {0, 0};
399 val[0] = mvsd_read(MVSD_FIFO);
400 val[1] = mvsd_read(MVSD_FIFO);
401 memcpy(p, ((void *)&val) + 4 - s, s);
402 s = 0;
403 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
404 }
405 if (s == 0) {
406 host->intr_en &=
407 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
408 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
409 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
410 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
411 host->intr_en |= MVSD_NOR_RX_READY;
412 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
413 }
414 }
415 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
416 s, intr_status, mvsd_read(MVSD_HW_STATE));
417 host->pio_ptr = p;
418 host->pio_size = s;
419 irq_handled = 1;
420 } else if (host->pio_size &&
421 (intr_status & host->intr_en &
422 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
423 u16 *p = host->pio_ptr;
424 int s = host->pio_size;
425 /*
426 * The TX_FIFO_8W bit is unreliable. When set, bursting
427 * 16 halfwords all at once in the FIFO drops data. Actually
428 * TX_AVAIL does go off after only one word is pushed even if
429 * TX_FIFO_8W remains set.
430 */
431 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
432 mvsd_write(MVSD_FIFO, get_unaligned(p++));
433 mvsd_write(MVSD_FIFO, get_unaligned(p++));
434 s -= 4;
435 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
436 }
437 if (s < 4) {
438 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
439 u16 val[2] = {0, 0};
440 memcpy(((void *)&val) + 4 - s, p, s);
441 mvsd_write(MVSD_FIFO, val[0]);
442 mvsd_write(MVSD_FIFO, val[1]);
443 s = 0;
444 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
445 }
446 if (s == 0) {
447 host->intr_en &=
448 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
449 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
450 }
451 }
452 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
453 s, intr_status, mvsd_read(MVSD_HW_STATE));
454 host->pio_ptr = p;
455 host->pio_size = s;
456 irq_handled = 1;
457 }
458
459 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
460
461 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
462 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
463 if (intr_status & host->intr_en & ~intr_done_mask) {
464 struct mmc_request *mrq = host->mrq;
465 struct mmc_command *cmd = mrq->cmd;
466 u32 err_status = 0;
467
468 del_timer(&host->timer);
469 host->mrq = NULL;
470
471 host->intr_en &= MVSD_NOR_CARD_INT;
472 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
473 mvsd_write(MVSD_ERR_INTR_EN, 0);
474
475 spin_unlock(&host->lock);
476
477 if (intr_status & MVSD_NOR_UNEXP_RSP) {
478 cmd->error = -EPROTO;
479 } else if (intr_status & MVSD_NOR_ERROR) {
480 err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
481 dev_dbg(host->dev, "err 0x%04x\n", err_status);
482 }
483
484 err_status = mvsd_finish_cmd(host, cmd, err_status);
485 if (mrq->data)
486 err_status = mvsd_finish_data(host, mrq->data, err_status);
487 if (err_status) {
488 dev_err(host->dev, "unhandled error status %#04x\n",
489 err_status);
490 cmd->error = -ENOMSG;
491 }
492
493 mmc_request_done(host->mmc, mrq);
494 irq_handled = 1;
495 } else
496 spin_unlock(&host->lock);
497
498 if (intr_status & MVSD_NOR_CARD_INT) {
499 mmc_signal_sdio_irq(host->mmc);
500 irq_handled = 1;
501 }
502
503 if (irq_handled)
504 return IRQ_HANDLED;
505
506 dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n",
507 intr_status, host->intr_en, host->pio_size);
508 return IRQ_NONE;
509}
510
511static void mvsd_timeout_timer(struct timer_list *t)
512{
513 struct mvsd_host *host = from_timer(host, t, timer);
514 void __iomem *iobase = host->base;
515 struct mmc_request *mrq;
516 unsigned long flags;
517
518 spin_lock_irqsave(&host->lock, flags);
519 mrq = host->mrq;
520 if (mrq) {
521 dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
522 dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n",
523 mvsd_read(MVSD_HW_STATE),
524 mvsd_read(MVSD_NOR_INTR_STATUS),
525 mvsd_read(MVSD_NOR_INTR_EN));
526
527 host->mrq = NULL;
528
529 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
530
531 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
532 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
533
534 host->intr_en &= MVSD_NOR_CARD_INT;
535 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
536 mvsd_write(MVSD_ERR_INTR_EN, 0);
537 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
538
539 mrq->cmd->error = -ETIMEDOUT;
540 mvsd_finish_cmd(host, mrq->cmd, 0);
541 if (mrq->data) {
542 mrq->data->error = -ETIMEDOUT;
543 mvsd_finish_data(host, mrq->data, 0);
544 }
545 }
546 spin_unlock_irqrestore(&host->lock, flags);
547
548 if (mrq)
549 mmc_request_done(host->mmc, mrq);
550}
551
552static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
553{
554 struct mvsd_host *host = mmc_priv(mmc);
555 void __iomem *iobase = host->base;
556 unsigned long flags;
557
558 spin_lock_irqsave(&host->lock, flags);
559 if (enable) {
560 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
561 host->intr_en |= MVSD_NOR_CARD_INT;
562 } else {
563 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
564 host->intr_en &= ~MVSD_NOR_CARD_INT;
565 }
566 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
567 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
568 spin_unlock_irqrestore(&host->lock, flags);
569}
570
571static void mvsd_power_up(struct mvsd_host *host)
572{
573 void __iomem *iobase = host->base;
574 dev_dbg(host->dev, "power up\n");
575 mvsd_write(MVSD_NOR_INTR_EN, 0);
576 mvsd_write(MVSD_ERR_INTR_EN, 0);
577 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
578 mvsd_write(MVSD_XFER_MODE, 0);
579 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
580 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
581 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
582 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
583}
584
585static void mvsd_power_down(struct mvsd_host *host)
586{
587 void __iomem *iobase = host->base;
588 dev_dbg(host->dev, "power down\n");
589 mvsd_write(MVSD_NOR_INTR_EN, 0);
590 mvsd_write(MVSD_ERR_INTR_EN, 0);
591 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
592 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
593 mvsd_write(MVSD_NOR_STATUS_EN, 0);
594 mvsd_write(MVSD_ERR_STATUS_EN, 0);
595 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
596 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
597}
598
599static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
600{
601 struct mvsd_host *host = mmc_priv(mmc);
602 void __iomem *iobase = host->base;
603 u32 ctrl_reg = 0;
604
605 if (ios->power_mode == MMC_POWER_UP)
606 mvsd_power_up(host);
607
608 if (ios->clock == 0) {
609 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
610 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
611 host->clock = 0;
612 dev_dbg(host->dev, "clock off\n");
613 } else if (ios->clock != host->clock) {
614 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
615 if (m > MVSD_BASE_DIV_MAX)
616 m = MVSD_BASE_DIV_MAX;
617 mvsd_write(MVSD_CLK_DIV, m);
618 host->clock = ios->clock;
619 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
620 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
621 ios->clock, host->base_clock / (m+1), m);
622 }
623
624 /* default transfer mode */
625 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
626 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
627
628 /* default to maximum timeout */
629 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
630 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
631
632 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
633 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
634
635 if (ios->bus_width == MMC_BUS_WIDTH_4)
636 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
637
638 /*
639 * The HI_SPEED_EN bit is causing trouble with many (but not all)
640 * high speed SD, SDHC and SDIO cards. Not enabling that bit
641 * makes all cards work. So let's just ignore that bit for now
642 * and revisit this issue if problems for not enabling this bit
643 * are ever reported.
644 */
645#if 0
646 if (ios->timing == MMC_TIMING_MMC_HS ||
647 ios->timing == MMC_TIMING_SD_HS)
648 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
649#endif
650
651 host->ctrl = ctrl_reg;
652 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
653 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
654 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
655 "push-pull" : "open-drain",
656 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
657 "4bit-width" : "1bit-width",
658 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
659 "high-speed" : "");
660
661 if (ios->power_mode == MMC_POWER_OFF)
662 mvsd_power_down(host);
663}
664
665static const struct mmc_host_ops mvsd_ops = {
666 .request = mvsd_request,
667 .get_ro = mmc_gpio_get_ro,
668 .set_ios = mvsd_set_ios,
669 .enable_sdio_irq = mvsd_enable_sdio_irq,
670};
671
672static void
673mv_conf_mbus_windows(struct mvsd_host *host,
674 const struct mbus_dram_target_info *dram)
675{
676 void __iomem *iobase = host->base;
677 int i;
678
679 for (i = 0; i < 4; i++) {
680 writel(0, iobase + MVSD_WINDOW_CTRL(i));
681 writel(0, iobase + MVSD_WINDOW_BASE(i));
682 }
683
684 for (i = 0; i < dram->num_cs; i++) {
685 const struct mbus_dram_window *cs = dram->cs + i;
686 writel(((cs->size - 1) & 0xffff0000) |
687 (cs->mbus_attr << 8) |
688 (dram->mbus_dram_target_id << 4) | 1,
689 iobase + MVSD_WINDOW_CTRL(i));
690 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
691 }
692}
693
694static int mvsd_probe(struct platform_device *pdev)
695{
696 struct device_node *np = pdev->dev.of_node;
697 struct mmc_host *mmc = NULL;
698 struct mvsd_host *host = NULL;
699 const struct mbus_dram_target_info *dram;
700 struct resource *r;
701 int ret, irq;
702
703 if (!np) {
704 dev_err(&pdev->dev, "no DT node\n");
705 return -ENODEV;
706 }
707 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
708 irq = platform_get_irq(pdev, 0);
709 if (!r || irq < 0)
710 return -ENXIO;
711
712 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
713 if (!mmc) {
714 ret = -ENOMEM;
715 goto out;
716 }
717
718 host = mmc_priv(mmc);
719 host->mmc = mmc;
720 host->dev = &pdev->dev;
721
722 /*
723 * Some non-DT platforms do not pass a clock, and the clock
724 * frequency is passed through platform_data. On DT platforms,
725 * a clock must always be passed, even if there is no gatable
726 * clock associated to the SDIO interface (it can simply be a
727 * fixed rate clock).
728 */
729 host->clk = devm_clk_get(&pdev->dev, NULL);
730 if (IS_ERR(host->clk)) {
731 dev_err(&pdev->dev, "no clock associated\n");
732 ret = -EINVAL;
733 goto out;
734 }
735 clk_prepare_enable(host->clk);
736
737 mmc->ops = &mvsd_ops;
738
739 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
740
741 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
742 mmc->f_max = MVSD_CLOCKRATE_MAX;
743
744 mmc->max_blk_size = 2048;
745 mmc->max_blk_count = 65535;
746
747 mmc->max_segs = 1;
748 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
749 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
750
751 host->base_clock = clk_get_rate(host->clk) / 2;
752 ret = mmc_of_parse(mmc);
753 if (ret < 0)
754 goto out;
755 if (maxfreq)
756 mmc->f_max = maxfreq;
757
758 spin_lock_init(&host->lock);
759
760 host->base = devm_ioremap_resource(&pdev->dev, r);
761 if (IS_ERR(host->base)) {
762 ret = PTR_ERR(host->base);
763 goto out;
764 }
765
766 /* (Re-)program MBUS remapping windows if we are asked to. */
767 dram = mv_mbus_dram_info();
768 if (dram)
769 mv_conf_mbus_windows(host, dram);
770
771 mvsd_power_down(host);
772
773 ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
774 if (ret) {
775 dev_err(&pdev->dev, "cannot assign irq %d\n", irq);
776 goto out;
777 }
778
779 timer_setup(&host->timer, mvsd_timeout_timer, 0);
780 platform_set_drvdata(pdev, mmc);
781 ret = mmc_add_host(mmc);
782 if (ret)
783 goto out;
784
785 if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
786 dev_dbg(&pdev->dev, "using GPIO for card detection\n");
787 else
788 dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n");
789
790 return 0;
791
792out:
793 if (mmc) {
794 if (!IS_ERR(host->clk))
795 clk_disable_unprepare(host->clk);
796 mmc_free_host(mmc);
797 }
798
799 return ret;
800}
801
802static int mvsd_remove(struct platform_device *pdev)
803{
804 struct mmc_host *mmc = platform_get_drvdata(pdev);
805
806 struct mvsd_host *host = mmc_priv(mmc);
807
808 mmc_remove_host(mmc);
809 del_timer_sync(&host->timer);
810 mvsd_power_down(host);
811
812 if (!IS_ERR(host->clk))
813 clk_disable_unprepare(host->clk);
814 mmc_free_host(mmc);
815
816 return 0;
817}
818
819static const struct of_device_id mvsdio_dt_ids[] = {
820 { .compatible = "marvell,orion-sdio" },
821 { /* sentinel */ }
822};
823MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
824
825static struct platform_driver mvsd_driver = {
826 .probe = mvsd_probe,
827 .remove = mvsd_remove,
828 .driver = {
829 .name = DRIVER_NAME,
830 .of_match_table = mvsdio_dt_ids,
831 },
832};
833
834module_platform_driver(mvsd_driver);
835
836/* maximum card clock frequency (default 50MHz) */
837module_param(maxfreq, int, 0);
838
839/* force PIO transfers all the time */
840module_param(nodma, int, 0);
841
842MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
843MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
844MODULE_LICENSE("GPL");
845MODULE_ALIAS("platform:mvsdio");