Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Chris Zhong <zyw@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef _CDN_DP_REG_H
16#define _CDN_DP_REG_H
17
18#include <linux/bitops.h>
19
20#define ADDR_IMEM 0x10000
21#define ADDR_DMEM 0x20000
22
23/* APB CFG addr */
24#define APB_CTRL 0
25#define XT_INT_CTRL 0x04
26#define MAILBOX_FULL_ADDR 0x08
27#define MAILBOX_EMPTY_ADDR 0x0c
28#define MAILBOX0_WR_DATA 0x10
29#define MAILBOX0_RD_DATA 0x14
30#define KEEP_ALIVE 0x18
31#define VER_L 0x1c
32#define VER_H 0x20
33#define VER_LIB_L_ADDR 0x24
34#define VER_LIB_H_ADDR 0x28
35#define SW_DEBUG_L 0x2c
36#define SW_DEBUG_H 0x30
37#define MAILBOX_INT_MASK 0x34
38#define MAILBOX_INT_STATUS 0x38
39#define SW_CLK_L 0x3c
40#define SW_CLK_H 0x40
41#define SW_EVENTS0 0x44
42#define SW_EVENTS1 0x48
43#define SW_EVENTS2 0x4c
44#define SW_EVENTS3 0x50
45#define XT_OCD_CTRL 0x60
46#define APB_INT_MASK 0x6c
47#define APB_STATUS_MASK 0x70
48
49/* audio decoder addr */
50#define AUDIO_SRC_CNTL 0x30000
51#define AUDIO_SRC_CNFG 0x30004
52#define COM_CH_STTS_BITS 0x30008
53#define STTS_BIT_CH(x) (0x3000c + ((x) << 2))
54#define SPDIF_CTRL_ADDR 0x3004c
55#define SPDIF_CH1_CS_3100_ADDR 0x30050
56#define SPDIF_CH1_CS_6332_ADDR 0x30054
57#define SPDIF_CH1_CS_9564_ADDR 0x30058
58#define SPDIF_CH1_CS_12796_ADDR 0x3005c
59#define SPDIF_CH1_CS_159128_ADDR 0x30060
60#define SPDIF_CH1_CS_191160_ADDR 0x30064
61#define SPDIF_CH2_CS_3100_ADDR 0x30068
62#define SPDIF_CH2_CS_6332_ADDR 0x3006c
63#define SPDIF_CH2_CS_9564_ADDR 0x30070
64#define SPDIF_CH2_CS_12796_ADDR 0x30074
65#define SPDIF_CH2_CS_159128_ADDR 0x30078
66#define SPDIF_CH2_CS_191160_ADDR 0x3007c
67#define SMPL2PKT_CNTL 0x30080
68#define SMPL2PKT_CNFG 0x30084
69#define FIFO_CNTL 0x30088
70#define FIFO_STTS 0x3008c
71
72/* source pif addr */
73#define SOURCE_PIF_WR_ADDR 0x30800
74#define SOURCE_PIF_WR_REQ 0x30804
75#define SOURCE_PIF_RD_ADDR 0x30808
76#define SOURCE_PIF_RD_REQ 0x3080c
77#define SOURCE_PIF_DATA_WR 0x30810
78#define SOURCE_PIF_DATA_RD 0x30814
79#define SOURCE_PIF_FIFO1_FLUSH 0x30818
80#define SOURCE_PIF_FIFO2_FLUSH 0x3081c
81#define SOURCE_PIF_STATUS 0x30820
82#define SOURCE_PIF_INTERRUPT_SOURCE 0x30824
83#define SOURCE_PIF_INTERRUPT_MASK 0x30828
84#define SOURCE_PIF_PKT_ALLOC_REG 0x3082c
85#define SOURCE_PIF_PKT_ALLOC_WR_EN 0x30830
86#define SOURCE_PIF_SW_RESET 0x30834
87
88/* bellow registers need access by mailbox */
89/* source car addr */
90#define SOURCE_HDTX_CAR 0x0900
91#define SOURCE_DPTX_CAR 0x0904
92#define SOURCE_PHY_CAR 0x0908
93#define SOURCE_CEC_CAR 0x090c
94#define SOURCE_CBUS_CAR 0x0910
95#define SOURCE_PKT_CAR 0x0918
96#define SOURCE_AIF_CAR 0x091c
97#define SOURCE_CIPHER_CAR 0x0920
98#define SOURCE_CRYPTO_CAR 0x0924
99
100/* clock meters addr */
101#define CM_CTRL 0x0a00
102#define CM_I2S_CTRL 0x0a04
103#define CM_SPDIF_CTRL 0x0a08
104#define CM_VID_CTRL 0x0a0c
105#define CM_LANE_CTRL 0x0a10
106#define I2S_NM_STABLE 0x0a14
107#define I2S_NCTS_STABLE 0x0a18
108#define SPDIF_NM_STABLE 0x0a1c
109#define SPDIF_NCTS_STABLE 0x0a20
110#define NMVID_MEAS_STABLE 0x0a24
111#define I2S_MEAS 0x0a40
112#define SPDIF_MEAS 0x0a80
113#define NMVID_MEAS 0x0ac0
114
115/* source vif addr */
116#define BND_HSYNC2VSYNC 0x0b00
117#define HSYNC2VSYNC_F1_L1 0x0b04
118#define HSYNC2VSYNC_F2_L1 0x0b08
119#define HSYNC2VSYNC_STATUS 0x0b0c
120#define HSYNC2VSYNC_POL_CTRL 0x0b10
121
122/* dptx phy addr */
123#define DP_TX_PHY_CONFIG_REG 0x2000
124#define DP_TX_PHY_SW_RESET 0x2004
125#define DP_TX_PHY_SCRAMBLER_SEED 0x2008
126#define DP_TX_PHY_TRAINING_01_04 0x200c
127#define DP_TX_PHY_TRAINING_05_08 0x2010
128#define DP_TX_PHY_TRAINING_09_10 0x2014
129#define TEST_COR 0x23fc
130
131/* dptx hpd addr */
132#define HPD_IRQ_DET_MIN_TIMER 0x2100
133#define HPD_IRQ_DET_MAX_TIMER 0x2104
134#define HPD_UNPLGED_DET_MIN_TIMER 0x2108
135#define HPD_STABLE_TIMER 0x210c
136#define HPD_FILTER_TIMER 0x2110
137#define HPD_EVENT_MASK 0x211c
138#define HPD_EVENT_DET 0x2120
139
140/* dpyx framer addr */
141#define DP_FRAMER_GLOBAL_CONFIG 0x2200
142#define DP_SW_RESET 0x2204
143#define DP_FRAMER_TU 0x2208
144#define DP_FRAMER_PXL_REPR 0x220c
145#define DP_FRAMER_SP 0x2210
146#define AUDIO_PACK_CONTROL 0x2214
147#define DP_VC_TABLE(x) (0x2218 + ((x) << 2))
148#define DP_VB_ID 0x2258
149#define DP_MTPH_LVP_CONTROL 0x225c
150#define DP_MTPH_SYMBOL_VALUES 0x2260
151#define DP_MTPH_ECF_CONTROL 0x2264
152#define DP_MTPH_ACT_CONTROL 0x2268
153#define DP_MTPH_STATUS 0x226c
154#define DP_INTERRUPT_SOURCE 0x2270
155#define DP_INTERRUPT_MASK 0x2274
156#define DP_FRONT_BACK_PORCH 0x2278
157#define DP_BYTE_COUNT 0x227c
158
159/* dptx stream addr */
160#define MSA_HORIZONTAL_0 0x2280
161#define MSA_HORIZONTAL_1 0x2284
162#define MSA_VERTICAL_0 0x2288
163#define MSA_VERTICAL_1 0x228c
164#define MSA_MISC 0x2290
165#define STREAM_CONFIG 0x2294
166#define AUDIO_PACK_STATUS 0x2298
167#define VIF_STATUS 0x229c
168#define PCK_STUFF_STATUS_0 0x22a0
169#define PCK_STUFF_STATUS_1 0x22a4
170#define INFO_PACK_STATUS 0x22a8
171#define RATE_GOVERNOR_STATUS 0x22ac
172#define DP_HORIZONTAL 0x22b0
173#define DP_VERTICAL_0 0x22b4
174#define DP_VERTICAL_1 0x22b8
175#define DP_BLOCK_SDP 0x22bc
176
177/* dptx glbl addr */
178#define DPTX_LANE_EN 0x2300
179#define DPTX_ENHNCD 0x2304
180#define DPTX_INT_MASK 0x2308
181#define DPTX_INT_STATUS 0x230c
182
183/* dp aux addr */
184#define DP_AUX_HOST_CONTROL 0x2800
185#define DP_AUX_INTERRUPT_SOURCE 0x2804
186#define DP_AUX_INTERRUPT_MASK 0x2808
187#define DP_AUX_SWAP_INVERSION_CONTROL 0x280c
188#define DP_AUX_SEND_NACK_TRANSACTION 0x2810
189#define DP_AUX_CLEAR_RX 0x2814
190#define DP_AUX_CLEAR_TX 0x2818
191#define DP_AUX_TIMER_STOP 0x281c
192#define DP_AUX_TIMER_CLEAR 0x2820
193#define DP_AUX_RESET_SW 0x2824
194#define DP_AUX_DIVIDE_2M 0x2828
195#define DP_AUX_TX_PREACHARGE_LENGTH 0x282c
196#define DP_AUX_FREQUENCY_1M_MAX 0x2830
197#define DP_AUX_FREQUENCY_1M_MIN 0x2834
198#define DP_AUX_RX_PRE_MIN 0x2838
199#define DP_AUX_RX_PRE_MAX 0x283c
200#define DP_AUX_TIMER_PRESET 0x2840
201#define DP_AUX_NACK_FORMAT 0x2844
202#define DP_AUX_TX_DATA 0x2848
203#define DP_AUX_RX_DATA 0x284c
204#define DP_AUX_TX_STATUS 0x2850
205#define DP_AUX_RX_STATUS 0x2854
206#define DP_AUX_RX_CYCLE_COUNTER 0x2858
207#define DP_AUX_MAIN_STATES 0x285c
208#define DP_AUX_MAIN_TIMER 0x2860
209#define DP_AUX_AFE_OUT 0x2864
210
211/* crypto addr */
212#define CRYPTO_HDCP_REVISION 0x5800
213#define HDCP_CRYPTO_CONFIG 0x5804
214#define CRYPTO_INTERRUPT_SOURCE 0x5808
215#define CRYPTO_INTERRUPT_MASK 0x580c
216#define CRYPTO22_CONFIG 0x5818
217#define CRYPTO22_STATUS 0x581c
218#define SHA_256_DATA_IN 0x583c
219#define SHA_256_DATA_OUT_(x) (0x5850 + ((x) << 2))
220#define AES_32_KEY_(x) (0x5870 + ((x) << 2))
221#define AES_32_DATA_IN 0x5880
222#define AES_32_DATA_OUT_(x) (0x5884 + ((x) << 2))
223#define CRYPTO14_CONFIG 0x58a0
224#define CRYPTO14_STATUS 0x58a4
225#define CRYPTO14_PRNM_OUT 0x58a8
226#define CRYPTO14_KM_0 0x58ac
227#define CRYPTO14_KM_1 0x58b0
228#define CRYPTO14_AN_0 0x58b4
229#define CRYPTO14_AN_1 0x58b8
230#define CRYPTO14_YOUR_KSV_0 0x58bc
231#define CRYPTO14_YOUR_KSV_1 0x58c0
232#define CRYPTO14_MI_0 0x58c4
233#define CRYPTO14_MI_1 0x58c8
234#define CRYPTO14_TI_0 0x58cc
235#define CRYPTO14_KI_0 0x58d0
236#define CRYPTO14_KI_1 0x58d4
237#define CRYPTO14_BLOCKS_NUM 0x58d8
238#define CRYPTO14_KEY_MEM_DATA_0 0x58dc
239#define CRYPTO14_KEY_MEM_DATA_1 0x58e0
240#define CRYPTO14_SHA1_MSG_DATA 0x58e4
241#define CRYPTO14_SHA1_V_VALUE_(x) (0x58e8 + ((x) << 2))
242#define TRNG_CTRL 0x58fc
243#define TRNG_DATA_RDY 0x5900
244#define TRNG_DATA 0x5904
245
246/* cipher addr */
247#define HDCP_REVISION 0x60000
248#define INTERRUPT_SOURCE 0x60004
249#define INTERRUPT_MASK 0x60008
250#define HDCP_CIPHER_CONFIG 0x6000c
251#define AES_128_KEY_0 0x60010
252#define AES_128_KEY_1 0x60014
253#define AES_128_KEY_2 0x60018
254#define AES_128_KEY_3 0x6001c
255#define AES_128_RANDOM_0 0x60020
256#define AES_128_RANDOM_1 0x60024
257#define CIPHER14_KM_0 0x60028
258#define CIPHER14_KM_1 0x6002c
259#define CIPHER14_STATUS 0x60030
260#define CIPHER14_RI_PJ_STATUS 0x60034
261#define CIPHER_MODE 0x60038
262#define CIPHER14_AN_0 0x6003c
263#define CIPHER14_AN_1 0x60040
264#define CIPHER22_AUTH 0x60044
265#define CIPHER14_R0_DP_STATUS 0x60048
266#define CIPHER14_BOOTSTRAP 0x6004c
267
268#define DPTX_FRMR_DATA_CLK_RSTN_EN BIT(11)
269#define DPTX_FRMR_DATA_CLK_EN BIT(10)
270#define DPTX_PHY_DATA_RSTN_EN BIT(9)
271#define DPTX_PHY_DATA_CLK_EN BIT(8)
272#define DPTX_PHY_CHAR_RSTN_EN BIT(7)
273#define DPTX_PHY_CHAR_CLK_EN BIT(6)
274#define SOURCE_AUX_SYS_CLK_RSTN_EN BIT(5)
275#define SOURCE_AUX_SYS_CLK_EN BIT(4)
276#define DPTX_SYS_CLK_RSTN_EN BIT(3)
277#define DPTX_SYS_CLK_EN BIT(2)
278#define CFG_DPTX_VIF_CLK_RSTN_EN BIT(1)
279#define CFG_DPTX_VIF_CLK_EN BIT(0)
280
281#define SOURCE_PHY_RSTN_EN BIT(1)
282#define SOURCE_PHY_CLK_EN BIT(0)
283
284#define SOURCE_PKT_SYS_RSTN_EN BIT(3)
285#define SOURCE_PKT_SYS_CLK_EN BIT(2)
286#define SOURCE_PKT_DATA_RSTN_EN BIT(1)
287#define SOURCE_PKT_DATA_CLK_EN BIT(0)
288
289#define SPDIF_CDR_CLK_RSTN_EN BIT(5)
290#define SPDIF_CDR_CLK_EN BIT(4)
291#define SOURCE_AIF_SYS_RSTN_EN BIT(3)
292#define SOURCE_AIF_SYS_CLK_EN BIT(2)
293#define SOURCE_AIF_CLK_RSTN_EN BIT(1)
294#define SOURCE_AIF_CLK_EN BIT(0)
295
296#define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN BIT(3)
297#define SOURCE_CIPHER_SYS_CLK_EN BIT(2)
298#define SOURCE_CIPHER_CHAR_CLK_RSTN_EN BIT(1)
299#define SOURCE_CIPHER_CHAR_CLK_EN BIT(0)
300
301#define SOURCE_CRYPTO_SYS_CLK_RSTN_EN BIT(1)
302#define SOURCE_CRYPTO_SYS_CLK_EN BIT(0)
303
304#define APB_IRAM_PATH BIT(2)
305#define APB_DRAM_PATH BIT(1)
306#define APB_XT_RESET BIT(0)
307
308#define MAILBOX_INT_MASK_BIT BIT(1)
309#define PIF_INT_MASK_BIT BIT(0)
310#define ALL_INT_MASK 3
311
312/* mailbox */
313#define MB_OPCODE_ID 0
314#define MB_MODULE_ID 1
315#define MB_SIZE_MSB_ID 2
316#define MB_SIZE_LSB_ID 3
317#define MB_DATA_ID 4
318
319#define MB_MODULE_ID_DP_TX 0x01
320#define MB_MODULE_ID_HDCP_TX 0x07
321#define MB_MODULE_ID_HDCP_RX 0x08
322#define MB_MODULE_ID_HDCP_GENERAL 0x09
323#define MB_MODULE_ID_GENERAL 0x0a
324
325/* general opcode */
326#define GENERAL_MAIN_CONTROL 0x01
327#define GENERAL_TEST_ECHO 0x02
328#define GENERAL_BUS_SETTINGS 0x03
329#define GENERAL_TEST_ACCESS 0x04
330
331#define DPTX_SET_POWER_MNG 0x00
332#define DPTX_SET_HOST_CAPABILITIES 0x01
333#define DPTX_GET_EDID 0x02
334#define DPTX_READ_DPCD 0x03
335#define DPTX_WRITE_DPCD 0x04
336#define DPTX_ENABLE_EVENT 0x05
337#define DPTX_WRITE_REGISTER 0x06
338#define DPTX_READ_REGISTER 0x07
339#define DPTX_WRITE_FIELD 0x08
340#define DPTX_TRAINING_CONTROL 0x09
341#define DPTX_READ_EVENT 0x0a
342#define DPTX_READ_LINK_STAT 0x0b
343#define DPTX_SET_VIDEO 0x0c
344#define DPTX_SET_AUDIO 0x0d
345#define DPTX_GET_LAST_AUX_STAUS 0x0e
346#define DPTX_SET_LINK_BREAK_POINT 0x0f
347#define DPTX_FORCE_LANES 0x10
348#define DPTX_HPD_STATE 0x11
349
350#define FW_STANDBY 0
351#define FW_ACTIVE 1
352
353#define DPTX_EVENT_ENABLE_HPD BIT(0)
354#define DPTX_EVENT_ENABLE_TRAINING BIT(1)
355
356#define LINK_TRAINING_NOT_ACTIVE 0
357#define LINK_TRAINING_RUN 1
358#define LINK_TRAINING_RESTART 2
359
360#define CONTROL_VIDEO_IDLE 0
361#define CONTROL_VIDEO_VALID 1
362
363#define TU_CNT_RST_EN BIT(15)
364#define VIF_BYPASS_INTERLACE BIT(13)
365#define INTERLACE_FMT_DET BIT(12)
366#define INTERLACE_DTCT_WIN 0x20
367
368#define DP_FRAMER_SP_INTERLACE_EN BIT(2)
369#define DP_FRAMER_SP_HSP BIT(1)
370#define DP_FRAMER_SP_VSP BIT(0)
371
372/* capability */
373#define AUX_HOST_INVERT 3
374#define FAST_LT_SUPPORT 1
375#define FAST_LT_NOT_SUPPORT 0
376#define LANE_MAPPING_NORMAL 0x1b
377#define LANE_MAPPING_FLIPPED 0xe4
378#define ENHANCED 1
379#define SCRAMBLER_EN BIT(4)
380
381#define FULL_LT_STARTED BIT(0)
382#define FASE_LT_STARTED BIT(1)
383#define CLK_RECOVERY_FINISHED BIT(2)
384#define EQ_PHASE_FINISHED BIT(3)
385#define FASE_LT_START_FINISHED BIT(4)
386#define CLK_RECOVERY_FAILED BIT(5)
387#define EQ_PHASE_FAILED BIT(6)
388#define FASE_LT_FAILED BIT(7)
389
390#define DPTX_HPD_EVENT BIT(0)
391#define DPTX_TRAINING_EVENT BIT(1)
392#define HDCP_TX_STATUS_EVENT BIT(4)
393#define HDCP2_TX_IS_KM_STORED_EVENT BIT(5)
394#define HDCP2_TX_STORE_KM_EVENT BIT(6)
395#define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT BIT(7)
396
397#define TU_SIZE 30
398#define CDN_DP_MAX_LINK_RATE DP_LINK_BW_5_4
399
400/* audio */
401#define AUDIO_PACK_EN BIT(8)
402#define SAMPLING_FREQ(x) (((x) & 0xf) << 16)
403#define ORIGINAL_SAMP_FREQ(x) (((x) & 0xf) << 24)
404#define SYNC_WR_TO_CH_ZERO BIT(1)
405#define I2S_DEC_START BIT(1)
406#define AUDIO_SW_RST BIT(0)
407#define SMPL2PKT_EN BIT(1)
408#define MAX_NUM_CH(x) (((x) & 0x1f) - 1)
409#define NUM_OF_I2S_PORTS(x) ((((x) / 2 - 1) & 0x3) << 5)
410#define AUDIO_TYPE_LPCM (2 << 7)
411#define CFG_SUB_PCKT_NUM(x) ((((x) - 1) & 0x7) << 11)
412#define AUDIO_CH_NUM(x) ((((x) - 1) & 0x1f) << 2)
413#define TRANS_SMPL_WIDTH_16 0
414#define TRANS_SMPL_WIDTH_24 BIT(11)
415#define TRANS_SMPL_WIDTH_32 (2 << 11)
416#define I2S_DEC_PORT_EN(x) (((x) & 0xf) << 17)
417#define SPDIF_ENABLE BIT(21)
418#define SPDIF_AVG_SEL BIT(20)
419#define SPDIF_JITTER_BYPASS BIT(19)
420#define SPDIF_FIFO_MID_RANGE(x) (((x) & 0xff) << 11)
421#define SPDIF_JITTER_THRSH(x) (((x) & 0xff) << 3)
422#define SPDIF_JITTER_AVG_WIN(x) ((x) & 0x7)
423
424/* Reference cycles when using lane clock as reference */
425#define LANE_REF_CYC 0x8000
426
427enum voltage_swing_level {
428 VOLTAGE_LEVEL_0,
429 VOLTAGE_LEVEL_1,
430 VOLTAGE_LEVEL_2,
431 VOLTAGE_LEVEL_3,
432};
433
434enum pre_emphasis_level {
435 PRE_EMPHASIS_LEVEL_0,
436 PRE_EMPHASIS_LEVEL_1,
437 PRE_EMPHASIS_LEVEL_2,
438 PRE_EMPHASIS_LEVEL_3,
439};
440
441enum pattern_set {
442 PTS1 = BIT(0),
443 PTS2 = BIT(1),
444 PTS3 = BIT(2),
445 PTS4 = BIT(3),
446 DP_NONE = BIT(4)
447};
448
449enum vic_color_depth {
450 BCS_6 = 0x1,
451 BCS_8 = 0x2,
452 BCS_10 = 0x4,
453 BCS_12 = 0x8,
454 BCS_16 = 0x10,
455};
456
457enum vic_bt_type {
458 BT_601 = 0x0,
459 BT_709 = 0x1,
460};
461
462void cdn_dp_clock_reset(struct cdn_dp_device *dp);
463
464void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, unsigned long clk);
465int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem,
466 u32 i_size, const u32 *d_mem, u32 d_size);
467int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable);
468int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip);
469int cdn_dp_event_config(struct cdn_dp_device *dp);
470u32 cdn_dp_get_event(struct cdn_dp_device *dp);
471int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
472int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value);
473int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len);
474int cdn_dp_get_edid_block(void *dp, u8 *edid,
475 unsigned int block, size_t length);
476int cdn_dp_train_link(struct cdn_dp_device *dp);
477int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active);
478int cdn_dp_config_video(struct cdn_dp_device *dp);
479int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
480int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
481int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
482#endif /* _CDN_DP_REG_H */