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1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23#include "drmP.h"
24#include "radeon.h"
25#include "avivod.h"
26#include "atom.h"
27#ifdef CONFIG_ACPI
28#include <linux/acpi.h>
29#endif
30#include <linux/power_supply.h>
31#include <linux/hwmon.h>
32#include <linux/hwmon-sysfs.h>
33
34#define RADEON_IDLE_LOOP_MS 100
35#define RADEON_RECLOCK_DELAY_MS 200
36#define RADEON_WAIT_VBLANK_TIMEOUT 200
37#define RADEON_WAIT_IDLE_TIMEOUT 200
38
39static const char *radeon_pm_state_type_name[5] = {
40 "Default",
41 "Powersave",
42 "Battery",
43 "Balanced",
44 "Performance",
45};
46
47static void radeon_dynpm_idle_work_handler(struct work_struct *work);
48static int radeon_debugfs_pm_init(struct radeon_device *rdev);
49static bool radeon_pm_in_vbl(struct radeon_device *rdev);
50static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
51static void radeon_pm_update_profile(struct radeon_device *rdev);
52static void radeon_pm_set_clocks(struct radeon_device *rdev);
53
54#define ACPI_AC_CLASS "ac_adapter"
55
56#ifdef CONFIG_ACPI
57static int radeon_acpi_event(struct notifier_block *nb,
58 unsigned long val,
59 void *data)
60{
61 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
62 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
63
64 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
65 if (power_supply_is_system_supplied() > 0)
66 DRM_DEBUG_DRIVER("pm: AC\n");
67 else
68 DRM_DEBUG_DRIVER("pm: DC\n");
69
70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
76 }
77 }
78 }
79
80 return NOTIFY_OK;
81}
82#endif
83
84static void radeon_pm_update_profile(struct radeon_device *rdev)
85{
86 switch (rdev->pm.profile) {
87 case PM_PROFILE_DEFAULT:
88 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
89 break;
90 case PM_PROFILE_AUTO:
91 if (power_supply_is_system_supplied() > 0) {
92 if (rdev->pm.active_crtc_count > 1)
93 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
94 else
95 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
96 } else {
97 if (rdev->pm.active_crtc_count > 1)
98 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
99 else
100 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
101 }
102 break;
103 case PM_PROFILE_LOW:
104 if (rdev->pm.active_crtc_count > 1)
105 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
106 else
107 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
108 break;
109 case PM_PROFILE_MID:
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
112 else
113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
114 break;
115 case PM_PROFILE_HIGH:
116 if (rdev->pm.active_crtc_count > 1)
117 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
118 else
119 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
120 break;
121 }
122
123 if (rdev->pm.active_crtc_count == 0) {
124 rdev->pm.requested_power_state_index =
125 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
126 rdev->pm.requested_clock_mode_index =
127 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
128 } else {
129 rdev->pm.requested_power_state_index =
130 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
131 rdev->pm.requested_clock_mode_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
133 }
134}
135
136static void radeon_unmap_vram_bos(struct radeon_device *rdev)
137{
138 struct radeon_bo *bo, *n;
139
140 if (list_empty(&rdev->gem.objects))
141 return;
142
143 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
144 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
145 ttm_bo_unmap_virtual(&bo->tbo);
146 }
147}
148
149static void radeon_sync_with_vblank(struct radeon_device *rdev)
150{
151 if (rdev->pm.active_crtcs) {
152 rdev->pm.vblank_sync = false;
153 wait_event_timeout(
154 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
155 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
156 }
157}
158
159static void radeon_set_power_state(struct radeon_device *rdev)
160{
161 u32 sclk, mclk;
162 bool misc_after = false;
163
164 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
165 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
166 return;
167
168 if (radeon_gui_idle(rdev)) {
169 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
170 clock_info[rdev->pm.requested_clock_mode_index].sclk;
171 if (sclk > rdev->pm.default_sclk)
172 sclk = rdev->pm.default_sclk;
173
174 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
175 clock_info[rdev->pm.requested_clock_mode_index].mclk;
176 if (mclk > rdev->pm.default_mclk)
177 mclk = rdev->pm.default_mclk;
178
179 /* upvolt before raising clocks, downvolt after lowering clocks */
180 if (sclk < rdev->pm.current_sclk)
181 misc_after = true;
182
183 radeon_sync_with_vblank(rdev);
184
185 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
186 if (!radeon_pm_in_vbl(rdev))
187 return;
188 }
189
190 radeon_pm_prepare(rdev);
191
192 if (!misc_after)
193 /* voltage, pcie lanes, etc.*/
194 radeon_pm_misc(rdev);
195
196 /* set engine clock */
197 if (sclk != rdev->pm.current_sclk) {
198 radeon_pm_debug_check_in_vbl(rdev, false);
199 radeon_set_engine_clock(rdev, sclk);
200 radeon_pm_debug_check_in_vbl(rdev, true);
201 rdev->pm.current_sclk = sclk;
202 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
203 }
204
205 /* set memory clock */
206 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_memory_clock(rdev, mclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_mclk = mclk;
211 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
212 }
213
214 if (misc_after)
215 /* voltage, pcie lanes, etc.*/
216 radeon_pm_misc(rdev);
217
218 radeon_pm_finish(rdev);
219
220 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
221 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
222 } else
223 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
224}
225
226static void radeon_pm_set_clocks(struct radeon_device *rdev)
227{
228 int i;
229
230 /* no need to take locks, etc. if nothing's going to change */
231 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
232 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
233 return;
234
235 mutex_lock(&rdev->ddev->struct_mutex);
236 mutex_lock(&rdev->vram_mutex);
237 mutex_lock(&rdev->cp.mutex);
238
239 /* gui idle int has issues on older chips it seems */
240 if (rdev->family >= CHIP_R600) {
241 if (rdev->irq.installed) {
242 /* wait for GPU idle */
243 rdev->pm.gui_idle = false;
244 rdev->irq.gui_idle = true;
245 radeon_irq_set(rdev);
246 wait_event_interruptible_timeout(
247 rdev->irq.idle_queue, rdev->pm.gui_idle,
248 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
249 rdev->irq.gui_idle = false;
250 radeon_irq_set(rdev);
251 }
252 } else {
253 if (rdev->cp.ready) {
254 struct radeon_fence *fence;
255 radeon_ring_alloc(rdev, 64);
256 radeon_fence_create(rdev, &fence);
257 radeon_fence_emit(rdev, fence);
258 radeon_ring_commit(rdev);
259 radeon_fence_wait(fence, false);
260 radeon_fence_unref(&fence);
261 }
262 }
263 radeon_unmap_vram_bos(rdev);
264
265 if (rdev->irq.installed) {
266 for (i = 0; i < rdev->num_crtc; i++) {
267 if (rdev->pm.active_crtcs & (1 << i)) {
268 rdev->pm.req_vblank |= (1 << i);
269 drm_vblank_get(rdev->ddev, i);
270 }
271 }
272 }
273
274 radeon_set_power_state(rdev);
275
276 if (rdev->irq.installed) {
277 for (i = 0; i < rdev->num_crtc; i++) {
278 if (rdev->pm.req_vblank & (1 << i)) {
279 rdev->pm.req_vblank &= ~(1 << i);
280 drm_vblank_put(rdev->ddev, i);
281 }
282 }
283 }
284
285 /* update display watermarks based on new power state */
286 radeon_update_bandwidth_info(rdev);
287 if (rdev->pm.active_crtc_count)
288 radeon_bandwidth_update(rdev);
289
290 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
291
292 mutex_unlock(&rdev->cp.mutex);
293 mutex_unlock(&rdev->vram_mutex);
294 mutex_unlock(&rdev->ddev->struct_mutex);
295}
296
297static void radeon_pm_print_states(struct radeon_device *rdev)
298{
299 int i, j;
300 struct radeon_power_state *power_state;
301 struct radeon_pm_clock_info *clock_info;
302
303 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
304 for (i = 0; i < rdev->pm.num_power_states; i++) {
305 power_state = &rdev->pm.power_state[i];
306 DRM_DEBUG_DRIVER("State %d: %s\n", i,
307 radeon_pm_state_type_name[power_state->type]);
308 if (i == rdev->pm.default_power_state_index)
309 DRM_DEBUG_DRIVER("\tDefault");
310 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
311 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
312 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
313 DRM_DEBUG_DRIVER("\tSingle display only\n");
314 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
315 for (j = 0; j < power_state->num_clock_modes; j++) {
316 clock_info = &(power_state->clock_info[j]);
317 if (rdev->flags & RADEON_IS_IGP)
318 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
319 j,
320 clock_info->sclk * 10,
321 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
322 else
323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
324 j,
325 clock_info->sclk * 10,
326 clock_info->mclk * 10,
327 clock_info->voltage.voltage,
328 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
329 }
330 }
331}
332
333static ssize_t radeon_get_pm_profile(struct device *dev,
334 struct device_attribute *attr,
335 char *buf)
336{
337 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
338 struct radeon_device *rdev = ddev->dev_private;
339 int cp = rdev->pm.profile;
340
341 return snprintf(buf, PAGE_SIZE, "%s\n",
342 (cp == PM_PROFILE_AUTO) ? "auto" :
343 (cp == PM_PROFILE_LOW) ? "low" :
344 (cp == PM_PROFILE_MID) ? "mid" :
345 (cp == PM_PROFILE_HIGH) ? "high" : "default");
346}
347
348static ssize_t radeon_set_pm_profile(struct device *dev,
349 struct device_attribute *attr,
350 const char *buf,
351 size_t count)
352{
353 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
354 struct radeon_device *rdev = ddev->dev_private;
355
356 mutex_lock(&rdev->pm.mutex);
357 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
358 if (strncmp("default", buf, strlen("default")) == 0)
359 rdev->pm.profile = PM_PROFILE_DEFAULT;
360 else if (strncmp("auto", buf, strlen("auto")) == 0)
361 rdev->pm.profile = PM_PROFILE_AUTO;
362 else if (strncmp("low", buf, strlen("low")) == 0)
363 rdev->pm.profile = PM_PROFILE_LOW;
364 else if (strncmp("mid", buf, strlen("mid")) == 0)
365 rdev->pm.profile = PM_PROFILE_MID;
366 else if (strncmp("high", buf, strlen("high")) == 0)
367 rdev->pm.profile = PM_PROFILE_HIGH;
368 else {
369 count = -EINVAL;
370 goto fail;
371 }
372 radeon_pm_update_profile(rdev);
373 radeon_pm_set_clocks(rdev);
374 } else
375 count = -EINVAL;
376
377fail:
378 mutex_unlock(&rdev->pm.mutex);
379
380 return count;
381}
382
383static ssize_t radeon_get_pm_method(struct device *dev,
384 struct device_attribute *attr,
385 char *buf)
386{
387 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
388 struct radeon_device *rdev = ddev->dev_private;
389 int pm = rdev->pm.pm_method;
390
391 return snprintf(buf, PAGE_SIZE, "%s\n",
392 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
393}
394
395static ssize_t radeon_set_pm_method(struct device *dev,
396 struct device_attribute *attr,
397 const char *buf,
398 size_t count)
399{
400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
401 struct radeon_device *rdev = ddev->dev_private;
402
403
404 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
405 mutex_lock(&rdev->pm.mutex);
406 rdev->pm.pm_method = PM_METHOD_DYNPM;
407 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
408 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
409 mutex_unlock(&rdev->pm.mutex);
410 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
411 mutex_lock(&rdev->pm.mutex);
412 /* disable dynpm */
413 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
414 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
415 rdev->pm.pm_method = PM_METHOD_PROFILE;
416 mutex_unlock(&rdev->pm.mutex);
417 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
418 } else {
419 count = -EINVAL;
420 goto fail;
421 }
422 radeon_pm_compute_clocks(rdev);
423fail:
424 return count;
425}
426
427static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
428static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
429
430static ssize_t radeon_hwmon_show_temp(struct device *dev,
431 struct device_attribute *attr,
432 char *buf)
433{
434 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
435 struct radeon_device *rdev = ddev->dev_private;
436 int temp;
437
438 switch (rdev->pm.int_thermal_type) {
439 case THERMAL_TYPE_RV6XX:
440 temp = rv6xx_get_temp(rdev);
441 break;
442 case THERMAL_TYPE_RV770:
443 temp = rv770_get_temp(rdev);
444 break;
445 case THERMAL_TYPE_EVERGREEN:
446 case THERMAL_TYPE_NI:
447 temp = evergreen_get_temp(rdev);
448 break;
449 case THERMAL_TYPE_SUMO:
450 temp = sumo_get_temp(rdev);
451 break;
452 default:
453 temp = 0;
454 break;
455 }
456
457 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
458}
459
460static ssize_t radeon_hwmon_show_name(struct device *dev,
461 struct device_attribute *attr,
462 char *buf)
463{
464 return sprintf(buf, "radeon\n");
465}
466
467static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
468static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
469
470static struct attribute *hwmon_attributes[] = {
471 &sensor_dev_attr_temp1_input.dev_attr.attr,
472 &sensor_dev_attr_name.dev_attr.attr,
473 NULL
474};
475
476static const struct attribute_group hwmon_attrgroup = {
477 .attrs = hwmon_attributes,
478};
479
480static int radeon_hwmon_init(struct radeon_device *rdev)
481{
482 int err = 0;
483
484 rdev->pm.int_hwmon_dev = NULL;
485
486 switch (rdev->pm.int_thermal_type) {
487 case THERMAL_TYPE_RV6XX:
488 case THERMAL_TYPE_RV770:
489 case THERMAL_TYPE_EVERGREEN:
490 case THERMAL_TYPE_NI:
491 case THERMAL_TYPE_SUMO:
492 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
493 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
494 err = PTR_ERR(rdev->pm.int_hwmon_dev);
495 dev_err(rdev->dev,
496 "Unable to register hwmon device: %d\n", err);
497 break;
498 }
499 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
500 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
501 &hwmon_attrgroup);
502 if (err) {
503 dev_err(rdev->dev,
504 "Unable to create hwmon sysfs file: %d\n", err);
505 hwmon_device_unregister(rdev->dev);
506 }
507 break;
508 default:
509 break;
510 }
511
512 return err;
513}
514
515static void radeon_hwmon_fini(struct radeon_device *rdev)
516{
517 if (rdev->pm.int_hwmon_dev) {
518 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
519 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
520 }
521}
522
523void radeon_pm_suspend(struct radeon_device *rdev)
524{
525 mutex_lock(&rdev->pm.mutex);
526 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
527 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
528 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
529 }
530 mutex_unlock(&rdev->pm.mutex);
531
532 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
533}
534
535void radeon_pm_resume(struct radeon_device *rdev)
536{
537 /* set up the default clocks if the MC ucode is loaded */
538 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
539 if (rdev->pm.default_vddc)
540 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
541 SET_VOLTAGE_TYPE_ASIC_VDDC);
542 if (rdev->pm.default_vddci)
543 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
544 SET_VOLTAGE_TYPE_ASIC_VDDCI);
545 if (rdev->pm.default_sclk)
546 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
547 if (rdev->pm.default_mclk)
548 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
549 }
550 /* asic init will reset the default power state */
551 mutex_lock(&rdev->pm.mutex);
552 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
553 rdev->pm.current_clock_mode_index = 0;
554 rdev->pm.current_sclk = rdev->pm.default_sclk;
555 rdev->pm.current_mclk = rdev->pm.default_mclk;
556 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
557 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
558 if (rdev->pm.pm_method == PM_METHOD_DYNPM
559 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
560 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
561 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
562 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
563 }
564 mutex_unlock(&rdev->pm.mutex);
565 radeon_pm_compute_clocks(rdev);
566}
567
568int radeon_pm_init(struct radeon_device *rdev)
569{
570 int ret;
571
572 /* default to profile method */
573 rdev->pm.pm_method = PM_METHOD_PROFILE;
574 rdev->pm.profile = PM_PROFILE_DEFAULT;
575 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
576 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
577 rdev->pm.dynpm_can_upclock = true;
578 rdev->pm.dynpm_can_downclock = true;
579 rdev->pm.default_sclk = rdev->clock.default_sclk;
580 rdev->pm.default_mclk = rdev->clock.default_mclk;
581 rdev->pm.current_sclk = rdev->clock.default_sclk;
582 rdev->pm.current_mclk = rdev->clock.default_mclk;
583 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
584
585 if (rdev->bios) {
586 if (rdev->is_atom_bios)
587 radeon_atombios_get_power_modes(rdev);
588 else
589 radeon_combios_get_power_modes(rdev);
590 radeon_pm_print_states(rdev);
591 radeon_pm_init_profile(rdev);
592 /* set up the default clocks if the MC ucode is loaded */
593 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
594 if (rdev->pm.default_vddc)
595 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
596 SET_VOLTAGE_TYPE_ASIC_VDDC);
597 if (rdev->pm.default_vddci)
598 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
599 SET_VOLTAGE_TYPE_ASIC_VDDCI);
600 if (rdev->pm.default_sclk)
601 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
602 if (rdev->pm.default_mclk)
603 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
604 }
605 }
606
607 /* set up the internal thermal sensor if applicable */
608 ret = radeon_hwmon_init(rdev);
609 if (ret)
610 return ret;
611
612 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
613
614 if (rdev->pm.num_power_states > 1) {
615 /* where's the best place to put these? */
616 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
617 if (ret)
618 DRM_ERROR("failed to create device file for power profile\n");
619 ret = device_create_file(rdev->dev, &dev_attr_power_method);
620 if (ret)
621 DRM_ERROR("failed to create device file for power method\n");
622
623#ifdef CONFIG_ACPI
624 rdev->acpi_nb.notifier_call = radeon_acpi_event;
625 register_acpi_notifier(&rdev->acpi_nb);
626#endif
627 if (radeon_debugfs_pm_init(rdev)) {
628 DRM_ERROR("Failed to register debugfs file for PM!\n");
629 }
630
631 DRM_INFO("radeon: power management initialized\n");
632 }
633
634 return 0;
635}
636
637void radeon_pm_fini(struct radeon_device *rdev)
638{
639 if (rdev->pm.num_power_states > 1) {
640 mutex_lock(&rdev->pm.mutex);
641 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
642 rdev->pm.profile = PM_PROFILE_DEFAULT;
643 radeon_pm_update_profile(rdev);
644 radeon_pm_set_clocks(rdev);
645 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
646 /* reset default clocks */
647 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
648 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
649 radeon_pm_set_clocks(rdev);
650 }
651 mutex_unlock(&rdev->pm.mutex);
652
653 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
654
655 device_remove_file(rdev->dev, &dev_attr_power_profile);
656 device_remove_file(rdev->dev, &dev_attr_power_method);
657#ifdef CONFIG_ACPI
658 unregister_acpi_notifier(&rdev->acpi_nb);
659#endif
660 }
661
662 if (rdev->pm.power_state)
663 kfree(rdev->pm.power_state);
664
665 radeon_hwmon_fini(rdev);
666}
667
668void radeon_pm_compute_clocks(struct radeon_device *rdev)
669{
670 struct drm_device *ddev = rdev->ddev;
671 struct drm_crtc *crtc;
672 struct radeon_crtc *radeon_crtc;
673
674 if (rdev->pm.num_power_states < 2)
675 return;
676
677 mutex_lock(&rdev->pm.mutex);
678
679 rdev->pm.active_crtcs = 0;
680 rdev->pm.active_crtc_count = 0;
681 list_for_each_entry(crtc,
682 &ddev->mode_config.crtc_list, head) {
683 radeon_crtc = to_radeon_crtc(crtc);
684 if (radeon_crtc->enabled) {
685 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
686 rdev->pm.active_crtc_count++;
687 }
688 }
689
690 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
691 radeon_pm_update_profile(rdev);
692 radeon_pm_set_clocks(rdev);
693 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
694 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
695 if (rdev->pm.active_crtc_count > 1) {
696 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
697 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
698
699 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
700 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
701 radeon_pm_get_dynpm_state(rdev);
702 radeon_pm_set_clocks(rdev);
703
704 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
705 }
706 } else if (rdev->pm.active_crtc_count == 1) {
707 /* TODO: Increase clocks if needed for current mode */
708
709 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
710 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
711 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
712 radeon_pm_get_dynpm_state(rdev);
713 radeon_pm_set_clocks(rdev);
714
715 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
716 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
717 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
718 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
719 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
720 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
721 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
722 }
723 } else { /* count == 0 */
724 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
725 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
726
727 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
728 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
729 radeon_pm_get_dynpm_state(rdev);
730 radeon_pm_set_clocks(rdev);
731 }
732 }
733 }
734 }
735
736 mutex_unlock(&rdev->pm.mutex);
737}
738
739static bool radeon_pm_in_vbl(struct radeon_device *rdev)
740{
741 int crtc, vpos, hpos, vbl_status;
742 bool in_vbl = true;
743
744 /* Iterate over all active crtc's. All crtc's must be in vblank,
745 * otherwise return in_vbl == false.
746 */
747 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
748 if (rdev->pm.active_crtcs & (1 << crtc)) {
749 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
750 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
751 !(vbl_status & DRM_SCANOUTPOS_INVBL))
752 in_vbl = false;
753 }
754 }
755
756 return in_vbl;
757}
758
759static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
760{
761 u32 stat_crtc = 0;
762 bool in_vbl = radeon_pm_in_vbl(rdev);
763
764 if (in_vbl == false)
765 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
766 finish ? "exit" : "entry");
767 return in_vbl;
768}
769
770static void radeon_dynpm_idle_work_handler(struct work_struct *work)
771{
772 struct radeon_device *rdev;
773 int resched;
774 rdev = container_of(work, struct radeon_device,
775 pm.dynpm_idle_work.work);
776
777 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
778 mutex_lock(&rdev->pm.mutex);
779 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
780 unsigned long irq_flags;
781 int not_processed = 0;
782
783 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
784 if (!list_empty(&rdev->fence_drv.emited)) {
785 struct list_head *ptr;
786 list_for_each(ptr, &rdev->fence_drv.emited) {
787 /* count up to 3, that's enought info */
788 if (++not_processed >= 3)
789 break;
790 }
791 }
792 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
793
794 if (not_processed >= 3) { /* should upclock */
795 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
796 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
797 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
798 rdev->pm.dynpm_can_upclock) {
799 rdev->pm.dynpm_planned_action =
800 DYNPM_ACTION_UPCLOCK;
801 rdev->pm.dynpm_action_timeout = jiffies +
802 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
803 }
804 } else if (not_processed == 0) { /* should downclock */
805 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
806 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
807 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
808 rdev->pm.dynpm_can_downclock) {
809 rdev->pm.dynpm_planned_action =
810 DYNPM_ACTION_DOWNCLOCK;
811 rdev->pm.dynpm_action_timeout = jiffies +
812 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
813 }
814 }
815
816 /* Note, radeon_pm_set_clocks is called with static_switch set
817 * to false since we want to wait for vbl to avoid flicker.
818 */
819 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
820 jiffies > rdev->pm.dynpm_action_timeout) {
821 radeon_pm_get_dynpm_state(rdev);
822 radeon_pm_set_clocks(rdev);
823 }
824
825 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
826 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
827 }
828 mutex_unlock(&rdev->pm.mutex);
829 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
830}
831
832/*
833 * Debugfs info
834 */
835#if defined(CONFIG_DEBUG_FS)
836
837static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
838{
839 struct drm_info_node *node = (struct drm_info_node *) m->private;
840 struct drm_device *dev = node->minor->dev;
841 struct radeon_device *rdev = dev->dev_private;
842
843 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
844 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
845 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
846 if (rdev->asic->get_memory_clock)
847 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
848 if (rdev->pm.current_vddc)
849 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
850 if (rdev->asic->get_pcie_lanes)
851 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
852
853 return 0;
854}
855
856static struct drm_info_list radeon_pm_info_list[] = {
857 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
858};
859#endif
860
861static int radeon_debugfs_pm_init(struct radeon_device *rdev)
862{
863#if defined(CONFIG_DEBUG_FS)
864 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
865#else
866 return 0;
867#endif
868}
1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23#include <drm/drmP.h>
24#include "radeon.h"
25#include "avivod.h"
26#include "atom.h"
27#include "r600_dpm.h"
28#include <linux/power_supply.h>
29#include <linux/hwmon.h>
30#include <linux/hwmon-sysfs.h>
31
32#define RADEON_IDLE_LOOP_MS 100
33#define RADEON_RECLOCK_DELAY_MS 200
34#define RADEON_WAIT_VBLANK_TIMEOUT 200
35
36static const char *radeon_pm_state_type_name[5] = {
37 "",
38 "Powersave",
39 "Battery",
40 "Balanced",
41 "Performance",
42};
43
44static void radeon_dynpm_idle_work_handler(struct work_struct *work);
45static int radeon_debugfs_pm_init(struct radeon_device *rdev);
46static bool radeon_pm_in_vbl(struct radeon_device *rdev);
47static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
48static void radeon_pm_update_profile(struct radeon_device *rdev);
49static void radeon_pm_set_clocks(struct radeon_device *rdev);
50
51int radeon_pm_get_type_index(struct radeon_device *rdev,
52 enum radeon_pm_state_type ps_type,
53 int instance)
54{
55 int i;
56 int found_instance = -1;
57
58 for (i = 0; i < rdev->pm.num_power_states; i++) {
59 if (rdev->pm.power_state[i].type == ps_type) {
60 found_instance++;
61 if (found_instance == instance)
62 return i;
63 }
64 }
65 /* return default if no match */
66 return rdev->pm.default_power_state_index;
67}
68
69void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
70{
71 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
72 mutex_lock(&rdev->pm.mutex);
73 if (power_supply_is_system_supplied() > 0)
74 rdev->pm.dpm.ac_power = true;
75 else
76 rdev->pm.dpm.ac_power = false;
77 if (rdev->family == CHIP_ARUBA) {
78 if (rdev->asic->dpm.enable_bapm)
79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
80 }
81 mutex_unlock(&rdev->pm.mutex);
82 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
83 if (rdev->pm.profile == PM_PROFILE_AUTO) {
84 mutex_lock(&rdev->pm.mutex);
85 radeon_pm_update_profile(rdev);
86 radeon_pm_set_clocks(rdev);
87 mutex_unlock(&rdev->pm.mutex);
88 }
89 }
90}
91
92static void radeon_pm_update_profile(struct radeon_device *rdev)
93{
94 switch (rdev->pm.profile) {
95 case PM_PROFILE_DEFAULT:
96 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
97 break;
98 case PM_PROFILE_AUTO:
99 if (power_supply_is_system_supplied() > 0) {
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
104 } else {
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
107 else
108 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
109 }
110 break;
111 case PM_PROFILE_LOW:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
116 break;
117 case PM_PROFILE_MID:
118 if (rdev->pm.active_crtc_count > 1)
119 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
120 else
121 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
122 break;
123 case PM_PROFILE_HIGH:
124 if (rdev->pm.active_crtc_count > 1)
125 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
126 else
127 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
128 break;
129 }
130
131 if (rdev->pm.active_crtc_count == 0) {
132 rdev->pm.requested_power_state_index =
133 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
134 rdev->pm.requested_clock_mode_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
136 } else {
137 rdev->pm.requested_power_state_index =
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
139 rdev->pm.requested_clock_mode_index =
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
141 }
142}
143
144static void radeon_unmap_vram_bos(struct radeon_device *rdev)
145{
146 struct radeon_bo *bo, *n;
147
148 if (list_empty(&rdev->gem.objects))
149 return;
150
151 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
152 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
153 ttm_bo_unmap_virtual(&bo->tbo);
154 }
155}
156
157static void radeon_sync_with_vblank(struct radeon_device *rdev)
158{
159 if (rdev->pm.active_crtcs) {
160 rdev->pm.vblank_sync = false;
161 wait_event_timeout(
162 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
163 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
164 }
165}
166
167static void radeon_set_power_state(struct radeon_device *rdev)
168{
169 u32 sclk, mclk;
170 bool misc_after = false;
171
172 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
173 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
174 return;
175
176 if (radeon_gui_idle(rdev)) {
177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
178 clock_info[rdev->pm.requested_clock_mode_index].sclk;
179 if (sclk > rdev->pm.default_sclk)
180 sclk = rdev->pm.default_sclk;
181
182 /* starting with BTC, there is one state that is used for both
183 * MH and SH. Difference is that we always use the high clock index for
184 * mclk and vddci.
185 */
186 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
187 (rdev->family >= CHIP_BARTS) &&
188 rdev->pm.active_crtc_count &&
189 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
190 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
193 else
194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
195 clock_info[rdev->pm.requested_clock_mode_index].mclk;
196
197 if (mclk > rdev->pm.default_mclk)
198 mclk = rdev->pm.default_mclk;
199
200 /* upvolt before raising clocks, downvolt after lowering clocks */
201 if (sclk < rdev->pm.current_sclk)
202 misc_after = true;
203
204 radeon_sync_with_vblank(rdev);
205
206 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
207 if (!radeon_pm_in_vbl(rdev))
208 return;
209 }
210
211 radeon_pm_prepare(rdev);
212
213 if (!misc_after)
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
216
217 /* set engine clock */
218 if (sclk != rdev->pm.current_sclk) {
219 radeon_pm_debug_check_in_vbl(rdev, false);
220 radeon_set_engine_clock(rdev, sclk);
221 radeon_pm_debug_check_in_vbl(rdev, true);
222 rdev->pm.current_sclk = sclk;
223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
224 }
225
226 /* set memory clock */
227 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
228 radeon_pm_debug_check_in_vbl(rdev, false);
229 radeon_set_memory_clock(rdev, mclk);
230 radeon_pm_debug_check_in_vbl(rdev, true);
231 rdev->pm.current_mclk = mclk;
232 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
233 }
234
235 if (misc_after)
236 /* voltage, pcie lanes, etc.*/
237 radeon_pm_misc(rdev);
238
239 radeon_pm_finish(rdev);
240
241 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
242 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
243 } else
244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
245}
246
247static void radeon_pm_set_clocks(struct radeon_device *rdev)
248{
249 struct drm_crtc *crtc;
250 int i, r;
251
252 /* no need to take locks, etc. if nothing's going to change */
253 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
254 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
255 return;
256
257 down_write(&rdev->pm.mclk_lock);
258 mutex_lock(&rdev->ring_lock);
259
260 /* wait for the rings to drain */
261 for (i = 0; i < RADEON_NUM_RINGS; i++) {
262 struct radeon_ring *ring = &rdev->ring[i];
263 if (!ring->ready) {
264 continue;
265 }
266 r = radeon_fence_wait_empty(rdev, i);
267 if (r) {
268 /* needs a GPU reset dont reset here */
269 mutex_unlock(&rdev->ring_lock);
270 up_write(&rdev->pm.mclk_lock);
271 return;
272 }
273 }
274
275 radeon_unmap_vram_bos(rdev);
276
277 if (rdev->irq.installed) {
278 i = 0;
279 drm_for_each_crtc(crtc, rdev->ddev) {
280 if (rdev->pm.active_crtcs & (1 << i)) {
281 /* This can fail if a modeset is in progress */
282 if (drm_crtc_vblank_get(crtc) == 0)
283 rdev->pm.req_vblank |= (1 << i);
284 else
285 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n",
286 i);
287 }
288 i++;
289 }
290 }
291
292 radeon_set_power_state(rdev);
293
294 if (rdev->irq.installed) {
295 i = 0;
296 drm_for_each_crtc(crtc, rdev->ddev) {
297 if (rdev->pm.req_vblank & (1 << i)) {
298 rdev->pm.req_vblank &= ~(1 << i);
299 drm_crtc_vblank_put(crtc);
300 }
301 i++;
302 }
303 }
304
305 /* update display watermarks based on new power state */
306 radeon_update_bandwidth_info(rdev);
307 if (rdev->pm.active_crtc_count)
308 radeon_bandwidth_update(rdev);
309
310 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
311
312 mutex_unlock(&rdev->ring_lock);
313 up_write(&rdev->pm.mclk_lock);
314}
315
316static void radeon_pm_print_states(struct radeon_device *rdev)
317{
318 int i, j;
319 struct radeon_power_state *power_state;
320 struct radeon_pm_clock_info *clock_info;
321
322 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
323 for (i = 0; i < rdev->pm.num_power_states; i++) {
324 power_state = &rdev->pm.power_state[i];
325 DRM_DEBUG_DRIVER("State %d: %s\n", i,
326 radeon_pm_state_type_name[power_state->type]);
327 if (i == rdev->pm.default_power_state_index)
328 DRM_DEBUG_DRIVER("\tDefault");
329 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
330 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
331 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
332 DRM_DEBUG_DRIVER("\tSingle display only\n");
333 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
334 for (j = 0; j < power_state->num_clock_modes; j++) {
335 clock_info = &(power_state->clock_info[j]);
336 if (rdev->flags & RADEON_IS_IGP)
337 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
338 j,
339 clock_info->sclk * 10);
340 else
341 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
342 j,
343 clock_info->sclk * 10,
344 clock_info->mclk * 10,
345 clock_info->voltage.voltage);
346 }
347 }
348}
349
350static ssize_t radeon_get_pm_profile(struct device *dev,
351 struct device_attribute *attr,
352 char *buf)
353{
354 struct drm_device *ddev = dev_get_drvdata(dev);
355 struct radeon_device *rdev = ddev->dev_private;
356 int cp = rdev->pm.profile;
357
358 return snprintf(buf, PAGE_SIZE, "%s\n",
359 (cp == PM_PROFILE_AUTO) ? "auto" :
360 (cp == PM_PROFILE_LOW) ? "low" :
361 (cp == PM_PROFILE_MID) ? "mid" :
362 (cp == PM_PROFILE_HIGH) ? "high" : "default");
363}
364
365static ssize_t radeon_set_pm_profile(struct device *dev,
366 struct device_attribute *attr,
367 const char *buf,
368 size_t count)
369{
370 struct drm_device *ddev = dev_get_drvdata(dev);
371 struct radeon_device *rdev = ddev->dev_private;
372
373 /* Can't set profile when the card is off */
374 if ((rdev->flags & RADEON_IS_PX) &&
375 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
376 return -EINVAL;
377
378 mutex_lock(&rdev->pm.mutex);
379 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
380 if (strncmp("default", buf, strlen("default")) == 0)
381 rdev->pm.profile = PM_PROFILE_DEFAULT;
382 else if (strncmp("auto", buf, strlen("auto")) == 0)
383 rdev->pm.profile = PM_PROFILE_AUTO;
384 else if (strncmp("low", buf, strlen("low")) == 0)
385 rdev->pm.profile = PM_PROFILE_LOW;
386 else if (strncmp("mid", buf, strlen("mid")) == 0)
387 rdev->pm.profile = PM_PROFILE_MID;
388 else if (strncmp("high", buf, strlen("high")) == 0)
389 rdev->pm.profile = PM_PROFILE_HIGH;
390 else {
391 count = -EINVAL;
392 goto fail;
393 }
394 radeon_pm_update_profile(rdev);
395 radeon_pm_set_clocks(rdev);
396 } else
397 count = -EINVAL;
398
399fail:
400 mutex_unlock(&rdev->pm.mutex);
401
402 return count;
403}
404
405static ssize_t radeon_get_pm_method(struct device *dev,
406 struct device_attribute *attr,
407 char *buf)
408{
409 struct drm_device *ddev = dev_get_drvdata(dev);
410 struct radeon_device *rdev = ddev->dev_private;
411 int pm = rdev->pm.pm_method;
412
413 return snprintf(buf, PAGE_SIZE, "%s\n",
414 (pm == PM_METHOD_DYNPM) ? "dynpm" :
415 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
416}
417
418static ssize_t radeon_set_pm_method(struct device *dev,
419 struct device_attribute *attr,
420 const char *buf,
421 size_t count)
422{
423 struct drm_device *ddev = dev_get_drvdata(dev);
424 struct radeon_device *rdev = ddev->dev_private;
425
426 /* Can't set method when the card is off */
427 if ((rdev->flags & RADEON_IS_PX) &&
428 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
429 count = -EINVAL;
430 goto fail;
431 }
432
433 /* we don't support the legacy modes with dpm */
434 if (rdev->pm.pm_method == PM_METHOD_DPM) {
435 count = -EINVAL;
436 goto fail;
437 }
438
439 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
440 mutex_lock(&rdev->pm.mutex);
441 rdev->pm.pm_method = PM_METHOD_DYNPM;
442 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
443 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
444 mutex_unlock(&rdev->pm.mutex);
445 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
446 mutex_lock(&rdev->pm.mutex);
447 /* disable dynpm */
448 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
449 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
450 rdev->pm.pm_method = PM_METHOD_PROFILE;
451 mutex_unlock(&rdev->pm.mutex);
452 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
453 } else {
454 count = -EINVAL;
455 goto fail;
456 }
457 radeon_pm_compute_clocks(rdev);
458fail:
459 return count;
460}
461
462static ssize_t radeon_get_dpm_state(struct device *dev,
463 struct device_attribute *attr,
464 char *buf)
465{
466 struct drm_device *ddev = dev_get_drvdata(dev);
467 struct radeon_device *rdev = ddev->dev_private;
468 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
469
470 return snprintf(buf, PAGE_SIZE, "%s\n",
471 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
472 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
473}
474
475static ssize_t radeon_set_dpm_state(struct device *dev,
476 struct device_attribute *attr,
477 const char *buf,
478 size_t count)
479{
480 struct drm_device *ddev = dev_get_drvdata(dev);
481 struct radeon_device *rdev = ddev->dev_private;
482
483 mutex_lock(&rdev->pm.mutex);
484 if (strncmp("battery", buf, strlen("battery")) == 0)
485 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
486 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
487 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
488 else if (strncmp("performance", buf, strlen("performance")) == 0)
489 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
490 else {
491 mutex_unlock(&rdev->pm.mutex);
492 count = -EINVAL;
493 goto fail;
494 }
495 mutex_unlock(&rdev->pm.mutex);
496
497 /* Can't set dpm state when the card is off */
498 if (!(rdev->flags & RADEON_IS_PX) ||
499 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
500 radeon_pm_compute_clocks(rdev);
501
502fail:
503 return count;
504}
505
506static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
507 struct device_attribute *attr,
508 char *buf)
509{
510 struct drm_device *ddev = dev_get_drvdata(dev);
511 struct radeon_device *rdev = ddev->dev_private;
512 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
513
514 if ((rdev->flags & RADEON_IS_PX) &&
515 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
516 return snprintf(buf, PAGE_SIZE, "off\n");
517
518 return snprintf(buf, PAGE_SIZE, "%s\n",
519 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
520 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
521}
522
523static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
524 struct device_attribute *attr,
525 const char *buf,
526 size_t count)
527{
528 struct drm_device *ddev = dev_get_drvdata(dev);
529 struct radeon_device *rdev = ddev->dev_private;
530 enum radeon_dpm_forced_level level;
531 int ret = 0;
532
533 /* Can't force performance level when the card is off */
534 if ((rdev->flags & RADEON_IS_PX) &&
535 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
536 return -EINVAL;
537
538 mutex_lock(&rdev->pm.mutex);
539 if (strncmp("low", buf, strlen("low")) == 0) {
540 level = RADEON_DPM_FORCED_LEVEL_LOW;
541 } else if (strncmp("high", buf, strlen("high")) == 0) {
542 level = RADEON_DPM_FORCED_LEVEL_HIGH;
543 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
544 level = RADEON_DPM_FORCED_LEVEL_AUTO;
545 } else {
546 count = -EINVAL;
547 goto fail;
548 }
549 if (rdev->asic->dpm.force_performance_level) {
550 if (rdev->pm.dpm.thermal_active) {
551 count = -EINVAL;
552 goto fail;
553 }
554 ret = radeon_dpm_force_performance_level(rdev, level);
555 if (ret)
556 count = -EINVAL;
557 }
558fail:
559 mutex_unlock(&rdev->pm.mutex);
560
561 return count;
562}
563
564static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
565 struct device_attribute *attr,
566 char *buf)
567{
568 struct radeon_device *rdev = dev_get_drvdata(dev);
569 u32 pwm_mode = 0;
570
571 if (rdev->asic->dpm.fan_ctrl_get_mode)
572 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
573
574 /* never 0 (full-speed), fuse or smc-controlled always */
575 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
576}
577
578static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
579 struct device_attribute *attr,
580 const char *buf,
581 size_t count)
582{
583 struct radeon_device *rdev = dev_get_drvdata(dev);
584 int err;
585 int value;
586
587 if(!rdev->asic->dpm.fan_ctrl_set_mode)
588 return -EINVAL;
589
590 err = kstrtoint(buf, 10, &value);
591 if (err)
592 return err;
593
594 switch (value) {
595 case 1: /* manual, percent-based */
596 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
597 break;
598 default: /* disable */
599 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
600 break;
601 }
602
603 return count;
604}
605
606static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
607 struct device_attribute *attr,
608 char *buf)
609{
610 return sprintf(buf, "%i\n", 0);
611}
612
613static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
614 struct device_attribute *attr,
615 char *buf)
616{
617 return sprintf(buf, "%i\n", 255);
618}
619
620static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
621 struct device_attribute *attr,
622 const char *buf, size_t count)
623{
624 struct radeon_device *rdev = dev_get_drvdata(dev);
625 int err;
626 u32 value;
627
628 err = kstrtou32(buf, 10, &value);
629 if (err)
630 return err;
631
632 value = (value * 100) / 255;
633
634 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
635 if (err)
636 return err;
637
638 return count;
639}
640
641static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
642 struct device_attribute *attr,
643 char *buf)
644{
645 struct radeon_device *rdev = dev_get_drvdata(dev);
646 int err;
647 u32 speed;
648
649 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
650 if (err)
651 return err;
652
653 speed = (speed * 255) / 100;
654
655 return sprintf(buf, "%i\n", speed);
656}
657
658static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
659static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
660static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
661static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
662 radeon_get_dpm_forced_performance_level,
663 radeon_set_dpm_forced_performance_level);
664
665static ssize_t radeon_hwmon_show_temp(struct device *dev,
666 struct device_attribute *attr,
667 char *buf)
668{
669 struct radeon_device *rdev = dev_get_drvdata(dev);
670 struct drm_device *ddev = rdev->ddev;
671 int temp;
672
673 /* Can't get temperature when the card is off */
674 if ((rdev->flags & RADEON_IS_PX) &&
675 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
676 return -EINVAL;
677
678 if (rdev->asic->pm.get_temperature)
679 temp = radeon_get_temperature(rdev);
680 else
681 temp = 0;
682
683 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
684}
685
686static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
687 struct device_attribute *attr,
688 char *buf)
689{
690 struct radeon_device *rdev = dev_get_drvdata(dev);
691 int hyst = to_sensor_dev_attr(attr)->index;
692 int temp;
693
694 if (hyst)
695 temp = rdev->pm.dpm.thermal.min_temp;
696 else
697 temp = rdev->pm.dpm.thermal.max_temp;
698
699 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
700}
701
702static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
703static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
704static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
705static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
706static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
707static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
708static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
709
710
711static struct attribute *hwmon_attributes[] = {
712 &sensor_dev_attr_temp1_input.dev_attr.attr,
713 &sensor_dev_attr_temp1_crit.dev_attr.attr,
714 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
715 &sensor_dev_attr_pwm1.dev_attr.attr,
716 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
717 &sensor_dev_attr_pwm1_min.dev_attr.attr,
718 &sensor_dev_attr_pwm1_max.dev_attr.attr,
719 NULL
720};
721
722static umode_t hwmon_attributes_visible(struct kobject *kobj,
723 struct attribute *attr, int index)
724{
725 struct device *dev = kobj_to_dev(kobj);
726 struct radeon_device *rdev = dev_get_drvdata(dev);
727 umode_t effective_mode = attr->mode;
728
729 /* Skip attributes if DPM is not enabled */
730 if (rdev->pm.pm_method != PM_METHOD_DPM &&
731 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
732 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
733 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
734 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
735 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
736 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
737 return 0;
738
739 /* Skip fan attributes if fan is not present */
740 if (rdev->pm.no_fan &&
741 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
742 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
743 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
744 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
745 return 0;
746
747 /* mask fan attributes if we have no bindings for this asic to expose */
748 if ((!rdev->asic->dpm.get_fan_speed_percent &&
749 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
750 (!rdev->asic->dpm.fan_ctrl_get_mode &&
751 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
752 effective_mode &= ~S_IRUGO;
753
754 if ((!rdev->asic->dpm.set_fan_speed_percent &&
755 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
756 (!rdev->asic->dpm.fan_ctrl_set_mode &&
757 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
758 effective_mode &= ~S_IWUSR;
759
760 /* hide max/min values if we can't both query and manage the fan */
761 if ((!rdev->asic->dpm.set_fan_speed_percent &&
762 !rdev->asic->dpm.get_fan_speed_percent) &&
763 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
764 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
765 return 0;
766
767 return effective_mode;
768}
769
770static const struct attribute_group hwmon_attrgroup = {
771 .attrs = hwmon_attributes,
772 .is_visible = hwmon_attributes_visible,
773};
774
775static const struct attribute_group *hwmon_groups[] = {
776 &hwmon_attrgroup,
777 NULL
778};
779
780static int radeon_hwmon_init(struct radeon_device *rdev)
781{
782 int err = 0;
783
784 switch (rdev->pm.int_thermal_type) {
785 case THERMAL_TYPE_RV6XX:
786 case THERMAL_TYPE_RV770:
787 case THERMAL_TYPE_EVERGREEN:
788 case THERMAL_TYPE_NI:
789 case THERMAL_TYPE_SUMO:
790 case THERMAL_TYPE_SI:
791 case THERMAL_TYPE_CI:
792 case THERMAL_TYPE_KV:
793 if (rdev->asic->pm.get_temperature == NULL)
794 return err;
795 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
796 "radeon", rdev,
797 hwmon_groups);
798 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
799 err = PTR_ERR(rdev->pm.int_hwmon_dev);
800 dev_err(rdev->dev,
801 "Unable to register hwmon device: %d\n", err);
802 }
803 break;
804 default:
805 break;
806 }
807
808 return err;
809}
810
811static void radeon_hwmon_fini(struct radeon_device *rdev)
812{
813 if (rdev->pm.int_hwmon_dev)
814 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
815}
816
817static void radeon_dpm_thermal_work_handler(struct work_struct *work)
818{
819 struct radeon_device *rdev =
820 container_of(work, struct radeon_device,
821 pm.dpm.thermal.work);
822 /* switch to the thermal state */
823 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
824
825 if (!rdev->pm.dpm_enabled)
826 return;
827
828 if (rdev->asic->pm.get_temperature) {
829 int temp = radeon_get_temperature(rdev);
830
831 if (temp < rdev->pm.dpm.thermal.min_temp)
832 /* switch back the user state */
833 dpm_state = rdev->pm.dpm.user_state;
834 } else {
835 if (rdev->pm.dpm.thermal.high_to_low)
836 /* switch back the user state */
837 dpm_state = rdev->pm.dpm.user_state;
838 }
839 mutex_lock(&rdev->pm.mutex);
840 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
841 rdev->pm.dpm.thermal_active = true;
842 else
843 rdev->pm.dpm.thermal_active = false;
844 rdev->pm.dpm.state = dpm_state;
845 mutex_unlock(&rdev->pm.mutex);
846
847 radeon_pm_compute_clocks(rdev);
848}
849
850static bool radeon_dpm_single_display(struct radeon_device *rdev)
851{
852 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
853 true : false;
854
855 /* check if the vblank period is too short to adjust the mclk */
856 if (single_display && rdev->asic->dpm.vblank_too_short) {
857 if (radeon_dpm_vblank_too_short(rdev))
858 single_display = false;
859 }
860
861 /* 120hz tends to be problematic even if they are under the
862 * vblank limit.
863 */
864 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
865 single_display = false;
866
867 return single_display;
868}
869
870static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
871 enum radeon_pm_state_type dpm_state)
872{
873 int i;
874 struct radeon_ps *ps;
875 u32 ui_class;
876 bool single_display = radeon_dpm_single_display(rdev);
877
878 /* certain older asics have a separare 3D performance state,
879 * so try that first if the user selected performance
880 */
881 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
882 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
883 /* balanced states don't exist at the moment */
884 if (dpm_state == POWER_STATE_TYPE_BALANCED)
885 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
886
887restart_search:
888 /* Pick the best power state based on current conditions */
889 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
890 ps = &rdev->pm.dpm.ps[i];
891 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
892 switch (dpm_state) {
893 /* user states */
894 case POWER_STATE_TYPE_BATTERY:
895 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
896 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
897 if (single_display)
898 return ps;
899 } else
900 return ps;
901 }
902 break;
903 case POWER_STATE_TYPE_BALANCED:
904 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
905 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
906 if (single_display)
907 return ps;
908 } else
909 return ps;
910 }
911 break;
912 case POWER_STATE_TYPE_PERFORMANCE:
913 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
914 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
915 if (single_display)
916 return ps;
917 } else
918 return ps;
919 }
920 break;
921 /* internal states */
922 case POWER_STATE_TYPE_INTERNAL_UVD:
923 if (rdev->pm.dpm.uvd_ps)
924 return rdev->pm.dpm.uvd_ps;
925 else
926 break;
927 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
928 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
929 return ps;
930 break;
931 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
932 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
933 return ps;
934 break;
935 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
936 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
937 return ps;
938 break;
939 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
940 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
941 return ps;
942 break;
943 case POWER_STATE_TYPE_INTERNAL_BOOT:
944 return rdev->pm.dpm.boot_ps;
945 case POWER_STATE_TYPE_INTERNAL_THERMAL:
946 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
947 return ps;
948 break;
949 case POWER_STATE_TYPE_INTERNAL_ACPI:
950 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
951 return ps;
952 break;
953 case POWER_STATE_TYPE_INTERNAL_ULV:
954 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
955 return ps;
956 break;
957 case POWER_STATE_TYPE_INTERNAL_3DPERF:
958 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
959 return ps;
960 break;
961 default:
962 break;
963 }
964 }
965 /* use a fallback state if we didn't match */
966 switch (dpm_state) {
967 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
968 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
969 goto restart_search;
970 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
971 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
972 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
973 if (rdev->pm.dpm.uvd_ps) {
974 return rdev->pm.dpm.uvd_ps;
975 } else {
976 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
977 goto restart_search;
978 }
979 case POWER_STATE_TYPE_INTERNAL_THERMAL:
980 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
981 goto restart_search;
982 case POWER_STATE_TYPE_INTERNAL_ACPI:
983 dpm_state = POWER_STATE_TYPE_BATTERY;
984 goto restart_search;
985 case POWER_STATE_TYPE_BATTERY:
986 case POWER_STATE_TYPE_BALANCED:
987 case POWER_STATE_TYPE_INTERNAL_3DPERF:
988 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
989 goto restart_search;
990 default:
991 break;
992 }
993
994 return NULL;
995}
996
997static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
998{
999 int i;
1000 struct radeon_ps *ps;
1001 enum radeon_pm_state_type dpm_state;
1002 int ret;
1003 bool single_display = radeon_dpm_single_display(rdev);
1004
1005 /* if dpm init failed */
1006 if (!rdev->pm.dpm_enabled)
1007 return;
1008
1009 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1010 /* add other state override checks here */
1011 if ((!rdev->pm.dpm.thermal_active) &&
1012 (!rdev->pm.dpm.uvd_active))
1013 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1014 }
1015 dpm_state = rdev->pm.dpm.state;
1016
1017 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1018 if (ps)
1019 rdev->pm.dpm.requested_ps = ps;
1020 else
1021 return;
1022
1023 /* no need to reprogram if nothing changed unless we are on BTC+ */
1024 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1025 /* vce just modifies an existing state so force a change */
1026 if (ps->vce_active != rdev->pm.dpm.vce_active)
1027 goto force;
1028 /* user has made a display change (such as timing) */
1029 if (rdev->pm.dpm.single_display != single_display)
1030 goto force;
1031 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1032 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1033 * all we need to do is update the display configuration.
1034 */
1035 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1036 /* update display watermarks based on new power state */
1037 radeon_bandwidth_update(rdev);
1038 /* update displays */
1039 radeon_dpm_display_configuration_changed(rdev);
1040 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1041 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1042 }
1043 return;
1044 } else {
1045 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1046 * nothing to do, if the num crtcs is > 1 and state is the same,
1047 * update display configuration.
1048 */
1049 if (rdev->pm.dpm.new_active_crtcs ==
1050 rdev->pm.dpm.current_active_crtcs) {
1051 return;
1052 } else {
1053 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1054 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1055 /* update display watermarks based on new power state */
1056 radeon_bandwidth_update(rdev);
1057 /* update displays */
1058 radeon_dpm_display_configuration_changed(rdev);
1059 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1060 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1061 return;
1062 }
1063 }
1064 }
1065 }
1066
1067force:
1068 if (radeon_dpm == 1) {
1069 printk("switching from power state:\n");
1070 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1071 printk("switching to power state:\n");
1072 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1073 }
1074
1075 down_write(&rdev->pm.mclk_lock);
1076 mutex_lock(&rdev->ring_lock);
1077
1078 /* update whether vce is active */
1079 ps->vce_active = rdev->pm.dpm.vce_active;
1080
1081 ret = radeon_dpm_pre_set_power_state(rdev);
1082 if (ret)
1083 goto done;
1084
1085 /* update display watermarks based on new power state */
1086 radeon_bandwidth_update(rdev);
1087 /* update displays */
1088 radeon_dpm_display_configuration_changed(rdev);
1089
1090 /* wait for the rings to drain */
1091 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1092 struct radeon_ring *ring = &rdev->ring[i];
1093 if (ring->ready)
1094 radeon_fence_wait_empty(rdev, i);
1095 }
1096
1097 /* program the new power state */
1098 radeon_dpm_set_power_state(rdev);
1099
1100 /* update current power state */
1101 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1102
1103 radeon_dpm_post_set_power_state(rdev);
1104
1105 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1106 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1107 rdev->pm.dpm.single_display = single_display;
1108
1109 if (rdev->asic->dpm.force_performance_level) {
1110 if (rdev->pm.dpm.thermal_active) {
1111 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1112 /* force low perf level for thermal */
1113 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1114 /* save the user's level */
1115 rdev->pm.dpm.forced_level = level;
1116 } else {
1117 /* otherwise, user selected level */
1118 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1119 }
1120 }
1121
1122done:
1123 mutex_unlock(&rdev->ring_lock);
1124 up_write(&rdev->pm.mclk_lock);
1125}
1126
1127void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1128{
1129 enum radeon_pm_state_type dpm_state;
1130
1131 if (rdev->asic->dpm.powergate_uvd) {
1132 mutex_lock(&rdev->pm.mutex);
1133 /* don't powergate anything if we
1134 have active but pause streams */
1135 enable |= rdev->pm.dpm.sd > 0;
1136 enable |= rdev->pm.dpm.hd > 0;
1137 /* enable/disable UVD */
1138 radeon_dpm_powergate_uvd(rdev, !enable);
1139 mutex_unlock(&rdev->pm.mutex);
1140 } else {
1141 if (enable) {
1142 mutex_lock(&rdev->pm.mutex);
1143 rdev->pm.dpm.uvd_active = true;
1144 /* disable this for now */
1145#if 0
1146 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1147 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1148 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1149 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1150 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1151 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1152 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1153 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1154 else
1155#endif
1156 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1157 rdev->pm.dpm.state = dpm_state;
1158 mutex_unlock(&rdev->pm.mutex);
1159 } else {
1160 mutex_lock(&rdev->pm.mutex);
1161 rdev->pm.dpm.uvd_active = false;
1162 mutex_unlock(&rdev->pm.mutex);
1163 }
1164
1165 radeon_pm_compute_clocks(rdev);
1166 }
1167}
1168
1169void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1170{
1171 if (enable) {
1172 mutex_lock(&rdev->pm.mutex);
1173 rdev->pm.dpm.vce_active = true;
1174 /* XXX select vce level based on ring/task */
1175 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1176 mutex_unlock(&rdev->pm.mutex);
1177 } else {
1178 mutex_lock(&rdev->pm.mutex);
1179 rdev->pm.dpm.vce_active = false;
1180 mutex_unlock(&rdev->pm.mutex);
1181 }
1182
1183 radeon_pm_compute_clocks(rdev);
1184}
1185
1186static void radeon_pm_suspend_old(struct radeon_device *rdev)
1187{
1188 mutex_lock(&rdev->pm.mutex);
1189 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1190 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1191 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1192 }
1193 mutex_unlock(&rdev->pm.mutex);
1194
1195 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1196}
1197
1198static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1199{
1200 mutex_lock(&rdev->pm.mutex);
1201 /* disable dpm */
1202 radeon_dpm_disable(rdev);
1203 /* reset the power state */
1204 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1205 rdev->pm.dpm_enabled = false;
1206 mutex_unlock(&rdev->pm.mutex);
1207}
1208
1209void radeon_pm_suspend(struct radeon_device *rdev)
1210{
1211 if (rdev->pm.pm_method == PM_METHOD_DPM)
1212 radeon_pm_suspend_dpm(rdev);
1213 else
1214 radeon_pm_suspend_old(rdev);
1215}
1216
1217static void radeon_pm_resume_old(struct radeon_device *rdev)
1218{
1219 /* set up the default clocks if the MC ucode is loaded */
1220 if ((rdev->family >= CHIP_BARTS) &&
1221 (rdev->family <= CHIP_CAYMAN) &&
1222 rdev->mc_fw) {
1223 if (rdev->pm.default_vddc)
1224 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1225 SET_VOLTAGE_TYPE_ASIC_VDDC);
1226 if (rdev->pm.default_vddci)
1227 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1228 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1229 if (rdev->pm.default_sclk)
1230 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1231 if (rdev->pm.default_mclk)
1232 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1233 }
1234 /* asic init will reset the default power state */
1235 mutex_lock(&rdev->pm.mutex);
1236 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1237 rdev->pm.current_clock_mode_index = 0;
1238 rdev->pm.current_sclk = rdev->pm.default_sclk;
1239 rdev->pm.current_mclk = rdev->pm.default_mclk;
1240 if (rdev->pm.power_state) {
1241 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1242 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1243 }
1244 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1245 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1246 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1247 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1248 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1249 }
1250 mutex_unlock(&rdev->pm.mutex);
1251 radeon_pm_compute_clocks(rdev);
1252}
1253
1254static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1255{
1256 int ret;
1257
1258 /* asic init will reset to the boot state */
1259 mutex_lock(&rdev->pm.mutex);
1260 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1261 radeon_dpm_setup_asic(rdev);
1262 ret = radeon_dpm_enable(rdev);
1263 mutex_unlock(&rdev->pm.mutex);
1264 if (ret)
1265 goto dpm_resume_fail;
1266 rdev->pm.dpm_enabled = true;
1267 return;
1268
1269dpm_resume_fail:
1270 DRM_ERROR("radeon: dpm resume failed\n");
1271 if ((rdev->family >= CHIP_BARTS) &&
1272 (rdev->family <= CHIP_CAYMAN) &&
1273 rdev->mc_fw) {
1274 if (rdev->pm.default_vddc)
1275 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1276 SET_VOLTAGE_TYPE_ASIC_VDDC);
1277 if (rdev->pm.default_vddci)
1278 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1279 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1280 if (rdev->pm.default_sclk)
1281 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1282 if (rdev->pm.default_mclk)
1283 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1284 }
1285}
1286
1287void radeon_pm_resume(struct radeon_device *rdev)
1288{
1289 if (rdev->pm.pm_method == PM_METHOD_DPM)
1290 radeon_pm_resume_dpm(rdev);
1291 else
1292 radeon_pm_resume_old(rdev);
1293}
1294
1295static int radeon_pm_init_old(struct radeon_device *rdev)
1296{
1297 int ret;
1298
1299 rdev->pm.profile = PM_PROFILE_DEFAULT;
1300 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1301 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1302 rdev->pm.dynpm_can_upclock = true;
1303 rdev->pm.dynpm_can_downclock = true;
1304 rdev->pm.default_sclk = rdev->clock.default_sclk;
1305 rdev->pm.default_mclk = rdev->clock.default_mclk;
1306 rdev->pm.current_sclk = rdev->clock.default_sclk;
1307 rdev->pm.current_mclk = rdev->clock.default_mclk;
1308 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1309
1310 if (rdev->bios) {
1311 if (rdev->is_atom_bios)
1312 radeon_atombios_get_power_modes(rdev);
1313 else
1314 radeon_combios_get_power_modes(rdev);
1315 radeon_pm_print_states(rdev);
1316 radeon_pm_init_profile(rdev);
1317 /* set up the default clocks if the MC ucode is loaded */
1318 if ((rdev->family >= CHIP_BARTS) &&
1319 (rdev->family <= CHIP_CAYMAN) &&
1320 rdev->mc_fw) {
1321 if (rdev->pm.default_vddc)
1322 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1323 SET_VOLTAGE_TYPE_ASIC_VDDC);
1324 if (rdev->pm.default_vddci)
1325 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1326 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1327 if (rdev->pm.default_sclk)
1328 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1329 if (rdev->pm.default_mclk)
1330 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1331 }
1332 }
1333
1334 /* set up the internal thermal sensor if applicable */
1335 ret = radeon_hwmon_init(rdev);
1336 if (ret)
1337 return ret;
1338
1339 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1340
1341 if (rdev->pm.num_power_states > 1) {
1342 if (radeon_debugfs_pm_init(rdev)) {
1343 DRM_ERROR("Failed to register debugfs file for PM!\n");
1344 }
1345
1346 DRM_INFO("radeon: power management initialized\n");
1347 }
1348
1349 return 0;
1350}
1351
1352static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1353{
1354 int i;
1355
1356 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1357 printk("== power state %d ==\n", i);
1358 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1359 }
1360}
1361
1362static int radeon_pm_init_dpm(struct radeon_device *rdev)
1363{
1364 int ret;
1365
1366 /* default to balanced state */
1367 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1368 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1369 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1370 rdev->pm.default_sclk = rdev->clock.default_sclk;
1371 rdev->pm.default_mclk = rdev->clock.default_mclk;
1372 rdev->pm.current_sclk = rdev->clock.default_sclk;
1373 rdev->pm.current_mclk = rdev->clock.default_mclk;
1374 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1375
1376 if (rdev->bios && rdev->is_atom_bios)
1377 radeon_atombios_get_power_modes(rdev);
1378 else
1379 return -EINVAL;
1380
1381 /* set up the internal thermal sensor if applicable */
1382 ret = radeon_hwmon_init(rdev);
1383 if (ret)
1384 return ret;
1385
1386 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1387 mutex_lock(&rdev->pm.mutex);
1388 radeon_dpm_init(rdev);
1389 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1390 if (radeon_dpm == 1)
1391 radeon_dpm_print_power_states(rdev);
1392 radeon_dpm_setup_asic(rdev);
1393 ret = radeon_dpm_enable(rdev);
1394 mutex_unlock(&rdev->pm.mutex);
1395 if (ret)
1396 goto dpm_failed;
1397 rdev->pm.dpm_enabled = true;
1398
1399 if (radeon_debugfs_pm_init(rdev)) {
1400 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1401 }
1402
1403 DRM_INFO("radeon: dpm initialized\n");
1404
1405 return 0;
1406
1407dpm_failed:
1408 rdev->pm.dpm_enabled = false;
1409 if ((rdev->family >= CHIP_BARTS) &&
1410 (rdev->family <= CHIP_CAYMAN) &&
1411 rdev->mc_fw) {
1412 if (rdev->pm.default_vddc)
1413 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1414 SET_VOLTAGE_TYPE_ASIC_VDDC);
1415 if (rdev->pm.default_vddci)
1416 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1417 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1418 if (rdev->pm.default_sclk)
1419 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1420 if (rdev->pm.default_mclk)
1421 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1422 }
1423 DRM_ERROR("radeon: dpm initialization failed\n");
1424 return ret;
1425}
1426
1427struct radeon_dpm_quirk {
1428 u32 chip_vendor;
1429 u32 chip_device;
1430 u32 subsys_vendor;
1431 u32 subsys_device;
1432};
1433
1434/* cards with dpm stability problems */
1435static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1436 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1437 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1438 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1439 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1440 { 0, 0, 0, 0 },
1441};
1442
1443int radeon_pm_init(struct radeon_device *rdev)
1444{
1445 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1446 bool disable_dpm = false;
1447
1448 /* Apply dpm quirks */
1449 while (p && p->chip_device != 0) {
1450 if (rdev->pdev->vendor == p->chip_vendor &&
1451 rdev->pdev->device == p->chip_device &&
1452 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1453 rdev->pdev->subsystem_device == p->subsys_device) {
1454 disable_dpm = true;
1455 break;
1456 }
1457 ++p;
1458 }
1459
1460 /* enable dpm on rv6xx+ */
1461 switch (rdev->family) {
1462 case CHIP_RV610:
1463 case CHIP_RV630:
1464 case CHIP_RV620:
1465 case CHIP_RV635:
1466 case CHIP_RV670:
1467 case CHIP_RS780:
1468 case CHIP_RS880:
1469 case CHIP_RV770:
1470 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1471 if (!rdev->rlc_fw)
1472 rdev->pm.pm_method = PM_METHOD_PROFILE;
1473 else if ((rdev->family >= CHIP_RV770) &&
1474 (!(rdev->flags & RADEON_IS_IGP)) &&
1475 (!rdev->smc_fw))
1476 rdev->pm.pm_method = PM_METHOD_PROFILE;
1477 else if (radeon_dpm == 1)
1478 rdev->pm.pm_method = PM_METHOD_DPM;
1479 else
1480 rdev->pm.pm_method = PM_METHOD_PROFILE;
1481 break;
1482 case CHIP_RV730:
1483 case CHIP_RV710:
1484 case CHIP_RV740:
1485 case CHIP_CEDAR:
1486 case CHIP_REDWOOD:
1487 case CHIP_JUNIPER:
1488 case CHIP_CYPRESS:
1489 case CHIP_HEMLOCK:
1490 case CHIP_PALM:
1491 case CHIP_SUMO:
1492 case CHIP_SUMO2:
1493 case CHIP_BARTS:
1494 case CHIP_TURKS:
1495 case CHIP_CAICOS:
1496 case CHIP_CAYMAN:
1497 case CHIP_ARUBA:
1498 case CHIP_TAHITI:
1499 case CHIP_PITCAIRN:
1500 case CHIP_VERDE:
1501 case CHIP_OLAND:
1502 case CHIP_HAINAN:
1503 case CHIP_BONAIRE:
1504 case CHIP_KABINI:
1505 case CHIP_KAVERI:
1506 case CHIP_HAWAII:
1507 case CHIP_MULLINS:
1508 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1509 if (!rdev->rlc_fw)
1510 rdev->pm.pm_method = PM_METHOD_PROFILE;
1511 else if ((rdev->family >= CHIP_RV770) &&
1512 (!(rdev->flags & RADEON_IS_IGP)) &&
1513 (!rdev->smc_fw))
1514 rdev->pm.pm_method = PM_METHOD_PROFILE;
1515 else if (disable_dpm && (radeon_dpm == -1))
1516 rdev->pm.pm_method = PM_METHOD_PROFILE;
1517 else if (radeon_dpm == 0)
1518 rdev->pm.pm_method = PM_METHOD_PROFILE;
1519 else
1520 rdev->pm.pm_method = PM_METHOD_DPM;
1521 break;
1522 default:
1523 /* default to profile method */
1524 rdev->pm.pm_method = PM_METHOD_PROFILE;
1525 break;
1526 }
1527
1528 if (rdev->pm.pm_method == PM_METHOD_DPM)
1529 return radeon_pm_init_dpm(rdev);
1530 else
1531 return radeon_pm_init_old(rdev);
1532}
1533
1534int radeon_pm_late_init(struct radeon_device *rdev)
1535{
1536 int ret = 0;
1537
1538 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1539 if (rdev->pm.dpm_enabled) {
1540 if (!rdev->pm.sysfs_initialized) {
1541 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1542 if (ret)
1543 DRM_ERROR("failed to create device file for dpm state\n");
1544 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1545 if (ret)
1546 DRM_ERROR("failed to create device file for dpm state\n");
1547 /* XXX: these are noops for dpm but are here for backwards compat */
1548 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1549 if (ret)
1550 DRM_ERROR("failed to create device file for power profile\n");
1551 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1552 if (ret)
1553 DRM_ERROR("failed to create device file for power method\n");
1554 rdev->pm.sysfs_initialized = true;
1555 }
1556
1557 mutex_lock(&rdev->pm.mutex);
1558 ret = radeon_dpm_late_enable(rdev);
1559 mutex_unlock(&rdev->pm.mutex);
1560 if (ret) {
1561 rdev->pm.dpm_enabled = false;
1562 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1563 } else {
1564 /* set the dpm state for PX since there won't be
1565 * a modeset to call this.
1566 */
1567 radeon_pm_compute_clocks(rdev);
1568 }
1569 }
1570 } else {
1571 if ((rdev->pm.num_power_states > 1) &&
1572 (!rdev->pm.sysfs_initialized)) {
1573 /* where's the best place to put these? */
1574 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1575 if (ret)
1576 DRM_ERROR("failed to create device file for power profile\n");
1577 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1578 if (ret)
1579 DRM_ERROR("failed to create device file for power method\n");
1580 if (!ret)
1581 rdev->pm.sysfs_initialized = true;
1582 }
1583 }
1584 return ret;
1585}
1586
1587static void radeon_pm_fini_old(struct radeon_device *rdev)
1588{
1589 if (rdev->pm.num_power_states > 1) {
1590 mutex_lock(&rdev->pm.mutex);
1591 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1592 rdev->pm.profile = PM_PROFILE_DEFAULT;
1593 radeon_pm_update_profile(rdev);
1594 radeon_pm_set_clocks(rdev);
1595 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1596 /* reset default clocks */
1597 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1598 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1599 radeon_pm_set_clocks(rdev);
1600 }
1601 mutex_unlock(&rdev->pm.mutex);
1602
1603 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1604
1605 device_remove_file(rdev->dev, &dev_attr_power_profile);
1606 device_remove_file(rdev->dev, &dev_attr_power_method);
1607 }
1608
1609 radeon_hwmon_fini(rdev);
1610 kfree(rdev->pm.power_state);
1611}
1612
1613static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1614{
1615 if (rdev->pm.num_power_states > 1) {
1616 mutex_lock(&rdev->pm.mutex);
1617 radeon_dpm_disable(rdev);
1618 mutex_unlock(&rdev->pm.mutex);
1619
1620 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1621 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1622 /* XXX backwards compat */
1623 device_remove_file(rdev->dev, &dev_attr_power_profile);
1624 device_remove_file(rdev->dev, &dev_attr_power_method);
1625 }
1626 radeon_dpm_fini(rdev);
1627
1628 radeon_hwmon_fini(rdev);
1629 kfree(rdev->pm.power_state);
1630}
1631
1632void radeon_pm_fini(struct radeon_device *rdev)
1633{
1634 if (rdev->pm.pm_method == PM_METHOD_DPM)
1635 radeon_pm_fini_dpm(rdev);
1636 else
1637 radeon_pm_fini_old(rdev);
1638}
1639
1640static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1641{
1642 struct drm_device *ddev = rdev->ddev;
1643 struct drm_crtc *crtc;
1644 struct radeon_crtc *radeon_crtc;
1645
1646 if (rdev->pm.num_power_states < 2)
1647 return;
1648
1649 mutex_lock(&rdev->pm.mutex);
1650
1651 rdev->pm.active_crtcs = 0;
1652 rdev->pm.active_crtc_count = 0;
1653 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1654 list_for_each_entry(crtc,
1655 &ddev->mode_config.crtc_list, head) {
1656 radeon_crtc = to_radeon_crtc(crtc);
1657 if (radeon_crtc->enabled) {
1658 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1659 rdev->pm.active_crtc_count++;
1660 }
1661 }
1662 }
1663
1664 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1665 radeon_pm_update_profile(rdev);
1666 radeon_pm_set_clocks(rdev);
1667 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1668 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1669 if (rdev->pm.active_crtc_count > 1) {
1670 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1671 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1672
1673 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1674 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1675 radeon_pm_get_dynpm_state(rdev);
1676 radeon_pm_set_clocks(rdev);
1677
1678 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1679 }
1680 } else if (rdev->pm.active_crtc_count == 1) {
1681 /* TODO: Increase clocks if needed for current mode */
1682
1683 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1684 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1685 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1686 radeon_pm_get_dynpm_state(rdev);
1687 radeon_pm_set_clocks(rdev);
1688
1689 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1690 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1691 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1692 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1693 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1694 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1695 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1696 }
1697 } else { /* count == 0 */
1698 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1699 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1700
1701 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1702 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1703 radeon_pm_get_dynpm_state(rdev);
1704 radeon_pm_set_clocks(rdev);
1705 }
1706 }
1707 }
1708 }
1709
1710 mutex_unlock(&rdev->pm.mutex);
1711}
1712
1713static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1714{
1715 struct drm_device *ddev = rdev->ddev;
1716 struct drm_crtc *crtc;
1717 struct radeon_crtc *radeon_crtc;
1718
1719 if (!rdev->pm.dpm_enabled)
1720 return;
1721
1722 mutex_lock(&rdev->pm.mutex);
1723
1724 /* update active crtc counts */
1725 rdev->pm.dpm.new_active_crtcs = 0;
1726 rdev->pm.dpm.new_active_crtc_count = 0;
1727 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1728 list_for_each_entry(crtc,
1729 &ddev->mode_config.crtc_list, head) {
1730 radeon_crtc = to_radeon_crtc(crtc);
1731 if (crtc->enabled) {
1732 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1733 rdev->pm.dpm.new_active_crtc_count++;
1734 }
1735 }
1736 }
1737
1738 /* update battery/ac status */
1739 if (power_supply_is_system_supplied() > 0)
1740 rdev->pm.dpm.ac_power = true;
1741 else
1742 rdev->pm.dpm.ac_power = false;
1743
1744 radeon_dpm_change_power_state_locked(rdev);
1745
1746 mutex_unlock(&rdev->pm.mutex);
1747
1748}
1749
1750void radeon_pm_compute_clocks(struct radeon_device *rdev)
1751{
1752 if (rdev->pm.pm_method == PM_METHOD_DPM)
1753 radeon_pm_compute_clocks_dpm(rdev);
1754 else
1755 radeon_pm_compute_clocks_old(rdev);
1756}
1757
1758static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1759{
1760 int crtc, vpos, hpos, vbl_status;
1761 bool in_vbl = true;
1762
1763 /* Iterate over all active crtc's. All crtc's must be in vblank,
1764 * otherwise return in_vbl == false.
1765 */
1766 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1767 if (rdev->pm.active_crtcs & (1 << crtc)) {
1768 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev,
1769 crtc,
1770 USE_REAL_VBLANKSTART,
1771 &vpos, &hpos, NULL, NULL,
1772 &rdev->mode_info.crtcs[crtc]->base.hwmode);
1773 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1774 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1775 in_vbl = false;
1776 }
1777 }
1778
1779 return in_vbl;
1780}
1781
1782static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1783{
1784 u32 stat_crtc = 0;
1785 bool in_vbl = radeon_pm_in_vbl(rdev);
1786
1787 if (in_vbl == false)
1788 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1789 finish ? "exit" : "entry");
1790 return in_vbl;
1791}
1792
1793static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1794{
1795 struct radeon_device *rdev;
1796 int resched;
1797 rdev = container_of(work, struct radeon_device,
1798 pm.dynpm_idle_work.work);
1799
1800 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1801 mutex_lock(&rdev->pm.mutex);
1802 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1803 int not_processed = 0;
1804 int i;
1805
1806 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1807 struct radeon_ring *ring = &rdev->ring[i];
1808
1809 if (ring->ready) {
1810 not_processed += radeon_fence_count_emitted(rdev, i);
1811 if (not_processed >= 3)
1812 break;
1813 }
1814 }
1815
1816 if (not_processed >= 3) { /* should upclock */
1817 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1818 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1819 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1820 rdev->pm.dynpm_can_upclock) {
1821 rdev->pm.dynpm_planned_action =
1822 DYNPM_ACTION_UPCLOCK;
1823 rdev->pm.dynpm_action_timeout = jiffies +
1824 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1825 }
1826 } else if (not_processed == 0) { /* should downclock */
1827 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1828 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1829 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1830 rdev->pm.dynpm_can_downclock) {
1831 rdev->pm.dynpm_planned_action =
1832 DYNPM_ACTION_DOWNCLOCK;
1833 rdev->pm.dynpm_action_timeout = jiffies +
1834 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1835 }
1836 }
1837
1838 /* Note, radeon_pm_set_clocks is called with static_switch set
1839 * to false since we want to wait for vbl to avoid flicker.
1840 */
1841 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1842 jiffies > rdev->pm.dynpm_action_timeout) {
1843 radeon_pm_get_dynpm_state(rdev);
1844 radeon_pm_set_clocks(rdev);
1845 }
1846
1847 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1848 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1849 }
1850 mutex_unlock(&rdev->pm.mutex);
1851 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1852}
1853
1854/*
1855 * Debugfs info
1856 */
1857#if defined(CONFIG_DEBUG_FS)
1858
1859static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1860{
1861 struct drm_info_node *node = (struct drm_info_node *) m->private;
1862 struct drm_device *dev = node->minor->dev;
1863 struct radeon_device *rdev = dev->dev_private;
1864 struct drm_device *ddev = rdev->ddev;
1865
1866 if ((rdev->flags & RADEON_IS_PX) &&
1867 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1868 seq_printf(m, "PX asic powered off\n");
1869 } else if (rdev->pm.dpm_enabled) {
1870 mutex_lock(&rdev->pm.mutex);
1871 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1872 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1873 else
1874 seq_printf(m, "Debugfs support not implemented for this asic\n");
1875 mutex_unlock(&rdev->pm.mutex);
1876 } else {
1877 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1878 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1879 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1880 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1881 else
1882 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1883 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1884 if (rdev->asic->pm.get_memory_clock)
1885 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1886 if (rdev->pm.current_vddc)
1887 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1888 if (rdev->asic->pm.get_pcie_lanes)
1889 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1890 }
1891
1892 return 0;
1893}
1894
1895static struct drm_info_list radeon_pm_info_list[] = {
1896 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1897};
1898#endif
1899
1900static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1901{
1902#if defined(CONFIG_DEBUG_FS)
1903 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1904#else
1905 return 0;
1906#endif
1907}