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1/*
2 * Copyright (C) 2009 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#define DSS_SUBSYS_NAME "DSI"
19
20#include <linux/kernel.h>
21#include <linux/mfd/syscon.h>
22#include <linux/regmap.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/mutex.h>
30#include <linux/module.h>
31#include <linux/semaphore.h>
32#include <linux/seq_file.h>
33#include <linux/platform_device.h>
34#include <linux/regulator/consumer.h>
35#include <linux/wait.h>
36#include <linux/workqueue.h>
37#include <linux/sched.h>
38#include <linux/slab.h>
39#include <linux/debugfs.h>
40#include <linux/pm_runtime.h>
41#include <linux/of.h>
42#include <linux/of_graph.h>
43#include <linux/of_platform.h>
44#include <linux/component.h>
45#include <linux/sys_soc.h>
46
47#include <video/mipi_display.h>
48
49#include "omapdss.h"
50#include "dss.h"
51
52#define DSI_CATCH_MISSING_TE
53
54struct dsi_reg { u16 module; u16 idx; };
55
56#define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
57
58/* DSI Protocol Engine */
59
60#define DSI_PROTO 0
61#define DSI_PROTO_SZ 0x200
62
63#define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
64#define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
65#define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
66#define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
67#define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
68#define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
69#define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
70#define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
71#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
72#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
73#define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
74#define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
75#define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
76#define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
77#define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
78#define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
79#define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
80#define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
81#define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
82#define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
83#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
84#define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
85#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
86#define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
87#define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
88#define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
89#define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
90#define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
91#define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
92#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
93#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
94#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
95#define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
96#define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
97
98/* DSIPHY_SCP */
99
100#define DSI_PHY 1
101#define DSI_PHY_OFFSET 0x200
102#define DSI_PHY_SZ 0x40
103
104#define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
105#define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
106#define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
107#define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
108#define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
109
110/* DSI_PLL_CTRL_SCP */
111
112#define DSI_PLL 2
113#define DSI_PLL_OFFSET 0x300
114#define DSI_PLL_SZ 0x20
115
116#define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
117#define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
118#define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
119#define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
120#define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
121
122#define REG_GET(dsi, idx, start, end) \
123 FLD_GET(dsi_read_reg(dsi, idx), start, end)
124
125#define REG_FLD_MOD(dsi, idx, val, start, end) \
126 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
127
128/* Global interrupts */
129#define DSI_IRQ_VC0 (1 << 0)
130#define DSI_IRQ_VC1 (1 << 1)
131#define DSI_IRQ_VC2 (1 << 2)
132#define DSI_IRQ_VC3 (1 << 3)
133#define DSI_IRQ_WAKEUP (1 << 4)
134#define DSI_IRQ_RESYNC (1 << 5)
135#define DSI_IRQ_PLL_LOCK (1 << 7)
136#define DSI_IRQ_PLL_UNLOCK (1 << 8)
137#define DSI_IRQ_PLL_RECALL (1 << 9)
138#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
139#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
140#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
141#define DSI_IRQ_TE_TRIGGER (1 << 16)
142#define DSI_IRQ_ACK_TRIGGER (1 << 17)
143#define DSI_IRQ_SYNC_LOST (1 << 18)
144#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
145#define DSI_IRQ_TA_TIMEOUT (1 << 20)
146#define DSI_IRQ_ERROR_MASK \
147 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
148 DSI_IRQ_TA_TIMEOUT)
149#define DSI_IRQ_CHANNEL_MASK 0xf
150
151/* Virtual channel interrupts */
152#define DSI_VC_IRQ_CS (1 << 0)
153#define DSI_VC_IRQ_ECC_CORR (1 << 1)
154#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
155#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
156#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
157#define DSI_VC_IRQ_BTA (1 << 5)
158#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
159#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
160#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
161#define DSI_VC_IRQ_ERROR_MASK \
162 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
163 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
164 DSI_VC_IRQ_FIFO_TX_UDF)
165
166/* ComplexIO interrupts */
167#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
168#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
169#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
170#define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
171#define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
172#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
173#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
174#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
175#define DSI_CIO_IRQ_ERRESC4 (1 << 8)
176#define DSI_CIO_IRQ_ERRESC5 (1 << 9)
177#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
178#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
179#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
180#define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
181#define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
182#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
183#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
184#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
185#define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
186#define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
187#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
188#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
189#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
190#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
191#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
192#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
193#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
194#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
195#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
196#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
197#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
198#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
199#define DSI_CIO_IRQ_ERROR_MASK \
200 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
201 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
202 DSI_CIO_IRQ_ERRSYNCESC5 | \
203 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
204 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
205 DSI_CIO_IRQ_ERRESC5 | \
206 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
207 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
208 DSI_CIO_IRQ_ERRCONTROL5 | \
209 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
210 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
211 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
212 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
213 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
214
215typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
216struct dsi_data;
217
218static int dsi_display_init_dispc(struct dsi_data *dsi);
219static void dsi_display_uninit_dispc(struct dsi_data *dsi);
220
221static int dsi_vc_send_null(struct dsi_data *dsi, int channel);
222
223/* DSI PLL HSDIV indices */
224#define HSDIV_DISPC 0
225#define HSDIV_DSI 1
226
227#define DSI_MAX_NR_ISRS 2
228#define DSI_MAX_NR_LANES 5
229
230enum dsi_model {
231 DSI_MODEL_OMAP3,
232 DSI_MODEL_OMAP4,
233 DSI_MODEL_OMAP5,
234};
235
236enum dsi_lane_function {
237 DSI_LANE_UNUSED = 0,
238 DSI_LANE_CLK,
239 DSI_LANE_DATA1,
240 DSI_LANE_DATA2,
241 DSI_LANE_DATA3,
242 DSI_LANE_DATA4,
243};
244
245struct dsi_lane_config {
246 enum dsi_lane_function function;
247 u8 polarity;
248};
249
250struct dsi_isr_data {
251 omap_dsi_isr_t isr;
252 void *arg;
253 u32 mask;
254};
255
256enum fifo_size {
257 DSI_FIFO_SIZE_0 = 0,
258 DSI_FIFO_SIZE_32 = 1,
259 DSI_FIFO_SIZE_64 = 2,
260 DSI_FIFO_SIZE_96 = 3,
261 DSI_FIFO_SIZE_128 = 4,
262};
263
264enum dsi_vc_source {
265 DSI_VC_SOURCE_L4 = 0,
266 DSI_VC_SOURCE_VP,
267};
268
269struct dsi_irq_stats {
270 unsigned long last_reset;
271 unsigned int irq_count;
272 unsigned int dsi_irqs[32];
273 unsigned int vc_irqs[4][32];
274 unsigned int cio_irqs[32];
275};
276
277struct dsi_isr_tables {
278 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
279 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
280 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
281};
282
283struct dsi_clk_calc_ctx {
284 struct dsi_data *dsi;
285 struct dss_pll *pll;
286
287 /* inputs */
288
289 const struct omap_dss_dsi_config *config;
290
291 unsigned long req_pck_min, req_pck_nom, req_pck_max;
292
293 /* outputs */
294
295 struct dss_pll_clock_info dsi_cinfo;
296 struct dispc_clock_info dispc_cinfo;
297
298 struct videomode vm;
299 struct omap_dss_dsi_videomode_timings dsi_vm;
300};
301
302struct dsi_lp_clock_info {
303 unsigned long lp_clk;
304 u16 lp_clk_div;
305};
306
307struct dsi_module_id_data {
308 u32 address;
309 int id;
310};
311
312enum dsi_quirks {
313 DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */
314 DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1),
315 DSI_QUIRK_VC_OCP_WIDTH = (1 << 2),
316 DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3),
317 DSI_QUIRK_GNQ = (1 << 4),
318 DSI_QUIRK_PHY_DCC = (1 << 5),
319};
320
321struct dsi_of_data {
322 enum dsi_model model;
323 const struct dss_pll_hw *pll_hw;
324 const struct dsi_module_id_data *modules;
325 unsigned int max_fck_freq;
326 unsigned int max_pll_lpdiv;
327 enum dsi_quirks quirks;
328};
329
330struct dsi_data {
331 struct device *dev;
332 void __iomem *proto_base;
333 void __iomem *phy_base;
334 void __iomem *pll_base;
335
336 const struct dsi_of_data *data;
337 int module_id;
338
339 int irq;
340
341 bool is_enabled;
342
343 struct clk *dss_clk;
344 struct regmap *syscon;
345 struct dss_device *dss;
346
347 struct dispc_clock_info user_dispc_cinfo;
348 struct dss_pll_clock_info user_dsi_cinfo;
349
350 struct dsi_lp_clock_info user_lp_cinfo;
351 struct dsi_lp_clock_info current_lp_cinfo;
352
353 struct dss_pll pll;
354
355 bool vdds_dsi_enabled;
356 struct regulator *vdds_dsi_reg;
357
358 struct {
359 enum dsi_vc_source source;
360 struct omap_dss_device *dssdev;
361 enum fifo_size tx_fifo_size;
362 enum fifo_size rx_fifo_size;
363 int vc_id;
364 } vc[4];
365
366 struct mutex lock;
367 struct semaphore bus_lock;
368
369 spinlock_t irq_lock;
370 struct dsi_isr_tables isr_tables;
371 /* space for a copy used by the interrupt handler */
372 struct dsi_isr_tables isr_tables_copy;
373
374 int update_channel;
375#ifdef DSI_PERF_MEASURE
376 unsigned int update_bytes;
377#endif
378
379 bool te_enabled;
380 bool ulps_enabled;
381
382 void (*framedone_callback)(int, void *);
383 void *framedone_data;
384
385 struct delayed_work framedone_timeout_work;
386
387#ifdef DSI_CATCH_MISSING_TE
388 struct timer_list te_timer;
389#endif
390
391 unsigned long cache_req_pck;
392 unsigned long cache_clk_freq;
393 struct dss_pll_clock_info cache_cinfo;
394
395 u32 errors;
396 spinlock_t errors_lock;
397#ifdef DSI_PERF_MEASURE
398 ktime_t perf_setup_time;
399 ktime_t perf_start_time;
400#endif
401 int debug_read;
402 int debug_write;
403 struct {
404 struct dss_debugfs_entry *irqs;
405 struct dss_debugfs_entry *regs;
406 } debugfs;
407
408#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
409 spinlock_t irq_stats_lock;
410 struct dsi_irq_stats irq_stats;
411#endif
412
413 unsigned int num_lanes_supported;
414 unsigned int line_buffer_size;
415
416 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
417 unsigned int num_lanes_used;
418
419 unsigned int scp_clk_refcount;
420
421 struct dss_lcd_mgr_config mgr_config;
422 struct videomode vm;
423 enum omap_dss_dsi_pixel_format pix_fmt;
424 enum omap_dss_dsi_mode mode;
425 struct omap_dss_dsi_videomode_timings vm_timings;
426
427 struct omap_dss_device output;
428};
429
430struct dsi_packet_sent_handler_data {
431 struct dsi_data *dsi;
432 struct completion *completion;
433};
434
435#ifdef DSI_PERF_MEASURE
436static bool dsi_perf;
437module_param(dsi_perf, bool, 0644);
438#endif
439
440static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev)
441{
442 return dev_get_drvdata(dssdev->dev);
443}
444
445static struct dsi_data *dsi_get_dsi_from_id(int module)
446{
447 struct omap_dss_device *out;
448 enum omap_dss_output_id id;
449
450 switch (module) {
451 case 0:
452 id = OMAP_DSS_OUTPUT_DSI1;
453 break;
454 case 1:
455 id = OMAP_DSS_OUTPUT_DSI2;
456 break;
457 default:
458 return NULL;
459 }
460
461 out = omap_dss_get_output(id);
462
463 return out ? to_dsi_data(out) : NULL;
464}
465
466static inline void dsi_write_reg(struct dsi_data *dsi,
467 const struct dsi_reg idx, u32 val)
468{
469 void __iomem *base;
470
471 switch(idx.module) {
472 case DSI_PROTO: base = dsi->proto_base; break;
473 case DSI_PHY: base = dsi->phy_base; break;
474 case DSI_PLL: base = dsi->pll_base; break;
475 default: return;
476 }
477
478 __raw_writel(val, base + idx.idx);
479}
480
481static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx)
482{
483 void __iomem *base;
484
485 switch(idx.module) {
486 case DSI_PROTO: base = dsi->proto_base; break;
487 case DSI_PHY: base = dsi->phy_base; break;
488 case DSI_PLL: base = dsi->pll_base; break;
489 default: return 0;
490 }
491
492 return __raw_readl(base + idx.idx);
493}
494
495static void dsi_bus_lock(struct omap_dss_device *dssdev)
496{
497 struct dsi_data *dsi = to_dsi_data(dssdev);
498
499 down(&dsi->bus_lock);
500}
501
502static void dsi_bus_unlock(struct omap_dss_device *dssdev)
503{
504 struct dsi_data *dsi = to_dsi_data(dssdev);
505
506 up(&dsi->bus_lock);
507}
508
509static bool dsi_bus_is_locked(struct dsi_data *dsi)
510{
511 return dsi->bus_lock.count == 0;
512}
513
514static void dsi_completion_handler(void *data, u32 mask)
515{
516 complete((struct completion *)data);
517}
518
519static inline bool wait_for_bit_change(struct dsi_data *dsi,
520 const struct dsi_reg idx,
521 int bitnum, int value)
522{
523 unsigned long timeout;
524 ktime_t wait;
525 int t;
526
527 /* first busyloop to see if the bit changes right away */
528 t = 100;
529 while (t-- > 0) {
530 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
531 return true;
532 }
533
534 /* then loop for 500ms, sleeping for 1ms in between */
535 timeout = jiffies + msecs_to_jiffies(500);
536 while (time_before(jiffies, timeout)) {
537 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
538 return true;
539
540 wait = ns_to_ktime(1000 * 1000);
541 set_current_state(TASK_UNINTERRUPTIBLE);
542 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
543 }
544
545 return false;
546}
547
548static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
549{
550 switch (fmt) {
551 case OMAP_DSS_DSI_FMT_RGB888:
552 case OMAP_DSS_DSI_FMT_RGB666:
553 return 24;
554 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
555 return 18;
556 case OMAP_DSS_DSI_FMT_RGB565:
557 return 16;
558 default:
559 BUG();
560 return 0;
561 }
562}
563
564#ifdef DSI_PERF_MEASURE
565static void dsi_perf_mark_setup(struct dsi_data *dsi)
566{
567 dsi->perf_setup_time = ktime_get();
568}
569
570static void dsi_perf_mark_start(struct dsi_data *dsi)
571{
572 dsi->perf_start_time = ktime_get();
573}
574
575static void dsi_perf_show(struct dsi_data *dsi, const char *name)
576{
577 ktime_t t, setup_time, trans_time;
578 u32 total_bytes;
579 u32 setup_us, trans_us, total_us;
580
581 if (!dsi_perf)
582 return;
583
584 t = ktime_get();
585
586 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
587 setup_us = (u32)ktime_to_us(setup_time);
588 if (setup_us == 0)
589 setup_us = 1;
590
591 trans_time = ktime_sub(t, dsi->perf_start_time);
592 trans_us = (u32)ktime_to_us(trans_time);
593 if (trans_us == 0)
594 trans_us = 1;
595
596 total_us = setup_us + trans_us;
597
598 total_bytes = dsi->update_bytes;
599
600 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n",
601 name,
602 setup_us,
603 trans_us,
604 total_us,
605 1000 * 1000 / total_us,
606 total_bytes,
607 total_bytes * 1000 / total_us);
608}
609#else
610static inline void dsi_perf_mark_setup(struct dsi_data *dsi)
611{
612}
613
614static inline void dsi_perf_mark_start(struct dsi_data *dsi)
615{
616}
617
618static inline void dsi_perf_show(struct dsi_data *dsi, const char *name)
619{
620}
621#endif
622
623static int verbose_irq;
624
625static void print_irq_status(u32 status)
626{
627 if (status == 0)
628 return;
629
630 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
631 return;
632
633#define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
634
635 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
636 status,
637 verbose_irq ? PIS(VC0) : "",
638 verbose_irq ? PIS(VC1) : "",
639 verbose_irq ? PIS(VC2) : "",
640 verbose_irq ? PIS(VC3) : "",
641 PIS(WAKEUP),
642 PIS(RESYNC),
643 PIS(PLL_LOCK),
644 PIS(PLL_UNLOCK),
645 PIS(PLL_RECALL),
646 PIS(COMPLEXIO_ERR),
647 PIS(HS_TX_TIMEOUT),
648 PIS(LP_RX_TIMEOUT),
649 PIS(TE_TRIGGER),
650 PIS(ACK_TRIGGER),
651 PIS(SYNC_LOST),
652 PIS(LDO_POWER_GOOD),
653 PIS(TA_TIMEOUT));
654#undef PIS
655}
656
657static void print_irq_status_vc(int channel, u32 status)
658{
659 if (status == 0)
660 return;
661
662 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
663 return;
664
665#define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
666
667 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
668 channel,
669 status,
670 PIS(CS),
671 PIS(ECC_CORR),
672 PIS(ECC_NO_CORR),
673 verbose_irq ? PIS(PACKET_SENT) : "",
674 PIS(BTA),
675 PIS(FIFO_TX_OVF),
676 PIS(FIFO_RX_OVF),
677 PIS(FIFO_TX_UDF),
678 PIS(PP_BUSY_CHANGE));
679#undef PIS
680}
681
682static void print_irq_status_cio(u32 status)
683{
684 if (status == 0)
685 return;
686
687#define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
688
689 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
690 status,
691 PIS(ERRSYNCESC1),
692 PIS(ERRSYNCESC2),
693 PIS(ERRSYNCESC3),
694 PIS(ERRESC1),
695 PIS(ERRESC2),
696 PIS(ERRESC3),
697 PIS(ERRCONTROL1),
698 PIS(ERRCONTROL2),
699 PIS(ERRCONTROL3),
700 PIS(STATEULPS1),
701 PIS(STATEULPS2),
702 PIS(STATEULPS3),
703 PIS(ERRCONTENTIONLP0_1),
704 PIS(ERRCONTENTIONLP1_1),
705 PIS(ERRCONTENTIONLP0_2),
706 PIS(ERRCONTENTIONLP1_2),
707 PIS(ERRCONTENTIONLP0_3),
708 PIS(ERRCONTENTIONLP1_3),
709 PIS(ULPSACTIVENOT_ALL0),
710 PIS(ULPSACTIVENOT_ALL1));
711#undef PIS
712}
713
714#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
715static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus,
716 u32 *vcstatus, u32 ciostatus)
717{
718 int i;
719
720 spin_lock(&dsi->irq_stats_lock);
721
722 dsi->irq_stats.irq_count++;
723 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
724
725 for (i = 0; i < 4; ++i)
726 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
727
728 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
729
730 spin_unlock(&dsi->irq_stats_lock);
731}
732#else
733#define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus)
734#endif
735
736static int debug_irq;
737
738static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus,
739 u32 *vcstatus, u32 ciostatus)
740{
741 int i;
742
743 if (irqstatus & DSI_IRQ_ERROR_MASK) {
744 DSSERR("DSI error, irqstatus %x\n", irqstatus);
745 print_irq_status(irqstatus);
746 spin_lock(&dsi->errors_lock);
747 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
748 spin_unlock(&dsi->errors_lock);
749 } else if (debug_irq) {
750 print_irq_status(irqstatus);
751 }
752
753 for (i = 0; i < 4; ++i) {
754 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
755 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
756 i, vcstatus[i]);
757 print_irq_status_vc(i, vcstatus[i]);
758 } else if (debug_irq) {
759 print_irq_status_vc(i, vcstatus[i]);
760 }
761 }
762
763 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
764 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
765 print_irq_status_cio(ciostatus);
766 } else if (debug_irq) {
767 print_irq_status_cio(ciostatus);
768 }
769}
770
771static void dsi_call_isrs(struct dsi_isr_data *isr_array,
772 unsigned int isr_array_size, u32 irqstatus)
773{
774 struct dsi_isr_data *isr_data;
775 int i;
776
777 for (i = 0; i < isr_array_size; i++) {
778 isr_data = &isr_array[i];
779 if (isr_data->isr && isr_data->mask & irqstatus)
780 isr_data->isr(isr_data->arg, irqstatus);
781 }
782}
783
784static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
785 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
786{
787 int i;
788
789 dsi_call_isrs(isr_tables->isr_table,
790 ARRAY_SIZE(isr_tables->isr_table),
791 irqstatus);
792
793 for (i = 0; i < 4; ++i) {
794 if (vcstatus[i] == 0)
795 continue;
796 dsi_call_isrs(isr_tables->isr_table_vc[i],
797 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
798 vcstatus[i]);
799 }
800
801 if (ciostatus != 0)
802 dsi_call_isrs(isr_tables->isr_table_cio,
803 ARRAY_SIZE(isr_tables->isr_table_cio),
804 ciostatus);
805}
806
807static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
808{
809 struct dsi_data *dsi = arg;
810 u32 irqstatus, vcstatus[4], ciostatus;
811 int i;
812
813 if (!dsi->is_enabled)
814 return IRQ_NONE;
815
816 spin_lock(&dsi->irq_lock);
817
818 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS);
819
820 /* IRQ is not for us */
821 if (!irqstatus) {
822 spin_unlock(&dsi->irq_lock);
823 return IRQ_NONE;
824 }
825
826 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
827 /* flush posted write */
828 dsi_read_reg(dsi, DSI_IRQSTATUS);
829
830 for (i = 0; i < 4; ++i) {
831 if ((irqstatus & (1 << i)) == 0) {
832 vcstatus[i] = 0;
833 continue;
834 }
835
836 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
837
838 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]);
839 /* flush posted write */
840 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
841 }
842
843 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
844 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
845
846 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
847 /* flush posted write */
848 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
849 } else {
850 ciostatus = 0;
851 }
852
853#ifdef DSI_CATCH_MISSING_TE
854 if (irqstatus & DSI_IRQ_TE_TRIGGER)
855 del_timer(&dsi->te_timer);
856#endif
857
858 /* make a copy and unlock, so that isrs can unregister
859 * themselves */
860 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
861 sizeof(dsi->isr_tables));
862
863 spin_unlock(&dsi->irq_lock);
864
865 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
866
867 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus);
868
869 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus);
870
871 return IRQ_HANDLED;
872}
873
874/* dsi->irq_lock has to be locked by the caller */
875static void _omap_dsi_configure_irqs(struct dsi_data *dsi,
876 struct dsi_isr_data *isr_array,
877 unsigned int isr_array_size,
878 u32 default_mask,
879 const struct dsi_reg enable_reg,
880 const struct dsi_reg status_reg)
881{
882 struct dsi_isr_data *isr_data;
883 u32 mask;
884 u32 old_mask;
885 int i;
886
887 mask = default_mask;
888
889 for (i = 0; i < isr_array_size; i++) {
890 isr_data = &isr_array[i];
891
892 if (isr_data->isr == NULL)
893 continue;
894
895 mask |= isr_data->mask;
896 }
897
898 old_mask = dsi_read_reg(dsi, enable_reg);
899 /* clear the irqstatus for newly enabled irqs */
900 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask);
901 dsi_write_reg(dsi, enable_reg, mask);
902
903 /* flush posted writes */
904 dsi_read_reg(dsi, enable_reg);
905 dsi_read_reg(dsi, status_reg);
906}
907
908/* dsi->irq_lock has to be locked by the caller */
909static void _omap_dsi_set_irqs(struct dsi_data *dsi)
910{
911 u32 mask = DSI_IRQ_ERROR_MASK;
912#ifdef DSI_CATCH_MISSING_TE
913 mask |= DSI_IRQ_TE_TRIGGER;
914#endif
915 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table,
916 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
917 DSI_IRQENABLE, DSI_IRQSTATUS);
918}
919
920/* dsi->irq_lock has to be locked by the caller */
921static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc)
922{
923 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc],
924 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
925 DSI_VC_IRQ_ERROR_MASK,
926 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
927}
928
929/* dsi->irq_lock has to be locked by the caller */
930static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi)
931{
932 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio,
933 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
934 DSI_CIO_IRQ_ERROR_MASK,
935 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
936}
937
938static void _dsi_initialize_irq(struct dsi_data *dsi)
939{
940 unsigned long flags;
941 int vc;
942
943 spin_lock_irqsave(&dsi->irq_lock, flags);
944
945 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
946
947 _omap_dsi_set_irqs(dsi);
948 for (vc = 0; vc < 4; ++vc)
949 _omap_dsi_set_irqs_vc(dsi, vc);
950 _omap_dsi_set_irqs_cio(dsi);
951
952 spin_unlock_irqrestore(&dsi->irq_lock, flags);
953}
954
955static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
956 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
957{
958 struct dsi_isr_data *isr_data;
959 int free_idx;
960 int i;
961
962 BUG_ON(isr == NULL);
963
964 /* check for duplicate entry and find a free slot */
965 free_idx = -1;
966 for (i = 0; i < isr_array_size; i++) {
967 isr_data = &isr_array[i];
968
969 if (isr_data->isr == isr && isr_data->arg == arg &&
970 isr_data->mask == mask) {
971 return -EINVAL;
972 }
973
974 if (isr_data->isr == NULL && free_idx == -1)
975 free_idx = i;
976 }
977
978 if (free_idx == -1)
979 return -EBUSY;
980
981 isr_data = &isr_array[free_idx];
982 isr_data->isr = isr;
983 isr_data->arg = arg;
984 isr_data->mask = mask;
985
986 return 0;
987}
988
989static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
990 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
991{
992 struct dsi_isr_data *isr_data;
993 int i;
994
995 for (i = 0; i < isr_array_size; i++) {
996 isr_data = &isr_array[i];
997 if (isr_data->isr != isr || isr_data->arg != arg ||
998 isr_data->mask != mask)
999 continue;
1000
1001 isr_data->isr = NULL;
1002 isr_data->arg = NULL;
1003 isr_data->mask = 0;
1004
1005 return 0;
1006 }
1007
1008 return -EINVAL;
1009}
1010
1011static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
1012 void *arg, u32 mask)
1013{
1014 unsigned long flags;
1015 int r;
1016
1017 spin_lock_irqsave(&dsi->irq_lock, flags);
1018
1019 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1020 ARRAY_SIZE(dsi->isr_tables.isr_table));
1021
1022 if (r == 0)
1023 _omap_dsi_set_irqs(dsi);
1024
1025 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1026
1027 return r;
1028}
1029
1030static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
1031 void *arg, u32 mask)
1032{
1033 unsigned long flags;
1034 int r;
1035
1036 spin_lock_irqsave(&dsi->irq_lock, flags);
1037
1038 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1039 ARRAY_SIZE(dsi->isr_tables.isr_table));
1040
1041 if (r == 0)
1042 _omap_dsi_set_irqs(dsi);
1043
1044 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1045
1046 return r;
1047}
1048
1049static int dsi_register_isr_vc(struct dsi_data *dsi, int channel,
1050 omap_dsi_isr_t isr, void *arg, u32 mask)
1051{
1052 unsigned long flags;
1053 int r;
1054
1055 spin_lock_irqsave(&dsi->irq_lock, flags);
1056
1057 r = _dsi_register_isr(isr, arg, mask,
1058 dsi->isr_tables.isr_table_vc[channel],
1059 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1060
1061 if (r == 0)
1062 _omap_dsi_set_irqs_vc(dsi, channel);
1063
1064 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1065
1066 return r;
1067}
1068
1069static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel,
1070 omap_dsi_isr_t isr, void *arg, u32 mask)
1071{
1072 unsigned long flags;
1073 int r;
1074
1075 spin_lock_irqsave(&dsi->irq_lock, flags);
1076
1077 r = _dsi_unregister_isr(isr, arg, mask,
1078 dsi->isr_tables.isr_table_vc[channel],
1079 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1080
1081 if (r == 0)
1082 _omap_dsi_set_irqs_vc(dsi, channel);
1083
1084 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1085
1086 return r;
1087}
1088
1089static int dsi_register_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1090 void *arg, u32 mask)
1091{
1092 unsigned long flags;
1093 int r;
1094
1095 spin_lock_irqsave(&dsi->irq_lock, flags);
1096
1097 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1098 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1099
1100 if (r == 0)
1101 _omap_dsi_set_irqs_cio(dsi);
1102
1103 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1104
1105 return r;
1106}
1107
1108static int dsi_unregister_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1109 void *arg, u32 mask)
1110{
1111 unsigned long flags;
1112 int r;
1113
1114 spin_lock_irqsave(&dsi->irq_lock, flags);
1115
1116 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1117 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1118
1119 if (r == 0)
1120 _omap_dsi_set_irqs_cio(dsi);
1121
1122 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1123
1124 return r;
1125}
1126
1127static u32 dsi_get_errors(struct dsi_data *dsi)
1128{
1129 unsigned long flags;
1130 u32 e;
1131
1132 spin_lock_irqsave(&dsi->errors_lock, flags);
1133 e = dsi->errors;
1134 dsi->errors = 0;
1135 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1136 return e;
1137}
1138
1139static int dsi_runtime_get(struct dsi_data *dsi)
1140{
1141 int r;
1142
1143 DSSDBG("dsi_runtime_get\n");
1144
1145 r = pm_runtime_get_sync(dsi->dev);
1146 WARN_ON(r < 0);
1147 return r < 0 ? r : 0;
1148}
1149
1150static void dsi_runtime_put(struct dsi_data *dsi)
1151{
1152 int r;
1153
1154 DSSDBG("dsi_runtime_put\n");
1155
1156 r = pm_runtime_put_sync(dsi->dev);
1157 WARN_ON(r < 0 && r != -ENOSYS);
1158}
1159
1160static int dsi_regulator_init(struct dsi_data *dsi)
1161{
1162 struct regulator *vdds_dsi;
1163
1164 if (dsi->vdds_dsi_reg != NULL)
1165 return 0;
1166
1167 vdds_dsi = devm_regulator_get(dsi->dev, "vdd");
1168
1169 if (IS_ERR(vdds_dsi)) {
1170 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1171 DSSERR("can't get DSI VDD regulator\n");
1172 return PTR_ERR(vdds_dsi);
1173 }
1174
1175 dsi->vdds_dsi_reg = vdds_dsi;
1176
1177 return 0;
1178}
1179
1180static void _dsi_print_reset_status(struct dsi_data *dsi)
1181{
1182 u32 l;
1183 int b0, b1, b2;
1184
1185 /* A dummy read using the SCP interface to any DSIPHY register is
1186 * required after DSIPHY reset to complete the reset of the DSI complex
1187 * I/O. */
1188 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1189
1190 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
1191 b0 = 28;
1192 b1 = 27;
1193 b2 = 26;
1194 } else {
1195 b0 = 24;
1196 b1 = 25;
1197 b2 = 26;
1198 }
1199
1200#define DSI_FLD_GET(fld, start, end)\
1201 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end)
1202
1203 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1204 DSI_FLD_GET(PLL_STATUS, 0, 0),
1205 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1206 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1207 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1208 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1209 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1210 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1211 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1212
1213#undef DSI_FLD_GET
1214}
1215
1216static inline int dsi_if_enable(struct dsi_data *dsi, bool enable)
1217{
1218 DSSDBG("dsi_if_enable(%d)\n", enable);
1219
1220 enable = enable ? 1 : 0;
1221 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */
1222
1223 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) {
1224 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1225 return -EIO;
1226 }
1227
1228 return 0;
1229}
1230
1231static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi)
1232{
1233 return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1234}
1235
1236static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi)
1237{
1238 return dsi->pll.cinfo.clkout[HSDIV_DSI];
1239}
1240
1241static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi)
1242{
1243 return dsi->pll.cinfo.clkdco / 16;
1244}
1245
1246static unsigned long dsi_fclk_rate(struct dsi_data *dsi)
1247{
1248 unsigned long r;
1249 enum dss_clk_source source;
1250
1251 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id);
1252 if (source == DSS_CLK_SRC_FCK) {
1253 /* DSI FCLK source is DSS_CLK_FCK */
1254 r = clk_get_rate(dsi->dss_clk);
1255 } else {
1256 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1257 r = dsi_get_pll_hsdiv_dsi_rate(dsi);
1258 }
1259
1260 return r;
1261}
1262
1263static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1264 unsigned long lp_clk_min, unsigned long lp_clk_max,
1265 struct dsi_lp_clock_info *lp_cinfo)
1266{
1267 unsigned int lp_clk_div;
1268 unsigned long lp_clk;
1269
1270 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1271 lp_clk = dsi_fclk / 2 / lp_clk_div;
1272
1273 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1274 return -EINVAL;
1275
1276 lp_cinfo->lp_clk_div = lp_clk_div;
1277 lp_cinfo->lp_clk = lp_clk;
1278
1279 return 0;
1280}
1281
1282static int dsi_set_lp_clk_divisor(struct dsi_data *dsi)
1283{
1284 unsigned long dsi_fclk;
1285 unsigned int lp_clk_div;
1286 unsigned long lp_clk;
1287 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv;
1288
1289
1290 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
1291
1292 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1293 return -EINVAL;
1294
1295 dsi_fclk = dsi_fclk_rate(dsi);
1296
1297 lp_clk = dsi_fclk / 2 / lp_clk_div;
1298
1299 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1300 dsi->current_lp_cinfo.lp_clk = lp_clk;
1301 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1302
1303 /* LP_CLK_DIVISOR */
1304 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1305
1306 /* LP_RX_SYNCHRO_ENABLE */
1307 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1308
1309 return 0;
1310}
1311
1312static void dsi_enable_scp_clk(struct dsi_data *dsi)
1313{
1314 if (dsi->scp_clk_refcount++ == 0)
1315 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1316}
1317
1318static void dsi_disable_scp_clk(struct dsi_data *dsi)
1319{
1320 WARN_ON(dsi->scp_clk_refcount == 0);
1321 if (--dsi->scp_clk_refcount == 0)
1322 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1323}
1324
1325enum dsi_pll_power_state {
1326 DSI_PLL_POWER_OFF = 0x0,
1327 DSI_PLL_POWER_ON_HSCLK = 0x1,
1328 DSI_PLL_POWER_ON_ALL = 0x2,
1329 DSI_PLL_POWER_ON_DIV = 0x3,
1330};
1331
1332static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state)
1333{
1334 int t = 0;
1335
1336 /* DSI-PLL power command 0x3 is not working */
1337 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) &&
1338 state == DSI_PLL_POWER_ON_DIV)
1339 state = DSI_PLL_POWER_ON_ALL;
1340
1341 /* PLL_PWR_CMD */
1342 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30);
1343
1344 /* PLL_PWR_STATUS */
1345 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) {
1346 if (++t > 1000) {
1347 DSSERR("Failed to set DSI PLL power mode to %d\n",
1348 state);
1349 return -ENODEV;
1350 }
1351 udelay(1);
1352 }
1353
1354 return 0;
1355}
1356
1357
1358static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi,
1359 struct dss_pll_clock_info *cinfo)
1360{
1361 unsigned long max_dsi_fck;
1362
1363 max_dsi_fck = dsi->data->max_fck_freq;
1364
1365 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
1366 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
1367}
1368
1369static int dsi_pll_enable(struct dss_pll *pll)
1370{
1371 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1372 int r = 0;
1373
1374 DSSDBG("PLL init\n");
1375
1376 r = dsi_regulator_init(dsi);
1377 if (r)
1378 return r;
1379
1380 r = dsi_runtime_get(dsi);
1381 if (r)
1382 return r;
1383
1384 /*
1385 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1386 */
1387 dsi_enable_scp_clk(dsi);
1388
1389 if (!dsi->vdds_dsi_enabled) {
1390 r = regulator_enable(dsi->vdds_dsi_reg);
1391 if (r)
1392 goto err0;
1393 dsi->vdds_dsi_enabled = true;
1394 }
1395
1396 /* XXX PLL does not come out of reset without this... */
1397 dispc_pck_free_enable(dsi->dss->dispc, 1);
1398
1399 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) {
1400 DSSERR("PLL not coming out of reset.\n");
1401 r = -ENODEV;
1402 dispc_pck_free_enable(dsi->dss->dispc, 0);
1403 goto err1;
1404 }
1405
1406 /* XXX ... but if left on, we get problems when planes do not
1407 * fill the whole display. No idea about this */
1408 dispc_pck_free_enable(dsi->dss->dispc, 0);
1409
1410 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL);
1411
1412 if (r)
1413 goto err1;
1414
1415 DSSDBG("PLL init done\n");
1416
1417 return 0;
1418err1:
1419 if (dsi->vdds_dsi_enabled) {
1420 regulator_disable(dsi->vdds_dsi_reg);
1421 dsi->vdds_dsi_enabled = false;
1422 }
1423err0:
1424 dsi_disable_scp_clk(dsi);
1425 dsi_runtime_put(dsi);
1426 return r;
1427}
1428
1429static void dsi_pll_uninit(struct dsi_data *dsi, bool disconnect_lanes)
1430{
1431 dsi_pll_power(dsi, DSI_PLL_POWER_OFF);
1432 if (disconnect_lanes) {
1433 WARN_ON(!dsi->vdds_dsi_enabled);
1434 regulator_disable(dsi->vdds_dsi_reg);
1435 dsi->vdds_dsi_enabled = false;
1436 }
1437
1438 dsi_disable_scp_clk(dsi);
1439 dsi_runtime_put(dsi);
1440
1441 DSSDBG("PLL uninit done\n");
1442}
1443
1444static void dsi_pll_disable(struct dss_pll *pll)
1445{
1446 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1447
1448 dsi_pll_uninit(dsi, true);
1449}
1450
1451static void dsi_dump_dsi_clocks(struct dsi_data *dsi, struct seq_file *s)
1452{
1453 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1454 enum dss_clk_source dispc_clk_src, dsi_clk_src;
1455 int dsi_module = dsi->module_id;
1456 struct dss_pll *pll = &dsi->pll;
1457
1458 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss);
1459 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module);
1460
1461 if (dsi_runtime_get(dsi))
1462 return;
1463
1464 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1465
1466 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
1467
1468 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
1469
1470 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n",
1471 cinfo->clkdco, cinfo->m);
1472
1473 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
1474 dss_get_clk_source_name(dsi_module == 0 ?
1475 DSS_CLK_SRC_PLL1_1 :
1476 DSS_CLK_SRC_PLL2_1),
1477 cinfo->clkout[HSDIV_DISPC],
1478 cinfo->mX[HSDIV_DISPC],
1479 dispc_clk_src == DSS_CLK_SRC_FCK ?
1480 "off" : "on");
1481
1482 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
1483 dss_get_clk_source_name(dsi_module == 0 ?
1484 DSS_CLK_SRC_PLL1_2 :
1485 DSS_CLK_SRC_PLL2_2),
1486 cinfo->clkout[HSDIV_DSI],
1487 cinfo->mX[HSDIV_DSI],
1488 dsi_clk_src == DSS_CLK_SRC_FCK ?
1489 "off" : "on");
1490
1491 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1492
1493 seq_printf(s, "dsi fclk source = %s\n",
1494 dss_get_clk_source_name(dsi_clk_src));
1495
1496 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi));
1497
1498 seq_printf(s, "DDR_CLK\t\t%lu\n",
1499 cinfo->clkdco / 4);
1500
1501 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi));
1502
1503 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1504
1505 dsi_runtime_put(dsi);
1506}
1507
1508void dsi_dump_clocks(struct seq_file *s)
1509{
1510 struct dsi_data *dsi;
1511 int i;
1512
1513 for (i = 0; i < MAX_NUM_DSI; i++) {
1514 dsi = dsi_get_dsi_from_id(i);
1515 if (dsi)
1516 dsi_dump_dsi_clocks(dsi, s);
1517 }
1518}
1519
1520#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1521static void dsi_dump_dsi_irqs(struct dsi_data *dsi, struct seq_file *s)
1522{
1523 unsigned long flags;
1524 struct dsi_irq_stats stats;
1525
1526 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1527
1528 stats = dsi->irq_stats;
1529 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1530 dsi->irq_stats.last_reset = jiffies;
1531
1532 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1533
1534 seq_printf(s, "period %u ms\n",
1535 jiffies_to_msecs(jiffies - stats.last_reset));
1536
1537 seq_printf(s, "irqs %d\n", stats.irq_count);
1538#define PIS(x) \
1539 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1540
1541 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1542 PIS(VC0);
1543 PIS(VC1);
1544 PIS(VC2);
1545 PIS(VC3);
1546 PIS(WAKEUP);
1547 PIS(RESYNC);
1548 PIS(PLL_LOCK);
1549 PIS(PLL_UNLOCK);
1550 PIS(PLL_RECALL);
1551 PIS(COMPLEXIO_ERR);
1552 PIS(HS_TX_TIMEOUT);
1553 PIS(LP_RX_TIMEOUT);
1554 PIS(TE_TRIGGER);
1555 PIS(ACK_TRIGGER);
1556 PIS(SYNC_LOST);
1557 PIS(LDO_POWER_GOOD);
1558 PIS(TA_TIMEOUT);
1559#undef PIS
1560
1561#define PIS(x) \
1562 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1563 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1564 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1565 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1566 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1567
1568 seq_printf(s, "-- VC interrupts --\n");
1569 PIS(CS);
1570 PIS(ECC_CORR);
1571 PIS(PACKET_SENT);
1572 PIS(FIFO_TX_OVF);
1573 PIS(FIFO_RX_OVF);
1574 PIS(BTA);
1575 PIS(ECC_NO_CORR);
1576 PIS(FIFO_TX_UDF);
1577 PIS(PP_BUSY_CHANGE);
1578#undef PIS
1579
1580#define PIS(x) \
1581 seq_printf(s, "%-20s %10d\n", #x, \
1582 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1583
1584 seq_printf(s, "-- CIO interrupts --\n");
1585 PIS(ERRSYNCESC1);
1586 PIS(ERRSYNCESC2);
1587 PIS(ERRSYNCESC3);
1588 PIS(ERRESC1);
1589 PIS(ERRESC2);
1590 PIS(ERRESC3);
1591 PIS(ERRCONTROL1);
1592 PIS(ERRCONTROL2);
1593 PIS(ERRCONTROL3);
1594 PIS(STATEULPS1);
1595 PIS(STATEULPS2);
1596 PIS(STATEULPS3);
1597 PIS(ERRCONTENTIONLP0_1);
1598 PIS(ERRCONTENTIONLP1_1);
1599 PIS(ERRCONTENTIONLP0_2);
1600 PIS(ERRCONTENTIONLP1_2);
1601 PIS(ERRCONTENTIONLP0_3);
1602 PIS(ERRCONTENTIONLP1_3);
1603 PIS(ULPSACTIVENOT_ALL0);
1604 PIS(ULPSACTIVENOT_ALL1);
1605#undef PIS
1606}
1607
1608static int dsi1_dump_irqs(struct seq_file *s, void *p)
1609{
1610 struct dsi_data *dsi = dsi_get_dsi_from_id(0);
1611
1612 dsi_dump_dsi_irqs(dsi, s);
1613 return 0;
1614}
1615
1616static int dsi2_dump_irqs(struct seq_file *s, void *p)
1617{
1618 struct dsi_data *dsi = dsi_get_dsi_from_id(1);
1619
1620 dsi_dump_dsi_irqs(dsi, s);
1621 return 0;
1622}
1623#endif
1624
1625static void dsi_dump_dsi_regs(struct dsi_data *dsi, struct seq_file *s)
1626{
1627#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r))
1628
1629 if (dsi_runtime_get(dsi))
1630 return;
1631 dsi_enable_scp_clk(dsi);
1632
1633 DUMPREG(DSI_REVISION);
1634 DUMPREG(DSI_SYSCONFIG);
1635 DUMPREG(DSI_SYSSTATUS);
1636 DUMPREG(DSI_IRQSTATUS);
1637 DUMPREG(DSI_IRQENABLE);
1638 DUMPREG(DSI_CTRL);
1639 DUMPREG(DSI_COMPLEXIO_CFG1);
1640 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1641 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1642 DUMPREG(DSI_CLK_CTRL);
1643 DUMPREG(DSI_TIMING1);
1644 DUMPREG(DSI_TIMING2);
1645 DUMPREG(DSI_VM_TIMING1);
1646 DUMPREG(DSI_VM_TIMING2);
1647 DUMPREG(DSI_VM_TIMING3);
1648 DUMPREG(DSI_CLK_TIMING);
1649 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1650 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1651 DUMPREG(DSI_COMPLEXIO_CFG2);
1652 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1653 DUMPREG(DSI_VM_TIMING4);
1654 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1655 DUMPREG(DSI_VM_TIMING5);
1656 DUMPREG(DSI_VM_TIMING6);
1657 DUMPREG(DSI_VM_TIMING7);
1658 DUMPREG(DSI_STOPCLK_TIMING);
1659
1660 DUMPREG(DSI_VC_CTRL(0));
1661 DUMPREG(DSI_VC_TE(0));
1662 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1663 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1664 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1665 DUMPREG(DSI_VC_IRQSTATUS(0));
1666 DUMPREG(DSI_VC_IRQENABLE(0));
1667
1668 DUMPREG(DSI_VC_CTRL(1));
1669 DUMPREG(DSI_VC_TE(1));
1670 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1671 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1672 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1673 DUMPREG(DSI_VC_IRQSTATUS(1));
1674 DUMPREG(DSI_VC_IRQENABLE(1));
1675
1676 DUMPREG(DSI_VC_CTRL(2));
1677 DUMPREG(DSI_VC_TE(2));
1678 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1679 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1680 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1681 DUMPREG(DSI_VC_IRQSTATUS(2));
1682 DUMPREG(DSI_VC_IRQENABLE(2));
1683
1684 DUMPREG(DSI_VC_CTRL(3));
1685 DUMPREG(DSI_VC_TE(3));
1686 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1687 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1688 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1689 DUMPREG(DSI_VC_IRQSTATUS(3));
1690 DUMPREG(DSI_VC_IRQENABLE(3));
1691
1692 DUMPREG(DSI_DSIPHY_CFG0);
1693 DUMPREG(DSI_DSIPHY_CFG1);
1694 DUMPREG(DSI_DSIPHY_CFG2);
1695 DUMPREG(DSI_DSIPHY_CFG5);
1696
1697 DUMPREG(DSI_PLL_CONTROL);
1698 DUMPREG(DSI_PLL_STATUS);
1699 DUMPREG(DSI_PLL_GO);
1700 DUMPREG(DSI_PLL_CONFIGURATION1);
1701 DUMPREG(DSI_PLL_CONFIGURATION2);
1702
1703 dsi_disable_scp_clk(dsi);
1704 dsi_runtime_put(dsi);
1705#undef DUMPREG
1706}
1707
1708static int dsi1_dump_regs(struct seq_file *s, void *p)
1709{
1710 struct dsi_data *dsi = dsi_get_dsi_from_id(0);
1711
1712 dsi_dump_dsi_regs(dsi, s);
1713 return 0;
1714}
1715
1716static int dsi2_dump_regs(struct seq_file *s, void *p)
1717{
1718 struct dsi_data *dsi = dsi_get_dsi_from_id(1);
1719
1720 dsi_dump_dsi_regs(dsi, s);
1721 return 0;
1722}
1723
1724enum dsi_cio_power_state {
1725 DSI_COMPLEXIO_POWER_OFF = 0x0,
1726 DSI_COMPLEXIO_POWER_ON = 0x1,
1727 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1728};
1729
1730static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state)
1731{
1732 int t = 0;
1733
1734 /* PWR_CMD */
1735 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27);
1736
1737 /* PWR_STATUS */
1738 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1),
1739 26, 25) != state) {
1740 if (++t > 1000) {
1741 DSSERR("failed to set complexio power state to "
1742 "%d\n", state);
1743 return -ENODEV;
1744 }
1745 udelay(1);
1746 }
1747
1748 return 0;
1749}
1750
1751static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi)
1752{
1753 int val;
1754
1755 /* line buffer on OMAP3 is 1024 x 24bits */
1756 /* XXX: for some reason using full buffer size causes
1757 * considerable TX slowdown with update sizes that fill the
1758 * whole buffer */
1759 if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1760 return 1023 * 3;
1761
1762 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1763
1764 switch (val) {
1765 case 1:
1766 return 512 * 3; /* 512x24 bits */
1767 case 2:
1768 return 682 * 3; /* 682x24 bits */
1769 case 3:
1770 return 853 * 3; /* 853x24 bits */
1771 case 4:
1772 return 1024 * 3; /* 1024x24 bits */
1773 case 5:
1774 return 1194 * 3; /* 1194x24 bits */
1775 case 6:
1776 return 1365 * 3; /* 1365x24 bits */
1777 case 7:
1778 return 1920 * 3; /* 1920x24 bits */
1779 default:
1780 BUG();
1781 return 0;
1782 }
1783}
1784
1785static int dsi_set_lane_config(struct dsi_data *dsi)
1786{
1787 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1788 static const enum dsi_lane_function functions[] = {
1789 DSI_LANE_CLK,
1790 DSI_LANE_DATA1,
1791 DSI_LANE_DATA2,
1792 DSI_LANE_DATA3,
1793 DSI_LANE_DATA4,
1794 };
1795 u32 r;
1796 int i;
1797
1798 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1);
1799
1800 for (i = 0; i < dsi->num_lanes_used; ++i) {
1801 unsigned int offset = offsets[i];
1802 unsigned int polarity, lane_number;
1803 unsigned int t;
1804
1805 for (t = 0; t < dsi->num_lanes_supported; ++t)
1806 if (dsi->lanes[t].function == functions[i])
1807 break;
1808
1809 if (t == dsi->num_lanes_supported)
1810 return -EINVAL;
1811
1812 lane_number = t;
1813 polarity = dsi->lanes[t].polarity;
1814
1815 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
1816 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
1817 }
1818
1819 /* clear the unused lanes */
1820 for (; i < dsi->num_lanes_supported; ++i) {
1821 unsigned int offset = offsets[i];
1822
1823 r = FLD_MOD(r, 0, offset + 2, offset);
1824 r = FLD_MOD(r, 0, offset + 3, offset + 3);
1825 }
1826
1827 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r);
1828
1829 return 0;
1830}
1831
1832static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns)
1833{
1834 /* convert time in ns to ddr ticks, rounding up */
1835 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1836
1837 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1838}
1839
1840static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr)
1841{
1842 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1843
1844 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1845}
1846
1847static void dsi_cio_timings(struct dsi_data *dsi)
1848{
1849 u32 r;
1850 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1851 u32 tlpx_half, tclk_trail, tclk_zero;
1852 u32 tclk_prepare;
1853
1854 /* calculate timings */
1855
1856 /* 1 * DDR_CLK = 2 * UI */
1857
1858 /* min 40ns + 4*UI max 85ns + 6*UI */
1859 ths_prepare = ns2ddr(dsi, 70) + 2;
1860
1861 /* min 145ns + 10*UI */
1862 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2;
1863
1864 /* min max(8*UI, 60ns+4*UI) */
1865 ths_trail = ns2ddr(dsi, 60) + 5;
1866
1867 /* min 100ns */
1868 ths_exit = ns2ddr(dsi, 145);
1869
1870 /* tlpx min 50n */
1871 tlpx_half = ns2ddr(dsi, 25);
1872
1873 /* min 60ns */
1874 tclk_trail = ns2ddr(dsi, 60) + 2;
1875
1876 /* min 38ns, max 95ns */
1877 tclk_prepare = ns2ddr(dsi, 65);
1878
1879 /* min tclk-prepare + tclk-zero = 300ns */
1880 tclk_zero = ns2ddr(dsi, 260);
1881
1882 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1883 ths_prepare, ddr2ns(dsi, ths_prepare),
1884 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero));
1885 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1886 ths_trail, ddr2ns(dsi, ths_trail),
1887 ths_exit, ddr2ns(dsi, ths_exit));
1888
1889 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1890 "tclk_zero %u (%uns)\n",
1891 tlpx_half, ddr2ns(dsi, tlpx_half),
1892 tclk_trail, ddr2ns(dsi, tclk_trail),
1893 tclk_zero, ddr2ns(dsi, tclk_zero));
1894 DSSDBG("tclk_prepare %u (%uns)\n",
1895 tclk_prepare, ddr2ns(dsi, tclk_prepare));
1896
1897 /* program timings */
1898
1899 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
1900 r = FLD_MOD(r, ths_prepare, 31, 24);
1901 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1902 r = FLD_MOD(r, ths_trail, 15, 8);
1903 r = FLD_MOD(r, ths_exit, 7, 0);
1904 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r);
1905
1906 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
1907 r = FLD_MOD(r, tlpx_half, 20, 16);
1908 r = FLD_MOD(r, tclk_trail, 15, 8);
1909 r = FLD_MOD(r, tclk_zero, 7, 0);
1910
1911 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) {
1912 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
1913 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
1914 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
1915 }
1916
1917 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r);
1918
1919 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
1920 r = FLD_MOD(r, tclk_prepare, 7, 0);
1921 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r);
1922}
1923
1924/* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1925static void dsi_cio_enable_lane_override(struct dsi_data *dsi,
1926 unsigned int mask_p,
1927 unsigned int mask_n)
1928{
1929 int i;
1930 u32 l;
1931 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
1932
1933 l = 0;
1934
1935 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1936 unsigned int p = dsi->lanes[i].polarity;
1937
1938 if (mask_p & (1 << i))
1939 l |= 1 << (i * 2 + (p ? 0 : 1));
1940
1941 if (mask_n & (1 << i))
1942 l |= 1 << (i * 2 + (p ? 1 : 0));
1943 }
1944
1945 /*
1946 * Bits in REGLPTXSCPDAT4TO0DXDY:
1947 * 17: DY0 18: DX0
1948 * 19: DY1 20: DX1
1949 * 21: DY2 22: DX2
1950 * 23: DY3 24: DX3
1951 * 25: DY4 26: DX4
1952 */
1953
1954 /* Set the lane override configuration */
1955
1956 /* REGLPTXSCPDAT4TO0DXDY */
1957 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
1958
1959 /* Enable lane override */
1960
1961 /* ENLPTXSCPDAT */
1962 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27);
1963}
1964
1965static void dsi_cio_disable_lane_override(struct dsi_data *dsi)
1966{
1967 /* Disable lane override */
1968 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
1969 /* Reset the lane override configuration */
1970 /* REGLPTXSCPDAT4TO0DXDY */
1971 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 22, 17);
1972}
1973
1974static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi)
1975{
1976 int t, i;
1977 bool in_use[DSI_MAX_NR_LANES];
1978 static const u8 offsets_old[] = { 28, 27, 26 };
1979 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
1980 const u8 *offsets;
1981
1982 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC)
1983 offsets = offsets_old;
1984 else
1985 offsets = offsets_new;
1986
1987 for (i = 0; i < dsi->num_lanes_supported; ++i)
1988 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
1989
1990 t = 100000;
1991 while (true) {
1992 u32 l;
1993 int ok;
1994
1995 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1996
1997 ok = 0;
1998 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1999 if (!in_use[i] || (l & (1 << offsets[i])))
2000 ok++;
2001 }
2002
2003 if (ok == dsi->num_lanes_supported)
2004 break;
2005
2006 if (--t == 0) {
2007 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2008 if (!in_use[i] || (l & (1 << offsets[i])))
2009 continue;
2010
2011 DSSERR("CIO TXCLKESC%d domain not coming " \
2012 "out of reset\n", i);
2013 }
2014 return -EIO;
2015 }
2016 }
2017
2018 return 0;
2019}
2020
2021/* return bitmask of enabled lanes, lane0 being the lsb */
2022static unsigned int dsi_get_lane_mask(struct dsi_data *dsi)
2023{
2024 unsigned int mask = 0;
2025 int i;
2026
2027 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2028 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2029 mask |= 1 << i;
2030 }
2031
2032 return mask;
2033}
2034
2035/* OMAP4 CONTROL_DSIPHY */
2036#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
2037
2038#define OMAP4_DSI2_LANEENABLE_SHIFT 29
2039#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
2040#define OMAP4_DSI1_LANEENABLE_SHIFT 24
2041#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
2042#define OMAP4_DSI1_PIPD_SHIFT 19
2043#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
2044#define OMAP4_DSI2_PIPD_SHIFT 14
2045#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
2046
2047static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes)
2048{
2049 u32 enable_mask, enable_shift;
2050 u32 pipd_mask, pipd_shift;
2051
2052 if (dsi->module_id == 0) {
2053 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
2054 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
2055 pipd_mask = OMAP4_DSI1_PIPD_MASK;
2056 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
2057 } else if (dsi->module_id == 1) {
2058 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
2059 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
2060 pipd_mask = OMAP4_DSI2_PIPD_MASK;
2061 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
2062 } else {
2063 return -ENODEV;
2064 }
2065
2066 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET,
2067 enable_mask | pipd_mask,
2068 (lanes << enable_shift) | (lanes << pipd_shift));
2069}
2070
2071/* OMAP5 CONTROL_DSIPHY */
2072
2073#define OMAP5_DSIPHY_SYSCON_OFFSET 0x74
2074
2075#define OMAP5_DSI1_LANEENABLE_SHIFT 24
2076#define OMAP5_DSI2_LANEENABLE_SHIFT 19
2077#define OMAP5_DSI_LANEENABLE_MASK 0x1f
2078
2079static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes)
2080{
2081 u32 enable_shift;
2082
2083 if (dsi->module_id == 0)
2084 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT;
2085 else if (dsi->module_id == 1)
2086 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT;
2087 else
2088 return -ENODEV;
2089
2090 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET,
2091 OMAP5_DSI_LANEENABLE_MASK << enable_shift,
2092 lanes << enable_shift);
2093}
2094
2095static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask)
2096{
2097 if (dsi->data->model == DSI_MODEL_OMAP4)
2098 return dsi_omap4_mux_pads(dsi, lane_mask);
2099 if (dsi->data->model == DSI_MODEL_OMAP5)
2100 return dsi_omap5_mux_pads(dsi, lane_mask);
2101 return 0;
2102}
2103
2104static void dsi_disable_pads(struct dsi_data *dsi)
2105{
2106 if (dsi->data->model == DSI_MODEL_OMAP4)
2107 dsi_omap4_mux_pads(dsi, 0);
2108 else if (dsi->data->model == DSI_MODEL_OMAP5)
2109 dsi_omap5_mux_pads(dsi, 0);
2110}
2111
2112static int dsi_cio_init(struct dsi_data *dsi)
2113{
2114 int r;
2115 u32 l;
2116
2117 DSSDBG("DSI CIO init starts");
2118
2119 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi));
2120 if (r)
2121 return r;
2122
2123 dsi_enable_scp_clk(dsi);
2124
2125 /* A dummy read using the SCP interface to any DSIPHY register is
2126 * required after DSIPHY reset to complete the reset of the DSI complex
2127 * I/O. */
2128 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
2129
2130 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) {
2131 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2132 r = -EIO;
2133 goto err_scp_clk_dom;
2134 }
2135
2136 r = dsi_set_lane_config(dsi);
2137 if (r)
2138 goto err_scp_clk_dom;
2139
2140 /* set TX STOP MODE timer to maximum for this operation */
2141 l = dsi_read_reg(dsi, DSI_TIMING1);
2142 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2143 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2144 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2145 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2146 dsi_write_reg(dsi, DSI_TIMING1, l);
2147
2148 if (dsi->ulps_enabled) {
2149 unsigned int mask_p;
2150 int i;
2151
2152 DSSDBG("manual ulps exit\n");
2153
2154 /* ULPS is exited by Mark-1 state for 1ms, followed by
2155 * stop state. DSS HW cannot do this via the normal
2156 * ULPS exit sequence, as after reset the DSS HW thinks
2157 * that we are not in ULPS mode, and refuses to send the
2158 * sequence. So we need to send the ULPS exit sequence
2159 * manually by setting positive lines high and negative lines
2160 * low for 1ms.
2161 */
2162
2163 mask_p = 0;
2164
2165 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2166 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2167 continue;
2168 mask_p |= 1 << i;
2169 }
2170
2171 dsi_cio_enable_lane_override(dsi, mask_p, 0);
2172 }
2173
2174 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON);
2175 if (r)
2176 goto err_cio_pwr;
2177
2178 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) {
2179 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2180 r = -ENODEV;
2181 goto err_cio_pwr_dom;
2182 }
2183
2184 dsi_if_enable(dsi, true);
2185 dsi_if_enable(dsi, false);
2186 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2187
2188 r = dsi_cio_wait_tx_clk_esc_reset(dsi);
2189 if (r)
2190 goto err_tx_clk_esc_rst;
2191
2192 if (dsi->ulps_enabled) {
2193 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2194 ktime_t wait = ns_to_ktime(1000 * 1000);
2195 set_current_state(TASK_UNINTERRUPTIBLE);
2196 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2197
2198 /* Disable the override. The lanes should be set to Mark-11
2199 * state by the HW */
2200 dsi_cio_disable_lane_override(dsi);
2201 }
2202
2203 /* FORCE_TX_STOP_MODE_IO */
2204 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15);
2205
2206 dsi_cio_timings(dsi);
2207
2208 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2209 /* DDR_CLK_ALWAYS_ON */
2210 REG_FLD_MOD(dsi, DSI_CLK_CTRL,
2211 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2212 }
2213
2214 dsi->ulps_enabled = false;
2215
2216 DSSDBG("CIO init done\n");
2217
2218 return 0;
2219
2220err_tx_clk_esc_rst:
2221 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2222err_cio_pwr_dom:
2223 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2224err_cio_pwr:
2225 if (dsi->ulps_enabled)
2226 dsi_cio_disable_lane_override(dsi);
2227err_scp_clk_dom:
2228 dsi_disable_scp_clk(dsi);
2229 dsi_disable_pads(dsi);
2230 return r;
2231}
2232
2233static void dsi_cio_uninit(struct dsi_data *dsi)
2234{
2235 /* DDR_CLK_ALWAYS_ON */
2236 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
2237
2238 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2239 dsi_disable_scp_clk(dsi);
2240 dsi_disable_pads(dsi);
2241}
2242
2243static void dsi_config_tx_fifo(struct dsi_data *dsi,
2244 enum fifo_size size1, enum fifo_size size2,
2245 enum fifo_size size3, enum fifo_size size4)
2246{
2247 u32 r = 0;
2248 int add = 0;
2249 int i;
2250
2251 dsi->vc[0].tx_fifo_size = size1;
2252 dsi->vc[1].tx_fifo_size = size2;
2253 dsi->vc[2].tx_fifo_size = size3;
2254 dsi->vc[3].tx_fifo_size = size4;
2255
2256 for (i = 0; i < 4; i++) {
2257 u8 v;
2258 int size = dsi->vc[i].tx_fifo_size;
2259
2260 if (add + size > 4) {
2261 DSSERR("Illegal FIFO configuration\n");
2262 BUG();
2263 return;
2264 }
2265
2266 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2267 r |= v << (8 * i);
2268 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2269 add += size;
2270 }
2271
2272 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r);
2273}
2274
2275static void dsi_config_rx_fifo(struct dsi_data *dsi,
2276 enum fifo_size size1, enum fifo_size size2,
2277 enum fifo_size size3, enum fifo_size size4)
2278{
2279 u32 r = 0;
2280 int add = 0;
2281 int i;
2282
2283 dsi->vc[0].rx_fifo_size = size1;
2284 dsi->vc[1].rx_fifo_size = size2;
2285 dsi->vc[2].rx_fifo_size = size3;
2286 dsi->vc[3].rx_fifo_size = size4;
2287
2288 for (i = 0; i < 4; i++) {
2289 u8 v;
2290 int size = dsi->vc[i].rx_fifo_size;
2291
2292 if (add + size > 4) {
2293 DSSERR("Illegal FIFO configuration\n");
2294 BUG();
2295 return;
2296 }
2297
2298 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2299 r |= v << (8 * i);
2300 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2301 add += size;
2302 }
2303
2304 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r);
2305}
2306
2307static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi)
2308{
2309 u32 r;
2310
2311 r = dsi_read_reg(dsi, DSI_TIMING1);
2312 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2313 dsi_write_reg(dsi, DSI_TIMING1, r);
2314
2315 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) {
2316 DSSERR("TX_STOP bit not going down\n");
2317 return -EIO;
2318 }
2319
2320 return 0;
2321}
2322
2323static bool dsi_vc_is_enabled(struct dsi_data *dsi, int channel)
2324{
2325 return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0);
2326}
2327
2328static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2329{
2330 struct dsi_packet_sent_handler_data *vp_data =
2331 (struct dsi_packet_sent_handler_data *) data;
2332 struct dsi_data *dsi = vp_data->dsi;
2333 const int channel = dsi->update_channel;
2334 u8 bit = dsi->te_enabled ? 30 : 31;
2335
2336 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0)
2337 complete(vp_data->completion);
2338}
2339
2340static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel)
2341{
2342 DECLARE_COMPLETION_ONSTACK(completion);
2343 struct dsi_packet_sent_handler_data vp_data = {
2344 .dsi = dsi,
2345 .completion = &completion
2346 };
2347 int r = 0;
2348 u8 bit;
2349
2350 bit = dsi->te_enabled ? 30 : 31;
2351
2352 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2353 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2354 if (r)
2355 goto err0;
2356
2357 /* Wait for completion only if TE_EN/TE_START is still set */
2358 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) {
2359 if (wait_for_completion_timeout(&completion,
2360 msecs_to_jiffies(10)) == 0) {
2361 DSSERR("Failed to complete previous frame transfer\n");
2362 r = -EIO;
2363 goto err1;
2364 }
2365 }
2366
2367 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2368 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2369
2370 return 0;
2371err1:
2372 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2373 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2374err0:
2375 return r;
2376}
2377
2378static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2379{
2380 struct dsi_packet_sent_handler_data *l4_data =
2381 (struct dsi_packet_sent_handler_data *) data;
2382 struct dsi_data *dsi = l4_data->dsi;
2383 const int channel = dsi->update_channel;
2384
2385 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0)
2386 complete(l4_data->completion);
2387}
2388
2389static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel)
2390{
2391 DECLARE_COMPLETION_ONSTACK(completion);
2392 struct dsi_packet_sent_handler_data l4_data = {
2393 .dsi = dsi,
2394 .completion = &completion
2395 };
2396 int r = 0;
2397
2398 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2399 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2400 if (r)
2401 goto err0;
2402
2403 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2404 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) {
2405 if (wait_for_completion_timeout(&completion,
2406 msecs_to_jiffies(10)) == 0) {
2407 DSSERR("Failed to complete previous l4 transfer\n");
2408 r = -EIO;
2409 goto err1;
2410 }
2411 }
2412
2413 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2414 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2415
2416 return 0;
2417err1:
2418 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2419 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2420err0:
2421 return r;
2422}
2423
2424static int dsi_sync_vc(struct dsi_data *dsi, int channel)
2425{
2426 WARN_ON(!dsi_bus_is_locked(dsi));
2427
2428 WARN_ON(in_interrupt());
2429
2430 if (!dsi_vc_is_enabled(dsi, channel))
2431 return 0;
2432
2433 switch (dsi->vc[channel].source) {
2434 case DSI_VC_SOURCE_VP:
2435 return dsi_sync_vc_vp(dsi, channel);
2436 case DSI_VC_SOURCE_L4:
2437 return dsi_sync_vc_l4(dsi, channel);
2438 default:
2439 BUG();
2440 return -EINVAL;
2441 }
2442}
2443
2444static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable)
2445{
2446 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2447 channel, enable);
2448
2449 enable = enable ? 1 : 0;
2450
2451 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0);
2452
2453 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 0, enable)) {
2454 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2455 return -EIO;
2456 }
2457
2458 return 0;
2459}
2460
2461static void dsi_vc_initial_config(struct dsi_data *dsi, int channel)
2462{
2463 u32 r;
2464
2465 DSSDBG("Initial config of virtual channel %d", channel);
2466
2467 r = dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2468
2469 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2470 DSSERR("VC(%d) busy when trying to configure it!\n",
2471 channel);
2472
2473 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2474 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2475 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2476 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2477 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2478 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2479 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2480 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH)
2481 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2482
2483 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2484 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2485
2486 dsi_write_reg(dsi, DSI_VC_CTRL(channel), r);
2487
2488 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2489}
2490
2491static int dsi_vc_config_source(struct dsi_data *dsi, int channel,
2492 enum dsi_vc_source source)
2493{
2494 if (dsi->vc[channel].source == source)
2495 return 0;
2496
2497 DSSDBG("Source config of virtual channel %d", channel);
2498
2499 dsi_sync_vc(dsi, channel);
2500
2501 dsi_vc_enable(dsi, channel, 0);
2502
2503 /* VC_BUSY */
2504 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 15, 0)) {
2505 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2506 return -EIO;
2507 }
2508
2509 /* SOURCE, 0 = L4, 1 = video port */
2510 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1);
2511
2512 /* DCS_CMD_ENABLE */
2513 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) {
2514 bool enable = source == DSI_VC_SOURCE_VP;
2515 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30);
2516 }
2517
2518 dsi_vc_enable(dsi, channel, 1);
2519
2520 dsi->vc[channel].source = source;
2521
2522 return 0;
2523}
2524
2525static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2526 bool enable)
2527{
2528 struct dsi_data *dsi = to_dsi_data(dssdev);
2529
2530 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2531
2532 WARN_ON(!dsi_bus_is_locked(dsi));
2533
2534 dsi_vc_enable(dsi, channel, 0);
2535 dsi_if_enable(dsi, 0);
2536
2537 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9);
2538
2539 dsi_vc_enable(dsi, channel, 1);
2540 dsi_if_enable(dsi, 1);
2541
2542 dsi_force_tx_stop_mode_io(dsi);
2543
2544 /* start the DDR clock by sending a NULL packet */
2545 if (dsi->vm_timings.ddr_clk_always_on && enable)
2546 dsi_vc_send_null(dsi, channel);
2547}
2548
2549static void dsi_vc_flush_long_data(struct dsi_data *dsi, int channel)
2550{
2551 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2552 u32 val;
2553 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2554 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2555 (val >> 0) & 0xff,
2556 (val >> 8) & 0xff,
2557 (val >> 16) & 0xff,
2558 (val >> 24) & 0xff);
2559 }
2560}
2561
2562static void dsi_show_rx_ack_with_err(u16 err)
2563{
2564 DSSERR("\tACK with ERROR (%#x):\n", err);
2565 if (err & (1 << 0))
2566 DSSERR("\t\tSoT Error\n");
2567 if (err & (1 << 1))
2568 DSSERR("\t\tSoT Sync Error\n");
2569 if (err & (1 << 2))
2570 DSSERR("\t\tEoT Sync Error\n");
2571 if (err & (1 << 3))
2572 DSSERR("\t\tEscape Mode Entry Command Error\n");
2573 if (err & (1 << 4))
2574 DSSERR("\t\tLP Transmit Sync Error\n");
2575 if (err & (1 << 5))
2576 DSSERR("\t\tHS Receive Timeout Error\n");
2577 if (err & (1 << 6))
2578 DSSERR("\t\tFalse Control Error\n");
2579 if (err & (1 << 7))
2580 DSSERR("\t\t(reserved7)\n");
2581 if (err & (1 << 8))
2582 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2583 if (err & (1 << 9))
2584 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2585 if (err & (1 << 10))
2586 DSSERR("\t\tChecksum Error\n");
2587 if (err & (1 << 11))
2588 DSSERR("\t\tData type not recognized\n");
2589 if (err & (1 << 12))
2590 DSSERR("\t\tInvalid VC ID\n");
2591 if (err & (1 << 13))
2592 DSSERR("\t\tInvalid Transmission Length\n");
2593 if (err & (1 << 14))
2594 DSSERR("\t\t(reserved14)\n");
2595 if (err & (1 << 15))
2596 DSSERR("\t\tDSI Protocol Violation\n");
2597}
2598
2599static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel)
2600{
2601 /* RX_FIFO_NOT_EMPTY */
2602 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2603 u32 val;
2604 u8 dt;
2605 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2606 DSSERR("\trawval %#08x\n", val);
2607 dt = FLD_GET(val, 5, 0);
2608 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2609 u16 err = FLD_GET(val, 23, 8);
2610 dsi_show_rx_ack_with_err(err);
2611 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2612 DSSERR("\tDCS short response, 1 byte: %#x\n",
2613 FLD_GET(val, 23, 8));
2614 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2615 DSSERR("\tDCS short response, 2 byte: %#x\n",
2616 FLD_GET(val, 23, 8));
2617 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2618 DSSERR("\tDCS long response, len %d\n",
2619 FLD_GET(val, 23, 8));
2620 dsi_vc_flush_long_data(dsi, channel);
2621 } else {
2622 DSSERR("\tunknown datatype 0x%02x\n", dt);
2623 }
2624 }
2625 return 0;
2626}
2627
2628static int dsi_vc_send_bta(struct dsi_data *dsi, int channel)
2629{
2630 if (dsi->debug_write || dsi->debug_read)
2631 DSSDBG("dsi_vc_send_bta %d\n", channel);
2632
2633 WARN_ON(!dsi_bus_is_locked(dsi));
2634
2635 /* RX_FIFO_NOT_EMPTY */
2636 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2637 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2638 dsi_vc_flush_receive_data(dsi, channel);
2639 }
2640
2641 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2642
2643 /* flush posted write */
2644 dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2645
2646 return 0;
2647}
2648
2649static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2650{
2651 struct dsi_data *dsi = to_dsi_data(dssdev);
2652 DECLARE_COMPLETION_ONSTACK(completion);
2653 int r = 0;
2654 u32 err;
2655
2656 r = dsi_register_isr_vc(dsi, channel, dsi_completion_handler,
2657 &completion, DSI_VC_IRQ_BTA);
2658 if (r)
2659 goto err0;
2660
2661 r = dsi_register_isr(dsi, dsi_completion_handler, &completion,
2662 DSI_IRQ_ERROR_MASK);
2663 if (r)
2664 goto err1;
2665
2666 r = dsi_vc_send_bta(dsi, channel);
2667 if (r)
2668 goto err2;
2669
2670 if (wait_for_completion_timeout(&completion,
2671 msecs_to_jiffies(500)) == 0) {
2672 DSSERR("Failed to receive BTA\n");
2673 r = -EIO;
2674 goto err2;
2675 }
2676
2677 err = dsi_get_errors(dsi);
2678 if (err) {
2679 DSSERR("Error while sending BTA: %x\n", err);
2680 r = -EIO;
2681 goto err2;
2682 }
2683err2:
2684 dsi_unregister_isr(dsi, dsi_completion_handler, &completion,
2685 DSI_IRQ_ERROR_MASK);
2686err1:
2687 dsi_unregister_isr_vc(dsi, channel, dsi_completion_handler,
2688 &completion, DSI_VC_IRQ_BTA);
2689err0:
2690 return r;
2691}
2692
2693static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel,
2694 u8 data_type, u16 len, u8 ecc)
2695{
2696 u32 val;
2697 u8 data_id;
2698
2699 WARN_ON(!dsi_bus_is_locked(dsi));
2700
2701 data_id = data_type | dsi->vc[channel].vc_id << 6;
2702
2703 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2704 FLD_VAL(ecc, 31, 24);
2705
2706 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val);
2707}
2708
2709static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel,
2710 u8 b1, u8 b2, u8 b3, u8 b4)
2711{
2712 u32 val;
2713
2714 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2715
2716/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2717 b1, b2, b3, b4, val); */
2718
2719 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2720}
2721
2722static int dsi_vc_send_long(struct dsi_data *dsi, int channel, u8 data_type,
2723 u8 *data, u16 len, u8 ecc)
2724{
2725 /*u32 val; */
2726 int i;
2727 u8 *p;
2728 int r = 0;
2729 u8 b1, b2, b3, b4;
2730
2731 if (dsi->debug_write)
2732 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2733
2734 /* len + header */
2735 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2736 DSSERR("unable to send long packet: packet too long.\n");
2737 return -EINVAL;
2738 }
2739
2740 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2741
2742 dsi_vc_write_long_header(dsi, channel, data_type, len, ecc);
2743
2744 p = data;
2745 for (i = 0; i < len >> 2; i++) {
2746 if (dsi->debug_write)
2747 DSSDBG("\tsending full packet %d\n", i);
2748
2749 b1 = *p++;
2750 b2 = *p++;
2751 b3 = *p++;
2752 b4 = *p++;
2753
2754 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, b4);
2755 }
2756
2757 i = len % 4;
2758 if (i) {
2759 b1 = 0; b2 = 0; b3 = 0;
2760
2761 if (dsi->debug_write)
2762 DSSDBG("\tsending remainder bytes %d\n", i);
2763
2764 switch (i) {
2765 case 3:
2766 b1 = *p++;
2767 b2 = *p++;
2768 b3 = *p++;
2769 break;
2770 case 2:
2771 b1 = *p++;
2772 b2 = *p++;
2773 break;
2774 case 1:
2775 b1 = *p++;
2776 break;
2777 }
2778
2779 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, 0);
2780 }
2781
2782 return r;
2783}
2784
2785static int dsi_vc_send_short(struct dsi_data *dsi, int channel, u8 data_type,
2786 u16 data, u8 ecc)
2787{
2788 u32 r;
2789 u8 data_id;
2790
2791 WARN_ON(!dsi_bus_is_locked(dsi));
2792
2793 if (dsi->debug_write)
2794 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2795 channel,
2796 data_type, data & 0xff, (data >> 8) & 0xff);
2797
2798 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2799
2800 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(channel)), 16, 16)) {
2801 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2802 return -EINVAL;
2803 }
2804
2805 data_id = data_type | dsi->vc[channel].vc_id << 6;
2806
2807 r = (data_id << 0) | (data << 8) | (ecc << 24);
2808
2809 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2810
2811 return 0;
2812}
2813
2814static int dsi_vc_send_null(struct dsi_data *dsi, int channel)
2815{
2816 return dsi_vc_send_long(dsi, channel, MIPI_DSI_NULL_PACKET, NULL, 0, 0);
2817}
2818
2819static int dsi_vc_write_nosync_common(struct dsi_data *dsi, int channel,
2820 u8 *data, int len,
2821 enum dss_dsi_content_type type)
2822{
2823 int r;
2824
2825 if (len == 0) {
2826 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2827 r = dsi_vc_send_short(dsi, channel,
2828 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2829 } else if (len == 1) {
2830 r = dsi_vc_send_short(dsi, channel,
2831 type == DSS_DSI_CONTENT_GENERIC ?
2832 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2833 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2834 } else if (len == 2) {
2835 r = dsi_vc_send_short(dsi, channel,
2836 type == DSS_DSI_CONTENT_GENERIC ?
2837 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2838 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2839 data[0] | (data[1] << 8), 0);
2840 } else {
2841 r = dsi_vc_send_long(dsi, channel,
2842 type == DSS_DSI_CONTENT_GENERIC ?
2843 MIPI_DSI_GENERIC_LONG_WRITE :
2844 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2845 }
2846
2847 return r;
2848}
2849
2850static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2851 u8 *data, int len)
2852{
2853 struct dsi_data *dsi = to_dsi_data(dssdev);
2854
2855 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2856 DSS_DSI_CONTENT_DCS);
2857}
2858
2859static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2860 u8 *data, int len)
2861{
2862 struct dsi_data *dsi = to_dsi_data(dssdev);
2863
2864 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2865 DSS_DSI_CONTENT_GENERIC);
2866}
2867
2868static int dsi_vc_write_common(struct omap_dss_device *dssdev,
2869 int channel, u8 *data, int len,
2870 enum dss_dsi_content_type type)
2871{
2872 struct dsi_data *dsi = to_dsi_data(dssdev);
2873 int r;
2874
2875 r = dsi_vc_write_nosync_common(dsi, channel, data, len, type);
2876 if (r)
2877 goto err;
2878
2879 r = dsi_vc_send_bta_sync(dssdev, channel);
2880 if (r)
2881 goto err;
2882
2883 /* RX_FIFO_NOT_EMPTY */
2884 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2885 DSSERR("rx fifo not empty after write, dumping data:\n");
2886 dsi_vc_flush_receive_data(dsi, channel);
2887 r = -EIO;
2888 goto err;
2889 }
2890
2891 return 0;
2892err:
2893 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
2894 channel, data[0], len);
2895 return r;
2896}
2897
2898static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2899 int len)
2900{
2901 return dsi_vc_write_common(dssdev, channel, data, len,
2902 DSS_DSI_CONTENT_DCS);
2903}
2904
2905static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2906 int len)
2907{
2908 return dsi_vc_write_common(dssdev, channel, data, len,
2909 DSS_DSI_CONTENT_GENERIC);
2910}
2911
2912static int dsi_vc_dcs_send_read_request(struct dsi_data *dsi, int channel,
2913 u8 dcs_cmd)
2914{
2915 int r;
2916
2917 if (dsi->debug_read)
2918 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2919 channel, dcs_cmd);
2920
2921 r = dsi_vc_send_short(dsi, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
2922 if (r) {
2923 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
2924 " failed\n", channel, dcs_cmd);
2925 return r;
2926 }
2927
2928 return 0;
2929}
2930
2931static int dsi_vc_generic_send_read_request(struct dsi_data *dsi, int channel,
2932 u8 *reqdata, int reqlen)
2933{
2934 u16 data;
2935 u8 data_type;
2936 int r;
2937
2938 if (dsi->debug_read)
2939 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
2940 channel, reqlen);
2941
2942 if (reqlen == 0) {
2943 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
2944 data = 0;
2945 } else if (reqlen == 1) {
2946 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
2947 data = reqdata[0];
2948 } else if (reqlen == 2) {
2949 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
2950 data = reqdata[0] | (reqdata[1] << 8);
2951 } else {
2952 BUG();
2953 return -EINVAL;
2954 }
2955
2956 r = dsi_vc_send_short(dsi, channel, data_type, data, 0);
2957 if (r) {
2958 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
2959 " failed\n", channel, reqlen);
2960 return r;
2961 }
2962
2963 return 0;
2964}
2965
2966static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf,
2967 int buflen, enum dss_dsi_content_type type)
2968{
2969 u32 val;
2970 u8 dt;
2971 int r;
2972
2973 /* RX_FIFO_NOT_EMPTY */
2974 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) {
2975 DSSERR("RX fifo empty when trying to read.\n");
2976 r = -EIO;
2977 goto err;
2978 }
2979
2980 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2981 if (dsi->debug_read)
2982 DSSDBG("\theader: %08x\n", val);
2983 dt = FLD_GET(val, 5, 0);
2984 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2985 u16 err = FLD_GET(val, 23, 8);
2986 dsi_show_rx_ack_with_err(err);
2987 r = -EIO;
2988 goto err;
2989
2990 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
2991 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
2992 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
2993 u8 data = FLD_GET(val, 15, 8);
2994 if (dsi->debug_read)
2995 DSSDBG("\t%s short response, 1 byte: %02x\n",
2996 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
2997 "DCS", data);
2998
2999 if (buflen < 1) {
3000 r = -EIO;
3001 goto err;
3002 }
3003
3004 buf[0] = data;
3005
3006 return 1;
3007 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3008 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3009 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3010 u16 data = FLD_GET(val, 23, 8);
3011 if (dsi->debug_read)
3012 DSSDBG("\t%s short response, 2 byte: %04x\n",
3013 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3014 "DCS", data);
3015
3016 if (buflen < 2) {
3017 r = -EIO;
3018 goto err;
3019 }
3020
3021 buf[0] = data & 0xff;
3022 buf[1] = (data >> 8) & 0xff;
3023
3024 return 2;
3025 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3026 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3027 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3028 int w;
3029 int len = FLD_GET(val, 23, 8);
3030 if (dsi->debug_read)
3031 DSSDBG("\t%s long response, len %d\n",
3032 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3033 "DCS", len);
3034
3035 if (len > buflen) {
3036 r = -EIO;
3037 goto err;
3038 }
3039
3040 /* two byte checksum ends the packet, not included in len */
3041 for (w = 0; w < len + 2;) {
3042 int b;
3043 val = dsi_read_reg(dsi,
3044 DSI_VC_SHORT_PACKET_HEADER(channel));
3045 if (dsi->debug_read)
3046 DSSDBG("\t\t%02x %02x %02x %02x\n",
3047 (val >> 0) & 0xff,
3048 (val >> 8) & 0xff,
3049 (val >> 16) & 0xff,
3050 (val >> 24) & 0xff);
3051
3052 for (b = 0; b < 4; ++b) {
3053 if (w < len)
3054 buf[w] = (val >> (b * 8)) & 0xff;
3055 /* we discard the 2 byte checksum */
3056 ++w;
3057 }
3058 }
3059
3060 return len;
3061 } else {
3062 DSSERR("\tunknown datatype 0x%02x\n", dt);
3063 r = -EIO;
3064 goto err;
3065 }
3066
3067err:
3068 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3069 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3070
3071 return r;
3072}
3073
3074static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3075 u8 *buf, int buflen)
3076{
3077 struct dsi_data *dsi = to_dsi_data(dssdev);
3078 int r;
3079
3080 r = dsi_vc_dcs_send_read_request(dsi, channel, dcs_cmd);
3081 if (r)
3082 goto err;
3083
3084 r = dsi_vc_send_bta_sync(dssdev, channel);
3085 if (r)
3086 goto err;
3087
3088 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
3089 DSS_DSI_CONTENT_DCS);
3090 if (r < 0)
3091 goto err;
3092
3093 if (r != buflen) {
3094 r = -EIO;
3095 goto err;
3096 }
3097
3098 return 0;
3099err:
3100 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3101 return r;
3102}
3103
3104static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3105 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3106{
3107 struct dsi_data *dsi = to_dsi_data(dssdev);
3108 int r;
3109
3110 r = dsi_vc_generic_send_read_request(dsi, channel, reqdata, reqlen);
3111 if (r)
3112 return r;
3113
3114 r = dsi_vc_send_bta_sync(dssdev, channel);
3115 if (r)
3116 return r;
3117
3118 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
3119 DSS_DSI_CONTENT_GENERIC);
3120 if (r < 0)
3121 return r;
3122
3123 if (r != buflen) {
3124 r = -EIO;
3125 return r;
3126 }
3127
3128 return 0;
3129}
3130
3131static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3132 u16 len)
3133{
3134 struct dsi_data *dsi = to_dsi_data(dssdev);
3135
3136 return dsi_vc_send_short(dsi, channel,
3137 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3138}
3139
3140static int dsi_enter_ulps(struct dsi_data *dsi)
3141{
3142 DECLARE_COMPLETION_ONSTACK(completion);
3143 int r, i;
3144 unsigned int mask;
3145
3146 DSSDBG("Entering ULPS");
3147
3148 WARN_ON(!dsi_bus_is_locked(dsi));
3149
3150 WARN_ON(dsi->ulps_enabled);
3151
3152 if (dsi->ulps_enabled)
3153 return 0;
3154
3155 /* DDR_CLK_ALWAYS_ON */
3156 if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) {
3157 dsi_if_enable(dsi, 0);
3158 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
3159 dsi_if_enable(dsi, 1);
3160 }
3161
3162 dsi_sync_vc(dsi, 0);
3163 dsi_sync_vc(dsi, 1);
3164 dsi_sync_vc(dsi, 2);
3165 dsi_sync_vc(dsi, 3);
3166
3167 dsi_force_tx_stop_mode_io(dsi);
3168
3169 dsi_vc_enable(dsi, 0, false);
3170 dsi_vc_enable(dsi, 1, false);
3171 dsi_vc_enable(dsi, 2, false);
3172 dsi_vc_enable(dsi, 3, false);
3173
3174 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3175 DSSERR("HS busy when enabling ULPS\n");
3176 return -EIO;
3177 }
3178
3179 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3180 DSSERR("LP busy when enabling ULPS\n");
3181 return -EIO;
3182 }
3183
3184 r = dsi_register_isr_cio(dsi, dsi_completion_handler, &completion,
3185 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3186 if (r)
3187 return r;
3188
3189 mask = 0;
3190
3191 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3192 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3193 continue;
3194 mask |= 1 << i;
3195 }
3196 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3197 /* LANEx_ULPS_SIG2 */
3198 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3199
3200 /* flush posted write and wait for SCP interface to finish the write */
3201 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3202
3203 if (wait_for_completion_timeout(&completion,
3204 msecs_to_jiffies(1000)) == 0) {
3205 DSSERR("ULPS enable timeout\n");
3206 r = -EIO;
3207 goto err;
3208 }
3209
3210 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3211 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3212
3213 /* Reset LANEx_ULPS_SIG2 */
3214 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3215
3216 /* flush posted write and wait for SCP interface to finish the write */
3217 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3218
3219 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ULPS);
3220
3221 dsi_if_enable(dsi, false);
3222
3223 dsi->ulps_enabled = true;
3224
3225 return 0;
3226
3227err:
3228 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3229 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3230 return r;
3231}
3232
3233static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks,
3234 bool x4, bool x16)
3235{
3236 unsigned long fck;
3237 unsigned long total_ticks;
3238 u32 r;
3239
3240 BUG_ON(ticks > 0x1fff);
3241
3242 /* ticks in DSI_FCK */
3243 fck = dsi_fclk_rate(dsi);
3244
3245 r = dsi_read_reg(dsi, DSI_TIMING2);
3246 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3247 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3248 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3249 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3250 dsi_write_reg(dsi, DSI_TIMING2, r);
3251
3252 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3253
3254 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3255 total_ticks,
3256 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3257 (total_ticks * 1000) / (fck / 1000 / 1000));
3258}
3259
3260static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks,
3261 bool x8, bool x16)
3262{
3263 unsigned long fck;
3264 unsigned long total_ticks;
3265 u32 r;
3266
3267 BUG_ON(ticks > 0x1fff);
3268
3269 /* ticks in DSI_FCK */
3270 fck = dsi_fclk_rate(dsi);
3271
3272 r = dsi_read_reg(dsi, DSI_TIMING1);
3273 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3274 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3275 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3276 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3277 dsi_write_reg(dsi, DSI_TIMING1, r);
3278
3279 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3280
3281 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3282 total_ticks,
3283 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3284 (total_ticks * 1000) / (fck / 1000 / 1000));
3285}
3286
3287static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks,
3288 bool x4, bool x16)
3289{
3290 unsigned long fck;
3291 unsigned long total_ticks;
3292 u32 r;
3293
3294 BUG_ON(ticks > 0x1fff);
3295
3296 /* ticks in DSI_FCK */
3297 fck = dsi_fclk_rate(dsi);
3298
3299 r = dsi_read_reg(dsi, DSI_TIMING1);
3300 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3301 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3302 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3303 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3304 dsi_write_reg(dsi, DSI_TIMING1, r);
3305
3306 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3307
3308 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3309 total_ticks,
3310 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3311 (total_ticks * 1000) / (fck / 1000 / 1000));
3312}
3313
3314static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks,
3315 bool x4, bool x16)
3316{
3317 unsigned long fck;
3318 unsigned long total_ticks;
3319 u32 r;
3320
3321 BUG_ON(ticks > 0x1fff);
3322
3323 /* ticks in TxByteClkHS */
3324 fck = dsi_get_txbyteclkhs(dsi);
3325
3326 r = dsi_read_reg(dsi, DSI_TIMING2);
3327 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3328 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3329 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3330 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3331 dsi_write_reg(dsi, DSI_TIMING2, r);
3332
3333 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3334
3335 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3336 total_ticks,
3337 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3338 (total_ticks * 1000) / (fck / 1000 / 1000));
3339}
3340
3341static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi)
3342{
3343 int num_line_buffers;
3344
3345 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3346 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3347 struct videomode *vm = &dsi->vm;
3348 /*
3349 * Don't use line buffers if width is greater than the video
3350 * port's line buffer size
3351 */
3352 if (dsi->line_buffer_size <= vm->hactive * bpp / 8)
3353 num_line_buffers = 0;
3354 else
3355 num_line_buffers = 2;
3356 } else {
3357 /* Use maximum number of line buffers in command mode */
3358 num_line_buffers = 2;
3359 }
3360
3361 /* LINE_BUFFER */
3362 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12);
3363}
3364
3365static void dsi_config_vp_sync_events(struct dsi_data *dsi)
3366{
3367 bool sync_end;
3368 u32 r;
3369
3370 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3371 sync_end = true;
3372 else
3373 sync_end = false;
3374
3375 r = dsi_read_reg(dsi, DSI_CTRL);
3376 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3377 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3378 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3379 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3380 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3381 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3382 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3383 dsi_write_reg(dsi, DSI_CTRL, r);
3384}
3385
3386static void dsi_config_blanking_modes(struct dsi_data *dsi)
3387{
3388 int blanking_mode = dsi->vm_timings.blanking_mode;
3389 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3390 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3391 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3392 u32 r;
3393
3394 /*
3395 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3396 * 1 = Long blanking packets are sent in corresponding blanking periods
3397 */
3398 r = dsi_read_reg(dsi, DSI_CTRL);
3399 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3400 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3401 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3402 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3403 dsi_write_reg(dsi, DSI_CTRL, r);
3404}
3405
3406/*
3407 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3408 * results in maximum transition time for data and clock lanes to enter and
3409 * exit HS mode. Hence, this is the scenario where the least amount of command
3410 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3411 * clock cycles that can be used to interleave command mode data in HS so that
3412 * all scenarios are satisfied.
3413 */
3414static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3415 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3416{
3417 int transition;
3418
3419 /*
3420 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3421 * time of data lanes only, if it isn't set, we need to consider HS
3422 * transition time of both data and clock lanes. HS transition time
3423 * of Scenario 3 is considered.
3424 */
3425 if (ddr_alwon) {
3426 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3427 } else {
3428 int trans1, trans2;
3429 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3430 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3431 enter_hs + 1;
3432 transition = max(trans1, trans2);
3433 }
3434
3435 return blank > transition ? blank - transition : 0;
3436}
3437
3438/*
3439 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3440 * results in maximum transition time for data lanes to enter and exit LP mode.
3441 * Hence, this is the scenario where the least amount of command mode data can
3442 * be interleaved. We program the minimum amount of bytes that can be
3443 * interleaved in LP so that all scenarios are satisfied.
3444 */
3445static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3446 int lp_clk_div, int tdsi_fclk)
3447{
3448 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3449 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3450 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3451 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3452 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3453
3454 /* maximum LP transition time according to Scenario 1 */
3455 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3456
3457 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3458 tlp_avail = thsbyte_clk * (blank - trans_lp);
3459
3460 ttxclkesc = tdsi_fclk * lp_clk_div;
3461
3462 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3463 26) / 16;
3464
3465 return max(lp_inter, 0);
3466}
3467
3468static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi)
3469{
3470 int blanking_mode;
3471 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3472 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3473 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3474 int tclk_trail, ths_exit, exiths_clk;
3475 bool ddr_alwon;
3476 struct videomode *vm = &dsi->vm;
3477 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3478 int ndl = dsi->num_lanes_used - 1;
3479 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
3480 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3481 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3482 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3483 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3484 u32 r;
3485
3486 r = dsi_read_reg(dsi, DSI_CTRL);
3487 blanking_mode = FLD_GET(r, 20, 20);
3488 hfp_blanking_mode = FLD_GET(r, 21, 21);
3489 hbp_blanking_mode = FLD_GET(r, 22, 22);
3490 hsa_blanking_mode = FLD_GET(r, 23, 23);
3491
3492 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3493 hbp = FLD_GET(r, 11, 0);
3494 hfp = FLD_GET(r, 23, 12);
3495 hsa = FLD_GET(r, 31, 24);
3496
3497 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3498 ddr_clk_post = FLD_GET(r, 7, 0);
3499 ddr_clk_pre = FLD_GET(r, 15, 8);
3500
3501 r = dsi_read_reg(dsi, DSI_VM_TIMING7);
3502 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3503 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3504
3505 r = dsi_read_reg(dsi, DSI_CLK_CTRL);
3506 lp_clk_div = FLD_GET(r, 12, 0);
3507 ddr_alwon = FLD_GET(r, 13, 13);
3508
3509 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3510 ths_exit = FLD_GET(r, 7, 0);
3511
3512 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3513 tclk_trail = FLD_GET(r, 15, 8);
3514
3515 exiths_clk = ths_exit + tclk_trail;
3516
3517 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3518 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3519
3520 if (!hsa_blanking_mode) {
3521 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3522 enter_hs_mode_lat, exit_hs_mode_lat,
3523 exiths_clk, ddr_clk_pre, ddr_clk_post);
3524 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3525 enter_hs_mode_lat, exit_hs_mode_lat,
3526 lp_clk_div, dsi_fclk_hsdiv);
3527 }
3528
3529 if (!hfp_blanking_mode) {
3530 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3531 enter_hs_mode_lat, exit_hs_mode_lat,
3532 exiths_clk, ddr_clk_pre, ddr_clk_post);
3533 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3534 enter_hs_mode_lat, exit_hs_mode_lat,
3535 lp_clk_div, dsi_fclk_hsdiv);
3536 }
3537
3538 if (!hbp_blanking_mode) {
3539 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3540 enter_hs_mode_lat, exit_hs_mode_lat,
3541 exiths_clk, ddr_clk_pre, ddr_clk_post);
3542
3543 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3544 enter_hs_mode_lat, exit_hs_mode_lat,
3545 lp_clk_div, dsi_fclk_hsdiv);
3546 }
3547
3548 if (!blanking_mode) {
3549 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3550 enter_hs_mode_lat, exit_hs_mode_lat,
3551 exiths_clk, ddr_clk_pre, ddr_clk_post);
3552
3553 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3554 enter_hs_mode_lat, exit_hs_mode_lat,
3555 lp_clk_div, dsi_fclk_hsdiv);
3556 }
3557
3558 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3559 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3560 bl_interleave_hs);
3561
3562 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3563 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3564 bl_interleave_lp);
3565
3566 r = dsi_read_reg(dsi, DSI_VM_TIMING4);
3567 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3568 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3569 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3570 dsi_write_reg(dsi, DSI_VM_TIMING4, r);
3571
3572 r = dsi_read_reg(dsi, DSI_VM_TIMING5);
3573 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3574 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3575 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3576 dsi_write_reg(dsi, DSI_VM_TIMING5, r);
3577
3578 r = dsi_read_reg(dsi, DSI_VM_TIMING6);
3579 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3580 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3581 dsi_write_reg(dsi, DSI_VM_TIMING6, r);
3582}
3583
3584static int dsi_proto_config(struct dsi_data *dsi)
3585{
3586 u32 r;
3587 int buswidth = 0;
3588
3589 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32,
3590 DSI_FIFO_SIZE_32,
3591 DSI_FIFO_SIZE_32,
3592 DSI_FIFO_SIZE_32);
3593
3594 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32,
3595 DSI_FIFO_SIZE_32,
3596 DSI_FIFO_SIZE_32,
3597 DSI_FIFO_SIZE_32);
3598
3599 /* XXX what values for the timeouts? */
3600 dsi_set_stop_state_counter(dsi, 0x1000, false, false);
3601 dsi_set_ta_timeout(dsi, 0x1fff, true, true);
3602 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true);
3603 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true);
3604
3605 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3606 case 16:
3607 buswidth = 0;
3608 break;
3609 case 18:
3610 buswidth = 1;
3611 break;
3612 case 24:
3613 buswidth = 2;
3614 break;
3615 default:
3616 BUG();
3617 return -EINVAL;
3618 }
3619
3620 r = dsi_read_reg(dsi, DSI_CTRL);
3621 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3622 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3623 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3624 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3625 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3626 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3627 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3628 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3629 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) {
3630 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3631 /* DCS_CMD_CODE, 1=start, 0=continue */
3632 r = FLD_MOD(r, 0, 25, 25);
3633 }
3634
3635 dsi_write_reg(dsi, DSI_CTRL, r);
3636
3637 dsi_config_vp_num_line_buffers(dsi);
3638
3639 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3640 dsi_config_vp_sync_events(dsi);
3641 dsi_config_blanking_modes(dsi);
3642 dsi_config_cmd_mode_interleaving(dsi);
3643 }
3644
3645 dsi_vc_initial_config(dsi, 0);
3646 dsi_vc_initial_config(dsi, 1);
3647 dsi_vc_initial_config(dsi, 2);
3648 dsi_vc_initial_config(dsi, 3);
3649
3650 return 0;
3651}
3652
3653static void dsi_proto_timings(struct dsi_data *dsi)
3654{
3655 unsigned int tlpx, tclk_zero, tclk_prepare, tclk_trail;
3656 unsigned int tclk_pre, tclk_post;
3657 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero;
3658 unsigned int ths_trail, ths_exit;
3659 unsigned int ddr_clk_pre, ddr_clk_post;
3660 unsigned int enter_hs_mode_lat, exit_hs_mode_lat;
3661 unsigned int ths_eot;
3662 int ndl = dsi->num_lanes_used - 1;
3663 u32 r;
3664
3665 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3666 ths_prepare = FLD_GET(r, 31, 24);
3667 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3668 ths_zero = ths_prepare_ths_zero - ths_prepare;
3669 ths_trail = FLD_GET(r, 15, 8);
3670 ths_exit = FLD_GET(r, 7, 0);
3671
3672 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3673 tlpx = FLD_GET(r, 20, 16) * 2;
3674 tclk_trail = FLD_GET(r, 15, 8);
3675 tclk_zero = FLD_GET(r, 7, 0);
3676
3677 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
3678 tclk_prepare = FLD_GET(r, 7, 0);
3679
3680 /* min 8*UI */
3681 tclk_pre = 20;
3682 /* min 60ns + 52*UI */
3683 tclk_post = ns2ddr(dsi, 60) + 26;
3684
3685 ths_eot = DIV_ROUND_UP(4, ndl);
3686
3687 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3688 4);
3689 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3690
3691 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3692 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3693
3694 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3695 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3696 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3697 dsi_write_reg(dsi, DSI_CLK_TIMING, r);
3698
3699 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3700 ddr_clk_pre,
3701 ddr_clk_post);
3702
3703 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3704 DIV_ROUND_UP(ths_prepare, 4) +
3705 DIV_ROUND_UP(ths_zero + 3, 4);
3706
3707 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3708
3709 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3710 FLD_VAL(exit_hs_mode_lat, 15, 0);
3711 dsi_write_reg(dsi, DSI_VM_TIMING7, r);
3712
3713 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3714 enter_hs_mode_lat, exit_hs_mode_lat);
3715
3716 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3717 /* TODO: Implement a video mode check_timings function */
3718 int hsa = dsi->vm_timings.hsa;
3719 int hfp = dsi->vm_timings.hfp;
3720 int hbp = dsi->vm_timings.hbp;
3721 int vsa = dsi->vm_timings.vsa;
3722 int vfp = dsi->vm_timings.vfp;
3723 int vbp = dsi->vm_timings.vbp;
3724 int window_sync = dsi->vm_timings.window_sync;
3725 bool hsync_end;
3726 struct videomode *vm = &dsi->vm;
3727 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3728 int tl, t_he, width_bytes;
3729
3730 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3731 t_he = hsync_end ?
3732 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3733
3734 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8);
3735
3736 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3737 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3738 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3739
3740 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3741 hfp, hsync_end ? hsa : 0, tl);
3742 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3743 vsa, vm->vactive);
3744
3745 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3746 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3747 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3748 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3749 dsi_write_reg(dsi, DSI_VM_TIMING1, r);
3750
3751 r = dsi_read_reg(dsi, DSI_VM_TIMING2);
3752 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3753 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3754 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3755 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3756 dsi_write_reg(dsi, DSI_VM_TIMING2, r);
3757
3758 r = dsi_read_reg(dsi, DSI_VM_TIMING3);
3759 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */
3760 r = FLD_MOD(r, tl, 31, 16); /* TL */
3761 dsi_write_reg(dsi, DSI_VM_TIMING3, r);
3762 }
3763}
3764
3765static int dsi_configure_pins(struct omap_dss_device *dssdev,
3766 const struct omap_dsi_pin_config *pin_cfg)
3767{
3768 struct dsi_data *dsi = to_dsi_data(dssdev);
3769 int num_pins;
3770 const int *pins;
3771 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3772 int num_lanes;
3773 int i;
3774
3775 static const enum dsi_lane_function functions[] = {
3776 DSI_LANE_CLK,
3777 DSI_LANE_DATA1,
3778 DSI_LANE_DATA2,
3779 DSI_LANE_DATA3,
3780 DSI_LANE_DATA4,
3781 };
3782
3783 num_pins = pin_cfg->num_pins;
3784 pins = pin_cfg->pins;
3785
3786 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3787 || num_pins % 2 != 0)
3788 return -EINVAL;
3789
3790 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3791 lanes[i].function = DSI_LANE_UNUSED;
3792
3793 num_lanes = 0;
3794
3795 for (i = 0; i < num_pins; i += 2) {
3796 u8 lane, pol;
3797 int dx, dy;
3798
3799 dx = pins[i];
3800 dy = pins[i + 1];
3801
3802 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3803 return -EINVAL;
3804
3805 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3806 return -EINVAL;
3807
3808 if (dx & 1) {
3809 if (dy != dx - 1)
3810 return -EINVAL;
3811 pol = 1;
3812 } else {
3813 if (dy != dx + 1)
3814 return -EINVAL;
3815 pol = 0;
3816 }
3817
3818 lane = dx / 2;
3819
3820 lanes[lane].function = functions[i / 2];
3821 lanes[lane].polarity = pol;
3822 num_lanes++;
3823 }
3824
3825 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3826 dsi->num_lanes_used = num_lanes;
3827
3828 return 0;
3829}
3830
3831static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3832{
3833 struct dsi_data *dsi = to_dsi_data(dssdev);
3834 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3835 struct omap_dss_device *out = &dsi->output;
3836 u8 data_type;
3837 u16 word_count;
3838 int r;
3839
3840 if (!out->dispc_channel_connected) {
3841 DSSERR("failed to enable display: no output/manager\n");
3842 return -ENODEV;
3843 }
3844
3845 r = dsi_display_init_dispc(dsi);
3846 if (r)
3847 goto err_init_dispc;
3848
3849 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3850 switch (dsi->pix_fmt) {
3851 case OMAP_DSS_DSI_FMT_RGB888:
3852 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3853 break;
3854 case OMAP_DSS_DSI_FMT_RGB666:
3855 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3856 break;
3857 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3858 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3859 break;
3860 case OMAP_DSS_DSI_FMT_RGB565:
3861 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3862 break;
3863 default:
3864 r = -EINVAL;
3865 goto err_pix_fmt;
3866 }
3867
3868 dsi_if_enable(dsi, false);
3869 dsi_vc_enable(dsi, channel, false);
3870
3871 /* MODE, 1 = video mode */
3872 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4);
3873
3874 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3875
3876 dsi_vc_write_long_header(dsi, channel, data_type,
3877 word_count, 0);
3878
3879 dsi_vc_enable(dsi, channel, true);
3880 dsi_if_enable(dsi, true);
3881 }
3882
3883 r = dss_mgr_enable(&dsi->output);
3884 if (r)
3885 goto err_mgr_enable;
3886
3887 return 0;
3888
3889err_mgr_enable:
3890 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3891 dsi_if_enable(dsi, false);
3892 dsi_vc_enable(dsi, channel, false);
3893 }
3894err_pix_fmt:
3895 dsi_display_uninit_dispc(dsi);
3896err_init_dispc:
3897 return r;
3898}
3899
3900static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3901{
3902 struct dsi_data *dsi = to_dsi_data(dssdev);
3903
3904 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3905 dsi_if_enable(dsi, false);
3906 dsi_vc_enable(dsi, channel, false);
3907
3908 /* MODE, 0 = command mode */
3909 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4);
3910
3911 dsi_vc_enable(dsi, channel, true);
3912 dsi_if_enable(dsi, true);
3913 }
3914
3915 dss_mgr_disable(&dsi->output);
3916
3917 dsi_display_uninit_dispc(dsi);
3918}
3919
3920static void dsi_update_screen_dispc(struct dsi_data *dsi)
3921{
3922 unsigned int bytespp;
3923 unsigned int bytespl;
3924 unsigned int bytespf;
3925 unsigned int total_len;
3926 unsigned int packet_payload;
3927 unsigned int packet_len;
3928 u32 l;
3929 int r;
3930 const unsigned channel = dsi->update_channel;
3931 const unsigned int line_buf_size = dsi->line_buffer_size;
3932 u16 w = dsi->vm.hactive;
3933 u16 h = dsi->vm.vactive;
3934
3935 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
3936
3937 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_VP);
3938
3939 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
3940 bytespl = w * bytespp;
3941 bytespf = bytespl * h;
3942
3943 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3944 * number of lines in a packet. See errata about VP_CLK_RATIO */
3945
3946 if (bytespf < line_buf_size)
3947 packet_payload = bytespf;
3948 else
3949 packet_payload = (line_buf_size) / bytespl * bytespl;
3950
3951 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3952 total_len = (bytespf / packet_payload) * packet_len;
3953
3954 if (bytespf % packet_payload)
3955 total_len += (bytespf % packet_payload) + 1;
3956
3957 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3958 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
3959
3960 dsi_vc_write_long_header(dsi, channel, MIPI_DSI_DCS_LONG_WRITE,
3961 packet_len, 0);
3962
3963 if (dsi->te_enabled)
3964 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3965 else
3966 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3967 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
3968
3969 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3970 * because DSS interrupts are not capable of waking up the CPU and the
3971 * framedone interrupt could be delayed for quite a long time. I think
3972 * the same goes for any DSS interrupts, but for some reason I have not
3973 * seen the problem anywhere else than here.
3974 */
3975 dispc_disable_sidle(dsi->dss->dispc);
3976
3977 dsi_perf_mark_start(dsi);
3978
3979 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3980 msecs_to_jiffies(250));
3981 BUG_ON(r == 0);
3982
3983 dss_mgr_set_timings(&dsi->output, &dsi->vm);
3984
3985 dss_mgr_start_update(&dsi->output);
3986
3987 if (dsi->te_enabled) {
3988 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3989 * for TE is longer than the timer allows */
3990 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3991
3992 dsi_vc_send_bta(dsi, channel);
3993
3994#ifdef DSI_CATCH_MISSING_TE
3995 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3996#endif
3997 }
3998}
3999
4000#ifdef DSI_CATCH_MISSING_TE
4001static void dsi_te_timeout(struct timer_list *unused)
4002{
4003 DSSERR("TE not received for 250ms!\n");
4004}
4005#endif
4006
4007static void dsi_handle_framedone(struct dsi_data *dsi, int error)
4008{
4009 /* SIDLEMODE back to smart-idle */
4010 dispc_enable_sidle(dsi->dss->dispc);
4011
4012 if (dsi->te_enabled) {
4013 /* enable LP_RX_TO again after the TE */
4014 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4015 }
4016
4017 dsi->framedone_callback(error, dsi->framedone_data);
4018
4019 if (!error)
4020 dsi_perf_show(dsi, "DISPC");
4021}
4022
4023static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4024{
4025 struct dsi_data *dsi = container_of(work, struct dsi_data,
4026 framedone_timeout_work.work);
4027 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4028 * 250ms which would conflict with this timeout work. What should be
4029 * done is first cancel the transfer on the HW, and then cancel the
4030 * possibly scheduled framedone work. However, cancelling the transfer
4031 * on the HW is buggy, and would probably require resetting the whole
4032 * DSI */
4033
4034 DSSERR("Framedone not received for 250ms!\n");
4035
4036 dsi_handle_framedone(dsi, -ETIMEDOUT);
4037}
4038
4039static void dsi_framedone_irq_callback(void *data)
4040{
4041 struct dsi_data *dsi = data;
4042
4043 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4044 * turns itself off. However, DSI still has the pixels in its buffers,
4045 * and is sending the data.
4046 */
4047
4048 cancel_delayed_work(&dsi->framedone_timeout_work);
4049
4050 dsi_handle_framedone(dsi, 0);
4051}
4052
4053static int dsi_update(struct omap_dss_device *dssdev, int channel,
4054 void (*callback)(int, void *), void *data)
4055{
4056 struct dsi_data *dsi = to_dsi_data(dssdev);
4057 u16 dw, dh;
4058
4059 dsi_perf_mark_setup(dsi);
4060
4061 dsi->update_channel = channel;
4062
4063 dsi->framedone_callback = callback;
4064 dsi->framedone_data = data;
4065
4066 dw = dsi->vm.hactive;
4067 dh = dsi->vm.vactive;
4068
4069#ifdef DSI_PERF_MEASURE
4070 dsi->update_bytes = dw * dh *
4071 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4072#endif
4073 dsi_update_screen_dispc(dsi);
4074
4075 return 0;
4076}
4077
4078/* Display funcs */
4079
4080static int dsi_configure_dispc_clocks(struct dsi_data *dsi)
4081{
4082 struct dispc_clock_info dispc_cinfo;
4083 int r;
4084 unsigned long fck;
4085
4086 fck = dsi_get_pll_hsdiv_dispc_rate(dsi);
4087
4088 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4089 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4090
4091 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo);
4092 if (r) {
4093 DSSERR("Failed to calc dispc clocks\n");
4094 return r;
4095 }
4096
4097 dsi->mgr_config.clock_info = dispc_cinfo;
4098
4099 return 0;
4100}
4101
4102static int dsi_display_init_dispc(struct dsi_data *dsi)
4103{
4104 enum omap_channel channel = dsi->output.dispc_channel;
4105 int r;
4106
4107 dss_select_lcd_clk_source(dsi->dss, channel, dsi->module_id == 0 ?
4108 DSS_CLK_SRC_PLL1_1 :
4109 DSS_CLK_SRC_PLL2_1);
4110
4111 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4112 r = dss_mgr_register_framedone_handler(&dsi->output,
4113 dsi_framedone_irq_callback, dsi);
4114 if (r) {
4115 DSSERR("can't register FRAMEDONE handler\n");
4116 goto err;
4117 }
4118
4119 dsi->mgr_config.stallmode = true;
4120 dsi->mgr_config.fifohandcheck = true;
4121 } else {
4122 dsi->mgr_config.stallmode = false;
4123 dsi->mgr_config.fifohandcheck = false;
4124 }
4125
4126 /*
4127 * override interlace, logic level and edge related parameters in
4128 * videomode with default values
4129 */
4130 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED;
4131 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW;
4132 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
4133 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW;
4134 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH;
4135 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE;
4136 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
4137 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW;
4138 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH;
4139 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4140 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4141
4142 dss_mgr_set_timings(&dsi->output, &dsi->vm);
4143
4144 r = dsi_configure_dispc_clocks(dsi);
4145 if (r)
4146 goto err1;
4147
4148 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4149 dsi->mgr_config.video_port_width =
4150 dsi_get_pixel_size(dsi->pix_fmt);
4151 dsi->mgr_config.lcden_sig_polarity = 0;
4152
4153 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config);
4154
4155 return 0;
4156err1:
4157 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4158 dss_mgr_unregister_framedone_handler(&dsi->output,
4159 dsi_framedone_irq_callback, dsi);
4160err:
4161 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4162 return r;
4163}
4164
4165static void dsi_display_uninit_dispc(struct dsi_data *dsi)
4166{
4167 enum omap_channel channel = dsi->output.dispc_channel;
4168
4169 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4170 dss_mgr_unregister_framedone_handler(&dsi->output,
4171 dsi_framedone_irq_callback, dsi);
4172
4173 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4174}
4175
4176static int dsi_configure_dsi_clocks(struct dsi_data *dsi)
4177{
4178 struct dss_pll_clock_info cinfo;
4179 int r;
4180
4181 cinfo = dsi->user_dsi_cinfo;
4182
4183 r = dss_pll_set_config(&dsi->pll, &cinfo);
4184 if (r) {
4185 DSSERR("Failed to set dsi clocks\n");
4186 return r;
4187 }
4188
4189 return 0;
4190}
4191
4192static int dsi_display_init_dsi(struct dsi_data *dsi)
4193{
4194 int r;
4195
4196 r = dss_pll_enable(&dsi->pll);
4197 if (r)
4198 goto err0;
4199
4200 r = dsi_configure_dsi_clocks(dsi);
4201 if (r)
4202 goto err1;
4203
4204 dss_select_dsi_clk_source(dsi->dss, dsi->module_id,
4205 dsi->module_id == 0 ?
4206 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2);
4207
4208 DSSDBG("PLL OK\n");
4209
4210 r = dsi_cio_init(dsi);
4211 if (r)
4212 goto err2;
4213
4214 _dsi_print_reset_status(dsi);
4215
4216 dsi_proto_timings(dsi);
4217 dsi_set_lp_clk_divisor(dsi);
4218
4219 if (1)
4220 _dsi_print_reset_status(dsi);
4221
4222 r = dsi_proto_config(dsi);
4223 if (r)
4224 goto err3;
4225
4226 /* enable interface */
4227 dsi_vc_enable(dsi, 0, 1);
4228 dsi_vc_enable(dsi, 1, 1);
4229 dsi_vc_enable(dsi, 2, 1);
4230 dsi_vc_enable(dsi, 3, 1);
4231 dsi_if_enable(dsi, 1);
4232 dsi_force_tx_stop_mode_io(dsi);
4233
4234 return 0;
4235err3:
4236 dsi_cio_uninit(dsi);
4237err2:
4238 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4239err1:
4240 dss_pll_disable(&dsi->pll);
4241err0:
4242 return r;
4243}
4244
4245static void dsi_display_uninit_dsi(struct dsi_data *dsi, bool disconnect_lanes,
4246 bool enter_ulps)
4247{
4248 if (enter_ulps && !dsi->ulps_enabled)
4249 dsi_enter_ulps(dsi);
4250
4251 /* disable interface */
4252 dsi_if_enable(dsi, 0);
4253 dsi_vc_enable(dsi, 0, 0);
4254 dsi_vc_enable(dsi, 1, 0);
4255 dsi_vc_enable(dsi, 2, 0);
4256 dsi_vc_enable(dsi, 3, 0);
4257
4258 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4259 dsi_cio_uninit(dsi);
4260 dsi_pll_uninit(dsi, disconnect_lanes);
4261}
4262
4263static int dsi_display_enable(struct omap_dss_device *dssdev)
4264{
4265 struct dsi_data *dsi = to_dsi_data(dssdev);
4266 int r = 0;
4267
4268 DSSDBG("dsi_display_enable\n");
4269
4270 WARN_ON(!dsi_bus_is_locked(dsi));
4271
4272 mutex_lock(&dsi->lock);
4273
4274 r = dsi_runtime_get(dsi);
4275 if (r)
4276 goto err_get_dsi;
4277
4278 _dsi_initialize_irq(dsi);
4279
4280 r = dsi_display_init_dsi(dsi);
4281 if (r)
4282 goto err_init_dsi;
4283
4284 mutex_unlock(&dsi->lock);
4285
4286 return 0;
4287
4288err_init_dsi:
4289 dsi_runtime_put(dsi);
4290err_get_dsi:
4291 mutex_unlock(&dsi->lock);
4292 DSSDBG("dsi_display_enable FAILED\n");
4293 return r;
4294}
4295
4296static void dsi_display_disable(struct omap_dss_device *dssdev,
4297 bool disconnect_lanes, bool enter_ulps)
4298{
4299 struct dsi_data *dsi = to_dsi_data(dssdev);
4300
4301 DSSDBG("dsi_display_disable\n");
4302
4303 WARN_ON(!dsi_bus_is_locked(dsi));
4304
4305 mutex_lock(&dsi->lock);
4306
4307 dsi_sync_vc(dsi, 0);
4308 dsi_sync_vc(dsi, 1);
4309 dsi_sync_vc(dsi, 2);
4310 dsi_sync_vc(dsi, 3);
4311
4312 dsi_display_uninit_dsi(dsi, disconnect_lanes, enter_ulps);
4313
4314 dsi_runtime_put(dsi);
4315
4316 mutex_unlock(&dsi->lock);
4317}
4318
4319static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4320{
4321 struct dsi_data *dsi = to_dsi_data(dssdev);
4322
4323 dsi->te_enabled = enable;
4324 return 0;
4325}
4326
4327#ifdef PRINT_VERBOSE_VM_TIMINGS
4328static void print_dsi_vm(const char *str,
4329 const struct omap_dss_dsi_videomode_timings *t)
4330{
4331 unsigned long byteclk = t->hsclk / 4;
4332 int bl, wc, pps, tot;
4333
4334 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4335 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4336 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4337 tot = bl + pps;
4338
4339#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4340
4341 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4342 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4343 str,
4344 byteclk,
4345 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4346 bl, pps, tot,
4347 TO_DSI_T(t->hss),
4348 TO_DSI_T(t->hsa),
4349 TO_DSI_T(t->hse),
4350 TO_DSI_T(t->hbp),
4351 TO_DSI_T(pps),
4352 TO_DSI_T(t->hfp),
4353
4354 TO_DSI_T(bl),
4355 TO_DSI_T(pps),
4356
4357 TO_DSI_T(tot));
4358#undef TO_DSI_T
4359}
4360
4361static void print_dispc_vm(const char *str, const struct videomode *vm)
4362{
4363 unsigned long pck = vm->pixelclock;
4364 int hact, bl, tot;
4365
4366 hact = vm->hactive;
4367 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch;
4368 tot = hact + bl;
4369
4370#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4371
4372 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4373 "%u/%u/%u/%u = %u + %u = %u\n",
4374 str,
4375 pck,
4376 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch,
4377 bl, hact, tot,
4378 TO_DISPC_T(vm->hsync_len),
4379 TO_DISPC_T(vm->hback_porch),
4380 TO_DISPC_T(hact),
4381 TO_DISPC_T(vm->hfront_porch),
4382 TO_DISPC_T(bl),
4383 TO_DISPC_T(hact),
4384 TO_DISPC_T(tot));
4385#undef TO_DISPC_T
4386}
4387
4388/* note: this is not quite accurate */
4389static void print_dsi_dispc_vm(const char *str,
4390 const struct omap_dss_dsi_videomode_timings *t)
4391{
4392 struct videomode vm = { 0 };
4393 unsigned long byteclk = t->hsclk / 4;
4394 unsigned long pck;
4395 u64 dsi_tput;
4396 int dsi_hact, dsi_htot;
4397
4398 dsi_tput = (u64)byteclk * t->ndl * 8;
4399 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4400 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4401 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4402
4403 vm.pixelclock = pck;
4404 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4405 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk);
4406 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk);
4407 vm.hactive = t->hact;
4408
4409 print_dispc_vm(str, &vm);
4410}
4411#endif /* PRINT_VERBOSE_VM_TIMINGS */
4412
4413static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4414 unsigned long pck, void *data)
4415{
4416 struct dsi_clk_calc_ctx *ctx = data;
4417 struct videomode *vm = &ctx->vm;
4418
4419 ctx->dispc_cinfo.lck_div = lckd;
4420 ctx->dispc_cinfo.pck_div = pckd;
4421 ctx->dispc_cinfo.lck = lck;
4422 ctx->dispc_cinfo.pck = pck;
4423
4424 *vm = *ctx->config->vm;
4425 vm->pixelclock = pck;
4426 vm->hactive = ctx->config->vm->hactive;
4427 vm->vactive = ctx->config->vm->vactive;
4428 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1;
4429 vm->vfront_porch = vm->vback_porch = 0;
4430
4431 return true;
4432}
4433
4434static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4435 void *data)
4436{
4437 struct dsi_clk_calc_ctx *ctx = data;
4438
4439 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4440 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4441
4442 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4443 ctx->req_pck_min, ctx->req_pck_max,
4444 dsi_cm_calc_dispc_cb, ctx);
4445}
4446
4447static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4448 unsigned long clkdco, void *data)
4449{
4450 struct dsi_clk_calc_ctx *ctx = data;
4451 struct dsi_data *dsi = ctx->dsi;
4452
4453 ctx->dsi_cinfo.n = n;
4454 ctx->dsi_cinfo.m = m;
4455 ctx->dsi_cinfo.fint = fint;
4456 ctx->dsi_cinfo.clkdco = clkdco;
4457
4458 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4459 dsi->data->max_fck_freq,
4460 dsi_cm_calc_hsdiv_cb, ctx);
4461}
4462
4463static bool dsi_cm_calc(struct dsi_data *dsi,
4464 const struct omap_dss_dsi_config *cfg,
4465 struct dsi_clk_calc_ctx *ctx)
4466{
4467 unsigned long clkin;
4468 int bitspp, ndl;
4469 unsigned long pll_min, pll_max;
4470 unsigned long pck, txbyteclk;
4471
4472 clkin = clk_get_rate(dsi->pll.clkin);
4473 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4474 ndl = dsi->num_lanes_used - 1;
4475
4476 /*
4477 * Here we should calculate minimum txbyteclk to be able to send the
4478 * frame in time, and also to handle TE. That's not very simple, though,
4479 * especially as we go to LP between each pixel packet due to HW
4480 * "feature". So let's just estimate very roughly and multiply by 1.5.
4481 */
4482 pck = cfg->vm->pixelclock;
4483 pck = pck * 3 / 2;
4484 txbyteclk = pck * bitspp / 8 / ndl;
4485
4486 memset(ctx, 0, sizeof(*ctx));
4487 ctx->dsi = dsi;
4488 ctx->pll = &dsi->pll;
4489 ctx->config = cfg;
4490 ctx->req_pck_min = pck;
4491 ctx->req_pck_nom = pck;
4492 ctx->req_pck_max = pck * 3 / 2;
4493
4494 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4495 pll_max = cfg->hs_clk_max * 4;
4496
4497 return dss_pll_calc_a(ctx->pll, clkin,
4498 pll_min, pll_max,
4499 dsi_cm_calc_pll_cb, ctx);
4500}
4501
4502static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4503{
4504 struct dsi_data *dsi = ctx->dsi;
4505 const struct omap_dss_dsi_config *cfg = ctx->config;
4506 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4507 int ndl = dsi->num_lanes_used - 1;
4508 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
4509 unsigned long byteclk = hsclk / 4;
4510
4511 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4512 int xres;
4513 int panel_htot, panel_hbl; /* pixels */
4514 int dispc_htot, dispc_hbl; /* pixels */
4515 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4516 int hfp, hsa, hbp;
4517 const struct videomode *req_vm;
4518 struct videomode *dispc_vm;
4519 struct omap_dss_dsi_videomode_timings *dsi_vm;
4520 u64 dsi_tput, dispc_tput;
4521
4522 dsi_tput = (u64)byteclk * ndl * 8;
4523
4524 req_vm = cfg->vm;
4525 req_pck_min = ctx->req_pck_min;
4526 req_pck_max = ctx->req_pck_max;
4527 req_pck_nom = ctx->req_pck_nom;
4528
4529 dispc_pck = ctx->dispc_cinfo.pck;
4530 dispc_tput = (u64)dispc_pck * bitspp;
4531
4532 xres = req_vm->hactive;
4533
4534 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch +
4535 req_vm->hsync_len;
4536 panel_htot = xres + panel_hbl;
4537
4538 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4539
4540 /*
4541 * When there are no line buffers, DISPC and DSI must have the
4542 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4543 */
4544 if (dsi->line_buffer_size < xres * bitspp / 8) {
4545 if (dispc_tput != dsi_tput)
4546 return false;
4547 } else {
4548 if (dispc_tput < dsi_tput)
4549 return false;
4550 }
4551
4552 /* DSI tput must be over the min requirement */
4553 if (dsi_tput < (u64)bitspp * req_pck_min)
4554 return false;
4555
4556 /* When non-burst mode, DSI tput must be below max requirement. */
4557 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4558 if (dsi_tput > (u64)bitspp * req_pck_max)
4559 return false;
4560 }
4561
4562 hss = DIV_ROUND_UP(4, ndl);
4563
4564 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4565 if (ndl == 3 && req_vm->hsync_len == 0)
4566 hse = 1;
4567 else
4568 hse = DIV_ROUND_UP(4, ndl);
4569 } else {
4570 hse = 0;
4571 }
4572
4573 /* DSI htot to match the panel's nominal pck */
4574 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4575
4576 /* fail if there would be no time for blanking */
4577 if (dsi_htot < hss + hse + dsi_hact)
4578 return false;
4579
4580 /* total DSI blanking needed to achieve panel's TL */
4581 dsi_hbl = dsi_htot - dsi_hact;
4582
4583 /* DISPC htot to match the DSI TL */
4584 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4585
4586 /* verify that the DSI and DISPC TLs are the same */
4587 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4588 return false;
4589
4590 dispc_hbl = dispc_htot - xres;
4591
4592 /* setup DSI videomode */
4593
4594 dsi_vm = &ctx->dsi_vm;
4595 memset(dsi_vm, 0, sizeof(*dsi_vm));
4596
4597 dsi_vm->hsclk = hsclk;
4598
4599 dsi_vm->ndl = ndl;
4600 dsi_vm->bitspp = bitspp;
4601
4602 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4603 hsa = 0;
4604 } else if (ndl == 3 && req_vm->hsync_len == 0) {
4605 hsa = 0;
4606 } else {
4607 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom);
4608 hsa = max(hsa - hse, 1);
4609 }
4610
4611 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom);
4612 hbp = max(hbp, 1);
4613
4614 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4615 if (hfp < 1) {
4616 int t;
4617 /* we need to take cycles from hbp */
4618
4619 t = 1 - hfp;
4620 hbp = max(hbp - t, 1);
4621 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4622
4623 if (hfp < 1 && hsa > 0) {
4624 /* we need to take cycles from hsa */
4625 t = 1 - hfp;
4626 hsa = max(hsa - t, 1);
4627 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4628 }
4629 }
4630
4631 if (hfp < 1)
4632 return false;
4633
4634 dsi_vm->hss = hss;
4635 dsi_vm->hsa = hsa;
4636 dsi_vm->hse = hse;
4637 dsi_vm->hbp = hbp;
4638 dsi_vm->hact = xres;
4639 dsi_vm->hfp = hfp;
4640
4641 dsi_vm->vsa = req_vm->vsync_len;
4642 dsi_vm->vbp = req_vm->vback_porch;
4643 dsi_vm->vact = req_vm->vactive;
4644 dsi_vm->vfp = req_vm->vfront_porch;
4645
4646 dsi_vm->trans_mode = cfg->trans_mode;
4647
4648 dsi_vm->blanking_mode = 0;
4649 dsi_vm->hsa_blanking_mode = 1;
4650 dsi_vm->hfp_blanking_mode = 1;
4651 dsi_vm->hbp_blanking_mode = 1;
4652
4653 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4654 dsi_vm->window_sync = 4;
4655
4656 /* setup DISPC videomode */
4657
4658 dispc_vm = &ctx->vm;
4659 *dispc_vm = *req_vm;
4660 dispc_vm->pixelclock = dispc_pck;
4661
4662 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4663 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck,
4664 req_pck_nom);
4665 hsa = max(hsa, 1);
4666 } else {
4667 hsa = 1;
4668 }
4669
4670 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom);
4671 hbp = max(hbp, 1);
4672
4673 hfp = dispc_hbl - hsa - hbp;
4674 if (hfp < 1) {
4675 int t;
4676 /* we need to take cycles from hbp */
4677
4678 t = 1 - hfp;
4679 hbp = max(hbp - t, 1);
4680 hfp = dispc_hbl - hsa - hbp;
4681
4682 if (hfp < 1) {
4683 /* we need to take cycles from hsa */
4684 t = 1 - hfp;
4685 hsa = max(hsa - t, 1);
4686 hfp = dispc_hbl - hsa - hbp;
4687 }
4688 }
4689
4690 if (hfp < 1)
4691 return false;
4692
4693 dispc_vm->hfront_porch = hfp;
4694 dispc_vm->hsync_len = hsa;
4695 dispc_vm->hback_porch = hbp;
4696
4697 return true;
4698}
4699
4700
4701static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4702 unsigned long pck, void *data)
4703{
4704 struct dsi_clk_calc_ctx *ctx = data;
4705
4706 ctx->dispc_cinfo.lck_div = lckd;
4707 ctx->dispc_cinfo.pck_div = pckd;
4708 ctx->dispc_cinfo.lck = lck;
4709 ctx->dispc_cinfo.pck = pck;
4710
4711 if (dsi_vm_calc_blanking(ctx) == false)
4712 return false;
4713
4714#ifdef PRINT_VERBOSE_VM_TIMINGS
4715 print_dispc_vm("dispc", &ctx->vm);
4716 print_dsi_vm("dsi ", &ctx->dsi_vm);
4717 print_dispc_vm("req ", ctx->config->vm);
4718 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4719#endif
4720
4721 return true;
4722}
4723
4724static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4725 void *data)
4726{
4727 struct dsi_clk_calc_ctx *ctx = data;
4728 unsigned long pck_max;
4729
4730 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4731 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4732
4733 /*
4734 * In burst mode we can let the dispc pck be arbitrarily high, but it
4735 * limits our scaling abilities. So for now, don't aim too high.
4736 */
4737
4738 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4739 pck_max = ctx->req_pck_max + 10000000;
4740 else
4741 pck_max = ctx->req_pck_max;
4742
4743 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4744 ctx->req_pck_min, pck_max,
4745 dsi_vm_calc_dispc_cb, ctx);
4746}
4747
4748static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4749 unsigned long clkdco, void *data)
4750{
4751 struct dsi_clk_calc_ctx *ctx = data;
4752 struct dsi_data *dsi = ctx->dsi;
4753
4754 ctx->dsi_cinfo.n = n;
4755 ctx->dsi_cinfo.m = m;
4756 ctx->dsi_cinfo.fint = fint;
4757 ctx->dsi_cinfo.clkdco = clkdco;
4758
4759 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min,
4760 dsi->data->max_fck_freq,
4761 dsi_vm_calc_hsdiv_cb, ctx);
4762}
4763
4764static bool dsi_vm_calc(struct dsi_data *dsi,
4765 const struct omap_dss_dsi_config *cfg,
4766 struct dsi_clk_calc_ctx *ctx)
4767{
4768 const struct videomode *vm = cfg->vm;
4769 unsigned long clkin;
4770 unsigned long pll_min;
4771 unsigned long pll_max;
4772 int ndl = dsi->num_lanes_used - 1;
4773 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4774 unsigned long byteclk_min;
4775
4776 clkin = clk_get_rate(dsi->pll.clkin);
4777
4778 memset(ctx, 0, sizeof(*ctx));
4779 ctx->dsi = dsi;
4780 ctx->pll = &dsi->pll;
4781 ctx->config = cfg;
4782
4783 /* these limits should come from the panel driver */
4784 ctx->req_pck_min = vm->pixelclock - 1000;
4785 ctx->req_pck_nom = vm->pixelclock;
4786 ctx->req_pck_max = vm->pixelclock + 1000;
4787
4788 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
4789 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
4790
4791 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
4792 pll_max = cfg->hs_clk_max * 4;
4793 } else {
4794 unsigned long byteclk_max;
4795 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
4796 ndl * 8);
4797
4798 pll_max = byteclk_max * 4 * 4;
4799 }
4800
4801 return dss_pll_calc_a(ctx->pll, clkin,
4802 pll_min, pll_max,
4803 dsi_vm_calc_pll_cb, ctx);
4804}
4805
4806static int dsi_set_config(struct omap_dss_device *dssdev,
4807 const struct omap_dss_dsi_config *config)
4808{
4809 struct dsi_data *dsi = to_dsi_data(dssdev);
4810 struct dsi_clk_calc_ctx ctx;
4811 bool ok;
4812 int r;
4813
4814 mutex_lock(&dsi->lock);
4815
4816 dsi->pix_fmt = config->pixel_format;
4817 dsi->mode = config->mode;
4818
4819 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
4820 ok = dsi_vm_calc(dsi, config, &ctx);
4821 else
4822 ok = dsi_cm_calc(dsi, config, &ctx);
4823
4824 if (!ok) {
4825 DSSERR("failed to find suitable DSI clock settings\n");
4826 r = -EINVAL;
4827 goto err;
4828 }
4829
4830 dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo);
4831
4832 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
4833 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
4834 if (r) {
4835 DSSERR("failed to find suitable DSI LP clock settings\n");
4836 goto err;
4837 }
4838
4839 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
4840 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
4841
4842 dsi->vm = ctx.vm;
4843 dsi->vm_timings = ctx.dsi_vm;
4844
4845 mutex_unlock(&dsi->lock);
4846
4847 return 0;
4848err:
4849 mutex_unlock(&dsi->lock);
4850
4851 return r;
4852}
4853
4854/*
4855 * Return a hardcoded channel for the DSI output. This should work for
4856 * current use cases, but this can be later expanded to either resolve
4857 * the channel in some more dynamic manner, or get the channel as a user
4858 * parameter.
4859 */
4860static enum omap_channel dsi_get_channel(struct dsi_data *dsi)
4861{
4862 switch (dsi->data->model) {
4863 case DSI_MODEL_OMAP3:
4864 return OMAP_DSS_CHANNEL_LCD;
4865
4866 case DSI_MODEL_OMAP4:
4867 switch (dsi->module_id) {
4868 case 0:
4869 return OMAP_DSS_CHANNEL_LCD;
4870 case 1:
4871 return OMAP_DSS_CHANNEL_LCD2;
4872 default:
4873 DSSWARN("unsupported module id\n");
4874 return OMAP_DSS_CHANNEL_LCD;
4875 }
4876
4877 case DSI_MODEL_OMAP5:
4878 switch (dsi->module_id) {
4879 case 0:
4880 return OMAP_DSS_CHANNEL_LCD;
4881 case 1:
4882 return OMAP_DSS_CHANNEL_LCD3;
4883 default:
4884 DSSWARN("unsupported module id\n");
4885 return OMAP_DSS_CHANNEL_LCD;
4886 }
4887
4888 default:
4889 DSSWARN("unsupported DSS version\n");
4890 return OMAP_DSS_CHANNEL_LCD;
4891 }
4892}
4893
4894static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4895{
4896 struct dsi_data *dsi = to_dsi_data(dssdev);
4897 int i;
4898
4899 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4900 if (!dsi->vc[i].dssdev) {
4901 dsi->vc[i].dssdev = dssdev;
4902 *channel = i;
4903 return 0;
4904 }
4905 }
4906
4907 DSSERR("cannot get VC for display %s", dssdev->name);
4908 return -ENOSPC;
4909}
4910
4911static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4912{
4913 struct dsi_data *dsi = to_dsi_data(dssdev);
4914
4915 if (vc_id < 0 || vc_id > 3) {
4916 DSSERR("VC ID out of range\n");
4917 return -EINVAL;
4918 }
4919
4920 if (channel < 0 || channel > 3) {
4921 DSSERR("Virtual Channel out of range\n");
4922 return -EINVAL;
4923 }
4924
4925 if (dsi->vc[channel].dssdev != dssdev) {
4926 DSSERR("Virtual Channel not allocated to display %s\n",
4927 dssdev->name);
4928 return -EINVAL;
4929 }
4930
4931 dsi->vc[channel].vc_id = vc_id;
4932
4933 return 0;
4934}
4935
4936static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4937{
4938 struct dsi_data *dsi = to_dsi_data(dssdev);
4939
4940 if ((channel >= 0 && channel <= 3) &&
4941 dsi->vc[channel].dssdev == dssdev) {
4942 dsi->vc[channel].dssdev = NULL;
4943 dsi->vc[channel].vc_id = 0;
4944 }
4945}
4946
4947
4948static int dsi_get_clocks(struct dsi_data *dsi)
4949{
4950 struct clk *clk;
4951
4952 clk = devm_clk_get(dsi->dev, "fck");
4953 if (IS_ERR(clk)) {
4954 DSSERR("can't get fck\n");
4955 return PTR_ERR(clk);
4956 }
4957
4958 dsi->dss_clk = clk;
4959
4960 return 0;
4961}
4962
4963static int dsi_connect(struct omap_dss_device *dssdev,
4964 struct omap_dss_device *dst)
4965{
4966 struct dsi_data *dsi = to_dsi_data(dssdev);
4967 int r;
4968
4969 r = dsi_regulator_init(dsi);
4970 if (r)
4971 return r;
4972
4973 r = dss_mgr_connect(&dsi->output, dssdev);
4974 if (r)
4975 return r;
4976
4977 r = omapdss_output_set_device(dssdev, dst);
4978 if (r) {
4979 DSSERR("failed to connect output to new device: %s\n",
4980 dssdev->name);
4981 dss_mgr_disconnect(&dsi->output, dssdev);
4982 return r;
4983 }
4984
4985 return 0;
4986}
4987
4988static void dsi_disconnect(struct omap_dss_device *dssdev,
4989 struct omap_dss_device *dst)
4990{
4991 struct dsi_data *dsi = to_dsi_data(dssdev);
4992
4993 WARN_ON(dst != dssdev->dst);
4994
4995 if (dst != dssdev->dst)
4996 return;
4997
4998 omapdss_output_unset_device(dssdev);
4999
5000 dss_mgr_disconnect(&dsi->output, dssdev);
5001}
5002
5003static const struct omapdss_dsi_ops dsi_ops = {
5004 .connect = dsi_connect,
5005 .disconnect = dsi_disconnect,
5006
5007 .bus_lock = dsi_bus_lock,
5008 .bus_unlock = dsi_bus_unlock,
5009
5010 .enable = dsi_display_enable,
5011 .disable = dsi_display_disable,
5012
5013 .enable_hs = dsi_vc_enable_hs,
5014
5015 .configure_pins = dsi_configure_pins,
5016 .set_config = dsi_set_config,
5017
5018 .enable_video_output = dsi_enable_video_output,
5019 .disable_video_output = dsi_disable_video_output,
5020
5021 .update = dsi_update,
5022
5023 .enable_te = dsi_enable_te,
5024
5025 .request_vc = dsi_request_vc,
5026 .set_vc_id = dsi_set_vc_id,
5027 .release_vc = dsi_release_vc,
5028
5029 .dcs_write = dsi_vc_dcs_write,
5030 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
5031 .dcs_read = dsi_vc_dcs_read,
5032
5033 .gen_write = dsi_vc_generic_write,
5034 .gen_write_nosync = dsi_vc_generic_write_nosync,
5035 .gen_read = dsi_vc_generic_read,
5036
5037 .bta_sync = dsi_vc_send_bta_sync,
5038
5039 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5040};
5041
5042static void dsi_init_output(struct dsi_data *dsi)
5043{
5044 struct omap_dss_device *out = &dsi->output;
5045
5046 out->dev = dsi->dev;
5047 out->id = dsi->module_id == 0 ?
5048 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5049
5050 out->output_type = OMAP_DISPLAY_TYPE_DSI;
5051 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5052 out->dispc_channel = dsi_get_channel(dsi);
5053 out->ops.dsi = &dsi_ops;
5054 out->owner = THIS_MODULE;
5055
5056 omapdss_register_output(out);
5057}
5058
5059static void dsi_uninit_output(struct dsi_data *dsi)
5060{
5061 struct omap_dss_device *out = &dsi->output;
5062
5063 omapdss_unregister_output(out);
5064}
5065
5066static int dsi_probe_of(struct dsi_data *dsi)
5067{
5068 struct device_node *node = dsi->dev->of_node;
5069 struct property *prop;
5070 u32 lane_arr[10];
5071 int len, num_pins;
5072 int r, i;
5073 struct device_node *ep;
5074 struct omap_dsi_pin_config pin_cfg;
5075
5076 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
5077 if (!ep)
5078 return 0;
5079
5080 prop = of_find_property(ep, "lanes", &len);
5081 if (prop == NULL) {
5082 dev_err(dsi->dev, "failed to find lane data\n");
5083 r = -EINVAL;
5084 goto err;
5085 }
5086
5087 num_pins = len / sizeof(u32);
5088
5089 if (num_pins < 4 || num_pins % 2 != 0 ||
5090 num_pins > dsi->num_lanes_supported * 2) {
5091 dev_err(dsi->dev, "bad number of lanes\n");
5092 r = -EINVAL;
5093 goto err;
5094 }
5095
5096 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5097 if (r) {
5098 dev_err(dsi->dev, "failed to read lane data\n");
5099 goto err;
5100 }
5101
5102 pin_cfg.num_pins = num_pins;
5103 for (i = 0; i < num_pins; ++i)
5104 pin_cfg.pins[i] = (int)lane_arr[i];
5105
5106 r = dsi_configure_pins(&dsi->output, &pin_cfg);
5107 if (r) {
5108 dev_err(dsi->dev, "failed to configure pins");
5109 goto err;
5110 }
5111
5112 of_node_put(ep);
5113
5114 return 0;
5115
5116err:
5117 of_node_put(ep);
5118 return r;
5119}
5120
5121static const struct dss_pll_ops dsi_pll_ops = {
5122 .enable = dsi_pll_enable,
5123 .disable = dsi_pll_disable,
5124 .set_config = dss_pll_write_config_type_a,
5125};
5126
5127static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
5128 .type = DSS_PLL_TYPE_A,
5129
5130 .n_max = (1 << 7) - 1,
5131 .m_max = (1 << 11) - 1,
5132 .mX_max = (1 << 4) - 1,
5133 .fint_min = 750000,
5134 .fint_max = 2100000,
5135 .clkdco_low = 1000000000,
5136 .clkdco_max = 1800000000,
5137
5138 .n_msb = 7,
5139 .n_lsb = 1,
5140 .m_msb = 18,
5141 .m_lsb = 8,
5142
5143 .mX_msb[0] = 22,
5144 .mX_lsb[0] = 19,
5145 .mX_msb[1] = 26,
5146 .mX_lsb[1] = 23,
5147
5148 .has_stopmode = true,
5149 .has_freqsel = true,
5150 .has_selfreqdco = false,
5151 .has_refsel = false,
5152};
5153
5154static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
5155 .type = DSS_PLL_TYPE_A,
5156
5157 .n_max = (1 << 8) - 1,
5158 .m_max = (1 << 12) - 1,
5159 .mX_max = (1 << 5) - 1,
5160 .fint_min = 500000,
5161 .fint_max = 2500000,
5162 .clkdco_low = 1000000000,
5163 .clkdco_max = 1800000000,
5164
5165 .n_msb = 8,
5166 .n_lsb = 1,
5167 .m_msb = 20,
5168 .m_lsb = 9,
5169
5170 .mX_msb[0] = 25,
5171 .mX_lsb[0] = 21,
5172 .mX_msb[1] = 30,
5173 .mX_lsb[1] = 26,
5174
5175 .has_stopmode = true,
5176 .has_freqsel = false,
5177 .has_selfreqdco = false,
5178 .has_refsel = false,
5179};
5180
5181static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
5182 .type = DSS_PLL_TYPE_A,
5183
5184 .n_max = (1 << 8) - 1,
5185 .m_max = (1 << 12) - 1,
5186 .mX_max = (1 << 5) - 1,
5187 .fint_min = 150000,
5188 .fint_max = 52000000,
5189 .clkdco_low = 1000000000,
5190 .clkdco_max = 1800000000,
5191
5192 .n_msb = 8,
5193 .n_lsb = 1,
5194 .m_msb = 20,
5195 .m_lsb = 9,
5196
5197 .mX_msb[0] = 25,
5198 .mX_lsb[0] = 21,
5199 .mX_msb[1] = 30,
5200 .mX_lsb[1] = 26,
5201
5202 .has_stopmode = true,
5203 .has_freqsel = false,
5204 .has_selfreqdco = true,
5205 .has_refsel = true,
5206};
5207
5208static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi)
5209{
5210 struct dss_pll *pll = &dsi->pll;
5211 struct clk *clk;
5212 int r;
5213
5214 clk = devm_clk_get(dsi->dev, "sys_clk");
5215 if (IS_ERR(clk)) {
5216 DSSERR("can't get sys_clk\n");
5217 return PTR_ERR(clk);
5218 }
5219
5220 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
5221 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
5222 pll->clkin = clk;
5223 pll->base = dsi->pll_base;
5224 pll->hw = dsi->data->pll_hw;
5225 pll->ops = &dsi_pll_ops;
5226
5227 r = dss_pll_register(dss, pll);
5228 if (r)
5229 return r;
5230
5231 return 0;
5232}
5233
5234/* DSI1 HW IP initialisation */
5235static const struct dsi_of_data dsi_of_data_omap34xx = {
5236 .model = DSI_MODEL_OMAP3,
5237 .pll_hw = &dss_omap3_dsi_pll_hw,
5238 .modules = (const struct dsi_module_id_data[]) {
5239 { .address = 0x4804fc00, .id = 0, },
5240 { },
5241 },
5242 .max_fck_freq = 173000000,
5243 .max_pll_lpdiv = (1 << 13) - 1,
5244 .quirks = DSI_QUIRK_REVERSE_TXCLKESC,
5245};
5246
5247static const struct dsi_of_data dsi_of_data_omap36xx = {
5248 .model = DSI_MODEL_OMAP3,
5249 .pll_hw = &dss_omap3_dsi_pll_hw,
5250 .modules = (const struct dsi_module_id_data[]) {
5251 { .address = 0x4804fc00, .id = 0, },
5252 { },
5253 },
5254 .max_fck_freq = 173000000,
5255 .max_pll_lpdiv = (1 << 13) - 1,
5256 .quirks = DSI_QUIRK_PLL_PWR_BUG,
5257};
5258
5259static const struct dsi_of_data dsi_of_data_omap4 = {
5260 .model = DSI_MODEL_OMAP4,
5261 .pll_hw = &dss_omap4_dsi_pll_hw,
5262 .modules = (const struct dsi_module_id_data[]) {
5263 { .address = 0x58004000, .id = 0, },
5264 { .address = 0x58005000, .id = 1, },
5265 { },
5266 },
5267 .max_fck_freq = 170000000,
5268 .max_pll_lpdiv = (1 << 13) - 1,
5269 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5270 | DSI_QUIRK_GNQ,
5271};
5272
5273static const struct dsi_of_data dsi_of_data_omap5 = {
5274 .model = DSI_MODEL_OMAP5,
5275 .pll_hw = &dss_omap5_dsi_pll_hw,
5276 .modules = (const struct dsi_module_id_data[]) {
5277 { .address = 0x58004000, .id = 0, },
5278 { .address = 0x58009000, .id = 1, },
5279 { },
5280 },
5281 .max_fck_freq = 209250000,
5282 .max_pll_lpdiv = (1 << 13) - 1,
5283 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH
5284 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC,
5285};
5286
5287static const struct of_device_id dsi_of_match[] = {
5288 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
5289 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
5290 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
5291 {},
5292};
5293
5294static const struct soc_device_attribute dsi_soc_devices[] = {
5295 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx },
5296 { .machine = "AM35*", .data = &dsi_of_data_omap34xx },
5297 { /* sentinel */ }
5298};
5299
5300static int dsi_bind(struct device *dev, struct device *master, void *data)
5301{
5302 struct platform_device *pdev = to_platform_device(dev);
5303 struct dss_device *dss = dss_get_device(master);
5304 const struct soc_device_attribute *soc;
5305 const struct dsi_module_id_data *d;
5306 u32 rev;
5307 int r, i;
5308 struct dsi_data *dsi;
5309 struct resource *dsi_mem;
5310 struct resource *res;
5311
5312 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
5313 if (!dsi)
5314 return -ENOMEM;
5315
5316 dsi->dss = dss;
5317 dsi->dev = dev;
5318 dev_set_drvdata(dev, dsi);
5319
5320 spin_lock_init(&dsi->irq_lock);
5321 spin_lock_init(&dsi->errors_lock);
5322 dsi->errors = 0;
5323
5324#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5325 spin_lock_init(&dsi->irq_stats_lock);
5326 dsi->irq_stats.last_reset = jiffies;
5327#endif
5328
5329 mutex_init(&dsi->lock);
5330 sema_init(&dsi->bus_lock, 1);
5331
5332 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5333 dsi_framedone_timeout_work_callback);
5334
5335#ifdef DSI_CATCH_MISSING_TE
5336 timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5337#endif
5338
5339 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto");
5340 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem);
5341 if (IS_ERR(dsi->proto_base))
5342 return PTR_ERR(dsi->proto_base);
5343
5344 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
5345 dsi->phy_base = devm_ioremap_resource(dev, res);
5346 if (IS_ERR(dsi->phy_base))
5347 return PTR_ERR(dsi->phy_base);
5348
5349 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
5350 dsi->pll_base = devm_ioremap_resource(dev, res);
5351 if (IS_ERR(dsi->pll_base))
5352 return PTR_ERR(dsi->pll_base);
5353
5354 dsi->irq = platform_get_irq(pdev, 0);
5355 if (dsi->irq < 0) {
5356 DSSERR("platform_get_irq failed\n");
5357 return -ENODEV;
5358 }
5359
5360 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler,
5361 IRQF_SHARED, dev_name(dev), dsi);
5362 if (r < 0) {
5363 DSSERR("request_irq failed\n");
5364 return r;
5365 }
5366
5367 soc = soc_device_match(dsi_soc_devices);
5368 if (soc)
5369 dsi->data = soc->data;
5370 else
5371 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data;
5372
5373 d = dsi->data->modules;
5374 while (d->address != 0 && d->address != dsi_mem->start)
5375 d++;
5376
5377 if (d->address == 0) {
5378 DSSERR("unsupported DSI module\n");
5379 return -ENODEV;
5380 }
5381
5382 dsi->module_id = d->id;
5383
5384 if (dsi->data->model == DSI_MODEL_OMAP4 ||
5385 dsi->data->model == DSI_MODEL_OMAP5) {
5386 struct device_node *np;
5387
5388 /*
5389 * The OMAP4/5 display DT bindings don't reference the padconf
5390 * syscon. Our only option to retrieve it is to find it by name.
5391 */
5392 np = of_find_node_by_name(NULL,
5393 dsi->data->model == DSI_MODEL_OMAP4 ?
5394 "omap4_padconf_global" : "omap5_padconf_global");
5395 if (!np)
5396 return -ENODEV;
5397
5398 dsi->syscon = syscon_node_to_regmap(np);
5399 of_node_put(np);
5400 }
5401
5402 /* DSI VCs initialization */
5403 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5404 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5405 dsi->vc[i].dssdev = NULL;
5406 dsi->vc[i].vc_id = 0;
5407 }
5408
5409 r = dsi_get_clocks(dsi);
5410 if (r)
5411 return r;
5412
5413 dsi_init_pll_data(dss, dsi);
5414
5415 pm_runtime_enable(dev);
5416
5417 r = dsi_runtime_get(dsi);
5418 if (r)
5419 goto err_runtime_get;
5420
5421 rev = dsi_read_reg(dsi, DSI_REVISION);
5422 dev_dbg(dev, "OMAP DSI rev %d.%d\n",
5423 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5424
5425 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5426 * of data to 3 by default */
5427 if (dsi->data->quirks & DSI_QUIRK_GNQ)
5428 /* NB_DATA_LANES */
5429 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9);
5430 else
5431 dsi->num_lanes_supported = 3;
5432
5433 dsi->line_buffer_size = dsi_get_line_buf_size(dsi);
5434
5435 dsi_init_output(dsi);
5436
5437 r = dsi_probe_of(dsi);
5438 if (r) {
5439 DSSERR("Invalid DSI DT data\n");
5440 goto err_probe_of;
5441 }
5442
5443 r = of_platform_populate(dev->of_node, NULL, NULL, dev);
5444 if (r)
5445 DSSERR("Failed to populate DSI child devices: %d\n", r);
5446
5447 dsi_runtime_put(dsi);
5448
5449 if (dsi->module_id == 0)
5450 dsi->debugfs.regs = dss_debugfs_create_file(dss, "dsi1_regs",
5451 dsi1_dump_regs,
5452 &dsi);
5453 else
5454 dsi->debugfs.regs = dss_debugfs_create_file(dss, "dsi2_regs",
5455 dsi2_dump_regs,
5456 &dsi);
5457#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5458 if (dsi->module_id == 0)
5459 dsi->debugfs.irqs = dss_debugfs_create_file(dss, "dsi1_irqs",
5460 dsi1_dump_irqs,
5461 &dsi);
5462 else
5463 dsi->debugfs.irqs = dss_debugfs_create_file(dss, "dsi2_irqs",
5464 dsi2_dump_irqs,
5465 &dsi);
5466#endif
5467
5468 return 0;
5469
5470err_probe_of:
5471 dsi_uninit_output(dsi);
5472 dsi_runtime_put(dsi);
5473
5474err_runtime_get:
5475 pm_runtime_disable(dev);
5476 return r;
5477}
5478
5479static void dsi_unbind(struct device *dev, struct device *master, void *data)
5480{
5481 struct dsi_data *dsi = dev_get_drvdata(dev);
5482
5483 dss_debugfs_remove_file(dsi->debugfs.irqs);
5484 dss_debugfs_remove_file(dsi->debugfs.regs);
5485
5486 of_platform_depopulate(dev);
5487
5488 WARN_ON(dsi->scp_clk_refcount > 0);
5489
5490 dss_pll_unregister(&dsi->pll);
5491
5492 dsi_uninit_output(dsi);
5493
5494 pm_runtime_disable(dev);
5495
5496 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5497 regulator_disable(dsi->vdds_dsi_reg);
5498 dsi->vdds_dsi_enabled = false;
5499 }
5500}
5501
5502static const struct component_ops dsi_component_ops = {
5503 .bind = dsi_bind,
5504 .unbind = dsi_unbind,
5505};
5506
5507static int dsi_probe(struct platform_device *pdev)
5508{
5509 return component_add(&pdev->dev, &dsi_component_ops);
5510}
5511
5512static int dsi_remove(struct platform_device *pdev)
5513{
5514 component_del(&pdev->dev, &dsi_component_ops);
5515 return 0;
5516}
5517
5518static int dsi_runtime_suspend(struct device *dev)
5519{
5520 struct dsi_data *dsi = dev_get_drvdata(dev);
5521
5522 dsi->is_enabled = false;
5523 /* ensure the irq handler sees the is_enabled value */
5524 smp_wmb();
5525 /* wait for current handler to finish before turning the DSI off */
5526 synchronize_irq(dsi->irq);
5527
5528 dispc_runtime_put(dsi->dss->dispc);
5529
5530 return 0;
5531}
5532
5533static int dsi_runtime_resume(struct device *dev)
5534{
5535 struct dsi_data *dsi = dev_get_drvdata(dev);
5536 int r;
5537
5538 r = dispc_runtime_get(dsi->dss->dispc);
5539 if (r)
5540 return r;
5541
5542 dsi->is_enabled = true;
5543 /* ensure the irq handler sees the is_enabled value */
5544 smp_wmb();
5545
5546 return 0;
5547}
5548
5549static const struct dev_pm_ops dsi_pm_ops = {
5550 .runtime_suspend = dsi_runtime_suspend,
5551 .runtime_resume = dsi_runtime_resume,
5552};
5553
5554struct platform_driver omap_dsihw_driver = {
5555 .probe = dsi_probe,
5556 .remove = dsi_remove,
5557 .driver = {
5558 .name = "omapdss_dsi",
5559 .pm = &dsi_pm_ops,
5560 .of_match_table = dsi_of_match,
5561 .suppress_bind_attrs = true,
5562 },
5563};