1/*
  2 * Copyright (C) 2013 Red Hat
  3 * Author: Rob Clark <robdclark@gmail.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms of the GNU General Public License version 2 as published by
  7 * the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful, but WITHOUT
 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12 * more details.
 13 *
 14 * You should have received a copy of the GNU General Public License along with
 15 * this program.  If not, see <http://www.gnu.org/licenses/>.
 16 */
 17
 18#ifndef __HDMI_CONNECTOR_H__
 19#define __HDMI_CONNECTOR_H__
 20
 21#include <linux/i2c.h>
 22#include <linux/clk.h>
 23#include <linux/platform_device.h>
 24#include <linux/regulator/consumer.h>
 25#include <linux/hdmi.h>
 26
 27#include "msm_drv.h"
 28#include "hdmi.xml.h"
 29
 30#define HDMI_MAX_NUM_GPIO	6
 31
 32struct hdmi_phy;
 33struct hdmi_platform_config;
 34
 35struct hdmi_gpio_data {
 36	int num;
 37	bool output;
 38	int value;
 39	const char *label;
 40};
 41
 42struct hdmi_audio {
 43	bool enabled;
 44	struct hdmi_audio_infoframe infoframe;
 45	int rate;
 46};
 47
 48struct hdmi_hdcp_ctrl;
 49
 50struct hdmi {
 51	struct drm_device *dev;
 52	struct platform_device *pdev;
 53	struct platform_device *audio_pdev;
 54
 55	const struct hdmi_platform_config *config;
 56
 57	/* audio state: */
 58	struct hdmi_audio audio;
 59
 60	/* video state: */
 61	bool power_on;
 62	unsigned long int pixclock;
 63
 64	void __iomem *mmio;
 65	void __iomem *qfprom_mmio;
 66	phys_addr_t mmio_phy_addr;
 67
 68	struct regulator **hpd_regs;
 69	struct regulator **pwr_regs;
 70	struct clk **hpd_clks;
 71	struct clk **pwr_clks;
 72
 73	struct hdmi_phy *phy;
 74	struct device *phy_dev;
 75
 76	struct i2c_adapter *i2c;
 77	struct drm_connector *connector;
 78	struct drm_bridge *bridge;
 79
 80	/* the encoder we are hooked to (outside of hdmi block) */
 81	struct drm_encoder *encoder;
 82
 83	bool hdmi_mode;               /* are we in hdmi mode? */
 84
 85	int irq;
 86	struct workqueue_struct *workq;
 87
 88	struct hdmi_hdcp_ctrl *hdcp_ctrl;
 89
 90	/*
 91	* spinlock to protect registers shared by different execution
 92	* REG_HDMI_CTRL
 93	* REG_HDMI_DDC_ARBITRATION
 94	* REG_HDMI_HDCP_INT_CTRL
 95	* REG_HDMI_HPD_CTRL
 96	*/
 97	spinlock_t reg_lock;
 98};
 99
100/* platform config data (ie. from DT, or pdata) */
101struct hdmi_platform_config {
102	const char *mmio_name;
103	const char *qfprom_mmio_name;
104
105	/* regulators that need to be on for hpd: */
106	const char **hpd_reg_names;
107	int hpd_reg_cnt;
108
109	/* regulators that need to be on for screen pwr: */
110	const char **pwr_reg_names;
111	int pwr_reg_cnt;
112
113	/* clks that need to be on for hpd: */
114	const char **hpd_clk_names;
115	const long unsigned *hpd_freq;
116	int hpd_clk_cnt;
117
118	/* clks that need to be on for screen pwr (ie pixel clk): */
119	const char **pwr_clk_names;
120	int pwr_clk_cnt;
121
122	/* gpio's: */
123	struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO];
124};
125
126void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
127
128static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
129{
130	msm_writel(data, hdmi->mmio + reg);
131}
132
133static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
134{
135	return msm_readl(hdmi->mmio + reg);
136}
137
138static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
139{
140	return msm_readl(hdmi->qfprom_mmio + reg);
141}
142
143/*
144 * hdmi phy:
145 */
146
147enum hdmi_phy_type {
148	MSM_HDMI_PHY_8x60,
149	MSM_HDMI_PHY_8960,
150	MSM_HDMI_PHY_8x74,
151	MSM_HDMI_PHY_8996,
152	MSM_HDMI_PHY_MAX,
153};
154
155struct hdmi_phy_cfg {
156	enum hdmi_phy_type type;
157	void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
158	void (*powerdown)(struct hdmi_phy *phy);
159	const char * const *reg_names;
160	int num_regs;
161	const char * const *clk_names;
162	int num_clks;
163};
164
165extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
166extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
167extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
168extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
169
170struct hdmi_phy {
171	struct platform_device *pdev;
172	void __iomem *mmio;
173	struct hdmi_phy_cfg *cfg;
174	const struct hdmi_phy_funcs *funcs;
175	struct regulator **regs;
176	struct clk **clks;
177};
178
179static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
180{
181	msm_writel(data, phy->mmio + reg);
182}
183
184static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
185{
186	return msm_readl(phy->mmio + reg);
187}
188
189int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
190void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy);
191void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock);
192void msm_hdmi_phy_powerdown(struct hdmi_phy *phy);
193void __init msm_hdmi_phy_driver_register(void);
194void __exit msm_hdmi_phy_driver_unregister(void);
195
196#ifdef CONFIG_COMMON_CLK
197int msm_hdmi_pll_8960_init(struct platform_device *pdev);
198int msm_hdmi_pll_8996_init(struct platform_device *pdev);
199#else
200static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
201{
202	return -ENODEV;
203}
204
205static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev)
206{
207	return -ENODEV;
208}
209#endif
210
211/*
212 * audio:
213 */
214/* Supported HDMI Audio channels and rates */
215#define	MSM_HDMI_AUDIO_CHANNEL_2	0
216#define	MSM_HDMI_AUDIO_CHANNEL_4	1
217#define	MSM_HDMI_AUDIO_CHANNEL_6	2
218#define	MSM_HDMI_AUDIO_CHANNEL_8	3
219
220#define	HDMI_SAMPLE_RATE_32KHZ		0
221#define	HDMI_SAMPLE_RATE_44_1KHZ	1
222#define	HDMI_SAMPLE_RATE_48KHZ		2
223#define	HDMI_SAMPLE_RATE_88_2KHZ	3
224#define	HDMI_SAMPLE_RATE_96KHZ		4
225#define	HDMI_SAMPLE_RATE_176_4KHZ	5
226#define	HDMI_SAMPLE_RATE_192KHZ		6
227
228int msm_hdmi_audio_update(struct hdmi *hdmi);
229int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
230	uint32_t num_of_channels, uint32_t channel_allocation,
231	uint32_t level_shift, bool down_mix);
232void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate);
233
234
235/*
236 * hdmi bridge:
237 */
238
239struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi);
240void msm_hdmi_bridge_destroy(struct drm_bridge *bridge);
241
242/*
243 * hdmi connector:
244 */
245
246void msm_hdmi_connector_irq(struct drm_connector *connector);
247struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi);
248
249/*
250 * i2c adapter for ddc:
251 */
252
253void msm_hdmi_i2c_irq(struct i2c_adapter *i2c);
254void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c);
255struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi);
256
257/*
258 * hdcp
259 */
260#ifdef CONFIG_DRM_MSM_HDMI_HDCP
261struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi);
262void msm_hdmi_hdcp_destroy(struct hdmi *hdmi);
263void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
264void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
265void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
266#else
267static inline struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi)
268{
269	return ERR_PTR(-ENXIO);
270}
271static inline void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) {}
272static inline void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
273static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
274static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
275#endif
276
277#endif /* __HDMI_CONNECTOR_H__ */