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1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Jie Qiu <jie.qiu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#include <drm/drmP.h>
15#include <drm/drm_atomic_helper.h>
16#include <drm/drm_crtc.h>
17#include <drm/drm_crtc_helper.h>
18#include <drm/drm_edid.h>
19#include <linux/arm-smccc.h>
20#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/hdmi.h>
23#include <linux/i2c.h>
24#include <linux/io.h>
25#include <linux/kernel.h>
26#include <linux/mfd/syscon.h>
27#include <linux/of_platform.h>
28#include <linux/of.h>
29#include <linux/of_gpio.h>
30#include <linux/of_graph.h>
31#include <linux/phy/phy.h>
32#include <linux/platform_device.h>
33#include <linux/regmap.h>
34#include <sound/hdmi-codec.h>
35#include "mtk_cec.h"
36#include "mtk_hdmi.h"
37#include "mtk_hdmi_regs.h"
38
39#define NCTS_BYTES 7
40
41enum mtk_hdmi_clk_id {
42 MTK_HDMI_CLK_HDMI_PIXEL,
43 MTK_HDMI_CLK_HDMI_PLL,
44 MTK_HDMI_CLK_AUD_BCLK,
45 MTK_HDMI_CLK_AUD_SPDIF,
46 MTK_HDMI_CLK_COUNT
47};
48
49enum hdmi_aud_input_type {
50 HDMI_AUD_INPUT_I2S = 0,
51 HDMI_AUD_INPUT_SPDIF,
52};
53
54enum hdmi_aud_i2s_fmt {
55 HDMI_I2S_MODE_RJT_24BIT = 0,
56 HDMI_I2S_MODE_RJT_16BIT,
57 HDMI_I2S_MODE_LJT_24BIT,
58 HDMI_I2S_MODE_LJT_16BIT,
59 HDMI_I2S_MODE_I2S_24BIT,
60 HDMI_I2S_MODE_I2S_16BIT
61};
62
63enum hdmi_aud_mclk {
64 HDMI_AUD_MCLK_128FS,
65 HDMI_AUD_MCLK_192FS,
66 HDMI_AUD_MCLK_256FS,
67 HDMI_AUD_MCLK_384FS,
68 HDMI_AUD_MCLK_512FS,
69 HDMI_AUD_MCLK_768FS,
70 HDMI_AUD_MCLK_1152FS,
71};
72
73enum hdmi_aud_channel_type {
74 HDMI_AUD_CHAN_TYPE_1_0 = 0,
75 HDMI_AUD_CHAN_TYPE_1_1,
76 HDMI_AUD_CHAN_TYPE_2_0,
77 HDMI_AUD_CHAN_TYPE_2_1,
78 HDMI_AUD_CHAN_TYPE_3_0,
79 HDMI_AUD_CHAN_TYPE_3_1,
80 HDMI_AUD_CHAN_TYPE_4_0,
81 HDMI_AUD_CHAN_TYPE_4_1,
82 HDMI_AUD_CHAN_TYPE_5_0,
83 HDMI_AUD_CHAN_TYPE_5_1,
84 HDMI_AUD_CHAN_TYPE_6_0,
85 HDMI_AUD_CHAN_TYPE_6_1,
86 HDMI_AUD_CHAN_TYPE_7_0,
87 HDMI_AUD_CHAN_TYPE_7_1,
88 HDMI_AUD_CHAN_TYPE_3_0_LRS,
89 HDMI_AUD_CHAN_TYPE_3_1_LRS,
90 HDMI_AUD_CHAN_TYPE_4_0_CLRS,
91 HDMI_AUD_CHAN_TYPE_4_1_CLRS,
92 HDMI_AUD_CHAN_TYPE_6_1_CS,
93 HDMI_AUD_CHAN_TYPE_6_1_CH,
94 HDMI_AUD_CHAN_TYPE_6_1_OH,
95 HDMI_AUD_CHAN_TYPE_6_1_CHR,
96 HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
97 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
98 HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
99 HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
100 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
101 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
102 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
103 HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
104 HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
105 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
106 HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
107 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
108 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
109 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
110 HDMI_AUD_CHAN_TYPE_6_0_CS,
111 HDMI_AUD_CHAN_TYPE_6_0_CH,
112 HDMI_AUD_CHAN_TYPE_6_0_OH,
113 HDMI_AUD_CHAN_TYPE_6_0_CHR,
114 HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
115 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
116 HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
117 HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
118 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
119 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
120 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
121 HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
122 HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
123 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
124 HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
125 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
126 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
127 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
128 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
129 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
130};
131
132enum hdmi_aud_channel_swap_type {
133 HDMI_AUD_SWAP_LR,
134 HDMI_AUD_SWAP_LFE_CC,
135 HDMI_AUD_SWAP_LSRS,
136 HDMI_AUD_SWAP_RLS_RRS,
137 HDMI_AUD_SWAP_LR_STATUS,
138};
139
140struct hdmi_audio_param {
141 enum hdmi_audio_coding_type aud_codec;
142 enum hdmi_audio_sample_size aud_sampe_size;
143 enum hdmi_aud_input_type aud_input_type;
144 enum hdmi_aud_i2s_fmt aud_i2s_fmt;
145 enum hdmi_aud_mclk aud_mclk;
146 enum hdmi_aud_channel_type aud_input_chan_type;
147 struct hdmi_codec_params codec_params;
148};
149
150struct mtk_hdmi {
151 struct drm_bridge bridge;
152 struct drm_bridge *next_bridge;
153 struct drm_connector conn;
154 struct device *dev;
155 struct phy *phy;
156 struct device *cec_dev;
157 struct i2c_adapter *ddc_adpt;
158 struct clk *clk[MTK_HDMI_CLK_COUNT];
159 struct drm_display_mode mode;
160 bool dvi_mode;
161 u32 min_clock;
162 u32 max_clock;
163 u32 max_hdisplay;
164 u32 max_vdisplay;
165 u32 ibias;
166 u32 ibias_up;
167 struct regmap *sys_regmap;
168 unsigned int sys_offset;
169 void __iomem *regs;
170 enum hdmi_colorspace csp;
171 struct hdmi_audio_param aud_param;
172 bool audio_enable;
173 bool powered;
174 bool enabled;
175};
176
177static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
178{
179 return container_of(b, struct mtk_hdmi, bridge);
180}
181
182static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c)
183{
184 return container_of(c, struct mtk_hdmi, conn);
185}
186
187static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
188{
189 return readl(hdmi->regs + offset);
190}
191
192static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
193{
194 writel(val, hdmi->regs + offset);
195}
196
197static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
198{
199 void __iomem *reg = hdmi->regs + offset;
200 u32 tmp;
201
202 tmp = readl(reg);
203 tmp &= ~bits;
204 writel(tmp, reg);
205}
206
207static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
208{
209 void __iomem *reg = hdmi->regs + offset;
210 u32 tmp;
211
212 tmp = readl(reg);
213 tmp |= bits;
214 writel(tmp, reg);
215}
216
217static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
218{
219 void __iomem *reg = hdmi->regs + offset;
220 u32 tmp;
221
222 tmp = readl(reg);
223 tmp = (tmp & ~mask) | (val & mask);
224 writel(tmp, reg);
225}
226
227static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
228{
229 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
230 VIDEO_SOURCE_SEL);
231}
232
233static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
234{
235 struct arm_smccc_res res;
236
237 /*
238 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
239 * output. This bit can only be controlled in ARM supervisor mode.
240 * The ARM trusted firmware provides an API for the HDMI driver to set
241 * this control bit to enable HDMI output in supervisor mode.
242 */
243 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, 0x80000000,
244 0, 0, 0, 0, 0, &res);
245
246 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
247 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
248 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
249 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
250}
251
252static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
253{
254 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
255 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
256}
257
258static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
259{
260 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
261}
262
263static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
264{
265 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
266}
267
268static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
269{
270 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
271 HDMI_RST, HDMI_RST);
272 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
273 HDMI_RST, 0);
274 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
275 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
276 ANLG_ON, ANLG_ON);
277}
278
279static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
280{
281 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
282 CFG2_NOTICE_EN);
283}
284
285static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
286{
287 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
288}
289
290static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
291{
292 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
293}
294
295static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
296 u8 len)
297{
298 u32 ctrl_reg = GRL_CTRL;
299 int i;
300 u8 *frame_data;
301 enum hdmi_infoframe_type frame_type;
302 u8 frame_ver;
303 u8 frame_len;
304 u8 checksum;
305 int ctrl_frame_en = 0;
306
307 frame_type = *buffer;
308 buffer += 1;
309 frame_ver = *buffer;
310 buffer += 1;
311 frame_len = *buffer;
312 buffer += 1;
313 checksum = *buffer;
314 buffer += 1;
315 frame_data = buffer;
316
317 dev_dbg(hdmi->dev,
318 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
319 frame_type, frame_ver, frame_len, checksum);
320
321 switch (frame_type) {
322 case HDMI_INFOFRAME_TYPE_AVI:
323 ctrl_frame_en = CTRL_AVI_EN;
324 ctrl_reg = GRL_CTRL;
325 break;
326 case HDMI_INFOFRAME_TYPE_SPD:
327 ctrl_frame_en = CTRL_SPD_EN;
328 ctrl_reg = GRL_CTRL;
329 break;
330 case HDMI_INFOFRAME_TYPE_AUDIO:
331 ctrl_frame_en = CTRL_AUDIO_EN;
332 ctrl_reg = GRL_CTRL;
333 break;
334 case HDMI_INFOFRAME_TYPE_VENDOR:
335 ctrl_frame_en = VS_EN;
336 ctrl_reg = GRL_ACP_ISRC_CTRL;
337 break;
338 }
339 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
340 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
341 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
342 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
343
344 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
345 for (i = 0; i < frame_len; i++)
346 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
347
348 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
349}
350
351static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
352{
353 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
354 AUDIO_PACKET_OFF);
355}
356
357static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
358{
359 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
360 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
361 usleep_range(2000, 4000);
362 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
363 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
364}
365
366static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
367{
368 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
369 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
370 COLOR_8BIT_MODE);
371}
372
373static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
374{
375 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
376 usleep_range(2000, 4000);
377 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
378}
379
380static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
381{
382 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
383 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
384 usleep_range(2000, 4000);
385 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
386 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
387}
388
389static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
390{
391 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
392 CTS_CTRL_SOFT);
393}
394
395static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
396 bool enable)
397{
398 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
399 NCTS_WRI_ANYTIME);
400}
401
402static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
403 struct drm_display_mode *mode)
404{
405 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
406
407 if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
408 mode->clock == 74250 &&
409 mode->vdisplay == 1080)
410 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
411 else
412 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
413}
414
415static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
416 enum hdmi_aud_channel_swap_type swap)
417{
418 u8 swap_bit;
419
420 switch (swap) {
421 case HDMI_AUD_SWAP_LR:
422 swap_bit = LR_SWAP;
423 break;
424 case HDMI_AUD_SWAP_LFE_CC:
425 swap_bit = LFE_CC_SWAP;
426 break;
427 case HDMI_AUD_SWAP_LSRS:
428 swap_bit = LSRS_SWAP;
429 break;
430 case HDMI_AUD_SWAP_RLS_RRS:
431 swap_bit = RLS_RRS_SWAP;
432 break;
433 case HDMI_AUD_SWAP_LR_STATUS:
434 swap_bit = LR_STATUS_SWAP;
435 break;
436 default:
437 swap_bit = LFE_CC_SWAP;
438 break;
439 }
440 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
441}
442
443static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
444 enum hdmi_audio_sample_size bit_num)
445{
446 u32 val;
447
448 switch (bit_num) {
449 case HDMI_AUDIO_SAMPLE_SIZE_16:
450 val = AOUT_16BIT;
451 break;
452 case HDMI_AUDIO_SAMPLE_SIZE_20:
453 val = AOUT_20BIT;
454 break;
455 case HDMI_AUDIO_SAMPLE_SIZE_24:
456 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
457 val = AOUT_24BIT;
458 break;
459 }
460
461 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
462}
463
464static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
465 enum hdmi_aud_i2s_fmt i2s_fmt)
466{
467 u32 val;
468
469 val = mtk_hdmi_read(hdmi, GRL_CFG0);
470 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
471
472 switch (i2s_fmt) {
473 case HDMI_I2S_MODE_RJT_24BIT:
474 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
475 break;
476 case HDMI_I2S_MODE_RJT_16BIT:
477 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
478 break;
479 case HDMI_I2S_MODE_LJT_24BIT:
480 default:
481 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
482 break;
483 case HDMI_I2S_MODE_LJT_16BIT:
484 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
485 break;
486 case HDMI_I2S_MODE_I2S_24BIT:
487 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
488 break;
489 case HDMI_I2S_MODE_I2S_16BIT:
490 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
491 break;
492 }
493 mtk_hdmi_write(hdmi, GRL_CFG0, val);
494}
495
496static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
497{
498 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
499 u8 val;
500
501 /* Disable high bitrate, set DST packet normal/double */
502 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
503
504 if (dst)
505 val = DST_NORMAL_DOUBLE | SACD_DST;
506 else
507 val = 0;
508
509 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
510}
511
512static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
513 enum hdmi_aud_channel_type channel_type,
514 u8 channel_count)
515{
516 unsigned int ch_switch;
517 u8 i2s_uv;
518
519 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
520 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
521 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
522 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
523
524 if (channel_count == 2) {
525 i2s_uv = I2S_UV_CH_EN(0);
526 } else if (channel_count == 3 || channel_count == 4) {
527 if (channel_count == 4 &&
528 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
529 channel_type == HDMI_AUD_CHAN_TYPE_4_0))
530 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
531 else
532 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
533 } else if (channel_count == 6 || channel_count == 5) {
534 if (channel_count == 6 &&
535 channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
536 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
537 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
538 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
539 } else {
540 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
541 I2S_UV_CH_EN(0);
542 }
543 } else if (channel_count == 8 || channel_count == 7) {
544 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
545 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
546 } else {
547 i2s_uv = I2S_UV_CH_EN(0);
548 }
549
550 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
551 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
552 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
553 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
554}
555
556static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
557 enum hdmi_aud_input_type input_type)
558{
559 u32 val;
560
561 val = mtk_hdmi_read(hdmi, GRL_CFG1);
562 if (input_type == HDMI_AUD_INPUT_I2S &&
563 (val & CFG1_SPDIF) == CFG1_SPDIF) {
564 val &= ~CFG1_SPDIF;
565 } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
566 (val & CFG1_SPDIF) == 0) {
567 val |= CFG1_SPDIF;
568 }
569 mtk_hdmi_write(hdmi, GRL_CFG1, val);
570}
571
572static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
573 u8 *channel_status)
574{
575 int i;
576
577 for (i = 0; i < 5; i++) {
578 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
579 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
580 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
581 }
582 for (; i < 24; i++) {
583 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
584 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
585 }
586}
587
588static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
589{
590 u32 val;
591
592 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
593 if (val & MIX_CTRL_SRC_EN) {
594 val &= ~MIX_CTRL_SRC_EN;
595 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
596 usleep_range(255, 512);
597 val |= MIX_CTRL_SRC_EN;
598 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
599 }
600}
601
602static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
603{
604 u32 val;
605
606 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
607 val &= ~MIX_CTRL_SRC_EN;
608 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
609 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
610}
611
612static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
613 enum hdmi_aud_mclk mclk)
614{
615 u32 val;
616
617 val = mtk_hdmi_read(hdmi, GRL_CFG5);
618 val &= CFG5_CD_RATIO_MASK;
619
620 switch (mclk) {
621 case HDMI_AUD_MCLK_128FS:
622 val |= CFG5_FS128;
623 break;
624 case HDMI_AUD_MCLK_256FS:
625 val |= CFG5_FS256;
626 break;
627 case HDMI_AUD_MCLK_384FS:
628 val |= CFG5_FS384;
629 break;
630 case HDMI_AUD_MCLK_512FS:
631 val |= CFG5_FS512;
632 break;
633 case HDMI_AUD_MCLK_768FS:
634 val |= CFG5_FS768;
635 break;
636 default:
637 val |= CFG5_FS256;
638 break;
639 }
640 mtk_hdmi_write(hdmi, GRL_CFG5, val);
641}
642
643struct hdmi_acr_n {
644 unsigned int clock;
645 unsigned int n[3];
646};
647
648/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
649static const struct hdmi_acr_n hdmi_rec_n_table[] = {
650 /* Clock, N: 32kHz 44.1kHz 48kHz */
651 { 25175, { 4576, 7007, 6864 } },
652 { 74176, { 11648, 17836, 11648 } },
653 { 148352, { 11648, 8918, 5824 } },
654 { 296703, { 5824, 4459, 5824 } },
655 { 297000, { 3072, 4704, 5120 } },
656 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
657};
658
659/**
660 * hdmi_recommended_n() - Return N value recommended by HDMI specification
661 * @freq: audio sample rate in Hz
662 * @clock: rounded TMDS clock in kHz
663 */
664static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
665{
666 const struct hdmi_acr_n *recommended;
667 unsigned int i;
668
669 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
670 if (clock == hdmi_rec_n_table[i].clock)
671 break;
672 }
673 recommended = hdmi_rec_n_table + i;
674
675 switch (freq) {
676 case 32000:
677 return recommended->n[0];
678 case 44100:
679 return recommended->n[1];
680 case 48000:
681 return recommended->n[2];
682 case 88200:
683 return recommended->n[1] * 2;
684 case 96000:
685 return recommended->n[2] * 2;
686 case 176400:
687 return recommended->n[1] * 4;
688 case 192000:
689 return recommended->n[2] * 4;
690 default:
691 return (128 * freq) / 1000;
692 }
693}
694
695static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
696{
697 switch (clock) {
698 case 25175:
699 return 25174825; /* 25.2/1.001 MHz */
700 case 74176:
701 return 74175824; /* 74.25/1.001 MHz */
702 case 148352:
703 return 148351648; /* 148.5/1.001 MHz */
704 case 296703:
705 return 296703297; /* 297/1.001 MHz */
706 default:
707 return clock * 1000;
708 }
709}
710
711static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
712 unsigned int tmds_clock, unsigned int n)
713{
714 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
715 128 * audio_sample_rate);
716}
717
718static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
719 unsigned int cts)
720{
721 unsigned char val[NCTS_BYTES];
722 int i;
723
724 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
725 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
726 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
727 memset(val, 0, sizeof(val));
728
729 val[0] = (cts >> 24) & 0xff;
730 val[1] = (cts >> 16) & 0xff;
731 val[2] = (cts >> 8) & 0xff;
732 val[3] = cts & 0xff;
733
734 val[4] = (n >> 16) & 0xff;
735 val[5] = (n >> 8) & 0xff;
736 val[6] = n & 0xff;
737
738 for (i = 0; i < NCTS_BYTES; i++)
739 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
740}
741
742static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
743 unsigned int sample_rate,
744 unsigned int clock)
745{
746 unsigned int n, cts;
747
748 n = hdmi_recommended_n(sample_rate, clock);
749 cts = hdmi_expected_cts(sample_rate, clock, n);
750
751 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
752 __func__, sample_rate, clock, n, cts);
753
754 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
755 AUDIO_I2S_NCTS_SEL);
756 do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
757}
758
759static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
760{
761 switch (channel_type) {
762 case HDMI_AUD_CHAN_TYPE_1_0:
763 case HDMI_AUD_CHAN_TYPE_1_1:
764 case HDMI_AUD_CHAN_TYPE_2_0:
765 return 2;
766 case HDMI_AUD_CHAN_TYPE_2_1:
767 case HDMI_AUD_CHAN_TYPE_3_0:
768 return 3;
769 case HDMI_AUD_CHAN_TYPE_3_1:
770 case HDMI_AUD_CHAN_TYPE_4_0:
771 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
772 return 4;
773 case HDMI_AUD_CHAN_TYPE_4_1:
774 case HDMI_AUD_CHAN_TYPE_5_0:
775 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
776 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
777 return 5;
778 case HDMI_AUD_CHAN_TYPE_5_1:
779 case HDMI_AUD_CHAN_TYPE_6_0:
780 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
781 case HDMI_AUD_CHAN_TYPE_6_0_CS:
782 case HDMI_AUD_CHAN_TYPE_6_0_CH:
783 case HDMI_AUD_CHAN_TYPE_6_0_OH:
784 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
785 return 6;
786 case HDMI_AUD_CHAN_TYPE_6_1:
787 case HDMI_AUD_CHAN_TYPE_6_1_CS:
788 case HDMI_AUD_CHAN_TYPE_6_1_CH:
789 case HDMI_AUD_CHAN_TYPE_6_1_OH:
790 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
791 case HDMI_AUD_CHAN_TYPE_7_0:
792 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
793 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
794 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
795 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
796 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
797 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
798 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
799 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
800 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
801 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
802 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
803 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
804 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
805 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
806 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
807 return 7;
808 case HDMI_AUD_CHAN_TYPE_7_1:
809 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
810 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
811 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
812 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
813 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
814 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
815 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
816 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
817 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
818 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
819 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
820 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
821 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
822 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
823 return 8;
824 default:
825 return 2;
826 }
827}
828
829static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
830{
831 unsigned long rate;
832 int ret;
833
834 /* The DPI driver already should have set TVDPLL to the correct rate */
835 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
836 if (ret) {
837 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
838 ret);
839 return ret;
840 }
841
842 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
843
844 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
845 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
846 rate);
847 else
848 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
849
850 mtk_hdmi_hw_config_sys(hdmi);
851 mtk_hdmi_hw_set_deep_color_mode(hdmi);
852 return 0;
853}
854
855static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
856 struct drm_display_mode *mode)
857{
858 mtk_hdmi_hw_reset(hdmi);
859 mtk_hdmi_hw_enable_notice(hdmi, true);
860 mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
861 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
862 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
863
864 mtk_hdmi_hw_msic_setting(hdmi, mode);
865}
866
867static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable)
868{
869 mtk_hdmi_hw_send_aud_packet(hdmi, enable);
870 return 0;
871}
872
873static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on)
874{
875 mtk_hdmi_hw_ncts_enable(hdmi, on);
876 return 0;
877}
878
879static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
880{
881 enum hdmi_aud_channel_type chan_type;
882 u8 chan_count;
883 bool dst;
884
885 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
886 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
887
888 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
889 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
890 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
891 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
892 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
893 }
894
895 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
896 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
897
898 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
899 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
900 mtk_hdmi_hw_audio_config(hdmi, dst);
901
902 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
903 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
904 else
905 chan_type = hdmi->aud_param.aud_input_chan_type;
906 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
907 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
908 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
909
910 return 0;
911}
912
913static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
914 struct drm_display_mode *display_mode)
915{
916 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
917
918 mtk_hdmi_aud_on_off_hw_ncts(hdmi, false);
919 mtk_hdmi_hw_aud_src_disable(hdmi);
920 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
921
922 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
923 switch (sample_rate) {
924 case 32000:
925 case 44100:
926 case 48000:
927 case 88200:
928 case 96000:
929 break;
930 default:
931 return -EINVAL;
932 }
933 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
934 } else {
935 switch (sample_rate) {
936 case 32000:
937 case 44100:
938 case 48000:
939 break;
940 default:
941 return -EINVAL;
942 }
943 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
944 }
945
946 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
947
948 mtk_hdmi_hw_aud_src_reenable(hdmi);
949 return 0;
950}
951
952static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
953 struct drm_display_mode *display_mode)
954{
955 mtk_hdmi_hw_aud_mute(hdmi);
956 mtk_hdmi_aud_enable_packet(hdmi, false);
957
958 mtk_hdmi_aud_set_input(hdmi);
959 mtk_hdmi_aud_set_src(hdmi, display_mode);
960 mtk_hdmi_hw_aud_set_channel_status(hdmi,
961 hdmi->aud_param.codec_params.iec.status);
962
963 usleep_range(50, 100);
964
965 mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
966 mtk_hdmi_aud_enable_packet(hdmi, true);
967 mtk_hdmi_hw_aud_unmute(hdmi);
968 return 0;
969}
970
971static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
972 struct drm_display_mode *mode)
973{
974 struct hdmi_avi_infoframe frame;
975 u8 buffer[17];
976 ssize_t err;
977
978 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
979 if (err < 0) {
980 dev_err(hdmi->dev,
981 "Failed to get AVI infoframe from mode: %zd\n", err);
982 return err;
983 }
984
985 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
986 if (err < 0) {
987 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
988 return err;
989 }
990
991 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
992 return 0;
993}
994
995static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
996 const char *vendor,
997 const char *product)
998{
999 struct hdmi_spd_infoframe frame;
1000 u8 buffer[29];
1001 ssize_t err;
1002
1003 err = hdmi_spd_infoframe_init(&frame, vendor, product);
1004 if (err < 0) {
1005 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1006 err);
1007 return err;
1008 }
1009
1010 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1011 if (err < 0) {
1012 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1013 return err;
1014 }
1015
1016 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1017 return 0;
1018}
1019
1020static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1021{
1022 struct hdmi_audio_infoframe frame;
1023 u8 buffer[14];
1024 ssize_t err;
1025
1026 err = hdmi_audio_infoframe_init(&frame);
1027 if (err < 0) {
1028 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1029 err);
1030 return err;
1031 }
1032
1033 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1034 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1035 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1036 frame.channels = mtk_hdmi_aud_get_chnl_count(
1037 hdmi->aud_param.aud_input_chan_type);
1038
1039 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1040 if (err < 0) {
1041 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1042 err);
1043 return err;
1044 }
1045
1046 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1047 return 0;
1048}
1049
1050static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1051 struct drm_display_mode *mode)
1052{
1053 struct hdmi_vendor_infoframe frame;
1054 u8 buffer[10];
1055 ssize_t err;
1056
1057 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1058 &hdmi->conn, mode);
1059 if (err) {
1060 dev_err(hdmi->dev,
1061 "Failed to get vendor infoframe from mode: %zd\n", err);
1062 return err;
1063 }
1064
1065 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1066 if (err < 0) {
1067 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1068 err);
1069 return err;
1070 }
1071
1072 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1073 return 0;
1074}
1075
1076static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1077{
1078 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1079
1080 hdmi->csp = HDMI_COLORSPACE_RGB;
1081 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1082 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1083 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1084 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1085 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1086 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1087
1088 return 0;
1089}
1090
1091static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1092{
1093 mtk_hdmi_aud_enable_packet(hdmi, true);
1094 hdmi->audio_enable = true;
1095}
1096
1097static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1098{
1099 mtk_hdmi_aud_enable_packet(hdmi, false);
1100 hdmi->audio_enable = false;
1101}
1102
1103static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1104 struct hdmi_audio_param *param)
1105{
1106 if (!hdmi->audio_enable) {
1107 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1108 return -EINVAL;
1109 }
1110 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1111 param->aud_codec, param->aud_input_type,
1112 param->aud_input_chan_type, param->codec_params.sample_rate);
1113 memcpy(&hdmi->aud_param, param, sizeof(*param));
1114 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1115}
1116
1117static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1118 struct drm_display_mode *mode)
1119{
1120 int ret;
1121
1122 mtk_hdmi_hw_vid_black(hdmi, true);
1123 mtk_hdmi_hw_aud_mute(hdmi);
1124 mtk_hdmi_hw_send_av_mute(hdmi);
1125 phy_power_off(hdmi->phy);
1126
1127 ret = mtk_hdmi_video_change_vpll(hdmi,
1128 mode->clock * 1000);
1129 if (ret) {
1130 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1131 return ret;
1132 }
1133 mtk_hdmi_video_set_display_mode(hdmi, mode);
1134
1135 phy_power_on(hdmi->phy);
1136 mtk_hdmi_aud_output_config(hdmi, mode);
1137
1138 mtk_hdmi_hw_vid_black(hdmi, false);
1139 mtk_hdmi_hw_aud_unmute(hdmi);
1140 mtk_hdmi_hw_send_av_unmute(hdmi);
1141
1142 return 0;
1143}
1144
1145static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1146 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1147 [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1148 [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1149 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1150};
1151
1152static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1153 struct device_node *np)
1154{
1155 int i;
1156
1157 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1158 hdmi->clk[i] = of_clk_get_by_name(np,
1159 mtk_hdmi_clk_names[i]);
1160 if (IS_ERR(hdmi->clk[i]))
1161 return PTR_ERR(hdmi->clk[i]);
1162 }
1163 return 0;
1164}
1165
1166static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1167{
1168 int ret;
1169
1170 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1171 if (ret)
1172 return ret;
1173
1174 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1175 if (ret)
1176 goto err;
1177
1178 return 0;
1179err:
1180 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1181 return ret;
1182}
1183
1184static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1185{
1186 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1187 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1188}
1189
1190static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn,
1191 bool force)
1192{
1193 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1194
1195 return mtk_cec_hpd_high(hdmi->cec_dev) ?
1196 connector_status_connected : connector_status_disconnected;
1197}
1198
1199static void hdmi_conn_destroy(struct drm_connector *conn)
1200{
1201 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1202
1203 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL);
1204
1205 drm_connector_cleanup(conn);
1206}
1207
1208static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
1209{
1210 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1211 struct edid *edid;
1212 int ret;
1213
1214 if (!hdmi->ddc_adpt)
1215 return -ENODEV;
1216
1217 edid = drm_get_edid(conn, hdmi->ddc_adpt);
1218 if (!edid)
1219 return -ENODEV;
1220
1221 hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1222
1223 drm_mode_connector_update_edid_property(conn, edid);
1224
1225 ret = drm_add_edid_modes(conn, edid);
1226 kfree(edid);
1227 return ret;
1228}
1229
1230static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn,
1231 struct drm_display_mode *mode)
1232{
1233 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1234
1235 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1236 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1237 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1238
1239 if (hdmi->bridge.next) {
1240 struct drm_display_mode adjusted_mode;
1241
1242 drm_mode_copy(&adjusted_mode, mode);
1243 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode,
1244 &adjusted_mode))
1245 return MODE_BAD;
1246 }
1247
1248 if (mode->clock < 27000)
1249 return MODE_CLOCK_LOW;
1250 if (mode->clock > 297000)
1251 return MODE_CLOCK_HIGH;
1252
1253 return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1254}
1255
1256static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn)
1257{
1258 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1259
1260 return hdmi->bridge.encoder;
1261}
1262
1263static const struct drm_connector_funcs mtk_hdmi_connector_funcs = {
1264 .detect = hdmi_conn_detect,
1265 .fill_modes = drm_helper_probe_single_connector_modes,
1266 .destroy = hdmi_conn_destroy,
1267 .reset = drm_atomic_helper_connector_reset,
1268 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1269 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1270};
1271
1272static const struct drm_connector_helper_funcs
1273 mtk_hdmi_connector_helper_funcs = {
1274 .get_modes = mtk_hdmi_conn_get_modes,
1275 .mode_valid = mtk_hdmi_conn_mode_valid,
1276 .best_encoder = mtk_hdmi_conn_best_enc,
1277};
1278
1279static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1280{
1281 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1282
1283 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
1284 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1285}
1286
1287/*
1288 * Bridge callbacks
1289 */
1290
1291static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge)
1292{
1293 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1294 int ret;
1295
1296 ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn,
1297 &mtk_hdmi_connector_funcs,
1298 DRM_MODE_CONNECTOR_HDMIA);
1299 if (ret) {
1300 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
1301 return ret;
1302 }
1303 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs);
1304
1305 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD;
1306 hdmi->conn.interlace_allowed = true;
1307 hdmi->conn.doublescan_allowed = false;
1308
1309 ret = drm_mode_connector_attach_encoder(&hdmi->conn,
1310 bridge->encoder);
1311 if (ret) {
1312 dev_err(hdmi->dev,
1313 "Failed to attach connector to encoder: %d\n", ret);
1314 return ret;
1315 }
1316
1317 if (hdmi->next_bridge) {
1318 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1319 bridge);
1320 if (ret) {
1321 dev_err(hdmi->dev,
1322 "Failed to attach external bridge: %d\n", ret);
1323 return ret;
1324 }
1325 }
1326
1327 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1328
1329 return 0;
1330}
1331
1332static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1333 const struct drm_display_mode *mode,
1334 struct drm_display_mode *adjusted_mode)
1335{
1336 return true;
1337}
1338
1339static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge)
1340{
1341 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1342
1343 if (!hdmi->enabled)
1344 return;
1345
1346 phy_power_off(hdmi->phy);
1347 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1348 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1349
1350 hdmi->enabled = false;
1351}
1352
1353static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
1354{
1355 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1356
1357 if (!hdmi->powered)
1358 return;
1359
1360 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1361 mtk_hdmi_hw_make_reg_writable(hdmi, false);
1362
1363 hdmi->powered = false;
1364}
1365
1366static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1367 struct drm_display_mode *mode,
1368 struct drm_display_mode *adjusted_mode)
1369{
1370 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1371
1372 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1373 adjusted_mode->name, adjusted_mode->hdisplay);
1374 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1375 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1376 adjusted_mode->htotal);
1377 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1378 adjusted_mode->hskew, adjusted_mode->vdisplay);
1379 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1380 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1381 adjusted_mode->vtotal);
1382 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1383 adjusted_mode->vscan, adjusted_mode->flags);
1384
1385 drm_mode_copy(&hdmi->mode, adjusted_mode);
1386}
1387
1388static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1389{
1390 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1391
1392 mtk_hdmi_hw_make_reg_writable(hdmi, true);
1393 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1394
1395 hdmi->powered = true;
1396}
1397
1398static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1399 struct drm_display_mode *mode)
1400{
1401 mtk_hdmi_setup_audio_infoframe(hdmi);
1402 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1403 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1404 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1405 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1406}
1407
1408static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1409{
1410 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1411
1412 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1413 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1414 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1415 phy_power_on(hdmi->phy);
1416 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1417
1418 hdmi->enabled = true;
1419}
1420
1421static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1422 .attach = mtk_hdmi_bridge_attach,
1423 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1424 .disable = mtk_hdmi_bridge_disable,
1425 .post_disable = mtk_hdmi_bridge_post_disable,
1426 .mode_set = mtk_hdmi_bridge_mode_set,
1427 .pre_enable = mtk_hdmi_bridge_pre_enable,
1428 .enable = mtk_hdmi_bridge_enable,
1429};
1430
1431static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1432 struct platform_device *pdev)
1433{
1434 struct device *dev = &pdev->dev;
1435 struct device_node *np = dev->of_node;
1436 struct device_node *cec_np, *remote, *i2c_np;
1437 struct platform_device *cec_pdev;
1438 struct regmap *regmap;
1439 struct resource *mem;
1440 int ret;
1441
1442 ret = mtk_hdmi_get_all_clk(hdmi, np);
1443 if (ret) {
1444 dev_err(dev, "Failed to get clocks: %d\n", ret);
1445 return ret;
1446 }
1447
1448 /* The CEC module handles HDMI hotplug detection */
1449 cec_np = of_find_compatible_node(np->parent, NULL,
1450 "mediatek,mt8173-cec");
1451 if (!cec_np) {
1452 dev_err(dev, "Failed to find CEC node\n");
1453 return -EINVAL;
1454 }
1455
1456 cec_pdev = of_find_device_by_node(cec_np);
1457 if (!cec_pdev) {
1458 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1459 cec_np);
1460 return -EPROBE_DEFER;
1461 }
1462 hdmi->cec_dev = &cec_pdev->dev;
1463
1464 /*
1465 * The mediatek,syscon-hdmi property contains a phandle link to the
1466 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1467 * registers it contains.
1468 */
1469 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1470 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1471 &hdmi->sys_offset);
1472 if (IS_ERR(regmap))
1473 ret = PTR_ERR(regmap);
1474 if (ret) {
1475 ret = PTR_ERR(regmap);
1476 dev_err(dev,
1477 "Failed to get system configuration registers: %d\n",
1478 ret);
1479 return ret;
1480 }
1481 hdmi->sys_regmap = regmap;
1482
1483 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1484 hdmi->regs = devm_ioremap_resource(dev, mem);
1485 if (IS_ERR(hdmi->regs))
1486 return PTR_ERR(hdmi->regs);
1487
1488 remote = of_graph_get_remote_node(np, 1, 0);
1489 if (!remote)
1490 return -EINVAL;
1491
1492 if (!of_device_is_compatible(remote, "hdmi-connector")) {
1493 hdmi->next_bridge = of_drm_find_bridge(remote);
1494 if (!hdmi->next_bridge) {
1495 dev_err(dev, "Waiting for external bridge\n");
1496 of_node_put(remote);
1497 return -EPROBE_DEFER;
1498 }
1499 }
1500
1501 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1502 if (!i2c_np) {
1503 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1504 remote);
1505 of_node_put(remote);
1506 return -EINVAL;
1507 }
1508 of_node_put(remote);
1509
1510 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1511 if (!hdmi->ddc_adpt) {
1512 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1513 return -EINVAL;
1514 }
1515
1516 return 0;
1517}
1518
1519/*
1520 * HDMI audio codec callbacks
1521 */
1522
1523static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1524 struct hdmi_codec_daifmt *daifmt,
1525 struct hdmi_codec_params *params)
1526{
1527 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1528 struct hdmi_audio_param hdmi_params;
1529 unsigned int chan = params->cea.channels;
1530
1531 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1532 params->sample_rate, params->sample_width, chan);
1533
1534 if (!hdmi->bridge.encoder)
1535 return -ENODEV;
1536
1537 switch (chan) {
1538 case 2:
1539 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1540 break;
1541 case 4:
1542 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1543 break;
1544 case 6:
1545 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1546 break;
1547 case 8:
1548 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1549 break;
1550 default:
1551 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1552 return -EINVAL;
1553 }
1554
1555 switch (params->sample_rate) {
1556 case 32000:
1557 case 44100:
1558 case 48000:
1559 case 88200:
1560 case 96000:
1561 case 176400:
1562 case 192000:
1563 break;
1564 default:
1565 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1566 params->sample_rate);
1567 return -EINVAL;
1568 }
1569
1570 switch (daifmt->fmt) {
1571 case HDMI_I2S:
1572 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1573 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1574 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1575 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1576 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1577 break;
1578 default:
1579 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1580 daifmt->fmt);
1581 return -EINVAL;
1582 }
1583
1584 memcpy(&hdmi_params.codec_params, params,
1585 sizeof(hdmi_params.codec_params));
1586
1587 mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1588
1589 return 0;
1590}
1591
1592static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1593{
1594 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1595
1596 dev_dbg(dev, "%s\n", __func__);
1597
1598 mtk_hdmi_audio_enable(hdmi);
1599
1600 return 0;
1601}
1602
1603static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1604{
1605 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1606
1607 dev_dbg(dev, "%s\n", __func__);
1608
1609 mtk_hdmi_audio_disable(hdmi);
1610}
1611
1612static int
1613mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1614{
1615 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1616
1617 dev_dbg(dev, "%s(%d)\n", __func__, enable);
1618
1619 if (enable)
1620 mtk_hdmi_hw_aud_mute(hdmi);
1621 else
1622 mtk_hdmi_hw_aud_unmute(hdmi);
1623
1624 return 0;
1625}
1626
1627static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1628{
1629 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1630
1631 dev_dbg(dev, "%s\n", __func__);
1632
1633 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
1634
1635 return 0;
1636}
1637
1638static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1639 .hw_params = mtk_hdmi_audio_hw_params,
1640 .audio_startup = mtk_hdmi_audio_startup,
1641 .audio_shutdown = mtk_hdmi_audio_shutdown,
1642 .digital_mute = mtk_hdmi_audio_digital_mute,
1643 .get_eld = mtk_hdmi_audio_get_eld,
1644};
1645
1646static void mtk_hdmi_register_audio_driver(struct device *dev)
1647{
1648 struct hdmi_codec_pdata codec_data = {
1649 .ops = &mtk_hdmi_audio_codec_ops,
1650 .max_i2s_channels = 2,
1651 .i2s = 1,
1652 };
1653 struct platform_device *pdev;
1654
1655 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1656 PLATFORM_DEVID_AUTO, &codec_data,
1657 sizeof(codec_data));
1658 if (IS_ERR(pdev))
1659 return;
1660
1661 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1662}
1663
1664static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1665{
1666 struct mtk_hdmi *hdmi;
1667 struct device *dev = &pdev->dev;
1668 int ret;
1669
1670 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1671 if (!hdmi)
1672 return -ENOMEM;
1673
1674 hdmi->dev = dev;
1675
1676 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1677 if (ret)
1678 return ret;
1679
1680 hdmi->phy = devm_phy_get(dev, "hdmi");
1681 if (IS_ERR(hdmi->phy)) {
1682 ret = PTR_ERR(hdmi->phy);
1683 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1684 return ret;
1685 }
1686
1687 platform_set_drvdata(pdev, hdmi);
1688
1689 ret = mtk_hdmi_output_init(hdmi);
1690 if (ret) {
1691 dev_err(dev, "Failed to initialize hdmi output\n");
1692 return ret;
1693 }
1694
1695 mtk_hdmi_register_audio_driver(dev);
1696
1697 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1698 hdmi->bridge.of_node = pdev->dev.of_node;
1699 drm_bridge_add(&hdmi->bridge);
1700
1701 ret = mtk_hdmi_clk_enable_audio(hdmi);
1702 if (ret) {
1703 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1704 goto err_bridge_remove;
1705 }
1706
1707 dev_dbg(dev, "mediatek hdmi probe success\n");
1708 return 0;
1709
1710err_bridge_remove:
1711 drm_bridge_remove(&hdmi->bridge);
1712 return ret;
1713}
1714
1715static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1716{
1717 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1718
1719 drm_bridge_remove(&hdmi->bridge);
1720 mtk_hdmi_clk_disable_audio(hdmi);
1721 return 0;
1722}
1723
1724#ifdef CONFIG_PM_SLEEP
1725static int mtk_hdmi_suspend(struct device *dev)
1726{
1727 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1728
1729 mtk_hdmi_clk_disable_audio(hdmi);
1730 dev_dbg(dev, "hdmi suspend success!\n");
1731 return 0;
1732}
1733
1734static int mtk_hdmi_resume(struct device *dev)
1735{
1736 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1737 int ret = 0;
1738
1739 ret = mtk_hdmi_clk_enable_audio(hdmi);
1740 if (ret) {
1741 dev_err(dev, "hdmi resume failed!\n");
1742 return ret;
1743 }
1744
1745 dev_dbg(dev, "hdmi resume success!\n");
1746 return 0;
1747}
1748#endif
1749static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1750 mtk_hdmi_suspend, mtk_hdmi_resume);
1751
1752static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1753 { .compatible = "mediatek,mt8173-hdmi", },
1754 {}
1755};
1756
1757static struct platform_driver mtk_hdmi_driver = {
1758 .probe = mtk_drm_hdmi_probe,
1759 .remove = mtk_drm_hdmi_remove,
1760 .driver = {
1761 .name = "mediatek-drm-hdmi",
1762 .of_match_table = mtk_drm_hdmi_of_ids,
1763 .pm = &mtk_hdmi_pm_ops,
1764 },
1765};
1766
1767static struct platform_driver * const mtk_hdmi_drivers[] = {
1768 &mtk_hdmi_phy_driver,
1769 &mtk_hdmi_ddc_driver,
1770 &mtk_cec_driver,
1771 &mtk_hdmi_driver,
1772};
1773
1774static int __init mtk_hdmitx_init(void)
1775{
1776 return platform_register_drivers(mtk_hdmi_drivers,
1777 ARRAY_SIZE(mtk_hdmi_drivers));
1778}
1779
1780static void __exit mtk_hdmitx_exit(void)
1781{
1782 platform_unregister_drivers(mtk_hdmi_drivers,
1783 ARRAY_SIZE(mtk_hdmi_drivers));
1784}
1785
1786module_init(mtk_hdmitx_init);
1787module_exit(mtk_hdmitx_exit);
1788
1789MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1790MODULE_DESCRIPTION("MediaTek HDMI Driver");
1791MODULE_LICENSE("GPL v2");