1/*
  2 * Copyright © 2014-2017 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 */
 24
 25#ifndef _INTEL_DEVICE_INFO_H_
 26#define _INTEL_DEVICE_INFO_H_
 27
 28#include "intel_display.h"
 29
 30struct drm_printer;
 31struct drm_i915_private;
 32
 33/* Keep in gen based order, and chronological order within a gen */
 34enum intel_platform {
 35	INTEL_PLATFORM_UNINITIALIZED = 0,
 36	/* gen2 */
 37	INTEL_I830,
 38	INTEL_I845G,
 39	INTEL_I85X,
 40	INTEL_I865G,
 41	/* gen3 */
 42	INTEL_I915G,
 43	INTEL_I915GM,
 44	INTEL_I945G,
 45	INTEL_I945GM,
 46	INTEL_G33,
 47	INTEL_PINEVIEW,
 48	/* gen4 */
 49	INTEL_I965G,
 50	INTEL_I965GM,
 51	INTEL_G45,
 52	INTEL_GM45,
 53	/* gen5 */
 54	INTEL_IRONLAKE,
 55	/* gen6 */
 56	INTEL_SANDYBRIDGE,
 57	/* gen7 */
 58	INTEL_IVYBRIDGE,
 59	INTEL_VALLEYVIEW,
 60	INTEL_HASWELL,
 61	/* gen8 */
 62	INTEL_BROADWELL,
 63	INTEL_CHERRYVIEW,
 64	/* gen9 */
 65	INTEL_SKYLAKE,
 66	INTEL_BROXTON,
 67	INTEL_KABYLAKE,
 68	INTEL_GEMINILAKE,
 69	INTEL_COFFEELAKE,
 70	/* gen10 */
 71	INTEL_CANNONLAKE,
 72	/* gen11 */
 73	INTEL_ICELAKE,
 74	INTEL_MAX_PLATFORMS
 75};
 76
 77#define DEV_INFO_FOR_EACH_FLAG(func) \
 78	func(is_mobile); \
 79	func(is_lp); \
 80	func(is_alpha_support); \
 81	/* Keep has_* in alphabetical order */ \
 82	func(has_64bit_reloc); \
 83	func(has_aliasing_ppgtt); \
 84	func(has_csr); \
 85	func(has_ddi); \
 86	func(has_dp_mst); \
 87	func(has_reset_engine); \
 88	func(has_fbc); \
 89	func(has_fpga_dbg); \
 90	func(has_full_ppgtt); \
 91	func(has_full_48bit_ppgtt); \
 92	func(has_gmch_display); \
 93	func(has_guc); \
 94	func(has_guc_ct); \
 95	func(has_hotplug); \
 96	func(has_l3_dpf); \
 97	func(has_llc); \
 98	func(has_logical_ring_contexts); \
 99	func(has_logical_ring_elsq); \
100	func(has_logical_ring_preemption); \
101	func(has_overlay); \
102	func(has_pooled_eu); \
103	func(has_psr); \
104	func(has_rc6); \
105	func(has_rc6p); \
106	func(has_resource_streamer); \
107	func(has_runtime_pm); \
108	func(has_snoop); \
109	func(unfenced_needs_alignment); \
110	func(cursor_needs_physical); \
111	func(hws_needs_physical); \
112	func(overlay_needs_physical); \
113	func(supports_tv); \
114	func(has_ipc);
115
116#define GEN_MAX_SLICES		(6) /* CNL upper bound */
117#define GEN_MAX_SUBSLICES	(7)
118
119struct sseu_dev_info {
120	u8 slice_mask;
121	u8 subslice_mask[GEN_MAX_SUBSLICES];
122	u16 eu_total;
123	u8 eu_per_subslice;
124	u8 min_eu_in_pool;
125	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
126	u8 subslice_7eu[3];
127	u8 has_slice_pg:1;
128	u8 has_subslice_pg:1;
129	u8 has_eu_pg:1;
130
131	/* Topology fields */
132	u8 max_slices;
133	u8 max_subslices;
134	u8 max_eus_per_subslice;
135
136	/* We don't have more than 8 eus per subslice at the moment and as we
137	 * store eus enabled using bits, no need to multiply by eus per
138	 * subslice.
139	 */
140	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
141};
142
143typedef u8 intel_ring_mask_t;
144
145struct intel_device_info {
146	u16 device_id;
147	u16 gen_mask;
148
149	u8 gen;
150	u8 gt; /* GT number, 0 if undefined */
151	u8 num_rings;
152	intel_ring_mask_t ring_mask; /* Rings supported by the HW */
153
154	enum intel_platform platform;
155	u32 platform_mask;
156
157	unsigned int page_sizes; /* page sizes supported by the HW */
158
159	u32 display_mmio_offset;
160
161	u8 num_pipes;
162	u8 num_sprites[I915_MAX_PIPES];
163	u8 num_scalers[I915_MAX_PIPES];
164
165#define DEFINE_FLAG(name) u8 name:1
166	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
167#undef DEFINE_FLAG
168	u16 ddb_size; /* in blocks */
169
170	/* Register offsets for the various display pipes and transcoders */
171	int pipe_offsets[I915_MAX_TRANSCODERS];
172	int trans_offsets[I915_MAX_TRANSCODERS];
173	int palette_offsets[I915_MAX_PIPES];
174	int cursor_offsets[I915_MAX_PIPES];
175
176	/* Slice/subslice/EU info */
177	struct sseu_dev_info sseu;
178
179	u32 cs_timestamp_frequency_khz;
180
181	struct color_luts {
182		u16 degamma_lut_size;
183		u16 gamma_lut_size;
184	} color;
185};
186
187struct intel_driver_caps {
188	unsigned int scheduler;
189};
190
191static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
192{
193	unsigned int i, total = 0;
194
195	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
196		total += hweight8(sseu->subslice_mask[i]);
197
198	return total;
199}
200
201static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
202			      int slice, int subslice)
203{
204	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
205					   BITS_PER_BYTE);
206	int slice_stride = sseu->max_subslices * subslice_stride;
207
208	return slice * slice_stride + subslice * subslice_stride;
209}
210
211static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
212			       int slice, int subslice)
213{
214	int i, offset = sseu_eu_idx(sseu, slice, subslice);
215	u16 eu_mask = 0;
216
217	for (i = 0;
218	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
219		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
220			(i * BITS_PER_BYTE);
221	}
222
223	return eu_mask;
224}
225
226static inline void sseu_set_eus(struct sseu_dev_info *sseu,
227				int slice, int subslice, u16 eu_mask)
228{
229	int i, offset = sseu_eu_idx(sseu, slice, subslice);
230
231	for (i = 0;
232	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
233		sseu->eu_mask[offset + i] =
234			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
235	}
236}
237
238const char *intel_platform_name(enum intel_platform platform);
239
240void intel_device_info_runtime_init(struct intel_device_info *info);
241void intel_device_info_dump(const struct intel_device_info *info,
242			    struct drm_printer *p);
243void intel_device_info_dump_flags(const struct intel_device_info *info,
244				  struct drm_printer *p);
245void intel_device_info_dump_runtime(const struct intel_device_info *info,
246				    struct drm_printer *p);
247void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
248				     struct drm_printer *p);
249
250void intel_driver_caps_print(const struct intel_driver_caps *caps,
251			     struct drm_printer *p);
252
253#endif