1/*
  2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 21 * SOFTWARE.
 22 *
 23 * Authors:
 24 *    Zhi Wang <zhi.a.wang@intel.com>
 25 *    Zhenyu Wang <zhenyuw@linux.intel.com>
 26 *    Xiao Zheng <xiao.zheng@intel.com>
 27 *
 28 * Contributors:
 29 *    Min He <min.he@intel.com>
 30 *    Bing Niu <bing.niu@intel.com>
 31 *
 32 */
 33
 34#ifndef _GVT_GTT_H_
 35#define _GVT_GTT_H_
 36
 37#define I915_GTT_PAGE_SHIFT         12
 38#define I915_GTT_PAGE_MASK		(~(I915_GTT_PAGE_SIZE - 1))
 39
 40struct intel_vgpu_mm;
 41
 42#define INTEL_GVT_INVALID_ADDR (~0UL)
 43
 44struct intel_gvt_gtt_entry {
 45	u64 val64;
 46	int type;
 47};
 48
 49struct intel_gvt_gtt_pte_ops {
 50	int (*get_entry)(void *pt,
 51			 struct intel_gvt_gtt_entry *e,
 52			 unsigned long index,
 53			 bool hypervisor_access,
 54			 unsigned long gpa,
 55			 struct intel_vgpu *vgpu);
 56	int (*set_entry)(void *pt,
 57			 struct intel_gvt_gtt_entry *e,
 58			 unsigned long index,
 59			 bool hypervisor_access,
 60			 unsigned long gpa,
 61			 struct intel_vgpu *vgpu);
 62	bool (*test_present)(struct intel_gvt_gtt_entry *e);
 63	void (*clear_present)(struct intel_gvt_gtt_entry *e);
 64	void (*set_present)(struct intel_gvt_gtt_entry *e);
 65	bool (*test_pse)(struct intel_gvt_gtt_entry *e);
 66	void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn);
 67	unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e);
 68};
 69
 70struct intel_gvt_gtt_gma_ops {
 71	unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma);
 72	unsigned long (*gma_to_pte_index)(unsigned long gma);
 73	unsigned long (*gma_to_pde_index)(unsigned long gma);
 74	unsigned long (*gma_to_l3_pdp_index)(unsigned long gma);
 75	unsigned long (*gma_to_l4_pdp_index)(unsigned long gma);
 76	unsigned long (*gma_to_pml4_index)(unsigned long gma);
 77};
 78
 79struct intel_gvt_gtt {
 80	struct intel_gvt_gtt_pte_ops *pte_ops;
 81	struct intel_gvt_gtt_gma_ops *gma_ops;
 82	int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
 83	void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
 84	struct list_head oos_page_use_list_head;
 85	struct list_head oos_page_free_list_head;
 86	struct list_head ppgtt_mm_lru_list_head;
 87
 88	struct page *scratch_page;
 89	unsigned long scratch_mfn;
 90};
 91
 92typedef enum {
 93	GTT_TYPE_INVALID = -1,
 94
 95	GTT_TYPE_GGTT_PTE,
 96
 97	GTT_TYPE_PPGTT_PTE_4K_ENTRY,
 98	GTT_TYPE_PPGTT_PTE_2M_ENTRY,
 99	GTT_TYPE_PPGTT_PTE_1G_ENTRY,
100
101	GTT_TYPE_PPGTT_PTE_ENTRY,
102
103	GTT_TYPE_PPGTT_PDE_ENTRY,
104	GTT_TYPE_PPGTT_PDP_ENTRY,
105	GTT_TYPE_PPGTT_PML4_ENTRY,
106
107	GTT_TYPE_PPGTT_ROOT_ENTRY,
108
109	GTT_TYPE_PPGTT_ROOT_L3_ENTRY,
110	GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
111
112	GTT_TYPE_PPGTT_ENTRY,
113
114	GTT_TYPE_PPGTT_PTE_PT,
115	GTT_TYPE_PPGTT_PDE_PT,
116	GTT_TYPE_PPGTT_PDP_PT,
117	GTT_TYPE_PPGTT_PML4_PT,
118
119	GTT_TYPE_MAX,
120} intel_gvt_gtt_type_t;
121
122enum intel_gvt_mm_type {
123	INTEL_GVT_MM_GGTT,
124	INTEL_GVT_MM_PPGTT,
125};
126
127#define GVT_RING_CTX_NR_PDPS	GEN8_3LVL_PDPES
128
129struct intel_vgpu_mm {
130	enum intel_gvt_mm_type type;
131	struct intel_vgpu *vgpu;
132
133	struct kref ref;
134	atomic_t pincount;
135
136	union {
137		struct {
138			intel_gvt_gtt_type_t root_entry_type;
139			/*
140			 * The 4 PDPs in ring context. For 48bit addressing,
141			 * only PDP0 is valid and point to PML4. For 32it
142			 * addressing, all 4 are used as true PDPs.
143			 */
144			u64 guest_pdps[GVT_RING_CTX_NR_PDPS];
145			u64 shadow_pdps[GVT_RING_CTX_NR_PDPS];
146			bool shadowed;
147
148			struct list_head list;
149			struct list_head lru_list;
150		} ppgtt_mm;
151		struct {
152			void *virtual_ggtt;
153		} ggtt_mm;
154	};
155};
156
157struct intel_vgpu_mm *intel_vgpu_create_ppgtt_mm(struct intel_vgpu *vgpu,
158		intel_gvt_gtt_type_t root_entry_type, u64 pdps[]);
159
160static inline void intel_vgpu_mm_get(struct intel_vgpu_mm *mm)
161{
162	kref_get(&mm->ref);
163}
164
165void _intel_vgpu_mm_release(struct kref *mm_ref);
166
167static inline void intel_vgpu_mm_put(struct intel_vgpu_mm *mm)
168{
169	kref_put(&mm->ref, _intel_vgpu_mm_release);
170}
171
172static inline void intel_vgpu_destroy_mm(struct intel_vgpu_mm *mm)
173{
174	intel_vgpu_mm_put(mm);
175}
176
177struct intel_vgpu_guest_page;
178
179struct intel_vgpu_scratch_pt {
180	struct page *page;
181	unsigned long page_mfn;
182};
183
184struct intel_vgpu_gtt {
185	struct intel_vgpu_mm *ggtt_mm;
186	unsigned long active_ppgtt_mm_bitmap;
187	struct list_head ppgtt_mm_list_head;
188	struct radix_tree_root spt_tree;
189	struct list_head oos_page_list_head;
190	struct list_head post_shadow_list_head;
191	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
192};
193
194extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
195extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
196void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old);
197void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu);
198
199extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
200void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
201extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
202
203extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
204		int page_table_level, void *root_entry);
205
206struct intel_vgpu_oos_page {
207	struct intel_vgpu_ppgtt_spt *spt;
208	struct list_head list;
209	struct list_head vm_list;
210	int id;
211	unsigned char mem[I915_GTT_PAGE_SIZE];
212};
213
214#define GTT_ENTRY_NUM_IN_ONE_PAGE 512
215
216/* Represent a vgpu shadow page table. */
217struct intel_vgpu_ppgtt_spt {
218	atomic_t refcount;
219	struct intel_vgpu *vgpu;
220
221	struct {
222		intel_gvt_gtt_type_t type;
223		void *vaddr;
224		struct page *page;
225		unsigned long mfn;
226	} shadow_page;
227
228	struct {
229		intel_gvt_gtt_type_t type;
230		unsigned long gfn;
231		unsigned long write_cnt;
232		struct intel_vgpu_oos_page *oos_page;
233	} guest_page;
234
235	DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE);
236	struct list_head post_shadow_list;
237};
238
239int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu);
240
241int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu);
242
243int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm);
244
245void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm);
246
247unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm,
248		unsigned long gma);
249
250struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu,
251		u64 pdps[]);
252
253struct intel_vgpu_mm *intel_vgpu_get_ppgtt_mm(struct intel_vgpu *vgpu,
254		intel_gvt_gtt_type_t root_entry_type, u64 pdps[]);
255
256int intel_vgpu_put_ppgtt_mm(struct intel_vgpu *vgpu, u64 pdps[]);
257
258int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu,
259	unsigned int off, void *p_data, unsigned int bytes);
260
261int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
262	unsigned int off, void *p_data, unsigned int bytes);
263
264#endif /* _GVT_GTT_H_ */