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1/* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14#include <drm/drmP.h>
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18#include <linux/clk.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/component.h>
23#include <linux/mfd/syscon.h>
24#include <linux/regmap.h>
25
26#include <video/of_display_timing.h>
27#include <video/of_videomode.h>
28#include <video/samsung_fimd.h>
29#include <drm/exynos_drm.h>
30
31#include "exynos_drm_drv.h"
32#include "exynos_drm_fb.h"
33#include "exynos_drm_crtc.h"
34#include "exynos_drm_plane.h"
35#include "exynos_drm_iommu.h"
36
37/*
38 * FIMD stands for Fully Interactive Mobile Display and
39 * as a display controller, it transfers contents drawn on memory
40 * to a LCD Panel through Display Interfaces such as RGB or
41 * CPU Interface.
42 */
43
44#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
45
46/* position control register for hardware window 0, 2 ~ 4.*/
47#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
49/*
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
52 */
53#define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54/* size control register for hardware windows 1 ~ 2. */
55#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
56
57#define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
58#define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
59
60#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
61#define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
62#define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
63#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
64
65/* color key control register for hardware window 1 ~ 4. */
66#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
67/* color key value register for hardware window 1 ~ 4. */
68#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
69
70/* I80 trigger control register */
71#define TRIGCON 0x1A4
72#define TRGMODE_ENABLE (1 << 0)
73#define SWTRGCMD_ENABLE (1 << 1)
74/* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
75#define HWTRGEN_ENABLE (1 << 3)
76#define HWTRGMASK_ENABLE (1 << 4)
77/* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
78#define HWTRIGEN_PER_ENABLE (1 << 31)
79
80/* display mode change control register except exynos4 */
81#define VIDOUT_CON 0x000
82#define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
83
84/* I80 interface control for main LDI register */
85#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
86#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
87#define LCD_CS_SETUP(x) ((x) << 16)
88#define LCD_WR_SETUP(x) ((x) << 12)
89#define LCD_WR_ACTIVE(x) ((x) << 8)
90#define LCD_WR_HOLD(x) ((x) << 4)
91#define I80IFEN_ENABLE (1 << 0)
92
93/* FIMD has totally five hardware windows. */
94#define WINDOWS_NR 5
95
96/* HW trigger flag on i80 panel. */
97#define I80_HW_TRG (1 << 1)
98
99struct fimd_driver_data {
100 unsigned int timing_base;
101 unsigned int lcdblk_offset;
102 unsigned int lcdblk_vt_shift;
103 unsigned int lcdblk_bypass_shift;
104 unsigned int lcdblk_mic_bypass_shift;
105 unsigned int trg_type;
106
107 unsigned int has_shadowcon:1;
108 unsigned int has_clksel:1;
109 unsigned int has_limited_fmt:1;
110 unsigned int has_vidoutcon:1;
111 unsigned int has_vtsel:1;
112 unsigned int has_mic_bypass:1;
113 unsigned int has_dp_clk:1;
114 unsigned int has_hw_trigger:1;
115 unsigned int has_trigger_per_te:1;
116};
117
118static struct fimd_driver_data s3c64xx_fimd_driver_data = {
119 .timing_base = 0x0,
120 .has_clksel = 1,
121 .has_limited_fmt = 1,
122};
123
124static struct fimd_driver_data exynos3_fimd_driver_data = {
125 .timing_base = 0x20000,
126 .lcdblk_offset = 0x210,
127 .lcdblk_bypass_shift = 1,
128 .has_shadowcon = 1,
129 .has_vidoutcon = 1,
130};
131
132static struct fimd_driver_data exynos4_fimd_driver_data = {
133 .timing_base = 0x0,
134 .lcdblk_offset = 0x210,
135 .lcdblk_vt_shift = 10,
136 .lcdblk_bypass_shift = 1,
137 .has_shadowcon = 1,
138 .has_vtsel = 1,
139};
140
141static struct fimd_driver_data exynos5_fimd_driver_data = {
142 .timing_base = 0x20000,
143 .lcdblk_offset = 0x214,
144 .lcdblk_vt_shift = 24,
145 .lcdblk_bypass_shift = 15,
146 .has_shadowcon = 1,
147 .has_vidoutcon = 1,
148 .has_vtsel = 1,
149 .has_dp_clk = 1,
150};
151
152static struct fimd_driver_data exynos5420_fimd_driver_data = {
153 .timing_base = 0x20000,
154 .lcdblk_offset = 0x214,
155 .lcdblk_vt_shift = 24,
156 .lcdblk_bypass_shift = 15,
157 .lcdblk_mic_bypass_shift = 11,
158 .has_shadowcon = 1,
159 .has_vidoutcon = 1,
160 .has_vtsel = 1,
161 .has_mic_bypass = 1,
162 .has_dp_clk = 1,
163};
164
165struct fimd_context {
166 struct device *dev;
167 struct drm_device *drm_dev;
168 struct exynos_drm_crtc *crtc;
169 struct exynos_drm_plane planes[WINDOWS_NR];
170 struct exynos_drm_plane_config configs[WINDOWS_NR];
171 struct clk *bus_clk;
172 struct clk *lcd_clk;
173 void __iomem *regs;
174 struct regmap *sysreg;
175 unsigned long irq_flags;
176 u32 vidcon0;
177 u32 vidcon1;
178 u32 vidout_con;
179 u32 i80ifcon;
180 bool i80_if;
181 bool suspended;
182 wait_queue_head_t wait_vsync_queue;
183 atomic_t wait_vsync_event;
184 atomic_t win_updated;
185 atomic_t triggering;
186 u32 clkdiv;
187
188 const struct fimd_driver_data *driver_data;
189 struct drm_encoder *encoder;
190 struct exynos_drm_clk dp_clk;
191};
192
193static const struct of_device_id fimd_driver_dt_match[] = {
194 { .compatible = "samsung,s3c6400-fimd",
195 .data = &s3c64xx_fimd_driver_data },
196 { .compatible = "samsung,exynos3250-fimd",
197 .data = &exynos3_fimd_driver_data },
198 { .compatible = "samsung,exynos4210-fimd",
199 .data = &exynos4_fimd_driver_data },
200 { .compatible = "samsung,exynos5250-fimd",
201 .data = &exynos5_fimd_driver_data },
202 { .compatible = "samsung,exynos5420-fimd",
203 .data = &exynos5420_fimd_driver_data },
204 {},
205};
206MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
207
208static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
209 DRM_PLANE_TYPE_PRIMARY,
210 DRM_PLANE_TYPE_OVERLAY,
211 DRM_PLANE_TYPE_OVERLAY,
212 DRM_PLANE_TYPE_OVERLAY,
213 DRM_PLANE_TYPE_CURSOR,
214};
215
216static const uint32_t fimd_formats[] = {
217 DRM_FORMAT_C8,
218 DRM_FORMAT_XRGB1555,
219 DRM_FORMAT_RGB565,
220 DRM_FORMAT_XRGB8888,
221 DRM_FORMAT_ARGB8888,
222};
223
224static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
225{
226 struct fimd_context *ctx = crtc->ctx;
227 u32 val;
228
229 if (ctx->suspended)
230 return -EPERM;
231
232 if (!test_and_set_bit(0, &ctx->irq_flags)) {
233 val = readl(ctx->regs + VIDINTCON0);
234
235 val |= VIDINTCON0_INT_ENABLE;
236
237 if (ctx->i80_if) {
238 val |= VIDINTCON0_INT_I80IFDONE;
239 val |= VIDINTCON0_INT_SYSMAINCON;
240 val &= ~VIDINTCON0_INT_SYSSUBCON;
241 } else {
242 val |= VIDINTCON0_INT_FRAME;
243
244 val &= ~VIDINTCON0_FRAMESEL0_MASK;
245 val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
246 val &= ~VIDINTCON0_FRAMESEL1_MASK;
247 val |= VIDINTCON0_FRAMESEL1_NONE;
248 }
249
250 writel(val, ctx->regs + VIDINTCON0);
251 }
252
253 return 0;
254}
255
256static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
257{
258 struct fimd_context *ctx = crtc->ctx;
259 u32 val;
260
261 if (ctx->suspended)
262 return;
263
264 if (test_and_clear_bit(0, &ctx->irq_flags)) {
265 val = readl(ctx->regs + VIDINTCON0);
266
267 val &= ~VIDINTCON0_INT_ENABLE;
268
269 if (ctx->i80_if) {
270 val &= ~VIDINTCON0_INT_I80IFDONE;
271 val &= ~VIDINTCON0_INT_SYSMAINCON;
272 val &= ~VIDINTCON0_INT_SYSSUBCON;
273 } else
274 val &= ~VIDINTCON0_INT_FRAME;
275
276 writel(val, ctx->regs + VIDINTCON0);
277 }
278}
279
280static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
281{
282 struct fimd_context *ctx = crtc->ctx;
283
284 if (ctx->suspended)
285 return;
286
287 atomic_set(&ctx->wait_vsync_event, 1);
288
289 /*
290 * wait for FIMD to signal VSYNC interrupt or return after
291 * timeout which is set to 50ms (refresh rate of 20).
292 */
293 if (!wait_event_timeout(ctx->wait_vsync_queue,
294 !atomic_read(&ctx->wait_vsync_event),
295 HZ/20))
296 DRM_DEBUG_KMS("vblank wait timed out.\n");
297}
298
299static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
300 bool enable)
301{
302 u32 val = readl(ctx->regs + WINCON(win));
303
304 if (enable)
305 val |= WINCONx_ENWIN;
306 else
307 val &= ~WINCONx_ENWIN;
308
309 writel(val, ctx->regs + WINCON(win));
310}
311
312static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
313 unsigned int win,
314 bool enable)
315{
316 u32 val = readl(ctx->regs + SHADOWCON);
317
318 if (enable)
319 val |= SHADOWCON_CHx_ENABLE(win);
320 else
321 val &= ~SHADOWCON_CHx_ENABLE(win);
322
323 writel(val, ctx->regs + SHADOWCON);
324}
325
326static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
327{
328 struct fimd_context *ctx = crtc->ctx;
329 unsigned int win, ch_enabled = 0;
330
331 DRM_DEBUG_KMS("%s\n", __FILE__);
332
333 /* Hardware is in unknown state, so ensure it gets enabled properly */
334 pm_runtime_get_sync(ctx->dev);
335
336 clk_prepare_enable(ctx->bus_clk);
337 clk_prepare_enable(ctx->lcd_clk);
338
339 /* Check if any channel is enabled. */
340 for (win = 0; win < WINDOWS_NR; win++) {
341 u32 val = readl(ctx->regs + WINCON(win));
342
343 if (val & WINCONx_ENWIN) {
344 fimd_enable_video_output(ctx, win, false);
345
346 if (ctx->driver_data->has_shadowcon)
347 fimd_enable_shadow_channel_path(ctx, win,
348 false);
349
350 ch_enabled = 1;
351 }
352 }
353
354 /* Wait for vsync, as disable channel takes effect at next vsync */
355 if (ch_enabled) {
356 ctx->suspended = false;
357
358 fimd_enable_vblank(ctx->crtc);
359 fimd_wait_for_vblank(ctx->crtc);
360 fimd_disable_vblank(ctx->crtc);
361
362 ctx->suspended = true;
363 }
364
365 clk_disable_unprepare(ctx->lcd_clk);
366 clk_disable_unprepare(ctx->bus_clk);
367
368 pm_runtime_put(ctx->dev);
369}
370
371
372static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
373 struct drm_crtc_state *state)
374{
375 struct drm_display_mode *mode = &state->adjusted_mode;
376 struct fimd_context *ctx = crtc->ctx;
377 unsigned long ideal_clk, lcd_rate;
378 u32 clkdiv;
379
380 if (mode->clock == 0) {
381 DRM_INFO("Mode has zero clock value.\n");
382 return -EINVAL;
383 }
384
385 ideal_clk = mode->clock * 1000;
386
387 if (ctx->i80_if) {
388 /*
389 * The frame done interrupt should be occurred prior to the
390 * next TE signal.
391 */
392 ideal_clk *= 2;
393 }
394
395 lcd_rate = clk_get_rate(ctx->lcd_clk);
396 if (2 * lcd_rate < ideal_clk) {
397 DRM_INFO("sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
398 lcd_rate, ideal_clk);
399 return -EINVAL;
400 }
401
402 /* Find the clock divider value that gets us closest to ideal_clk */
403 clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
404 if (clkdiv >= 0x200) {
405 DRM_INFO("requested pixel clock(%lu) too low\n", ideal_clk);
406 return -EINVAL;
407 }
408
409 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
410
411 return 0;
412}
413
414static void fimd_setup_trigger(struct fimd_context *ctx)
415{
416 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
417 u32 trg_type = ctx->driver_data->trg_type;
418 u32 val = readl(timing_base + TRIGCON);
419
420 val &= ~(TRGMODE_ENABLE);
421
422 if (trg_type == I80_HW_TRG) {
423 if (ctx->driver_data->has_hw_trigger)
424 val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
425 if (ctx->driver_data->has_trigger_per_te)
426 val |= HWTRIGEN_PER_ENABLE;
427 } else {
428 val |= TRGMODE_ENABLE;
429 }
430
431 writel(val, timing_base + TRIGCON);
432}
433
434static void fimd_commit(struct exynos_drm_crtc *crtc)
435{
436 struct fimd_context *ctx = crtc->ctx;
437 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
438 const struct fimd_driver_data *driver_data = ctx->driver_data;
439 void *timing_base = ctx->regs + driver_data->timing_base;
440 u32 val;
441
442 if (ctx->suspended)
443 return;
444
445 /* nothing to do if we haven't set the mode yet */
446 if (mode->htotal == 0 || mode->vtotal == 0)
447 return;
448
449 if (ctx->i80_if) {
450 val = ctx->i80ifcon | I80IFEN_ENABLE;
451 writel(val, timing_base + I80IFCONFAx(0));
452
453 /* disable auto frame rate */
454 writel(0, timing_base + I80IFCONFBx(0));
455
456 /* set video type selection to I80 interface */
457 if (driver_data->has_vtsel && ctx->sysreg &&
458 regmap_update_bits(ctx->sysreg,
459 driver_data->lcdblk_offset,
460 0x3 << driver_data->lcdblk_vt_shift,
461 0x1 << driver_data->lcdblk_vt_shift)) {
462 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
463 return;
464 }
465 } else {
466 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
467 u32 vidcon1;
468
469 /* setup polarity values */
470 vidcon1 = ctx->vidcon1;
471 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
472 vidcon1 |= VIDCON1_INV_VSYNC;
473 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
474 vidcon1 |= VIDCON1_INV_HSYNC;
475 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
476
477 /* setup vertical timing values. */
478 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
479 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
480 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
481
482 val = VIDTCON0_VBPD(vbpd - 1) |
483 VIDTCON0_VFPD(vfpd - 1) |
484 VIDTCON0_VSPW(vsync_len - 1);
485 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
486
487 /* setup horizontal timing values. */
488 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
489 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
490 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
491
492 val = VIDTCON1_HBPD(hbpd - 1) |
493 VIDTCON1_HFPD(hfpd - 1) |
494 VIDTCON1_HSPW(hsync_len - 1);
495 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
496 }
497
498 if (driver_data->has_vidoutcon)
499 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
500
501 /* set bypass selection */
502 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
503 driver_data->lcdblk_offset,
504 0x1 << driver_data->lcdblk_bypass_shift,
505 0x1 << driver_data->lcdblk_bypass_shift)) {
506 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
507 return;
508 }
509
510 /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
511 * bit should be cleared.
512 */
513 if (driver_data->has_mic_bypass && ctx->sysreg &&
514 regmap_update_bits(ctx->sysreg,
515 driver_data->lcdblk_offset,
516 0x1 << driver_data->lcdblk_mic_bypass_shift,
517 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
518 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
519 return;
520 }
521
522 /* setup horizontal and vertical display size. */
523 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
524 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
525 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
526 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
527 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
528
529 fimd_setup_trigger(ctx);
530
531 /*
532 * fields of register with prefix '_F' would be updated
533 * at vsync(same as dma start)
534 */
535 val = ctx->vidcon0;
536 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
537
538 if (ctx->driver_data->has_clksel)
539 val |= VIDCON0_CLKSEL_LCD;
540
541 if (ctx->clkdiv > 1)
542 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
543
544 writel(val, ctx->regs + VIDCON0);
545}
546
547
548static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
549 uint32_t pixel_format, int width)
550{
551 unsigned long val;
552
553 val = WINCONx_ENWIN;
554
555 /*
556 * In case of s3c64xx, window 0 doesn't support alpha channel.
557 * So the request format is ARGB8888 then change it to XRGB8888.
558 */
559 if (ctx->driver_data->has_limited_fmt && !win) {
560 if (pixel_format == DRM_FORMAT_ARGB8888)
561 pixel_format = DRM_FORMAT_XRGB8888;
562 }
563
564 switch (pixel_format) {
565 case DRM_FORMAT_C8:
566 val |= WINCON0_BPPMODE_8BPP_PALETTE;
567 val |= WINCONx_BURSTLEN_8WORD;
568 val |= WINCONx_BYTSWP;
569 break;
570 case DRM_FORMAT_XRGB1555:
571 val |= WINCON0_BPPMODE_16BPP_1555;
572 val |= WINCONx_HAWSWP;
573 val |= WINCONx_BURSTLEN_16WORD;
574 break;
575 case DRM_FORMAT_RGB565:
576 val |= WINCON0_BPPMODE_16BPP_565;
577 val |= WINCONx_HAWSWP;
578 val |= WINCONx_BURSTLEN_16WORD;
579 break;
580 case DRM_FORMAT_XRGB8888:
581 val |= WINCON0_BPPMODE_24BPP_888;
582 val |= WINCONx_WSWP;
583 val |= WINCONx_BURSTLEN_16WORD;
584 break;
585 case DRM_FORMAT_ARGB8888:
586 default:
587 val |= WINCON1_BPPMODE_25BPP_A1888
588 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
589 val |= WINCONx_WSWP;
590 val |= WINCONx_BURSTLEN_16WORD;
591 break;
592 }
593
594 /*
595 * Setting dma-burst to 16Word causes permanent tearing for very small
596 * buffers, e.g. cursor buffer. Burst Mode switching which based on
597 * plane size is not recommended as plane size varies alot towards the
598 * end of the screen and rapid movement causes unstable DMA, but it is
599 * still better to change dma-burst than displaying garbage.
600 */
601
602 if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
603 val &= ~WINCONx_BURSTLEN_MASK;
604 val |= WINCONx_BURSTLEN_4WORD;
605 }
606
607 writel(val, ctx->regs + WINCON(win));
608
609 /* hardware window 0 doesn't support alpha channel. */
610 if (win != 0) {
611 /* OSD alpha */
612 val = VIDISD14C_ALPHA0_R(0xf) |
613 VIDISD14C_ALPHA0_G(0xf) |
614 VIDISD14C_ALPHA0_B(0xf) |
615 VIDISD14C_ALPHA1_R(0xf) |
616 VIDISD14C_ALPHA1_G(0xf) |
617 VIDISD14C_ALPHA1_B(0xf);
618
619 writel(val, ctx->regs + VIDOSD_C(win));
620
621 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
622 VIDW_ALPHA_G(0xf);
623 writel(val, ctx->regs + VIDWnALPHA0(win));
624 writel(val, ctx->regs + VIDWnALPHA1(win));
625 }
626}
627
628static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
629{
630 unsigned int keycon0 = 0, keycon1 = 0;
631
632 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
633 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
634
635 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
636
637 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
638 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
639}
640
641/**
642 * shadow_protect_win() - disable updating values from shadow registers at vsync
643 *
644 * @win: window to protect registers for
645 * @protect: 1 to protect (disable updates)
646 */
647static void fimd_shadow_protect_win(struct fimd_context *ctx,
648 unsigned int win, bool protect)
649{
650 u32 reg, bits, val;
651
652 /*
653 * SHADOWCON/PRTCON register is used for enabling timing.
654 *
655 * for example, once only width value of a register is set,
656 * if the dma is started then fimd hardware could malfunction so
657 * with protect window setting, the register fields with prefix '_F'
658 * wouldn't be updated at vsync also but updated once unprotect window
659 * is set.
660 */
661
662 if (ctx->driver_data->has_shadowcon) {
663 reg = SHADOWCON;
664 bits = SHADOWCON_WINx_PROTECT(win);
665 } else {
666 reg = PRTCON;
667 bits = PRTCON_PROTECT;
668 }
669
670 val = readl(ctx->regs + reg);
671 if (protect)
672 val |= bits;
673 else
674 val &= ~bits;
675 writel(val, ctx->regs + reg);
676}
677
678static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
679{
680 struct fimd_context *ctx = crtc->ctx;
681 int i;
682
683 if (ctx->suspended)
684 return;
685
686 for (i = 0; i < WINDOWS_NR; i++)
687 fimd_shadow_protect_win(ctx, i, true);
688}
689
690static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
691{
692 struct fimd_context *ctx = crtc->ctx;
693 int i;
694
695 if (ctx->suspended)
696 return;
697
698 for (i = 0; i < WINDOWS_NR; i++)
699 fimd_shadow_protect_win(ctx, i, false);
700
701 exynos_crtc_handle_event(crtc);
702}
703
704static void fimd_update_plane(struct exynos_drm_crtc *crtc,
705 struct exynos_drm_plane *plane)
706{
707 struct exynos_drm_plane_state *state =
708 to_exynos_plane_state(plane->base.state);
709 struct fimd_context *ctx = crtc->ctx;
710 struct drm_framebuffer *fb = state->base.fb;
711 dma_addr_t dma_addr;
712 unsigned long val, size, offset;
713 unsigned int last_x, last_y, buf_offsize, line_size;
714 unsigned int win = plane->index;
715 unsigned int cpp = fb->format->cpp[0];
716 unsigned int pitch = fb->pitches[0];
717
718 if (ctx->suspended)
719 return;
720
721 offset = state->src.x * cpp;
722 offset += state->src.y * pitch;
723
724 /* buffer start address */
725 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
726 val = (unsigned long)dma_addr;
727 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
728
729 /* buffer end address */
730 size = pitch * state->crtc.h;
731 val = (unsigned long)(dma_addr + size);
732 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
733
734 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
735 (unsigned long)dma_addr, val, size);
736 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
737 state->crtc.w, state->crtc.h);
738
739 /* buffer size */
740 buf_offsize = pitch - (state->crtc.w * cpp);
741 line_size = state->crtc.w * cpp;
742 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
743 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
744 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
745 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
746 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
747
748 /* OSD position */
749 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
750 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
751 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
752 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
753 writel(val, ctx->regs + VIDOSD_A(win));
754
755 last_x = state->crtc.x + state->crtc.w;
756 if (last_x)
757 last_x--;
758 last_y = state->crtc.y + state->crtc.h;
759 if (last_y)
760 last_y--;
761
762 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
763 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
764
765 writel(val, ctx->regs + VIDOSD_B(win));
766
767 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
768 state->crtc.x, state->crtc.y, last_x, last_y);
769
770 /* OSD size */
771 if (win != 3 && win != 4) {
772 u32 offset = VIDOSD_D(win);
773 if (win == 0)
774 offset = VIDOSD_C(win);
775 val = state->crtc.w * state->crtc.h;
776 writel(val, ctx->regs + offset);
777
778 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
779 }
780
781 fimd_win_set_pixfmt(ctx, win, fb->format->format, state->src.w);
782
783 /* hardware window 0 doesn't support color key. */
784 if (win != 0)
785 fimd_win_set_colkey(ctx, win);
786
787 fimd_enable_video_output(ctx, win, true);
788
789 if (ctx->driver_data->has_shadowcon)
790 fimd_enable_shadow_channel_path(ctx, win, true);
791
792 if (ctx->i80_if)
793 atomic_set(&ctx->win_updated, 1);
794}
795
796static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
797 struct exynos_drm_plane *plane)
798{
799 struct fimd_context *ctx = crtc->ctx;
800 unsigned int win = plane->index;
801
802 if (ctx->suspended)
803 return;
804
805 fimd_enable_video_output(ctx, win, false);
806
807 if (ctx->driver_data->has_shadowcon)
808 fimd_enable_shadow_channel_path(ctx, win, false);
809}
810
811static void fimd_enable(struct exynos_drm_crtc *crtc)
812{
813 struct fimd_context *ctx = crtc->ctx;
814
815 if (!ctx->suspended)
816 return;
817
818 ctx->suspended = false;
819
820 pm_runtime_get_sync(ctx->dev);
821
822 /* if vblank was enabled status, enable it again. */
823 if (test_and_clear_bit(0, &ctx->irq_flags))
824 fimd_enable_vblank(ctx->crtc);
825
826 fimd_commit(ctx->crtc);
827}
828
829static void fimd_disable(struct exynos_drm_crtc *crtc)
830{
831 struct fimd_context *ctx = crtc->ctx;
832 int i;
833
834 if (ctx->suspended)
835 return;
836
837 /*
838 * We need to make sure that all windows are disabled before we
839 * suspend that connector. Otherwise we might try to scan from
840 * a destroyed buffer later.
841 */
842 for (i = 0; i < WINDOWS_NR; i++)
843 fimd_disable_plane(crtc, &ctx->planes[i]);
844
845 fimd_enable_vblank(crtc);
846 fimd_wait_for_vblank(crtc);
847 fimd_disable_vblank(crtc);
848
849 writel(0, ctx->regs + VIDCON0);
850
851 pm_runtime_put_sync(ctx->dev);
852 ctx->suspended = true;
853}
854
855static void fimd_trigger(struct device *dev)
856{
857 struct fimd_context *ctx = dev_get_drvdata(dev);
858 const struct fimd_driver_data *driver_data = ctx->driver_data;
859 void *timing_base = ctx->regs + driver_data->timing_base;
860 u32 reg;
861
862 /*
863 * Skips triggering if in triggering state, because multiple triggering
864 * requests can cause panel reset.
865 */
866 if (atomic_read(&ctx->triggering))
867 return;
868
869 /* Enters triggering mode */
870 atomic_set(&ctx->triggering, 1);
871
872 reg = readl(timing_base + TRIGCON);
873 reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
874 writel(reg, timing_base + TRIGCON);
875
876 /*
877 * Exits triggering mode if vblank is not enabled yet, because when the
878 * VIDINTCON0 register is not set, it can not exit from triggering mode.
879 */
880 if (!test_bit(0, &ctx->irq_flags))
881 atomic_set(&ctx->triggering, 0);
882}
883
884static void fimd_te_handler(struct exynos_drm_crtc *crtc)
885{
886 struct fimd_context *ctx = crtc->ctx;
887 u32 trg_type = ctx->driver_data->trg_type;
888
889 /* Checks the crtc is detached already from encoder */
890 if (!ctx->drm_dev)
891 return;
892
893 if (trg_type == I80_HW_TRG)
894 goto out;
895
896 /*
897 * If there is a page flip request, triggers and handles the page flip
898 * event so that current fb can be updated into panel GRAM.
899 */
900 if (atomic_add_unless(&ctx->win_updated, -1, 0))
901 fimd_trigger(ctx->dev);
902
903out:
904 /* Wakes up vsync event queue */
905 if (atomic_read(&ctx->wait_vsync_event)) {
906 atomic_set(&ctx->wait_vsync_event, 0);
907 wake_up(&ctx->wait_vsync_queue);
908 }
909
910 if (test_bit(0, &ctx->irq_flags))
911 drm_crtc_handle_vblank(&ctx->crtc->base);
912}
913
914static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
915{
916 struct fimd_context *ctx = container_of(clk, struct fimd_context,
917 dp_clk);
918 u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
919 writel(val, ctx->regs + DP_MIE_CLKCON);
920}
921
922static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
923 .enable = fimd_enable,
924 .disable = fimd_disable,
925 .enable_vblank = fimd_enable_vblank,
926 .disable_vblank = fimd_disable_vblank,
927 .atomic_begin = fimd_atomic_begin,
928 .update_plane = fimd_update_plane,
929 .disable_plane = fimd_disable_plane,
930 .atomic_flush = fimd_atomic_flush,
931 .atomic_check = fimd_atomic_check,
932 .te_handler = fimd_te_handler,
933};
934
935static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
936{
937 struct fimd_context *ctx = (struct fimd_context *)dev_id;
938 u32 val, clear_bit;
939
940 val = readl(ctx->regs + VIDINTCON1);
941
942 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
943 if (val & clear_bit)
944 writel(clear_bit, ctx->regs + VIDINTCON1);
945
946 /* check the crtc is detached already from encoder */
947 if (!ctx->drm_dev)
948 goto out;
949
950 if (!ctx->i80_if)
951 drm_crtc_handle_vblank(&ctx->crtc->base);
952
953 if (ctx->i80_if) {
954 /* Exits triggering mode */
955 atomic_set(&ctx->triggering, 0);
956 } else {
957 /* set wait vsync event to zero and wake up queue. */
958 if (atomic_read(&ctx->wait_vsync_event)) {
959 atomic_set(&ctx->wait_vsync_event, 0);
960 wake_up(&ctx->wait_vsync_queue);
961 }
962 }
963
964out:
965 return IRQ_HANDLED;
966}
967
968static int fimd_bind(struct device *dev, struct device *master, void *data)
969{
970 struct fimd_context *ctx = dev_get_drvdata(dev);
971 struct drm_device *drm_dev = data;
972 struct exynos_drm_plane *exynos_plane;
973 unsigned int i;
974 int ret;
975
976 ctx->drm_dev = drm_dev;
977
978 for (i = 0; i < WINDOWS_NR; i++) {
979 ctx->configs[i].pixel_formats = fimd_formats;
980 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
981 ctx->configs[i].zpos = i;
982 ctx->configs[i].type = fimd_win_types[i];
983 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
984 &ctx->configs[i]);
985 if (ret)
986 return ret;
987 }
988
989 exynos_plane = &ctx->planes[DEFAULT_WIN];
990 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
991 EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
992 if (IS_ERR(ctx->crtc))
993 return PTR_ERR(ctx->crtc);
994
995 if (ctx->driver_data->has_dp_clk) {
996 ctx->dp_clk.enable = fimd_dp_clock_enable;
997 ctx->crtc->pipe_clk = &ctx->dp_clk;
998 }
999
1000 if (ctx->encoder)
1001 exynos_dpi_bind(drm_dev, ctx->encoder);
1002
1003 if (is_drm_iommu_supported(drm_dev))
1004 fimd_clear_channels(ctx->crtc);
1005
1006 return drm_iommu_attach_device(drm_dev, dev);
1007}
1008
1009static void fimd_unbind(struct device *dev, struct device *master,
1010 void *data)
1011{
1012 struct fimd_context *ctx = dev_get_drvdata(dev);
1013
1014 fimd_disable(ctx->crtc);
1015
1016 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
1017
1018 if (ctx->encoder)
1019 exynos_dpi_remove(ctx->encoder);
1020}
1021
1022static const struct component_ops fimd_component_ops = {
1023 .bind = fimd_bind,
1024 .unbind = fimd_unbind,
1025};
1026
1027static int fimd_probe(struct platform_device *pdev)
1028{
1029 struct device *dev = &pdev->dev;
1030 struct fimd_context *ctx;
1031 struct device_node *i80_if_timings;
1032 struct resource *res;
1033 int ret;
1034
1035 if (!dev->of_node)
1036 return -ENODEV;
1037
1038 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1039 if (!ctx)
1040 return -ENOMEM;
1041
1042 ctx->dev = dev;
1043 ctx->suspended = true;
1044 ctx->driver_data = of_device_get_match_data(dev);
1045
1046 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1047 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1048 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1049 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1050
1051 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1052 if (i80_if_timings) {
1053 u32 val;
1054
1055 ctx->i80_if = true;
1056
1057 if (ctx->driver_data->has_vidoutcon)
1058 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1059 else
1060 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1061 /*
1062 * The user manual describes that this "DSI_EN" bit is required
1063 * to enable I80 24-bit data interface.
1064 */
1065 ctx->vidcon0 |= VIDCON0_DSI_EN;
1066
1067 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1068 val = 0;
1069 ctx->i80ifcon = LCD_CS_SETUP(val);
1070 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1071 val = 0;
1072 ctx->i80ifcon |= LCD_WR_SETUP(val);
1073 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1074 val = 1;
1075 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1076 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1077 val = 0;
1078 ctx->i80ifcon |= LCD_WR_HOLD(val);
1079 }
1080 of_node_put(i80_if_timings);
1081
1082 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1083 "samsung,sysreg");
1084 if (IS_ERR(ctx->sysreg)) {
1085 dev_warn(dev, "failed to get system register.\n");
1086 ctx->sysreg = NULL;
1087 }
1088
1089 ctx->bus_clk = devm_clk_get(dev, "fimd");
1090 if (IS_ERR(ctx->bus_clk)) {
1091 dev_err(dev, "failed to get bus clock\n");
1092 return PTR_ERR(ctx->bus_clk);
1093 }
1094
1095 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1096 if (IS_ERR(ctx->lcd_clk)) {
1097 dev_err(dev, "failed to get lcd clock\n");
1098 return PTR_ERR(ctx->lcd_clk);
1099 }
1100
1101 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102
1103 ctx->regs = devm_ioremap_resource(dev, res);
1104 if (IS_ERR(ctx->regs))
1105 return PTR_ERR(ctx->regs);
1106
1107 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1108 ctx->i80_if ? "lcd_sys" : "vsync");
1109 if (!res) {
1110 dev_err(dev, "irq request failed.\n");
1111 return -ENXIO;
1112 }
1113
1114 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1115 0, "drm_fimd", ctx);
1116 if (ret) {
1117 dev_err(dev, "irq request failed.\n");
1118 return ret;
1119 }
1120
1121 init_waitqueue_head(&ctx->wait_vsync_queue);
1122 atomic_set(&ctx->wait_vsync_event, 0);
1123
1124 platform_set_drvdata(pdev, ctx);
1125
1126 ctx->encoder = exynos_dpi_probe(dev);
1127 if (IS_ERR(ctx->encoder))
1128 return PTR_ERR(ctx->encoder);
1129
1130 pm_runtime_enable(dev);
1131
1132 ret = component_add(dev, &fimd_component_ops);
1133 if (ret)
1134 goto err_disable_pm_runtime;
1135
1136 return ret;
1137
1138err_disable_pm_runtime:
1139 pm_runtime_disable(dev);
1140
1141 return ret;
1142}
1143
1144static int fimd_remove(struct platform_device *pdev)
1145{
1146 pm_runtime_disable(&pdev->dev);
1147
1148 component_del(&pdev->dev, &fimd_component_ops);
1149
1150 return 0;
1151}
1152
1153#ifdef CONFIG_PM
1154static int exynos_fimd_suspend(struct device *dev)
1155{
1156 struct fimd_context *ctx = dev_get_drvdata(dev);
1157
1158 clk_disable_unprepare(ctx->lcd_clk);
1159 clk_disable_unprepare(ctx->bus_clk);
1160
1161 return 0;
1162}
1163
1164static int exynos_fimd_resume(struct device *dev)
1165{
1166 struct fimd_context *ctx = dev_get_drvdata(dev);
1167 int ret;
1168
1169 ret = clk_prepare_enable(ctx->bus_clk);
1170 if (ret < 0) {
1171 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1172 return ret;
1173 }
1174
1175 ret = clk_prepare_enable(ctx->lcd_clk);
1176 if (ret < 0) {
1177 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1178 return ret;
1179 }
1180
1181 return 0;
1182}
1183#endif
1184
1185static const struct dev_pm_ops exynos_fimd_pm_ops = {
1186 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1187};
1188
1189struct platform_driver fimd_driver = {
1190 .probe = fimd_probe,
1191 .remove = fimd_remove,
1192 .driver = {
1193 .name = "exynos4-fb",
1194 .owner = THIS_MODULE,
1195 .pm = &exynos_fimd_pm_ops,
1196 .of_match_table = fimd_driver_dt_match,
1197 },
1198};