1/*
 2 * Copyright (C) 2012 Russell King
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 *
 8 * Armada 510 (aka Dove) variant support
 9 */
10#include <linux/clk.h>
11#include <linux/io.h>
12#include <drm/drm_crtc_helper.h>
13#include "armada_crtc.h"
14#include "armada_drm.h"
15#include "armada_hw.h"
16
17static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
18{
19	struct clk *clk;
20
21	clk = devm_clk_get(dev, "ext_ref_clk1");
22	if (IS_ERR(clk))
23		return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk);
24
25	dcrtc->extclk[0] = clk;
26
27	/* Lower the watermark so to eliminate jitter at higher bandwidths */
28	armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
29
30	return 0;
31}
32
33/*
34 * Armada510 specific SCLK register selection.
35 * This gets called with sclk = NULL to test whether the mode is
36 * supportable, and again with sclk != NULL to set the clocks up for
37 * that.  The former can return an error, but the latter is expected
38 * not to.
39 *
40 * We currently are pretty rudimentary here, always selecting
41 * EXT_REF_CLK_1 for LCD0 and erroring LCD1.  This needs improvement!
42 */
43static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
44	const struct drm_display_mode *mode, uint32_t *sclk)
45{
46	struct clk *clk = dcrtc->extclk[0];
47	int ret;
48
49	if (dcrtc->num == 1)
50		return -EINVAL;
51
52	if (IS_ERR(clk))
53		return PTR_ERR(clk);
54
55	if (dcrtc->clk != clk) {
56		ret = clk_prepare_enable(clk);
57		if (ret)
58			return ret;
59		dcrtc->clk = clk;
60	}
61
62	if (sclk) {
63		uint32_t rate, ref, div;
64
65		rate = mode->clock * 1000;
66		ref = clk_round_rate(clk, rate);
67		div = DIV_ROUND_UP(ref, rate);
68		if (div < 1)
69			div = 1;
70
71		clk_set_rate(clk, ref);
72		*sclk = div | SCLK_510_EXTCLK1;
73	}
74
75	return 0;
76}
77
78const struct armada_variant armada510_ops = {
79	.has_spu_adv_reg = true,
80	.spu_adv_reg = ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
81	.init = armada510_crtc_init,
82	.compute_clock = armada510_crtc_compute_clock,
83};