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1/*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/ioport.h>
23#include <linux/irq.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/spinlock.h>
31#include <linux/slab.h>
32
33struct gpio_rcar_bank_info {
34 u32 iointsel;
35 u32 inoutsel;
36 u32 outdt;
37 u32 posneg;
38 u32 edglevel;
39 u32 bothedge;
40 u32 intmsk;
41};
42
43struct gpio_rcar_priv {
44 void __iomem *base;
45 spinlock_t lock;
46 struct platform_device *pdev;
47 struct gpio_chip gpio_chip;
48 struct irq_chip irq_chip;
49 unsigned int irq_parent;
50 atomic_t wakeup_path;
51 bool has_both_edge_trigger;
52 struct gpio_rcar_bank_info bank_info;
53};
54
55#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
56#define INOUTSEL 0x04 /* General Input/Output Switching Register */
57#define OUTDT 0x08 /* General Output Register */
58#define INDT 0x0c /* General Input Register */
59#define INTDT 0x10 /* Interrupt Display Register */
60#define INTCLR 0x14 /* Interrupt Clear Register */
61#define INTMSK 0x18 /* Interrupt Mask Register */
62#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
63#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
64#define EDGLEVEL 0x24 /* Edge/level Select Register */
65#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
66#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
67
68#define RCAR_MAX_GPIO_PER_BANK 32
69
70static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
71{
72 return ioread32(p->base + offs);
73}
74
75static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
76 u32 value)
77{
78 iowrite32(value, p->base + offs);
79}
80
81static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
82 int bit, bool value)
83{
84 u32 tmp = gpio_rcar_read(p, offs);
85
86 if (value)
87 tmp |= BIT(bit);
88 else
89 tmp &= ~BIT(bit);
90
91 gpio_rcar_write(p, offs, tmp);
92}
93
94static void gpio_rcar_irq_disable(struct irq_data *d)
95{
96 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
97 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
98
99 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
100}
101
102static void gpio_rcar_irq_enable(struct irq_data *d)
103{
104 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
105 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
106
107 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
108}
109
110static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
111 unsigned int hwirq,
112 bool active_high_rising_edge,
113 bool level_trigger,
114 bool both)
115{
116 unsigned long flags;
117
118 /* follow steps in the GPIO documentation for
119 * "Setting Edge-Sensitive Interrupt Input Mode" and
120 * "Setting Level-Sensitive Interrupt Input Mode"
121 */
122
123 spin_lock_irqsave(&p->lock, flags);
124
125 /* Configure postive or negative logic in POSNEG */
126 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
127
128 /* Configure edge or level trigger in EDGLEVEL */
129 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
130
131 /* Select one edge or both edges in BOTHEDGE */
132 if (p->has_both_edge_trigger)
133 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
134
135 /* Select "Interrupt Input Mode" in IOINTSEL */
136 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
137
138 /* Write INTCLR in case of edge trigger */
139 if (!level_trigger)
140 gpio_rcar_write(p, INTCLR, BIT(hwirq));
141
142 spin_unlock_irqrestore(&p->lock, flags);
143}
144
145static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
146{
147 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
148 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
149 unsigned int hwirq = irqd_to_hwirq(d);
150
151 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
152
153 switch (type & IRQ_TYPE_SENSE_MASK) {
154 case IRQ_TYPE_LEVEL_HIGH:
155 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
156 false);
157 break;
158 case IRQ_TYPE_LEVEL_LOW:
159 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
160 false);
161 break;
162 case IRQ_TYPE_EDGE_RISING:
163 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
164 false);
165 break;
166 case IRQ_TYPE_EDGE_FALLING:
167 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
168 false);
169 break;
170 case IRQ_TYPE_EDGE_BOTH:
171 if (!p->has_both_edge_trigger)
172 return -EINVAL;
173 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
174 true);
175 break;
176 default:
177 return -EINVAL;
178 }
179 return 0;
180}
181
182static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
183{
184 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
185 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
186 int error;
187
188 if (p->irq_parent) {
189 error = irq_set_irq_wake(p->irq_parent, on);
190 if (error) {
191 dev_dbg(&p->pdev->dev,
192 "irq %u doesn't support irq_set_wake\n",
193 p->irq_parent);
194 p->irq_parent = 0;
195 }
196 }
197
198 if (on)
199 atomic_inc(&p->wakeup_path);
200 else
201 atomic_dec(&p->wakeup_path);
202
203 return 0;
204}
205
206static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
207{
208 struct gpio_rcar_priv *p = dev_id;
209 u32 pending;
210 unsigned int offset, irqs_handled = 0;
211
212 while ((pending = gpio_rcar_read(p, INTDT) &
213 gpio_rcar_read(p, INTMSK))) {
214 offset = __ffs(pending);
215 gpio_rcar_write(p, INTCLR, BIT(offset));
216 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
217 offset));
218 irqs_handled++;
219 }
220
221 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
222}
223
224static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
225 unsigned int gpio,
226 bool output)
227{
228 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
229 unsigned long flags;
230
231 /* follow steps in the GPIO documentation for
232 * "Setting General Output Mode" and
233 * "Setting General Input Mode"
234 */
235
236 spin_lock_irqsave(&p->lock, flags);
237
238 /* Configure postive logic in POSNEG */
239 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
240
241 /* Select "General Input/Output Mode" in IOINTSEL */
242 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
243
244 /* Select Input Mode or Output Mode in INOUTSEL */
245 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
246
247 spin_unlock_irqrestore(&p->lock, flags);
248}
249
250static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
251{
252 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
253 int error;
254
255 error = pm_runtime_get_sync(&p->pdev->dev);
256 if (error < 0)
257 return error;
258
259 error = pinctrl_gpio_request(chip->base + offset);
260 if (error)
261 pm_runtime_put(&p->pdev->dev);
262
263 return error;
264}
265
266static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
267{
268 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
269
270 pinctrl_gpio_free(chip->base + offset);
271
272 /*
273 * Set the GPIO as an input to ensure that the next GPIO request won't
274 * drive the GPIO pin as an output.
275 */
276 gpio_rcar_config_general_input_output_mode(chip, offset, false);
277
278 pm_runtime_put(&p->pdev->dev);
279}
280
281static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
282{
283 gpio_rcar_config_general_input_output_mode(chip, offset, false);
284 return 0;
285}
286
287static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
288{
289 u32 bit = BIT(offset);
290
291 /* testing on r8a7790 shows that INDT does not show correct pin state
292 * when configured as output, so use OUTDT in case of output pins */
293 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
294 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
295 else
296 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
297}
298
299static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
300{
301 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
302 unsigned long flags;
303
304 spin_lock_irqsave(&p->lock, flags);
305 gpio_rcar_modify_bit(p, OUTDT, offset, value);
306 spin_unlock_irqrestore(&p->lock, flags);
307}
308
309static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
310 unsigned long *bits)
311{
312 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
313 unsigned long flags;
314 u32 val, bankmask;
315
316 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
317 if (!bankmask)
318 return;
319
320 spin_lock_irqsave(&p->lock, flags);
321 val = gpio_rcar_read(p, OUTDT);
322 val &= ~bankmask;
323 val |= (bankmask & bits[0]);
324 gpio_rcar_write(p, OUTDT, val);
325 spin_unlock_irqrestore(&p->lock, flags);
326}
327
328static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
329 int value)
330{
331 /* write GPIO value to output before selecting output mode of pin */
332 gpio_rcar_set(chip, offset, value);
333 gpio_rcar_config_general_input_output_mode(chip, offset, true);
334 return 0;
335}
336
337struct gpio_rcar_info {
338 bool has_both_edge_trigger;
339};
340
341static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
342 .has_both_edge_trigger = false,
343};
344
345static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
346 .has_both_edge_trigger = true,
347};
348
349static const struct of_device_id gpio_rcar_of_table[] = {
350 {
351 .compatible = "renesas,gpio-r8a7743",
352 /* RZ/G1 GPIO is identical to R-Car Gen2. */
353 .data = &gpio_rcar_info_gen2,
354 }, {
355 .compatible = "renesas,gpio-r8a7790",
356 .data = &gpio_rcar_info_gen2,
357 }, {
358 .compatible = "renesas,gpio-r8a7791",
359 .data = &gpio_rcar_info_gen2,
360 }, {
361 .compatible = "renesas,gpio-r8a7792",
362 .data = &gpio_rcar_info_gen2,
363 }, {
364 .compatible = "renesas,gpio-r8a7793",
365 .data = &gpio_rcar_info_gen2,
366 }, {
367 .compatible = "renesas,gpio-r8a7794",
368 .data = &gpio_rcar_info_gen2,
369 }, {
370 .compatible = "renesas,gpio-r8a7795",
371 /* Gen3 GPIO is identical to Gen2. */
372 .data = &gpio_rcar_info_gen2,
373 }, {
374 .compatible = "renesas,gpio-r8a7796",
375 /* Gen3 GPIO is identical to Gen2. */
376 .data = &gpio_rcar_info_gen2,
377 }, {
378 .compatible = "renesas,rcar-gen1-gpio",
379 .data = &gpio_rcar_info_gen1,
380 }, {
381 .compatible = "renesas,rcar-gen2-gpio",
382 .data = &gpio_rcar_info_gen2,
383 }, {
384 .compatible = "renesas,rcar-gen3-gpio",
385 /* Gen3 GPIO is identical to Gen2. */
386 .data = &gpio_rcar_info_gen2,
387 }, {
388 .compatible = "renesas,gpio-rcar",
389 .data = &gpio_rcar_info_gen1,
390 }, {
391 /* Terminator */
392 },
393};
394
395MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
396
397static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
398{
399 struct device_node *np = p->pdev->dev.of_node;
400 const struct gpio_rcar_info *info;
401 struct of_phandle_args args;
402 int ret;
403
404 info = of_device_get_match_data(&p->pdev->dev);
405
406 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
407 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
408 p->has_both_edge_trigger = info->has_both_edge_trigger;
409
410 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
411 dev_warn(&p->pdev->dev,
412 "Invalid number of gpio lines %u, using %u\n", *npins,
413 RCAR_MAX_GPIO_PER_BANK);
414 *npins = RCAR_MAX_GPIO_PER_BANK;
415 }
416
417 return 0;
418}
419
420static int gpio_rcar_probe(struct platform_device *pdev)
421{
422 struct gpio_rcar_priv *p;
423 struct resource *io, *irq;
424 struct gpio_chip *gpio_chip;
425 struct irq_chip *irq_chip;
426 struct device *dev = &pdev->dev;
427 const char *name = dev_name(dev);
428 unsigned int npins;
429 int ret;
430
431 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
432 if (!p)
433 return -ENOMEM;
434
435 p->pdev = pdev;
436 spin_lock_init(&p->lock);
437
438 /* Get device configuration from DT node */
439 ret = gpio_rcar_parse_dt(p, &npins);
440 if (ret < 0)
441 return ret;
442
443 platform_set_drvdata(pdev, p);
444
445 pm_runtime_enable(dev);
446
447 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
448 if (!irq) {
449 dev_err(dev, "missing IRQ\n");
450 ret = -EINVAL;
451 goto err0;
452 }
453
454 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
455 p->base = devm_ioremap_resource(dev, io);
456 if (IS_ERR(p->base)) {
457 ret = PTR_ERR(p->base);
458 goto err0;
459 }
460
461 gpio_chip = &p->gpio_chip;
462 gpio_chip->request = gpio_rcar_request;
463 gpio_chip->free = gpio_rcar_free;
464 gpio_chip->direction_input = gpio_rcar_direction_input;
465 gpio_chip->get = gpio_rcar_get;
466 gpio_chip->direction_output = gpio_rcar_direction_output;
467 gpio_chip->set = gpio_rcar_set;
468 gpio_chip->set_multiple = gpio_rcar_set_multiple;
469 gpio_chip->label = name;
470 gpio_chip->parent = dev;
471 gpio_chip->owner = THIS_MODULE;
472 gpio_chip->base = -1;
473 gpio_chip->ngpio = npins;
474
475 irq_chip = &p->irq_chip;
476 irq_chip->name = name;
477 irq_chip->parent_device = dev;
478 irq_chip->irq_mask = gpio_rcar_irq_disable;
479 irq_chip->irq_unmask = gpio_rcar_irq_enable;
480 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
481 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
482 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
483
484 ret = gpiochip_add_data(gpio_chip, p);
485 if (ret) {
486 dev_err(dev, "failed to add GPIO controller\n");
487 goto err0;
488 }
489
490 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
491 IRQ_TYPE_NONE);
492 if (ret) {
493 dev_err(dev, "cannot add irqchip\n");
494 goto err1;
495 }
496
497 p->irq_parent = irq->start;
498 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
499 IRQF_SHARED, name, p)) {
500 dev_err(dev, "failed to request IRQ\n");
501 ret = -ENOENT;
502 goto err1;
503 }
504
505 dev_info(dev, "driving %d GPIOs\n", npins);
506
507 return 0;
508
509err1:
510 gpiochip_remove(gpio_chip);
511err0:
512 pm_runtime_disable(dev);
513 return ret;
514}
515
516static int gpio_rcar_remove(struct platform_device *pdev)
517{
518 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
519
520 gpiochip_remove(&p->gpio_chip);
521
522 pm_runtime_disable(&pdev->dev);
523 return 0;
524}
525
526#ifdef CONFIG_PM_SLEEP
527static int gpio_rcar_suspend(struct device *dev)
528{
529 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
530
531 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
532 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
533 p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
534 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
535 p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
536 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
537 if (p->has_both_edge_trigger)
538 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
539
540 if (atomic_read(&p->wakeup_path))
541 device_set_wakeup_path(dev);
542
543 return 0;
544}
545
546static int gpio_rcar_resume(struct device *dev)
547{
548 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
549 unsigned int offset;
550 u32 mask;
551
552 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
553 mask = BIT(offset);
554 /* I/O pin */
555 if (!(p->bank_info.iointsel & mask)) {
556 if (p->bank_info.inoutsel & mask)
557 gpio_rcar_direction_output(
558 &p->gpio_chip, offset,
559 !!(p->bank_info.outdt & mask));
560 else
561 gpio_rcar_direction_input(&p->gpio_chip,
562 offset);
563 } else {
564 /* Interrupt pin */
565 gpio_rcar_config_interrupt_input_mode(
566 p,
567 offset,
568 !(p->bank_info.posneg & mask),
569 !(p->bank_info.edglevel & mask),
570 !!(p->bank_info.bothedge & mask));
571
572 if (p->bank_info.intmsk & mask)
573 gpio_rcar_write(p, MSKCLR, mask);
574 }
575 }
576
577 return 0;
578}
579#endif /* CONFIG_PM_SLEEP*/
580
581static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
582
583static struct platform_driver gpio_rcar_device_driver = {
584 .probe = gpio_rcar_probe,
585 .remove = gpio_rcar_remove,
586 .driver = {
587 .name = "gpio_rcar",
588 .pm = &gpio_rcar_pm_ops,
589 .of_match_table = of_match_ptr(gpio_rcar_of_table),
590 }
591};
592
593module_platform_driver(gpio_rcar_device_driver);
594
595MODULE_AUTHOR("Magnus Damm");
596MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
597MODULE_LICENSE("GPL v2");