1/*
  2 * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
  3 *
  4 * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
  5 *
  6 * This program is free software; you can redistribute it and/or
  7 * modify it under the terms of the GNU General Public License version
  8 * 2 as published by the Free Software Foundation.
  9 *
 10 * This program is distributed in the hope that it will be useful,
 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13 * GNU General Public License for more details.
 14 *
 15 * Author: Yang, Bin <bin.yang@intel.com>
 16 */
 17
 18#include <linux/interrupt.h>
 19#include <linux/module.h>
 20#include <linux/platform_device.h>
 21#include <linux/gpio/driver.h>
 22#include <linux/seq_file.h>
 23#include <linux/bitops.h>
 24#include <linux/regmap.h>
 25#include <linux/mfd/intel_soc_pmic.h>
 26
 27#define CRYSTALCOVE_GPIO_NUM	16
 28#define CRYSTALCOVE_VGPIO_NUM	95
 29
 30#define UPDATE_IRQ_TYPE		BIT(0)
 31#define UPDATE_IRQ_MASK		BIT(1)
 32
 33#define GPIO0IRQ		0x0b
 34#define GPIO1IRQ		0x0c
 35#define MGPIO0IRQS0		0x19
 36#define MGPIO1IRQS0		0x1a
 37#define MGPIO0IRQSX		0x1b
 38#define MGPIO1IRQSX		0x1c
 39#define GPIO0P0CTLO		0x2b
 40#define GPIO0P0CTLI		0x33
 41#define GPIO1P0CTLO		0x3b
 42#define GPIO1P0CTLI		0x43
 43#define GPIOPANELCTL		0x52
 44
 45#define CTLI_INTCNT_DIS		(0)
 46#define CTLI_INTCNT_NE		(1 << 1)
 47#define CTLI_INTCNT_PE		(2 << 1)
 48#define CTLI_INTCNT_BE		(3 << 1)
 49
 50#define CTLO_DIR_IN		(0)
 51#define CTLO_DIR_OUT		(1 << 5)
 52
 53#define CTLO_DRV_CMOS		(0)
 54#define CTLO_DRV_OD		(1 << 4)
 55
 56#define CTLO_DRV_REN		(1 << 3)
 57
 58#define CTLO_RVAL_2KDW		(0)
 59#define CTLO_RVAL_2KUP		(1 << 1)
 60#define CTLO_RVAL_50KDW		(2 << 1)
 61#define CTLO_RVAL_50KUP		(3 << 1)
 62
 63#define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
 64#define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)
 65
 66enum ctrl_register {
 67	CTRL_IN,
 68	CTRL_OUT,
 69};
 70
 71/**
 72 * struct crystalcove_gpio - Crystal Cove GPIO controller
 73 * @buslock: for bus lock/sync and unlock.
 74 * @chip: the abstract gpio_chip structure.
 75 * @regmap: the regmap from the parent device.
 76 * @update: pending IRQ setting update, to be written to the chip upon unlock.
 77 * @intcnt_value: the Interrupt Detect value to be written.
 78 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
 79 */
 80struct crystalcove_gpio {
 81	struct mutex buslock; /* irq_bus_lock */
 82	struct gpio_chip chip;
 83	struct regmap *regmap;
 84	int update;
 85	int intcnt_value;
 86	bool set_irq_mask;
 87};
 88
 89static inline int to_reg(int gpio, enum ctrl_register reg_type)
 90{
 91	int reg;
 92
 93	if (gpio >= CRYSTALCOVE_GPIO_NUM) {
 94		/*
 95		 * Virtual GPIO called from ACPI, for now we only support
 96		 * the panel ctl.
 97		 */
 98		switch (gpio) {
 99		case 0x5e:
100			return GPIOPANELCTL;
101		default:
102			return -EOPNOTSUPP;
103		}
104	}
105
106	if (reg_type == CTRL_IN) {
107		if (gpio < 8)
108			reg = GPIO0P0CTLI;
109		else
110			reg = GPIO1P0CTLI;
111	} else {
112		if (gpio < 8)
113			reg = GPIO0P0CTLO;
114		else
115			reg = GPIO1P0CTLO;
116	}
117
118	return reg + gpio % 8;
119}
120
121static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
122					int gpio)
123{
124	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
125	int mask = BIT(gpio % 8);
126
127	if (cg->set_irq_mask)
128		regmap_update_bits(cg->regmap, mirqs0, mask, mask);
129	else
130		regmap_update_bits(cg->regmap, mirqs0, mask, 0);
131}
132
133static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
134{
135	int reg = to_reg(gpio, CTRL_IN);
136
137	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
138}
139
140static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
141{
142	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
143	int reg = to_reg(gpio, CTRL_OUT);
144
145	if (reg < 0)
146		return 0;
147
148	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
149}
150
151static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
152				    int value)
153{
154	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
155	int reg = to_reg(gpio, CTRL_OUT);
156
157	if (reg < 0)
158		return 0;
159
160	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
161}
162
163static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
164{
165	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
166	unsigned int val;
167	int ret, reg = to_reg(gpio, CTRL_IN);
168
169	if (reg < 0)
170		return 0;
171
172	ret = regmap_read(cg->regmap, reg, &val);
173	if (ret)
174		return ret;
175
176	return val & 0x1;
177}
178
179static void crystalcove_gpio_set(struct gpio_chip *chip,
180				 unsigned gpio, int value)
181{
182	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
183	int reg = to_reg(gpio, CTRL_OUT);
184
185	if (reg < 0)
186		return;
187
188	if (value)
189		regmap_update_bits(cg->regmap, reg, 1, 1);
190	else
191		regmap_update_bits(cg->regmap, reg, 1, 0);
192}
193
194static int crystalcove_irq_type(struct irq_data *data, unsigned type)
195{
196	struct crystalcove_gpio *cg =
197		gpiochip_get_data(irq_data_get_irq_chip_data(data));
198
199	if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)
200		return 0;
201
202	switch (type) {
203	case IRQ_TYPE_NONE:
204		cg->intcnt_value = CTLI_INTCNT_DIS;
205		break;
206	case IRQ_TYPE_EDGE_BOTH:
207		cg->intcnt_value = CTLI_INTCNT_BE;
208		break;
209	case IRQ_TYPE_EDGE_RISING:
210		cg->intcnt_value = CTLI_INTCNT_PE;
211		break;
212	case IRQ_TYPE_EDGE_FALLING:
213		cg->intcnt_value = CTLI_INTCNT_NE;
214		break;
215	default:
216		return -EINVAL;
217	}
218
219	cg->update |= UPDATE_IRQ_TYPE;
220
221	return 0;
222}
223
224static void crystalcove_bus_lock(struct irq_data *data)
225{
226	struct crystalcove_gpio *cg =
227		gpiochip_get_data(irq_data_get_irq_chip_data(data));
228
229	mutex_lock(&cg->buslock);
230}
231
232static void crystalcove_bus_sync_unlock(struct irq_data *data)
233{
234	struct crystalcove_gpio *cg =
235		gpiochip_get_data(irq_data_get_irq_chip_data(data));
236	int gpio = data->hwirq;
237
238	if (cg->update & UPDATE_IRQ_TYPE)
239		crystalcove_update_irq_ctrl(cg, gpio);
240	if (cg->update & UPDATE_IRQ_MASK)
241		crystalcove_update_irq_mask(cg, gpio);
242	cg->update = 0;
243
244	mutex_unlock(&cg->buslock);
245}
246
247static void crystalcove_irq_unmask(struct irq_data *data)
248{
249	struct crystalcove_gpio *cg =
250		gpiochip_get_data(irq_data_get_irq_chip_data(data));
251
252	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
253		cg->set_irq_mask = false;
254		cg->update |= UPDATE_IRQ_MASK;
255	}
256}
257
258static void crystalcove_irq_mask(struct irq_data *data)
259{
260	struct crystalcove_gpio *cg =
261		gpiochip_get_data(irq_data_get_irq_chip_data(data));
262
263	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
264		cg->set_irq_mask = true;
265		cg->update |= UPDATE_IRQ_MASK;
266	}
267}
268
269static struct irq_chip crystalcove_irqchip = {
270	.name			= "Crystal Cove",
271	.irq_mask		= crystalcove_irq_mask,
272	.irq_unmask		= crystalcove_irq_unmask,
273	.irq_set_type		= crystalcove_irq_type,
274	.irq_bus_lock		= crystalcove_bus_lock,
275	.irq_bus_sync_unlock	= crystalcove_bus_sync_unlock,
276	.flags			= IRQCHIP_SKIP_SET_WAKE,
277};
278
279static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
280{
281	struct crystalcove_gpio *cg = data;
282	unsigned int p0, p1;
283	int pending;
284	int gpio;
285	unsigned int virq;
286
287	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
288	    regmap_read(cg->regmap, GPIO1IRQ, &p1))
289		return IRQ_NONE;
290
291	regmap_write(cg->regmap, GPIO0IRQ, p0);
292	regmap_write(cg->regmap, GPIO1IRQ, p1);
293
294	pending = p0 | p1 << 8;
295
296	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
297		if (pending & BIT(gpio)) {
298			virq = irq_find_mapping(cg->chip.irq.domain, gpio);
299			handle_nested_irq(virq);
300		}
301	}
302
303	return IRQ_HANDLED;
304}
305
306static void crystalcove_gpio_dbg_show(struct seq_file *s,
307				      struct gpio_chip *chip)
308{
309	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
310	int gpio, offset;
311	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
312
313	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
314		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
315		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
316		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
317			    &mirqs0);
318		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
319			    &mirqsx);
320		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
321			    &irq);
322
323		offset = gpio % 8;
324		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
325			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
326			   ctli & 0x1 ? "hi" : "lo",
327			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
328			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
329			   ctlo,
330			   mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
331			   mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
332			   irq & BIT(offset) ? "pending" : "       ");
333	}
334}
335
336static int crystalcove_gpio_probe(struct platform_device *pdev)
337{
338	int irq = platform_get_irq(pdev, 0);
339	struct crystalcove_gpio *cg;
340	int retval;
341	struct device *dev = pdev->dev.parent;
342	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
343
344	if (irq < 0)
345		return irq;
346
347	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
348	if (!cg)
349		return -ENOMEM;
350
351	platform_set_drvdata(pdev, cg);
352
353	mutex_init(&cg->buslock);
354	cg->chip.label = KBUILD_MODNAME;
355	cg->chip.direction_input = crystalcove_gpio_dir_in;
356	cg->chip.direction_output = crystalcove_gpio_dir_out;
357	cg->chip.get = crystalcove_gpio_get;
358	cg->chip.set = crystalcove_gpio_set;
359	cg->chip.base = -1;
360	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
361	cg->chip.can_sleep = true;
362	cg->chip.parent = dev;
363	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
364	cg->regmap = pmic->regmap;
365
366	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
367	if (retval) {
368		dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
369		return retval;
370	}
371
372	gpiochip_irqchip_add_nested(&cg->chip, &crystalcove_irqchip, 0,
373				    handle_simple_irq, IRQ_TYPE_NONE);
374
375	retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
376				      IRQF_ONESHOT, KBUILD_MODNAME, cg);
377
378	if (retval) {
379		dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
380		return retval;
381	}
382
383	gpiochip_set_nested_irqchip(&cg->chip, &crystalcove_irqchip, irq);
384
385	return 0;
386}
387
388static int crystalcove_gpio_remove(struct platform_device *pdev)
389{
390	struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
391	int irq = platform_get_irq(pdev, 0);
392
393	if (irq >= 0)
394		free_irq(irq, cg);
395	return 0;
396}
397
398static struct platform_driver crystalcove_gpio_driver = {
399	.probe = crystalcove_gpio_probe,
400	.remove = crystalcove_gpio_remove,
401	.driver = {
402		.name = "crystal_cove_gpio",
403	},
404};
405
406module_platform_driver(crystalcove_gpio_driver);
407
408MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
409MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
410MODULE_LICENSE("GPL v2");