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1/*
2 * Atheros AR71XX/AR724X/AR913X GPIO API support
3 *
4 * Copyright (C) 2015 Alban Bedel <albeu@free.fr>
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/gpio/driver.h>
15#include <linux/platform_data/gpio-ath79.h>
16#include <linux/of_device.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/irq.h>
20
21#define AR71XX_GPIO_REG_OE 0x00
22#define AR71XX_GPIO_REG_IN 0x04
23#define AR71XX_GPIO_REG_SET 0x0c
24#define AR71XX_GPIO_REG_CLEAR 0x10
25
26#define AR71XX_GPIO_REG_INT_ENABLE 0x14
27#define AR71XX_GPIO_REG_INT_TYPE 0x18
28#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
29#define AR71XX_GPIO_REG_INT_PENDING 0x20
30#define AR71XX_GPIO_REG_INT_MASK 0x24
31
32struct ath79_gpio_ctrl {
33 struct gpio_chip gc;
34 void __iomem *base;
35 raw_spinlock_t lock;
36 unsigned long both_edges;
37};
38
39static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
40{
41 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
42
43 return container_of(gc, struct ath79_gpio_ctrl, gc);
44}
45
46static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
47{
48 return readl(ctrl->base + reg);
49}
50
51static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
52 unsigned reg, u32 val)
53{
54 return writel(val, ctrl->base + reg);
55}
56
57static bool ath79_gpio_update_bits(
58 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
59{
60 u32 old_val, new_val;
61
62 old_val = ath79_gpio_read(ctrl, reg);
63 new_val = (old_val & ~mask) | (bits & mask);
64
65 if (new_val != old_val)
66 ath79_gpio_write(ctrl, reg, new_val);
67
68 return new_val != old_val;
69}
70
71static void ath79_gpio_irq_unmask(struct irq_data *data)
72{
73 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
74 u32 mask = BIT(irqd_to_hwirq(data));
75 unsigned long flags;
76
77 raw_spin_lock_irqsave(&ctrl->lock, flags);
78 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
79 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
80}
81
82static void ath79_gpio_irq_mask(struct irq_data *data)
83{
84 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
85 u32 mask = BIT(irqd_to_hwirq(data));
86 unsigned long flags;
87
88 raw_spin_lock_irqsave(&ctrl->lock, flags);
89 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
90 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
91}
92
93static void ath79_gpio_irq_enable(struct irq_data *data)
94{
95 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
96 u32 mask = BIT(irqd_to_hwirq(data));
97 unsigned long flags;
98
99 raw_spin_lock_irqsave(&ctrl->lock, flags);
100 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
101 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
102 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
103}
104
105static void ath79_gpio_irq_disable(struct irq_data *data)
106{
107 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
108 u32 mask = BIT(irqd_to_hwirq(data));
109 unsigned long flags;
110
111 raw_spin_lock_irqsave(&ctrl->lock, flags);
112 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
113 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
114 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
115}
116
117static int ath79_gpio_irq_set_type(struct irq_data *data,
118 unsigned int flow_type)
119{
120 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
121 u32 mask = BIT(irqd_to_hwirq(data));
122 u32 type = 0, polarity = 0;
123 unsigned long flags;
124 bool disabled;
125
126 switch (flow_type) {
127 case IRQ_TYPE_EDGE_RISING:
128 polarity |= mask;
129 case IRQ_TYPE_EDGE_FALLING:
130 case IRQ_TYPE_EDGE_BOTH:
131 break;
132
133 case IRQ_TYPE_LEVEL_HIGH:
134 polarity |= mask;
135 /* fall through */
136 case IRQ_TYPE_LEVEL_LOW:
137 type |= mask;
138 break;
139
140 default:
141 return -EINVAL;
142 }
143
144 raw_spin_lock_irqsave(&ctrl->lock, flags);
145
146 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
147 ctrl->both_edges |= mask;
148 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
149 } else {
150 ctrl->both_edges &= ~mask;
151 }
152
153 /* As the IRQ configuration can't be loaded atomically we
154 * have to disable the interrupt while the configuration state
155 * is invalid.
156 */
157 disabled = ath79_gpio_update_bits(
158 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
159
160 ath79_gpio_update_bits(
161 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
162 ath79_gpio_update_bits(
163 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
164
165 if (disabled)
166 ath79_gpio_update_bits(
167 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
168
169 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
170
171 return 0;
172}
173
174static struct irq_chip ath79_gpio_irqchip = {
175 .name = "gpio-ath79",
176 .irq_enable = ath79_gpio_irq_enable,
177 .irq_disable = ath79_gpio_irq_disable,
178 .irq_mask = ath79_gpio_irq_mask,
179 .irq_unmask = ath79_gpio_irq_unmask,
180 .irq_set_type = ath79_gpio_irq_set_type,
181};
182
183static void ath79_gpio_irq_handler(struct irq_desc *desc)
184{
185 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
186 struct irq_chip *irqchip = irq_desc_get_chip(desc);
187 struct ath79_gpio_ctrl *ctrl =
188 container_of(gc, struct ath79_gpio_ctrl, gc);
189 unsigned long flags, pending;
190 u32 both_edges, state;
191 int irq;
192
193 chained_irq_enter(irqchip, desc);
194
195 raw_spin_lock_irqsave(&ctrl->lock, flags);
196
197 pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
198
199 /* Update the polarity of the both edges irqs */
200 both_edges = ctrl->both_edges & pending;
201 if (both_edges) {
202 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
203 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
204 both_edges, ~state);
205 }
206
207 raw_spin_unlock_irqrestore(&ctrl->lock, flags);
208
209 if (pending) {
210 for_each_set_bit(irq, &pending, gc->ngpio)
211 generic_handle_irq(
212 irq_linear_revmap(gc->irq.domain, irq));
213 }
214
215 chained_irq_exit(irqchip, desc);
216}
217
218static const struct of_device_id ath79_gpio_of_match[] = {
219 { .compatible = "qca,ar7100-gpio" },
220 { .compatible = "qca,ar9340-gpio" },
221 {},
222};
223MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
224
225static int ath79_gpio_probe(struct platform_device *pdev)
226{
227 struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
228 struct device_node *np = pdev->dev.of_node;
229 struct ath79_gpio_ctrl *ctrl;
230 struct resource *res;
231 u32 ath79_gpio_count;
232 bool oe_inverted;
233 int err;
234
235 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
236 if (!ctrl)
237 return -ENOMEM;
238 platform_set_drvdata(pdev, ctrl);
239
240 if (np) {
241 err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
242 if (err) {
243 dev_err(&pdev->dev, "ngpios property is not valid\n");
244 return err;
245 }
246 oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
247 } else if (pdata) {
248 ath79_gpio_count = pdata->ngpios;
249 oe_inverted = pdata->oe_inverted;
250 } else {
251 dev_err(&pdev->dev, "No DT node or platform data found\n");
252 return -EINVAL;
253 }
254
255 if (ath79_gpio_count >= 32) {
256 dev_err(&pdev->dev, "ngpios must be less than 32\n");
257 return -EINVAL;
258 }
259
260 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
261 if (!res)
262 return -EINVAL;
263 ctrl->base = devm_ioremap_nocache(
264 &pdev->dev, res->start, resource_size(res));
265 if (!ctrl->base)
266 return -ENOMEM;
267
268 raw_spin_lock_init(&ctrl->lock);
269 err = bgpio_init(&ctrl->gc, &pdev->dev, 4,
270 ctrl->base + AR71XX_GPIO_REG_IN,
271 ctrl->base + AR71XX_GPIO_REG_SET,
272 ctrl->base + AR71XX_GPIO_REG_CLEAR,
273 oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
274 oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
275 0);
276 if (err) {
277 dev_err(&pdev->dev, "bgpio_init failed\n");
278 return err;
279 }
280 /* Use base 0 to stay compatible with legacy platforms */
281 ctrl->gc.base = 0;
282
283 err = gpiochip_add_data(&ctrl->gc, ctrl);
284 if (err) {
285 dev_err(&pdev->dev,
286 "cannot add AR71xx GPIO chip, error=%d", err);
287 return err;
288 }
289
290 if (np && !of_property_read_bool(np, "interrupt-controller"))
291 return 0;
292
293 err = gpiochip_irqchip_add(&ctrl->gc, &ath79_gpio_irqchip, 0,
294 handle_simple_irq, IRQ_TYPE_NONE);
295 if (err) {
296 dev_err(&pdev->dev, "failed to add gpiochip_irqchip\n");
297 goto gpiochip_remove;
298 }
299
300 gpiochip_set_chained_irqchip(&ctrl->gc, &ath79_gpio_irqchip,
301 platform_get_irq(pdev, 0),
302 ath79_gpio_irq_handler);
303
304 return 0;
305
306gpiochip_remove:
307 gpiochip_remove(&ctrl->gc);
308 return err;
309}
310
311static int ath79_gpio_remove(struct platform_device *pdev)
312{
313 struct ath79_gpio_ctrl *ctrl = platform_get_drvdata(pdev);
314
315 gpiochip_remove(&ctrl->gc);
316 return 0;
317}
318
319static struct platform_driver ath79_gpio_driver = {
320 .driver = {
321 .name = "ath79-gpio",
322 .of_match_table = ath79_gpio_of_match,
323 },
324 .probe = ath79_gpio_probe,
325 .remove = ath79_gpio_remove,
326};
327
328module_platform_driver(ath79_gpio_driver);
329
330MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
331MODULE_LICENSE("GPL v2");