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1/*
2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
3 * Author: Lin Huang <hl@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/arm-smccc.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/devfreq.h>
19#include <linux/devfreq-event.h>
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pm_opp.h>
25#include <linux/regulator/consumer.h>
26#include <linux/rwsem.h>
27#include <linux/suspend.h>
28
29#include <soc/rockchip/rockchip_sip.h>
30
31struct dram_timing {
32 unsigned int ddr3_speed_bin;
33 unsigned int pd_idle;
34 unsigned int sr_idle;
35 unsigned int sr_mc_gate_idle;
36 unsigned int srpd_lite_idle;
37 unsigned int standby_idle;
38 unsigned int auto_pd_dis_freq;
39 unsigned int dram_dll_dis_freq;
40 unsigned int phy_dll_dis_freq;
41 unsigned int ddr3_odt_dis_freq;
42 unsigned int ddr3_drv;
43 unsigned int ddr3_odt;
44 unsigned int phy_ddr3_ca_drv;
45 unsigned int phy_ddr3_dq_drv;
46 unsigned int phy_ddr3_odt;
47 unsigned int lpddr3_odt_dis_freq;
48 unsigned int lpddr3_drv;
49 unsigned int lpddr3_odt;
50 unsigned int phy_lpddr3_ca_drv;
51 unsigned int phy_lpddr3_dq_drv;
52 unsigned int phy_lpddr3_odt;
53 unsigned int lpddr4_odt_dis_freq;
54 unsigned int lpddr4_drv;
55 unsigned int lpddr4_dq_odt;
56 unsigned int lpddr4_ca_odt;
57 unsigned int phy_lpddr4_ca_drv;
58 unsigned int phy_lpddr4_ck_cs_drv;
59 unsigned int phy_lpddr4_dq_drv;
60 unsigned int phy_lpddr4_odt;
61};
62
63struct rk3399_dmcfreq {
64 struct device *dev;
65 struct devfreq *devfreq;
66 struct devfreq_simple_ondemand_data ondemand_data;
67 struct clk *dmc_clk;
68 struct devfreq_event_dev *edev;
69 struct mutex lock;
70 struct dram_timing timing;
71
72 /*
73 * DDR Converser of Frequency (DCF) is used to implement DDR frequency
74 * conversion without the participation of CPU, we will implement and
75 * control it in arm trust firmware.
76 */
77 wait_queue_head_t wait_dcf_queue;
78 int irq;
79 int wait_dcf_flag;
80 struct regulator *vdd_center;
81 unsigned long rate, target_rate;
82 unsigned long volt, target_volt;
83};
84
85static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
86 u32 flags)
87{
88 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
89 struct dev_pm_opp *opp;
90 unsigned long old_clk_rate = dmcfreq->rate;
91 unsigned long target_volt, target_rate;
92 int err;
93
94 opp = devfreq_recommended_opp(dev, freq, flags);
95 if (IS_ERR(opp))
96 return PTR_ERR(opp);
97
98 target_rate = dev_pm_opp_get_freq(opp);
99 target_volt = dev_pm_opp_get_voltage(opp);
100 dev_pm_opp_put(opp);
101
102 if (dmcfreq->rate == target_rate)
103 return 0;
104
105 mutex_lock(&dmcfreq->lock);
106
107 /*
108 * If frequency scaling from low to high, adjust voltage first.
109 * If frequency scaling from high to low, adjust frequency first.
110 */
111 if (old_clk_rate < target_rate) {
112 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
113 target_volt);
114 if (err) {
115 dev_err(dev, "Cannot to set voltage %lu uV\n",
116 target_volt);
117 goto out;
118 }
119 }
120 dmcfreq->wait_dcf_flag = 1;
121
122 err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
123 if (err) {
124 dev_err(dev, "Cannot to set frequency %lu (%d)\n",
125 target_rate, err);
126 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
127 dmcfreq->volt);
128 goto out;
129 }
130
131 /*
132 * Wait until bcf irq happen, it means freq scaling finish in
133 * arm trust firmware, use 100ms as timeout time.
134 */
135 if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
136 !dmcfreq->wait_dcf_flag, HZ / 10))
137 dev_warn(dev, "Timeout waiting for dcf interrupt\n");
138
139 /*
140 * Check the dpll rate,
141 * There only two result we will get,
142 * 1. Ddr frequency scaling fail, we still get the old rate.
143 * 2. Ddr frequency scaling sucessful, we get the rate we set.
144 */
145 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
146
147 /* If get the incorrect rate, set voltage to old value. */
148 if (dmcfreq->rate != target_rate) {
149 dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
150 Current frequency %lu\n", target_rate, dmcfreq->rate);
151 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
152 dmcfreq->volt);
153 goto out;
154 } else if (old_clk_rate > target_rate)
155 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
156 target_volt);
157 if (err)
158 dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
159
160 dmcfreq->rate = target_rate;
161 dmcfreq->volt = target_volt;
162
163out:
164 mutex_unlock(&dmcfreq->lock);
165 return err;
166}
167
168static int rk3399_dmcfreq_get_dev_status(struct device *dev,
169 struct devfreq_dev_status *stat)
170{
171 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
172 struct devfreq_event_data edata;
173 int ret = 0;
174
175 ret = devfreq_event_get_event(dmcfreq->edev, &edata);
176 if (ret < 0)
177 return ret;
178
179 stat->current_frequency = dmcfreq->rate;
180 stat->busy_time = edata.load_count;
181 stat->total_time = edata.total_count;
182
183 return ret;
184}
185
186static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
187{
188 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
189
190 *freq = dmcfreq->rate;
191
192 return 0;
193}
194
195static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
196 .polling_ms = 200,
197 .target = rk3399_dmcfreq_target,
198 .get_dev_status = rk3399_dmcfreq_get_dev_status,
199 .get_cur_freq = rk3399_dmcfreq_get_cur_freq,
200};
201
202static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
203{
204 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
205 int ret = 0;
206
207 ret = devfreq_event_disable_edev(dmcfreq->edev);
208 if (ret < 0) {
209 dev_err(dev, "failed to disable the devfreq-event devices\n");
210 return ret;
211 }
212
213 ret = devfreq_suspend_device(dmcfreq->devfreq);
214 if (ret < 0) {
215 dev_err(dev, "failed to suspend the devfreq devices\n");
216 return ret;
217 }
218
219 return 0;
220}
221
222static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
223{
224 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
225 int ret = 0;
226
227 ret = devfreq_event_enable_edev(dmcfreq->edev);
228 if (ret < 0) {
229 dev_err(dev, "failed to enable the devfreq-event devices\n");
230 return ret;
231 }
232
233 ret = devfreq_resume_device(dmcfreq->devfreq);
234 if (ret < 0) {
235 dev_err(dev, "failed to resume the devfreq devices\n");
236 return ret;
237 }
238 return ret;
239}
240
241static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
242 rk3399_dmcfreq_resume);
243
244static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
245{
246 struct rk3399_dmcfreq *dmcfreq = dev_id;
247 struct arm_smccc_res res;
248
249 dmcfreq->wait_dcf_flag = 0;
250 wake_up(&dmcfreq->wait_dcf_queue);
251
252 /* Clear the DCF interrupt */
253 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
254 ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
255 0, 0, 0, 0, &res);
256
257 return IRQ_HANDLED;
258}
259
260static int of_get_ddr_timings(struct dram_timing *timing,
261 struct device_node *np)
262{
263 int ret = 0;
264
265 ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
266 &timing->ddr3_speed_bin);
267 ret |= of_property_read_u32(np, "rockchip,pd_idle",
268 &timing->pd_idle);
269 ret |= of_property_read_u32(np, "rockchip,sr_idle",
270 &timing->sr_idle);
271 ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
272 &timing->sr_mc_gate_idle);
273 ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
274 &timing->srpd_lite_idle);
275 ret |= of_property_read_u32(np, "rockchip,standby_idle",
276 &timing->standby_idle);
277 ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
278 &timing->auto_pd_dis_freq);
279 ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
280 &timing->dram_dll_dis_freq);
281 ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
282 &timing->phy_dll_dis_freq);
283 ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
284 &timing->ddr3_odt_dis_freq);
285 ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
286 &timing->ddr3_drv);
287 ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
288 &timing->ddr3_odt);
289 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
290 &timing->phy_ddr3_ca_drv);
291 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
292 &timing->phy_ddr3_dq_drv);
293 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
294 &timing->phy_ddr3_odt);
295 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
296 &timing->lpddr3_odt_dis_freq);
297 ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
298 &timing->lpddr3_drv);
299 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
300 &timing->lpddr3_odt);
301 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
302 &timing->phy_lpddr3_ca_drv);
303 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
304 &timing->phy_lpddr3_dq_drv);
305 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
306 &timing->phy_lpddr3_odt);
307 ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
308 &timing->lpddr4_odt_dis_freq);
309 ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
310 &timing->lpddr4_drv);
311 ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
312 &timing->lpddr4_dq_odt);
313 ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
314 &timing->lpddr4_ca_odt);
315 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
316 &timing->phy_lpddr4_ca_drv);
317 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
318 &timing->phy_lpddr4_ck_cs_drv);
319 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
320 &timing->phy_lpddr4_dq_drv);
321 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
322 &timing->phy_lpddr4_odt);
323
324 return ret;
325}
326
327static int rk3399_dmcfreq_probe(struct platform_device *pdev)
328{
329 struct arm_smccc_res res;
330 struct device *dev = &pdev->dev;
331 struct device_node *np = pdev->dev.of_node;
332 struct rk3399_dmcfreq *data;
333 int ret, irq, index, size;
334 uint32_t *timing;
335 struct dev_pm_opp *opp;
336
337 irq = platform_get_irq(pdev, 0);
338 if (irq < 0) {
339 dev_err(&pdev->dev,
340 "Cannot get the dmc interrupt resource: %d\n", irq);
341 return irq;
342 }
343 data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
344 if (!data)
345 return -ENOMEM;
346
347 mutex_init(&data->lock);
348
349 data->vdd_center = devm_regulator_get(dev, "center");
350 if (IS_ERR(data->vdd_center)) {
351 dev_err(dev, "Cannot get the regulator \"center\"\n");
352 return PTR_ERR(data->vdd_center);
353 }
354
355 data->dmc_clk = devm_clk_get(dev, "dmc_clk");
356 if (IS_ERR(data->dmc_clk)) {
357 dev_err(dev, "Cannot get the clk dmc_clk\n");
358 return PTR_ERR(data->dmc_clk);
359 };
360
361 data->irq = irq;
362 ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
363 dev_name(dev), data);
364 if (ret) {
365 dev_err(dev, "Failed to request dmc irq: %d\n", ret);
366 return ret;
367 }
368
369 init_waitqueue_head(&data->wait_dcf_queue);
370 data->wait_dcf_flag = 0;
371
372 data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
373 if (IS_ERR(data->edev))
374 return -EPROBE_DEFER;
375
376 ret = devfreq_event_enable_edev(data->edev);
377 if (ret < 0) {
378 dev_err(dev, "failed to enable devfreq-event devices\n");
379 return ret;
380 }
381
382 /*
383 * Get dram timing and pass it to arm trust firmware,
384 * the dram drvier in arm trust firmware will get these
385 * timing and to do dram initial.
386 */
387 if (!of_get_ddr_timings(&data->timing, np)) {
388 timing = &data->timing.ddr3_speed_bin;
389 size = sizeof(struct dram_timing) / 4;
390 for (index = 0; index < size; index++) {
391 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
392 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
393 0, 0, 0, 0, &res);
394 if (res.a0) {
395 dev_err(dev, "Failed to set dram param: %ld\n",
396 res.a0);
397 return -EINVAL;
398 }
399 }
400 }
401
402 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
403 ROCKCHIP_SIP_CONFIG_DRAM_INIT,
404 0, 0, 0, 0, &res);
405
406 /*
407 * We add a devfreq driver to our parent since it has a device tree node
408 * with operating points.
409 */
410 if (dev_pm_opp_of_add_table(dev)) {
411 dev_err(dev, "Invalid operating-points in device tree.\n");
412 return -EINVAL;
413 }
414
415 of_property_read_u32(np, "upthreshold",
416 &data->ondemand_data.upthreshold);
417 of_property_read_u32(np, "downdifferential",
418 &data->ondemand_data.downdifferential);
419
420 data->rate = clk_get_rate(data->dmc_clk);
421
422 opp = devfreq_recommended_opp(dev, &data->rate, 0);
423 if (IS_ERR(opp))
424 return PTR_ERR(opp);
425
426 data->rate = dev_pm_opp_get_freq(opp);
427 data->volt = dev_pm_opp_get_voltage(opp);
428 dev_pm_opp_put(opp);
429
430 rk3399_devfreq_dmc_profile.initial_freq = data->rate;
431
432 data->devfreq = devm_devfreq_add_device(dev,
433 &rk3399_devfreq_dmc_profile,
434 DEVFREQ_GOV_SIMPLE_ONDEMAND,
435 &data->ondemand_data);
436 if (IS_ERR(data->devfreq))
437 return PTR_ERR(data->devfreq);
438 devm_devfreq_register_opp_notifier(dev, data->devfreq);
439
440 data->dev = dev;
441 platform_set_drvdata(pdev, data);
442
443 return 0;
444}
445
446static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
447 { .compatible = "rockchip,rk3399-dmc" },
448 { },
449};
450MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
451
452static struct platform_driver rk3399_dmcfreq_driver = {
453 .probe = rk3399_dmcfreq_probe,
454 .driver = {
455 .name = "rk3399-dmc-freq",
456 .pm = &rk3399_dmcfreq_pm,
457 .of_match_table = rk3399dmc_devfreq_of_match,
458 },
459};
460module_platform_driver(rk3399_dmcfreq_driver);
461
462MODULE_LICENSE("GPL v2");
463MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
464MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");