1/*
  2 * linux/arch/arm/mach-at91/at91rm9200_time.c
  3 *
  4 *  Copyright (C) 2003 SAN People
  5 *  Copyright (C) 2003 ATMEL
  6 *
  7 * This program is free software; you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License as published by
  9 * the Free Software Foundation; either version 2 of the License, or
 10 * (at your option) any later version.
 11 *
 12 * This program is distributed in the hope that it will be useful,
 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15 * GNU General Public License for more details.
 16 *
 17 * You should have received a copy of the GNU General Public License
 18 * along with this program; if not, write to the Free Software
 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 20 */
 21
 22#include <linux/kernel.h>
 23#include <linux/interrupt.h>
 24#include <linux/irq.h>
 25#include <linux/clk.h>
 26#include <linux/clockchips.h>
 27#include <linux/export.h>
 28#include <linux/mfd/syscon.h>
 29#include <linux/mfd/syscon/atmel-st.h>
 30#include <linux/of_irq.h>
 31#include <linux/regmap.h>
 32
 33static unsigned long last_crtr;
 34static u32 irqmask;
 35static struct clock_event_device clkevt;
 36static struct regmap *regmap_st;
 37static int timer_latch;
 38
 39/*
 40 * The ST_CRTR is updated asynchronously to the master clock ... but
 41 * the updates as seen by the CPU don't seem to be strictly monotonic.
 42 * Waiting until we read the same value twice avoids glitching.
 43 */
 44static inline unsigned long read_CRTR(void)
 45{
 46	unsigned int x1, x2;
 47
 48	regmap_read(regmap_st, AT91_ST_CRTR, &x1);
 49	do {
 50		regmap_read(regmap_st, AT91_ST_CRTR, &x2);
 51		if (x1 == x2)
 52			break;
 53		x1 = x2;
 54	} while (1);
 55	return x1;
 56}
 57
 58/*
 59 * IRQ handler for the timer.
 60 */
 61static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
 62{
 63	u32 sr;
 64
 65	regmap_read(regmap_st, AT91_ST_SR, &sr);
 66	sr &= irqmask;
 67
 68	/*
 69	 * irqs should be disabled here, but as the irq is shared they are only
 70	 * guaranteed to be off if the timer irq is registered first.
 71	 */
 72	WARN_ON_ONCE(!irqs_disabled());
 73
 74	/* simulate "oneshot" timer with alarm */
 75	if (sr & AT91_ST_ALMS) {
 76		clkevt.event_handler(&clkevt);
 77		return IRQ_HANDLED;
 78	}
 79
 80	/* periodic mode should handle delayed ticks */
 81	if (sr & AT91_ST_PITS) {
 82		u32	crtr = read_CRTR();
 83
 84		while (((crtr - last_crtr) & AT91_ST_CRTV) >= timer_latch) {
 85			last_crtr += timer_latch;
 86			clkevt.event_handler(&clkevt);
 87		}
 88		return IRQ_HANDLED;
 89	}
 90
 91	/* this irq is shared ... */
 92	return IRQ_NONE;
 93}
 94
 95static u64 read_clk32k(struct clocksource *cs)
 96{
 97	return read_CRTR();
 98}
 99
100static struct clocksource clk32k = {
101	.name		= "32k_counter",
102	.rating		= 150,
103	.read		= read_clk32k,
104	.mask		= CLOCKSOURCE_MASK(20),
105	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
106};
107
108static void clkdev32k_disable_and_flush_irq(void)
109{
110	unsigned int val;
111
112	/* Disable and flush pending timer interrupts */
113	regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
114	regmap_read(regmap_st, AT91_ST_SR, &val);
115	last_crtr = read_CRTR();
116}
117
118static int clkevt32k_shutdown(struct clock_event_device *evt)
119{
120	clkdev32k_disable_and_flush_irq();
121	irqmask = 0;
122	regmap_write(regmap_st, AT91_ST_IER, irqmask);
123	return 0;
124}
125
126static int clkevt32k_set_oneshot(struct clock_event_device *dev)
127{
128	clkdev32k_disable_and_flush_irq();
129
130	/*
131	 * ALM for oneshot irqs, set by next_event()
132	 * before 32 seconds have passed.
133	 */
134	irqmask = AT91_ST_ALMS;
135	regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
136	regmap_write(regmap_st, AT91_ST_IER, irqmask);
137	return 0;
138}
139
140static int clkevt32k_set_periodic(struct clock_event_device *dev)
141{
142	clkdev32k_disable_and_flush_irq();
143
144	/* PIT for periodic irqs; fixed rate of 1/HZ */
145	irqmask = AT91_ST_PITS;
146	regmap_write(regmap_st, AT91_ST_PIMR, timer_latch);
147	regmap_write(regmap_st, AT91_ST_IER, irqmask);
148	return 0;
149}
150
151static int
152clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
153{
154	u32		alm;
155	int		status = 0;
156	unsigned int	val;
157
158	BUG_ON(delta < 2);
159
160	/* The alarm IRQ uses absolute time (now+delta), not the relative
161	 * time (delta) in our calling convention.  Like all clockevents
162	 * using such "match" hardware, we have a race to defend against.
163	 *
164	 * Our defense here is to have set up the clockevent device so the
165	 * delta is at least two.  That way we never end up writing RTAR
166	 * with the value then held in CRTR ... which would mean the match
167	 * wouldn't trigger until 32 seconds later, after CRTR wraps.
168	 */
169	alm = read_CRTR();
170
171	/* Cancel any pending alarm; flush any pending IRQ */
172	regmap_write(regmap_st, AT91_ST_RTAR, alm);
173	regmap_read(regmap_st, AT91_ST_SR, &val);
174
175	/* Schedule alarm by writing RTAR. */
176	alm += delta;
177	regmap_write(regmap_st, AT91_ST_RTAR, alm);
178
179	return status;
180}
181
182static struct clock_event_device clkevt = {
183	.name			= "at91_tick",
184	.features		= CLOCK_EVT_FEAT_PERIODIC |
185				  CLOCK_EVT_FEAT_ONESHOT,
186	.rating			= 150,
187	.set_next_event		= clkevt32k_next_event,
188	.set_state_shutdown	= clkevt32k_shutdown,
189	.set_state_periodic	= clkevt32k_set_periodic,
190	.set_state_oneshot	= clkevt32k_set_oneshot,
191	.tick_resume		= clkevt32k_shutdown,
192};
193
194/*
195 * ST (system timer) module supports both clockevents and clocksource.
196 */
197static int __init atmel_st_timer_init(struct device_node *node)
198{
199	struct clk *sclk;
200	unsigned int sclk_rate, val;
201	int irq, ret;
202
203	regmap_st = syscon_node_to_regmap(node);
204	if (IS_ERR(regmap_st)) {
205		pr_err("Unable to get regmap\n");
206		return PTR_ERR(regmap_st);
207	}
208
209	/* Disable all timer interrupts, and clear any pending ones */
210	regmap_write(regmap_st, AT91_ST_IDR,
211		AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
212	regmap_read(regmap_st, AT91_ST_SR, &val);
213
214	/* Get the interrupts property */
215	irq  = irq_of_parse_and_map(node, 0);
216	if (!irq) {
217		pr_err("Unable to get IRQ from DT\n");
218		return -EINVAL;
219	}
220
221	/* Make IRQs happen for the system timer */
222	ret = request_irq(irq, at91rm9200_timer_interrupt,
223			  IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
224			  "at91_tick", regmap_st);
225	if (ret) {
226		pr_err("Unable to setup IRQ\n");
227		return ret;
228	}
229
230	sclk = of_clk_get(node, 0);
231	if (IS_ERR(sclk)) {
232		pr_err("Unable to get slow clock\n");
233		return PTR_ERR(sclk);
234	}
235
236	ret = clk_prepare_enable(sclk);
237	if (ret) {
238		pr_err("Could not enable slow clock\n");
239		return ret;
240	}
241
242	sclk_rate = clk_get_rate(sclk);
243	if (!sclk_rate) {
244		pr_err("Invalid slow clock rate\n");
245		return -EINVAL;
246	}
247	timer_latch = (sclk_rate + HZ / 2) / HZ;
248
249	/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
250	 * directly for the clocksource and all clockevents, after adjusting
251	 * its prescaler from the 1 Hz default.
252	 */
253	regmap_write(regmap_st, AT91_ST_RTMR, 1);
254
255	/* Setup timer clockevent, with minimum of two ticks (important!!) */
256	clkevt.cpumask = cpumask_of(0);
257	clockevents_config_and_register(&clkevt, sclk_rate,
258					2, AT91_ST_ALMV);
259
260	/* register clocksource */
261	return clocksource_register_hz(&clk32k, sclk_rate);
262}
263TIMER_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
264		       atmel_st_timer_init);