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1/*
2 * AmLogic S905 / GXBB Clock Controller Driver
3 *
4 * Copyright (c) 2016 AmLogic, Inc.
5 * Michael Turquette <mturquette@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/clk.h>
21#include <linux/clk-provider.h>
22#include <linux/init.h>
23#include <linux/of_address.h>
24#include <linux/of_device.h>
25#include <linux/mfd/syscon.h>
26#include <linux/platform_device.h>
27#include <linux/regmap.h>
28
29#include "clkc.h"
30#include "gxbb.h"
31#include "clk-regmap.h"
32
33static DEFINE_SPINLOCK(meson_clk_lock);
34
35static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = {
36 PLL_RATE(96000000, 32, 1, 3),
37 PLL_RATE(99000000, 33, 1, 3),
38 PLL_RATE(102000000, 34, 1, 3),
39 PLL_RATE(105000000, 35, 1, 3),
40 PLL_RATE(108000000, 36, 1, 3),
41 PLL_RATE(111000000, 37, 1, 3),
42 PLL_RATE(114000000, 38, 1, 3),
43 PLL_RATE(117000000, 39, 1, 3),
44 PLL_RATE(120000000, 40, 1, 3),
45 PLL_RATE(123000000, 41, 1, 3),
46 PLL_RATE(126000000, 42, 1, 3),
47 PLL_RATE(129000000, 43, 1, 3),
48 PLL_RATE(132000000, 44, 1, 3),
49 PLL_RATE(135000000, 45, 1, 3),
50 PLL_RATE(138000000, 46, 1, 3),
51 PLL_RATE(141000000, 47, 1, 3),
52 PLL_RATE(144000000, 48, 1, 3),
53 PLL_RATE(147000000, 49, 1, 3),
54 PLL_RATE(150000000, 50, 1, 3),
55 PLL_RATE(153000000, 51, 1, 3),
56 PLL_RATE(156000000, 52, 1, 3),
57 PLL_RATE(159000000, 53, 1, 3),
58 PLL_RATE(162000000, 54, 1, 3),
59 PLL_RATE(165000000, 55, 1, 3),
60 PLL_RATE(168000000, 56, 1, 3),
61 PLL_RATE(171000000, 57, 1, 3),
62 PLL_RATE(174000000, 58, 1, 3),
63 PLL_RATE(177000000, 59, 1, 3),
64 PLL_RATE(180000000, 60, 1, 3),
65 PLL_RATE(183000000, 61, 1, 3),
66 PLL_RATE(186000000, 62, 1, 3),
67 PLL_RATE(192000000, 32, 1, 2),
68 PLL_RATE(198000000, 33, 1, 2),
69 PLL_RATE(204000000, 34, 1, 2),
70 PLL_RATE(210000000, 35, 1, 2),
71 PLL_RATE(216000000, 36, 1, 2),
72 PLL_RATE(222000000, 37, 1, 2),
73 PLL_RATE(228000000, 38, 1, 2),
74 PLL_RATE(234000000, 39, 1, 2),
75 PLL_RATE(240000000, 40, 1, 2),
76 PLL_RATE(246000000, 41, 1, 2),
77 PLL_RATE(252000000, 42, 1, 2),
78 PLL_RATE(258000000, 43, 1, 2),
79 PLL_RATE(264000000, 44, 1, 2),
80 PLL_RATE(270000000, 45, 1, 2),
81 PLL_RATE(276000000, 46, 1, 2),
82 PLL_RATE(282000000, 47, 1, 2),
83 PLL_RATE(288000000, 48, 1, 2),
84 PLL_RATE(294000000, 49, 1, 2),
85 PLL_RATE(300000000, 50, 1, 2),
86 PLL_RATE(306000000, 51, 1, 2),
87 PLL_RATE(312000000, 52, 1, 2),
88 PLL_RATE(318000000, 53, 1, 2),
89 PLL_RATE(324000000, 54, 1, 2),
90 PLL_RATE(330000000, 55, 1, 2),
91 PLL_RATE(336000000, 56, 1, 2),
92 PLL_RATE(342000000, 57, 1, 2),
93 PLL_RATE(348000000, 58, 1, 2),
94 PLL_RATE(354000000, 59, 1, 2),
95 PLL_RATE(360000000, 60, 1, 2),
96 PLL_RATE(366000000, 61, 1, 2),
97 PLL_RATE(372000000, 62, 1, 2),
98 PLL_RATE(384000000, 32, 1, 1),
99 PLL_RATE(396000000, 33, 1, 1),
100 PLL_RATE(408000000, 34, 1, 1),
101 PLL_RATE(420000000, 35, 1, 1),
102 PLL_RATE(432000000, 36, 1, 1),
103 PLL_RATE(444000000, 37, 1, 1),
104 PLL_RATE(456000000, 38, 1, 1),
105 PLL_RATE(468000000, 39, 1, 1),
106 PLL_RATE(480000000, 40, 1, 1),
107 PLL_RATE(492000000, 41, 1, 1),
108 PLL_RATE(504000000, 42, 1, 1),
109 PLL_RATE(516000000, 43, 1, 1),
110 PLL_RATE(528000000, 44, 1, 1),
111 PLL_RATE(540000000, 45, 1, 1),
112 PLL_RATE(552000000, 46, 1, 1),
113 PLL_RATE(564000000, 47, 1, 1),
114 PLL_RATE(576000000, 48, 1, 1),
115 PLL_RATE(588000000, 49, 1, 1),
116 PLL_RATE(600000000, 50, 1, 1),
117 PLL_RATE(612000000, 51, 1, 1),
118 PLL_RATE(624000000, 52, 1, 1),
119 PLL_RATE(636000000, 53, 1, 1),
120 PLL_RATE(648000000, 54, 1, 1),
121 PLL_RATE(660000000, 55, 1, 1),
122 PLL_RATE(672000000, 56, 1, 1),
123 PLL_RATE(684000000, 57, 1, 1),
124 PLL_RATE(696000000, 58, 1, 1),
125 PLL_RATE(708000000, 59, 1, 1),
126 PLL_RATE(720000000, 60, 1, 1),
127 PLL_RATE(732000000, 61, 1, 1),
128 PLL_RATE(744000000, 62, 1, 1),
129 PLL_RATE(768000000, 32, 1, 0),
130 PLL_RATE(792000000, 33, 1, 0),
131 PLL_RATE(816000000, 34, 1, 0),
132 PLL_RATE(840000000, 35, 1, 0),
133 PLL_RATE(864000000, 36, 1, 0),
134 PLL_RATE(888000000, 37, 1, 0),
135 PLL_RATE(912000000, 38, 1, 0),
136 PLL_RATE(936000000, 39, 1, 0),
137 PLL_RATE(960000000, 40, 1, 0),
138 PLL_RATE(984000000, 41, 1, 0),
139 PLL_RATE(1008000000, 42, 1, 0),
140 PLL_RATE(1032000000, 43, 1, 0),
141 PLL_RATE(1056000000, 44, 1, 0),
142 PLL_RATE(1080000000, 45, 1, 0),
143 PLL_RATE(1104000000, 46, 1, 0),
144 PLL_RATE(1128000000, 47, 1, 0),
145 PLL_RATE(1152000000, 48, 1, 0),
146 PLL_RATE(1176000000, 49, 1, 0),
147 PLL_RATE(1200000000, 50, 1, 0),
148 PLL_RATE(1224000000, 51, 1, 0),
149 PLL_RATE(1248000000, 52, 1, 0),
150 PLL_RATE(1272000000, 53, 1, 0),
151 PLL_RATE(1296000000, 54, 1, 0),
152 PLL_RATE(1320000000, 55, 1, 0),
153 PLL_RATE(1344000000, 56, 1, 0),
154 PLL_RATE(1368000000, 57, 1, 0),
155 PLL_RATE(1392000000, 58, 1, 0),
156 PLL_RATE(1416000000, 59, 1, 0),
157 PLL_RATE(1440000000, 60, 1, 0),
158 PLL_RATE(1464000000, 61, 1, 0),
159 PLL_RATE(1488000000, 62, 1, 0),
160 { /* sentinel */ },
161};
162
163static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
164 PLL_RATE(504000000, 42, 1, 1),
165 PLL_RATE(516000000, 43, 1, 1),
166 PLL_RATE(528000000, 44, 1, 1),
167 PLL_RATE(540000000, 45, 1, 1),
168 PLL_RATE(552000000, 46, 1, 1),
169 PLL_RATE(564000000, 47, 1, 1),
170 PLL_RATE(576000000, 48, 1, 1),
171 PLL_RATE(588000000, 49, 1, 1),
172 PLL_RATE(600000000, 50, 1, 1),
173 PLL_RATE(612000000, 51, 1, 1),
174 PLL_RATE(624000000, 52, 1, 1),
175 PLL_RATE(636000000, 53, 1, 1),
176 PLL_RATE(648000000, 54, 1, 1),
177 PLL_RATE(660000000, 55, 1, 1),
178 PLL_RATE(672000000, 56, 1, 1),
179 PLL_RATE(684000000, 57, 1, 1),
180 PLL_RATE(696000000, 58, 1, 1),
181 PLL_RATE(708000000, 59, 1, 1),
182 PLL_RATE(720000000, 60, 1, 1),
183 PLL_RATE(732000000, 61, 1, 1),
184 PLL_RATE(744000000, 62, 1, 1),
185 PLL_RATE(756000000, 63, 1, 1),
186 PLL_RATE(768000000, 64, 1, 1),
187 PLL_RATE(780000000, 65, 1, 1),
188 PLL_RATE(792000000, 66, 1, 1),
189 { /* sentinel */ },
190};
191
192static struct clk_regmap gxbb_fixed_pll = {
193 .data = &(struct meson_clk_pll_data){
194 .m = {
195 .reg_off = HHI_MPLL_CNTL,
196 .shift = 0,
197 .width = 9,
198 },
199 .n = {
200 .reg_off = HHI_MPLL_CNTL,
201 .shift = 9,
202 .width = 5,
203 },
204 .od = {
205 .reg_off = HHI_MPLL_CNTL,
206 .shift = 16,
207 .width = 2,
208 },
209 .frac = {
210 .reg_off = HHI_MPLL_CNTL2,
211 .shift = 0,
212 .width = 12,
213 },
214 .l = {
215 .reg_off = HHI_MPLL_CNTL,
216 .shift = 31,
217 .width = 1,
218 },
219 .rst = {
220 .reg_off = HHI_MPLL_CNTL,
221 .shift = 29,
222 .width = 1,
223 },
224 },
225 .hw.init = &(struct clk_init_data){
226 .name = "fixed_pll",
227 .ops = &meson_clk_pll_ro_ops,
228 .parent_names = (const char *[]){ "xtal" },
229 .num_parents = 1,
230 .flags = CLK_GET_RATE_NOCACHE,
231 },
232};
233
234static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
235 .mult = 2,
236 .div = 1,
237 .hw.init = &(struct clk_init_data){
238 .name = "hdmi_pll_pre_mult",
239 .ops = &clk_fixed_factor_ops,
240 .parent_names = (const char *[]){ "xtal" },
241 .num_parents = 1,
242 },
243};
244
245static struct clk_regmap gxbb_hdmi_pll = {
246 .data = &(struct meson_clk_pll_data){
247 .m = {
248 .reg_off = HHI_HDMI_PLL_CNTL,
249 .shift = 0,
250 .width = 9,
251 },
252 .n = {
253 .reg_off = HHI_HDMI_PLL_CNTL,
254 .shift = 9,
255 .width = 5,
256 },
257 .frac = {
258 .reg_off = HHI_HDMI_PLL_CNTL2,
259 .shift = 0,
260 .width = 12,
261 },
262 .od = {
263 .reg_off = HHI_HDMI_PLL_CNTL2,
264 .shift = 16,
265 .width = 2,
266 },
267 .od2 = {
268 .reg_off = HHI_HDMI_PLL_CNTL2,
269 .shift = 22,
270 .width = 2,
271 },
272 .od3 = {
273 .reg_off = HHI_HDMI_PLL_CNTL2,
274 .shift = 18,
275 .width = 2,
276 },
277 .l = {
278 .reg_off = HHI_HDMI_PLL_CNTL,
279 .shift = 31,
280 .width = 1,
281 },
282 .rst = {
283 .reg_off = HHI_HDMI_PLL_CNTL,
284 .shift = 28,
285 .width = 1,
286 },
287 },
288 .hw.init = &(struct clk_init_data){
289 .name = "hdmi_pll",
290 .ops = &meson_clk_pll_ro_ops,
291 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
292 .num_parents = 1,
293 .flags = CLK_GET_RATE_NOCACHE,
294 },
295};
296
297static struct clk_regmap gxl_hdmi_pll = {
298 .data = &(struct meson_clk_pll_data){
299 .m = {
300 .reg_off = HHI_HDMI_PLL_CNTL,
301 .shift = 0,
302 .width = 9,
303 },
304 .n = {
305 .reg_off = HHI_HDMI_PLL_CNTL,
306 .shift = 9,
307 .width = 5,
308 },
309 .frac = {
310 /*
311 * On gxl, there is a register shift due to
312 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
313 * so we compute the register offset based on the PLL
314 * base to get it right
315 */
316 .reg_off = HHI_HDMI_PLL_CNTL + 4,
317 .shift = 0,
318 .width = 12,
319 },
320 .od = {
321 .reg_off = HHI_HDMI_PLL_CNTL + 8,
322 .shift = 21,
323 .width = 2,
324 },
325 .od2 = {
326 .reg_off = HHI_HDMI_PLL_CNTL + 8,
327 .shift = 23,
328 .width = 2,
329 },
330 .od3 = {
331 .reg_off = HHI_HDMI_PLL_CNTL + 8,
332 .shift = 19,
333 .width = 2,
334 },
335 .l = {
336 .reg_off = HHI_HDMI_PLL_CNTL,
337 .shift = 31,
338 .width = 1,
339 },
340 .rst = {
341 .reg_off = HHI_HDMI_PLL_CNTL,
342 .shift = 29,
343 .width = 1,
344 },
345 },
346 .hw.init = &(struct clk_init_data){
347 .name = "hdmi_pll",
348 .ops = &meson_clk_pll_ro_ops,
349 .parent_names = (const char *[]){ "xtal" },
350 .num_parents = 1,
351 .flags = CLK_GET_RATE_NOCACHE,
352 },
353};
354
355static struct clk_regmap gxbb_sys_pll = {
356 .data = &(struct meson_clk_pll_data){
357 .m = {
358 .reg_off = HHI_SYS_PLL_CNTL,
359 .shift = 0,
360 .width = 9,
361 },
362 .n = {
363 .reg_off = HHI_SYS_PLL_CNTL,
364 .shift = 9,
365 .width = 5,
366 },
367 .od = {
368 .reg_off = HHI_SYS_PLL_CNTL,
369 .shift = 10,
370 .width = 2,
371 },
372 .l = {
373 .reg_off = HHI_SYS_PLL_CNTL,
374 .shift = 31,
375 .width = 1,
376 },
377 .rst = {
378 .reg_off = HHI_SYS_PLL_CNTL,
379 .shift = 29,
380 .width = 1,
381 },
382 },
383 .hw.init = &(struct clk_init_data){
384 .name = "sys_pll",
385 .ops = &meson_clk_pll_ro_ops,
386 .parent_names = (const char *[]){ "xtal" },
387 .num_parents = 1,
388 .flags = CLK_GET_RATE_NOCACHE,
389 },
390};
391
392static const struct reg_sequence gxbb_gp0_init_regs[] = {
393 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
394 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
395 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
396 { .reg = HHI_GP0_PLL_CNTL, .def = 0x4a000228 },
397};
398
399static struct clk_regmap gxbb_gp0_pll = {
400 .data = &(struct meson_clk_pll_data){
401 .m = {
402 .reg_off = HHI_GP0_PLL_CNTL,
403 .shift = 0,
404 .width = 9,
405 },
406 .n = {
407 .reg_off = HHI_GP0_PLL_CNTL,
408 .shift = 9,
409 .width = 5,
410 },
411 .od = {
412 .reg_off = HHI_GP0_PLL_CNTL,
413 .shift = 16,
414 .width = 2,
415 },
416 .l = {
417 .reg_off = HHI_GP0_PLL_CNTL,
418 .shift = 31,
419 .width = 1,
420 },
421 .rst = {
422 .reg_off = HHI_GP0_PLL_CNTL,
423 .shift = 29,
424 .width = 1,
425 },
426 .table = gxbb_gp0_pll_rate_table,
427 .init_regs = gxbb_gp0_init_regs,
428 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
429 },
430 .hw.init = &(struct clk_init_data){
431 .name = "gp0_pll",
432 .ops = &meson_clk_pll_ops,
433 .parent_names = (const char *[]){ "xtal" },
434 .num_parents = 1,
435 .flags = CLK_GET_RATE_NOCACHE,
436 },
437};
438
439static const struct reg_sequence gxl_gp0_init_regs[] = {
440 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
441 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
442 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
443 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
444 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
445 { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
446};
447
448static struct clk_regmap gxl_gp0_pll = {
449 .data = &(struct meson_clk_pll_data){
450 .m = {
451 .reg_off = HHI_GP0_PLL_CNTL,
452 .shift = 0,
453 .width = 9,
454 },
455 .n = {
456 .reg_off = HHI_GP0_PLL_CNTL,
457 .shift = 9,
458 .width = 5,
459 },
460 .od = {
461 .reg_off = HHI_GP0_PLL_CNTL,
462 .shift = 16,
463 .width = 2,
464 },
465 .frac = {
466 .reg_off = HHI_GP0_PLL_CNTL1,
467 .shift = 0,
468 .width = 10,
469 },
470 .l = {
471 .reg_off = HHI_GP0_PLL_CNTL,
472 .shift = 31,
473 .width = 1,
474 },
475 .rst = {
476 .reg_off = HHI_GP0_PLL_CNTL,
477 .shift = 29,
478 .width = 1,
479 },
480 .table = gxl_gp0_pll_rate_table,
481 .init_regs = gxl_gp0_init_regs,
482 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
483 },
484 .hw.init = &(struct clk_init_data){
485 .name = "gp0_pll",
486 .ops = &meson_clk_pll_ops,
487 .parent_names = (const char *[]){ "xtal" },
488 .num_parents = 1,
489 .flags = CLK_GET_RATE_NOCACHE,
490 },
491};
492
493static struct clk_fixed_factor gxbb_fclk_div2_div = {
494 .mult = 1,
495 .div = 2,
496 .hw.init = &(struct clk_init_data){
497 .name = "fclk_div2_div",
498 .ops = &clk_fixed_factor_ops,
499 .parent_names = (const char *[]){ "fixed_pll" },
500 .num_parents = 1,
501 },
502};
503
504static struct clk_regmap gxbb_fclk_div2 = {
505 .data = &(struct clk_regmap_gate_data){
506 .offset = HHI_MPLL_CNTL6,
507 .bit_idx = 27,
508 },
509 .hw.init = &(struct clk_init_data){
510 .name = "fclk_div2",
511 .ops = &clk_regmap_gate_ops,
512 .parent_names = (const char *[]){ "fclk_div2_div" },
513 .num_parents = 1,
514 },
515};
516
517static struct clk_fixed_factor gxbb_fclk_div3_div = {
518 .mult = 1,
519 .div = 3,
520 .hw.init = &(struct clk_init_data){
521 .name = "fclk_div3_div",
522 .ops = &clk_fixed_factor_ops,
523 .parent_names = (const char *[]){ "fixed_pll" },
524 .num_parents = 1,
525 },
526};
527
528static struct clk_regmap gxbb_fclk_div3 = {
529 .data = &(struct clk_regmap_gate_data){
530 .offset = HHI_MPLL_CNTL6,
531 .bit_idx = 28,
532 },
533 .hw.init = &(struct clk_init_data){
534 .name = "fclk_div3",
535 .ops = &clk_regmap_gate_ops,
536 .parent_names = (const char *[]){ "fclk_div3_div" },
537 .num_parents = 1,
538 },
539};
540
541static struct clk_fixed_factor gxbb_fclk_div4_div = {
542 .mult = 1,
543 .div = 4,
544 .hw.init = &(struct clk_init_data){
545 .name = "fclk_div4_div",
546 .ops = &clk_fixed_factor_ops,
547 .parent_names = (const char *[]){ "fixed_pll" },
548 .num_parents = 1,
549 },
550};
551
552static struct clk_regmap gxbb_fclk_div4 = {
553 .data = &(struct clk_regmap_gate_data){
554 .offset = HHI_MPLL_CNTL6,
555 .bit_idx = 29,
556 },
557 .hw.init = &(struct clk_init_data){
558 .name = "fclk_div4",
559 .ops = &clk_regmap_gate_ops,
560 .parent_names = (const char *[]){ "fclk_div4_div" },
561 .num_parents = 1,
562 },
563};
564
565static struct clk_fixed_factor gxbb_fclk_div5_div = {
566 .mult = 1,
567 .div = 5,
568 .hw.init = &(struct clk_init_data){
569 .name = "fclk_div5_div",
570 .ops = &clk_fixed_factor_ops,
571 .parent_names = (const char *[]){ "fixed_pll" },
572 .num_parents = 1,
573 },
574};
575
576static struct clk_regmap gxbb_fclk_div5 = {
577 .data = &(struct clk_regmap_gate_data){
578 .offset = HHI_MPLL_CNTL6,
579 .bit_idx = 30,
580 },
581 .hw.init = &(struct clk_init_data){
582 .name = "fclk_div5",
583 .ops = &clk_regmap_gate_ops,
584 .parent_names = (const char *[]){ "fclk_div5_div" },
585 .num_parents = 1,
586 },
587};
588
589static struct clk_fixed_factor gxbb_fclk_div7_div = {
590 .mult = 1,
591 .div = 7,
592 .hw.init = &(struct clk_init_data){
593 .name = "fclk_div7_div",
594 .ops = &clk_fixed_factor_ops,
595 .parent_names = (const char *[]){ "fixed_pll" },
596 .num_parents = 1,
597 },
598};
599
600static struct clk_regmap gxbb_fclk_div7 = {
601 .data = &(struct clk_regmap_gate_data){
602 .offset = HHI_MPLL_CNTL6,
603 .bit_idx = 31,
604 },
605 .hw.init = &(struct clk_init_data){
606 .name = "fclk_div7",
607 .ops = &clk_regmap_gate_ops,
608 .parent_names = (const char *[]){ "fclk_div7_div" },
609 .num_parents = 1,
610 },
611};
612
613static struct clk_regmap gxbb_mpll_prediv = {
614 .data = &(struct clk_regmap_div_data){
615 .offset = HHI_MPLL_CNTL5,
616 .shift = 12,
617 .width = 1,
618 },
619 .hw.init = &(struct clk_init_data){
620 .name = "mpll_prediv",
621 .ops = &clk_regmap_divider_ro_ops,
622 .parent_names = (const char *[]){ "fixed_pll" },
623 .num_parents = 1,
624 },
625};
626
627static struct clk_regmap gxbb_mpll0_div = {
628 .data = &(struct meson_clk_mpll_data){
629 .sdm = {
630 .reg_off = HHI_MPLL_CNTL7,
631 .shift = 0,
632 .width = 14,
633 },
634 .sdm_en = {
635 .reg_off = HHI_MPLL_CNTL7,
636 .shift = 15,
637 .width = 1,
638 },
639 .n2 = {
640 .reg_off = HHI_MPLL_CNTL7,
641 .shift = 16,
642 .width = 9,
643 },
644 .ssen = {
645 .reg_off = HHI_MPLL_CNTL,
646 .shift = 25,
647 .width = 1,
648 },
649 .lock = &meson_clk_lock,
650 },
651 .hw.init = &(struct clk_init_data){
652 .name = "mpll0_div",
653 .ops = &meson_clk_mpll_ops,
654 .parent_names = (const char *[]){ "mpll_prediv" },
655 .num_parents = 1,
656 },
657};
658
659static struct clk_regmap gxbb_mpll0 = {
660 .data = &(struct clk_regmap_gate_data){
661 .offset = HHI_MPLL_CNTL7,
662 .bit_idx = 14,
663 },
664 .hw.init = &(struct clk_init_data){
665 .name = "mpll0",
666 .ops = &clk_regmap_gate_ops,
667 .parent_names = (const char *[]){ "mpll0_div" },
668 .num_parents = 1,
669 .flags = CLK_SET_RATE_PARENT,
670 },
671};
672
673static struct clk_regmap gxbb_mpll1_div = {
674 .data = &(struct meson_clk_mpll_data){
675 .sdm = {
676 .reg_off = HHI_MPLL_CNTL8,
677 .shift = 0,
678 .width = 14,
679 },
680 .sdm_en = {
681 .reg_off = HHI_MPLL_CNTL8,
682 .shift = 15,
683 .width = 1,
684 },
685 .n2 = {
686 .reg_off = HHI_MPLL_CNTL8,
687 .shift = 16,
688 .width = 9,
689 },
690 .lock = &meson_clk_lock,
691 },
692 .hw.init = &(struct clk_init_data){
693 .name = "mpll1_div",
694 .ops = &meson_clk_mpll_ops,
695 .parent_names = (const char *[]){ "mpll_prediv" },
696 .num_parents = 1,
697 },
698};
699
700static struct clk_regmap gxbb_mpll1 = {
701 .data = &(struct clk_regmap_gate_data){
702 .offset = HHI_MPLL_CNTL8,
703 .bit_idx = 14,
704 },
705 .hw.init = &(struct clk_init_data){
706 .name = "mpll1",
707 .ops = &clk_regmap_gate_ops,
708 .parent_names = (const char *[]){ "mpll1_div" },
709 .num_parents = 1,
710 .flags = CLK_SET_RATE_PARENT,
711 },
712};
713
714static struct clk_regmap gxbb_mpll2_div = {
715 .data = &(struct meson_clk_mpll_data){
716 .sdm = {
717 .reg_off = HHI_MPLL_CNTL9,
718 .shift = 0,
719 .width = 14,
720 },
721 .sdm_en = {
722 .reg_off = HHI_MPLL_CNTL9,
723 .shift = 15,
724 .width = 1,
725 },
726 .n2 = {
727 .reg_off = HHI_MPLL_CNTL9,
728 .shift = 16,
729 .width = 9,
730 },
731 .lock = &meson_clk_lock,
732 },
733 .hw.init = &(struct clk_init_data){
734 .name = "mpll2_div",
735 .ops = &meson_clk_mpll_ops,
736 .parent_names = (const char *[]){ "mpll_prediv" },
737 .num_parents = 1,
738 },
739};
740
741static struct clk_regmap gxbb_mpll2 = {
742 .data = &(struct clk_regmap_gate_data){
743 .offset = HHI_MPLL_CNTL9,
744 .bit_idx = 14,
745 },
746 .hw.init = &(struct clk_init_data){
747 .name = "mpll2",
748 .ops = &clk_regmap_gate_ops,
749 .parent_names = (const char *[]){ "mpll2_div" },
750 .num_parents = 1,
751 .flags = CLK_SET_RATE_PARENT,
752 },
753};
754
755static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
756static const char * const clk81_parent_names[] = {
757 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
758 "fclk_div3", "fclk_div5"
759};
760
761static struct clk_regmap gxbb_mpeg_clk_sel = {
762 .data = &(struct clk_regmap_mux_data){
763 .offset = HHI_MPEG_CLK_CNTL,
764 .mask = 0x7,
765 .shift = 12,
766 .table = mux_table_clk81,
767 },
768 .hw.init = &(struct clk_init_data){
769 .name = "mpeg_clk_sel",
770 .ops = &clk_regmap_mux_ro_ops,
771 /*
772 * bits 14:12 selects from 8 possible parents:
773 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
774 * fclk_div4, fclk_div3, fclk_div5
775 */
776 .parent_names = clk81_parent_names,
777 .num_parents = ARRAY_SIZE(clk81_parent_names),
778 },
779};
780
781static struct clk_regmap gxbb_mpeg_clk_div = {
782 .data = &(struct clk_regmap_div_data){
783 .offset = HHI_MPEG_CLK_CNTL,
784 .shift = 0,
785 .width = 7,
786 },
787 .hw.init = &(struct clk_init_data){
788 .name = "mpeg_clk_div",
789 .ops = &clk_regmap_divider_ro_ops,
790 .parent_names = (const char *[]){ "mpeg_clk_sel" },
791 .num_parents = 1,
792 },
793};
794
795/* the mother of dragons gates */
796static struct clk_regmap gxbb_clk81 = {
797 .data = &(struct clk_regmap_gate_data){
798 .offset = HHI_MPEG_CLK_CNTL,
799 .bit_idx = 7,
800 },
801 .hw.init = &(struct clk_init_data){
802 .name = "clk81",
803 .ops = &clk_regmap_gate_ops,
804 .parent_names = (const char *[]){ "mpeg_clk_div" },
805 .num_parents = 1,
806 .flags = CLK_IS_CRITICAL,
807 },
808};
809
810static struct clk_regmap gxbb_sar_adc_clk_sel = {
811 .data = &(struct clk_regmap_mux_data){
812 .offset = HHI_SAR_CLK_CNTL,
813 .mask = 0x3,
814 .shift = 9,
815 },
816 .hw.init = &(struct clk_init_data){
817 .name = "sar_adc_clk_sel",
818 .ops = &clk_regmap_mux_ops,
819 /* NOTE: The datasheet doesn't list the parents for bit 10 */
820 .parent_names = (const char *[]){ "xtal", "clk81", },
821 .num_parents = 2,
822 },
823};
824
825static struct clk_regmap gxbb_sar_adc_clk_div = {
826 .data = &(struct clk_regmap_div_data){
827 .offset = HHI_SAR_CLK_CNTL,
828 .shift = 0,
829 .width = 8,
830 },
831 .hw.init = &(struct clk_init_data){
832 .name = "sar_adc_clk_div",
833 .ops = &clk_regmap_divider_ops,
834 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
835 .num_parents = 1,
836 },
837};
838
839static struct clk_regmap gxbb_sar_adc_clk = {
840 .data = &(struct clk_regmap_gate_data){
841 .offset = HHI_SAR_CLK_CNTL,
842 .bit_idx = 8,
843 },
844 .hw.init = &(struct clk_init_data){
845 .name = "sar_adc_clk",
846 .ops = &clk_regmap_gate_ops,
847 .parent_names = (const char *[]){ "sar_adc_clk_div" },
848 .num_parents = 1,
849 .flags = CLK_SET_RATE_PARENT,
850 },
851};
852
853/*
854 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
855 * muxed by a glitch-free switch.
856 */
857
858static const char * const gxbb_mali_0_1_parent_names[] = {
859 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
860 "fclk_div4", "fclk_div3", "fclk_div5"
861};
862
863static struct clk_regmap gxbb_mali_0_sel = {
864 .data = &(struct clk_regmap_mux_data){
865 .offset = HHI_MALI_CLK_CNTL,
866 .mask = 0x7,
867 .shift = 9,
868 },
869 .hw.init = &(struct clk_init_data){
870 .name = "mali_0_sel",
871 .ops = &clk_regmap_mux_ops,
872 /*
873 * bits 10:9 selects from 8 possible parents:
874 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
875 * fclk_div4, fclk_div3, fclk_div5
876 */
877 .parent_names = gxbb_mali_0_1_parent_names,
878 .num_parents = 8,
879 .flags = CLK_SET_RATE_NO_REPARENT,
880 },
881};
882
883static struct clk_regmap gxbb_mali_0_div = {
884 .data = &(struct clk_regmap_div_data){
885 .offset = HHI_MALI_CLK_CNTL,
886 .shift = 0,
887 .width = 7,
888 },
889 .hw.init = &(struct clk_init_data){
890 .name = "mali_0_div",
891 .ops = &clk_regmap_divider_ops,
892 .parent_names = (const char *[]){ "mali_0_sel" },
893 .num_parents = 1,
894 .flags = CLK_SET_RATE_NO_REPARENT,
895 },
896};
897
898static struct clk_regmap gxbb_mali_0 = {
899 .data = &(struct clk_regmap_gate_data){
900 .offset = HHI_MALI_CLK_CNTL,
901 .bit_idx = 8,
902 },
903 .hw.init = &(struct clk_init_data){
904 .name = "mali_0",
905 .ops = &clk_regmap_gate_ops,
906 .parent_names = (const char *[]){ "mali_0_div" },
907 .num_parents = 1,
908 .flags = CLK_SET_RATE_PARENT,
909 },
910};
911
912static struct clk_regmap gxbb_mali_1_sel = {
913 .data = &(struct clk_regmap_mux_data){
914 .offset = HHI_MALI_CLK_CNTL,
915 .mask = 0x7,
916 .shift = 25,
917 },
918 .hw.init = &(struct clk_init_data){
919 .name = "mali_1_sel",
920 .ops = &clk_regmap_mux_ops,
921 /*
922 * bits 10:9 selects from 8 possible parents:
923 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
924 * fclk_div4, fclk_div3, fclk_div5
925 */
926 .parent_names = gxbb_mali_0_1_parent_names,
927 .num_parents = 8,
928 .flags = CLK_SET_RATE_NO_REPARENT,
929 },
930};
931
932static struct clk_regmap gxbb_mali_1_div = {
933 .data = &(struct clk_regmap_div_data){
934 .offset = HHI_MALI_CLK_CNTL,
935 .shift = 16,
936 .width = 7,
937 },
938 .hw.init = &(struct clk_init_data){
939 .name = "mali_1_div",
940 .ops = &clk_regmap_divider_ops,
941 .parent_names = (const char *[]){ "mali_1_sel" },
942 .num_parents = 1,
943 .flags = CLK_SET_RATE_NO_REPARENT,
944 },
945};
946
947static struct clk_regmap gxbb_mali_1 = {
948 .data = &(struct clk_regmap_gate_data){
949 .offset = HHI_MALI_CLK_CNTL,
950 .bit_idx = 24,
951 },
952 .hw.init = &(struct clk_init_data){
953 .name = "mali_1",
954 .ops = &clk_regmap_gate_ops,
955 .parent_names = (const char *[]){ "mali_1_div" },
956 .num_parents = 1,
957 .flags = CLK_SET_RATE_PARENT,
958 },
959};
960
961static const char * const gxbb_mali_parent_names[] = {
962 "mali_0", "mali_1"
963};
964
965static struct clk_regmap gxbb_mali = {
966 .data = &(struct clk_regmap_mux_data){
967 .offset = HHI_MALI_CLK_CNTL,
968 .mask = 1,
969 .shift = 31,
970 },
971 .hw.init = &(struct clk_init_data){
972 .name = "mali",
973 .ops = &clk_regmap_mux_ops,
974 .parent_names = gxbb_mali_parent_names,
975 .num_parents = 2,
976 .flags = CLK_SET_RATE_NO_REPARENT,
977 },
978};
979
980static struct clk_regmap gxbb_cts_amclk_sel = {
981 .data = &(struct clk_regmap_mux_data){
982 .offset = HHI_AUD_CLK_CNTL,
983 .mask = 0x3,
984 .shift = 9,
985 .table = (u32[]){ 1, 2, 3 },
986 },
987 .hw.init = &(struct clk_init_data){
988 .name = "cts_amclk_sel",
989 .ops = &clk_regmap_mux_ops,
990 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
991 .num_parents = 3,
992 .flags = CLK_SET_RATE_PARENT,
993 },
994};
995
996static struct clk_regmap gxbb_cts_amclk_div = {
997 .data = &(struct meson_clk_audio_div_data){
998 .div = {
999 .reg_off = HHI_AUD_CLK_CNTL,
1000 .shift = 0,
1001 .width = 8,
1002 },
1003 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1004 },
1005 .hw.init = &(struct clk_init_data){
1006 .name = "cts_amclk_div",
1007 .ops = &meson_clk_audio_divider_ops,
1008 .parent_names = (const char *[]){ "cts_amclk_sel" },
1009 .num_parents = 1,
1010 .flags = CLK_SET_RATE_PARENT,
1011 },
1012};
1013
1014static struct clk_regmap gxbb_cts_amclk = {
1015 .data = &(struct clk_regmap_gate_data){
1016 .offset = HHI_AUD_CLK_CNTL,
1017 .bit_idx = 8,
1018 },
1019 .hw.init = &(struct clk_init_data){
1020 .name = "cts_amclk",
1021 .ops = &clk_regmap_gate_ops,
1022 .parent_names = (const char *[]){ "cts_amclk_div" },
1023 .num_parents = 1,
1024 .flags = CLK_SET_RATE_PARENT,
1025 },
1026};
1027
1028static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1029 .data = &(struct clk_regmap_mux_data){
1030 .offset = HHI_AUD_CLK_CNTL2,
1031 .mask = 0x3,
1032 .shift = 25,
1033 .table = (u32[]){ 1, 2, 3 },
1034 },
1035 .hw.init = &(struct clk_init_data) {
1036 .name = "cts_mclk_i958_sel",
1037 .ops = &clk_regmap_mux_ops,
1038 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
1039 .num_parents = 3,
1040 .flags = CLK_SET_RATE_PARENT,
1041 },
1042};
1043
1044static struct clk_regmap gxbb_cts_mclk_i958_div = {
1045 .data = &(struct clk_regmap_div_data){
1046 .offset = HHI_AUD_CLK_CNTL2,
1047 .shift = 16,
1048 .width = 8,
1049 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1050 },
1051 .hw.init = &(struct clk_init_data) {
1052 .name = "cts_mclk_i958_div",
1053 .ops = &clk_regmap_divider_ops,
1054 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
1055 .num_parents = 1,
1056 .flags = CLK_SET_RATE_PARENT,
1057 },
1058};
1059
1060static struct clk_regmap gxbb_cts_mclk_i958 = {
1061 .data = &(struct clk_regmap_gate_data){
1062 .offset = HHI_AUD_CLK_CNTL2,
1063 .bit_idx = 24,
1064 },
1065 .hw.init = &(struct clk_init_data){
1066 .name = "cts_mclk_i958",
1067 .ops = &clk_regmap_gate_ops,
1068 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
1069 .num_parents = 1,
1070 .flags = CLK_SET_RATE_PARENT,
1071 },
1072};
1073
1074static struct clk_regmap gxbb_cts_i958 = {
1075 .data = &(struct clk_regmap_mux_data){
1076 .offset = HHI_AUD_CLK_CNTL2,
1077 .mask = 0x1,
1078 .shift = 27,
1079 },
1080 .hw.init = &(struct clk_init_data){
1081 .name = "cts_i958",
1082 .ops = &clk_regmap_mux_ops,
1083 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
1084 .num_parents = 2,
1085 /*
1086 *The parent is specific to origin of the audio data. Let the
1087 * consumer choose the appropriate parent
1088 */
1089 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1090 },
1091};
1092
1093static struct clk_regmap gxbb_32k_clk_div = {
1094 .data = &(struct clk_regmap_div_data){
1095 .offset = HHI_32K_CLK_CNTL,
1096 .shift = 0,
1097 .width = 14,
1098 },
1099 .hw.init = &(struct clk_init_data){
1100 .name = "32k_clk_div",
1101 .ops = &clk_regmap_divider_ops,
1102 .parent_names = (const char *[]){ "32k_clk_sel" },
1103 .num_parents = 1,
1104 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1105 },
1106};
1107
1108static struct clk_regmap gxbb_32k_clk = {
1109 .data = &(struct clk_regmap_gate_data){
1110 .offset = HHI_32K_CLK_CNTL,
1111 .bit_idx = 15,
1112 },
1113 .hw.init = &(struct clk_init_data){
1114 .name = "32k_clk",
1115 .ops = &clk_regmap_gate_ops,
1116 .parent_names = (const char *[]){ "32k_clk_div" },
1117 .num_parents = 1,
1118 .flags = CLK_SET_RATE_PARENT,
1119 },
1120};
1121
1122static const char * const gxbb_32k_clk_parent_names[] = {
1123 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1124};
1125
1126static struct clk_regmap gxbb_32k_clk_sel = {
1127 .data = &(struct clk_regmap_mux_data){
1128 .offset = HHI_32K_CLK_CNTL,
1129 .mask = 0x3,
1130 .shift = 16,
1131 },
1132 .hw.init = &(struct clk_init_data){
1133 .name = "32k_clk_sel",
1134 .ops = &clk_regmap_mux_ops,
1135 .parent_names = gxbb_32k_clk_parent_names,
1136 .num_parents = 4,
1137 .flags = CLK_SET_RATE_PARENT,
1138 },
1139};
1140
1141static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
1142 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1143
1144 /*
1145 * Following these parent clocks, we should also have had mpll2, mpll3
1146 * and gp0_pll but these clocks are too precious to be used here. All
1147 * the necessary rates for MMC and NAND operation can be acheived using
1148 * xtal or fclk_div clocks
1149 */
1150};
1151
1152/* SDIO clock */
1153static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1154 .data = &(struct clk_regmap_mux_data){
1155 .offset = HHI_SD_EMMC_CLK_CNTL,
1156 .mask = 0x7,
1157 .shift = 9,
1158 },
1159 .hw.init = &(struct clk_init_data) {
1160 .name = "sd_emmc_a_clk0_sel",
1161 .ops = &clk_regmap_mux_ops,
1162 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1163 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1164 .flags = CLK_SET_RATE_PARENT,
1165 },
1166};
1167
1168static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1169 .data = &(struct clk_regmap_div_data){
1170 .offset = HHI_SD_EMMC_CLK_CNTL,
1171 .shift = 0,
1172 .width = 7,
1173 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1174 },
1175 .hw.init = &(struct clk_init_data) {
1176 .name = "sd_emmc_a_clk0_div",
1177 .ops = &clk_regmap_divider_ops,
1178 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1179 .num_parents = 1,
1180 .flags = CLK_SET_RATE_PARENT,
1181 },
1182};
1183
1184static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1185 .data = &(struct clk_regmap_gate_data){
1186 .offset = HHI_SD_EMMC_CLK_CNTL,
1187 .bit_idx = 7,
1188 },
1189 .hw.init = &(struct clk_init_data){
1190 .name = "sd_emmc_a_clk0",
1191 .ops = &clk_regmap_gate_ops,
1192 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1193 .num_parents = 1,
1194 .flags = CLK_SET_RATE_PARENT,
1195 },
1196};
1197
1198/* SDcard clock */
1199static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1200 .data = &(struct clk_regmap_mux_data){
1201 .offset = HHI_SD_EMMC_CLK_CNTL,
1202 .mask = 0x7,
1203 .shift = 25,
1204 },
1205 .hw.init = &(struct clk_init_data) {
1206 .name = "sd_emmc_b_clk0_sel",
1207 .ops = &clk_regmap_mux_ops,
1208 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1209 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1210 .flags = CLK_SET_RATE_PARENT,
1211 },
1212};
1213
1214static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1215 .data = &(struct clk_regmap_div_data){
1216 .offset = HHI_SD_EMMC_CLK_CNTL,
1217 .shift = 16,
1218 .width = 7,
1219 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1220 },
1221 .hw.init = &(struct clk_init_data) {
1222 .name = "sd_emmc_b_clk0_div",
1223 .ops = &clk_regmap_divider_ops,
1224 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1225 .num_parents = 1,
1226 .flags = CLK_SET_RATE_PARENT,
1227 },
1228};
1229
1230static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1231 .data = &(struct clk_regmap_gate_data){
1232 .offset = HHI_SD_EMMC_CLK_CNTL,
1233 .bit_idx = 23,
1234 },
1235 .hw.init = &(struct clk_init_data){
1236 .name = "sd_emmc_b_clk0",
1237 .ops = &clk_regmap_gate_ops,
1238 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1239 .num_parents = 1,
1240 .flags = CLK_SET_RATE_PARENT,
1241 },
1242};
1243
1244/* EMMC/NAND clock */
1245static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1246 .data = &(struct clk_regmap_mux_data){
1247 .offset = HHI_NAND_CLK_CNTL,
1248 .mask = 0x7,
1249 .shift = 9,
1250 },
1251 .hw.init = &(struct clk_init_data) {
1252 .name = "sd_emmc_c_clk0_sel",
1253 .ops = &clk_regmap_mux_ops,
1254 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1255 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1256 .flags = CLK_SET_RATE_PARENT,
1257 },
1258};
1259
1260static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1261 .data = &(struct clk_regmap_div_data){
1262 .offset = HHI_NAND_CLK_CNTL,
1263 .shift = 0,
1264 .width = 7,
1265 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1266 },
1267 .hw.init = &(struct clk_init_data) {
1268 .name = "sd_emmc_c_clk0_div",
1269 .ops = &clk_regmap_divider_ops,
1270 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1271 .num_parents = 1,
1272 .flags = CLK_SET_RATE_PARENT,
1273 },
1274};
1275
1276static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1277 .data = &(struct clk_regmap_gate_data){
1278 .offset = HHI_NAND_CLK_CNTL,
1279 .bit_idx = 7,
1280 },
1281 .hw.init = &(struct clk_init_data){
1282 .name = "sd_emmc_c_clk0",
1283 .ops = &clk_regmap_gate_ops,
1284 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1285 .num_parents = 1,
1286 .flags = CLK_SET_RATE_PARENT,
1287 },
1288};
1289
1290/* VPU Clock */
1291
1292static const char * const gxbb_vpu_parent_names[] = {
1293 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1294};
1295
1296static struct clk_regmap gxbb_vpu_0_sel = {
1297 .data = &(struct clk_regmap_mux_data){
1298 .offset = HHI_VPU_CLK_CNTL,
1299 .mask = 0x3,
1300 .shift = 9,
1301 },
1302 .hw.init = &(struct clk_init_data){
1303 .name = "vpu_0_sel",
1304 .ops = &clk_regmap_mux_ops,
1305 /*
1306 * bits 9:10 selects from 4 possible parents:
1307 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1308 */
1309 .parent_names = gxbb_vpu_parent_names,
1310 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1311 .flags = CLK_SET_RATE_NO_REPARENT,
1312 },
1313};
1314
1315static struct clk_regmap gxbb_vpu_0_div = {
1316 .data = &(struct clk_regmap_div_data){
1317 .offset = HHI_VPU_CLK_CNTL,
1318 .shift = 0,
1319 .width = 7,
1320 },
1321 .hw.init = &(struct clk_init_data){
1322 .name = "vpu_0_div",
1323 .ops = &clk_regmap_divider_ops,
1324 .parent_names = (const char *[]){ "vpu_0_sel" },
1325 .num_parents = 1,
1326 .flags = CLK_SET_RATE_PARENT,
1327 },
1328};
1329
1330static struct clk_regmap gxbb_vpu_0 = {
1331 .data = &(struct clk_regmap_gate_data){
1332 .offset = HHI_VPU_CLK_CNTL,
1333 .bit_idx = 8,
1334 },
1335 .hw.init = &(struct clk_init_data) {
1336 .name = "vpu_0",
1337 .ops = &clk_regmap_gate_ops,
1338 .parent_names = (const char *[]){ "vpu_0_div" },
1339 .num_parents = 1,
1340 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1341 },
1342};
1343
1344static struct clk_regmap gxbb_vpu_1_sel = {
1345 .data = &(struct clk_regmap_mux_data){
1346 .offset = HHI_VPU_CLK_CNTL,
1347 .mask = 0x3,
1348 .shift = 25,
1349 },
1350 .hw.init = &(struct clk_init_data){
1351 .name = "vpu_1_sel",
1352 .ops = &clk_regmap_mux_ops,
1353 /*
1354 * bits 25:26 selects from 4 possible parents:
1355 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1356 */
1357 .parent_names = gxbb_vpu_parent_names,
1358 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1359 .flags = CLK_SET_RATE_NO_REPARENT,
1360 },
1361};
1362
1363static struct clk_regmap gxbb_vpu_1_div = {
1364 .data = &(struct clk_regmap_div_data){
1365 .offset = HHI_VPU_CLK_CNTL,
1366 .shift = 16,
1367 .width = 7,
1368 },
1369 .hw.init = &(struct clk_init_data){
1370 .name = "vpu_1_div",
1371 .ops = &clk_regmap_divider_ops,
1372 .parent_names = (const char *[]){ "vpu_1_sel" },
1373 .num_parents = 1,
1374 .flags = CLK_SET_RATE_PARENT,
1375 },
1376};
1377
1378static struct clk_regmap gxbb_vpu_1 = {
1379 .data = &(struct clk_regmap_gate_data){
1380 .offset = HHI_VPU_CLK_CNTL,
1381 .bit_idx = 24,
1382 },
1383 .hw.init = &(struct clk_init_data) {
1384 .name = "vpu_1",
1385 .ops = &clk_regmap_gate_ops,
1386 .parent_names = (const char *[]){ "vpu_1_div" },
1387 .num_parents = 1,
1388 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1389 },
1390};
1391
1392static struct clk_regmap gxbb_vpu = {
1393 .data = &(struct clk_regmap_mux_data){
1394 .offset = HHI_VPU_CLK_CNTL,
1395 .mask = 1,
1396 .shift = 31,
1397 },
1398 .hw.init = &(struct clk_init_data){
1399 .name = "vpu",
1400 .ops = &clk_regmap_mux_ops,
1401 /*
1402 * bit 31 selects from 2 possible parents:
1403 * vpu_0 or vpu_1
1404 */
1405 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1406 .num_parents = 2,
1407 .flags = CLK_SET_RATE_NO_REPARENT,
1408 },
1409};
1410
1411/* VAPB Clock */
1412
1413static const char * const gxbb_vapb_parent_names[] = {
1414 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1415};
1416
1417static struct clk_regmap gxbb_vapb_0_sel = {
1418 .data = &(struct clk_regmap_mux_data){
1419 .offset = HHI_VAPBCLK_CNTL,
1420 .mask = 0x3,
1421 .shift = 9,
1422 },
1423 .hw.init = &(struct clk_init_data){
1424 .name = "vapb_0_sel",
1425 .ops = &clk_regmap_mux_ops,
1426 /*
1427 * bits 9:10 selects from 4 possible parents:
1428 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1429 */
1430 .parent_names = gxbb_vapb_parent_names,
1431 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1432 .flags = CLK_SET_RATE_NO_REPARENT,
1433 },
1434};
1435
1436static struct clk_regmap gxbb_vapb_0_div = {
1437 .data = &(struct clk_regmap_div_data){
1438 .offset = HHI_VAPBCLK_CNTL,
1439 .shift = 0,
1440 .width = 7,
1441 },
1442 .hw.init = &(struct clk_init_data){
1443 .name = "vapb_0_div",
1444 .ops = &clk_regmap_divider_ops,
1445 .parent_names = (const char *[]){ "vapb_0_sel" },
1446 .num_parents = 1,
1447 .flags = CLK_SET_RATE_PARENT,
1448 },
1449};
1450
1451static struct clk_regmap gxbb_vapb_0 = {
1452 .data = &(struct clk_regmap_gate_data){
1453 .offset = HHI_VAPBCLK_CNTL,
1454 .bit_idx = 8,
1455 },
1456 .hw.init = &(struct clk_init_data) {
1457 .name = "vapb_0",
1458 .ops = &clk_regmap_gate_ops,
1459 .parent_names = (const char *[]){ "vapb_0_div" },
1460 .num_parents = 1,
1461 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1462 },
1463};
1464
1465static struct clk_regmap gxbb_vapb_1_sel = {
1466 .data = &(struct clk_regmap_mux_data){
1467 .offset = HHI_VAPBCLK_CNTL,
1468 .mask = 0x3,
1469 .shift = 25,
1470 },
1471 .hw.init = &(struct clk_init_data){
1472 .name = "vapb_1_sel",
1473 .ops = &clk_regmap_mux_ops,
1474 /*
1475 * bits 25:26 selects from 4 possible parents:
1476 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1477 */
1478 .parent_names = gxbb_vapb_parent_names,
1479 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1480 .flags = CLK_SET_RATE_NO_REPARENT,
1481 },
1482};
1483
1484static struct clk_regmap gxbb_vapb_1_div = {
1485 .data = &(struct clk_regmap_div_data){
1486 .offset = HHI_VAPBCLK_CNTL,
1487 .shift = 16,
1488 .width = 7,
1489 },
1490 .hw.init = &(struct clk_init_data){
1491 .name = "vapb_1_div",
1492 .ops = &clk_regmap_divider_ops,
1493 .parent_names = (const char *[]){ "vapb_1_sel" },
1494 .num_parents = 1,
1495 .flags = CLK_SET_RATE_PARENT,
1496 },
1497};
1498
1499static struct clk_regmap gxbb_vapb_1 = {
1500 .data = &(struct clk_regmap_gate_data){
1501 .offset = HHI_VAPBCLK_CNTL,
1502 .bit_idx = 24,
1503 },
1504 .hw.init = &(struct clk_init_data) {
1505 .name = "vapb_1",
1506 .ops = &clk_regmap_gate_ops,
1507 .parent_names = (const char *[]){ "vapb_1_div" },
1508 .num_parents = 1,
1509 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1510 },
1511};
1512
1513static struct clk_regmap gxbb_vapb_sel = {
1514 .data = &(struct clk_regmap_mux_data){
1515 .offset = HHI_VAPBCLK_CNTL,
1516 .mask = 1,
1517 .shift = 31,
1518 },
1519 .hw.init = &(struct clk_init_data){
1520 .name = "vapb_sel",
1521 .ops = &clk_regmap_mux_ops,
1522 /*
1523 * bit 31 selects from 2 possible parents:
1524 * vapb_0 or vapb_1
1525 */
1526 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1527 .num_parents = 2,
1528 .flags = CLK_SET_RATE_NO_REPARENT,
1529 },
1530};
1531
1532static struct clk_regmap gxbb_vapb = {
1533 .data = &(struct clk_regmap_gate_data){
1534 .offset = HHI_VAPBCLK_CNTL,
1535 .bit_idx = 30,
1536 },
1537 .hw.init = &(struct clk_init_data) {
1538 .name = "vapb",
1539 .ops = &clk_regmap_gate_ops,
1540 .parent_names = (const char *[]){ "vapb_sel" },
1541 .num_parents = 1,
1542 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1543 },
1544};
1545
1546/* Everything Else (EE) domain gates */
1547static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1548static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
1549static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
1550static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
1551static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
1552static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
1553static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
1554static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
1555static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
1556static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
1557static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
1558static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
1559static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
1560static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
1561static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
1562static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
1563static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
1564static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
1565static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
1566static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
1567static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
1568static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
1569
1570static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
1571static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
1572static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
1573static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
1574static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
1575static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
1576static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
1577static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
1578static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
1579static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
1580static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
1581static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
1582static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
1583static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
1584static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
1585static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
1586static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
1587static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
1588static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
1589static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
1590static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
1591static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
1592static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
1593static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
1594static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
1595
1596static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1597static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1598static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
1599static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
1600static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
1601static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
1602static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
1603static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
1604static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
1605static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
1606static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
1607static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1608static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
1609
1610static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
1611static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
1612static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1613static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1614static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
1615static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
1616static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
1617static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
1618static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
1619static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
1620static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
1621static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
1622static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
1623static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
1624static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
1625static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
1626
1627/* Always On (AO) domain gates */
1628
1629static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
1630static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
1631static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
1632static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
1633static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
1634
1635/* Array of all clocks provided by this provider */
1636
1637static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1638 .hws = {
1639 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1640 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
1641 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1642 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1643 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1644 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1645 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1646 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1647 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
1648 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1649 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1650 [CLKID_CLK81] = &gxbb_clk81.hw,
1651 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1652 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1653 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1654 [CLKID_DDR] = &gxbb_ddr.hw,
1655 [CLKID_DOS] = &gxbb_dos.hw,
1656 [CLKID_ISA] = &gxbb_isa.hw,
1657 [CLKID_PL301] = &gxbb_pl301.hw,
1658 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1659 [CLKID_SPICC] = &gxbb_spicc.hw,
1660 [CLKID_I2C] = &gxbb_i2c.hw,
1661 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1662 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1663 [CLKID_RNG0] = &gxbb_rng0.hw,
1664 [CLKID_UART0] = &gxbb_uart0.hw,
1665 [CLKID_SDHC] = &gxbb_sdhc.hw,
1666 [CLKID_STREAM] = &gxbb_stream.hw,
1667 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1668 [CLKID_SDIO] = &gxbb_sdio.hw,
1669 [CLKID_ABUF] = &gxbb_abuf.hw,
1670 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1671 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1672 [CLKID_SPI] = &gxbb_spi.hw,
1673 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1674 [CLKID_ETH] = &gxbb_eth.hw,
1675 [CLKID_DEMUX] = &gxbb_demux.hw,
1676 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1677 [CLKID_IEC958] = &gxbb_iec958.hw,
1678 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1679 [CLKID_AMCLK] = &gxbb_amclk.hw,
1680 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1681 [CLKID_MIXER] = &gxbb_mixer.hw,
1682 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1683 [CLKID_ADC] = &gxbb_adc.hw,
1684 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1685 [CLKID_AIU] = &gxbb_aiu.hw,
1686 [CLKID_UART1] = &gxbb_uart1.hw,
1687 [CLKID_G2D] = &gxbb_g2d.hw,
1688 [CLKID_USB0] = &gxbb_usb0.hw,
1689 [CLKID_USB1] = &gxbb_usb1.hw,
1690 [CLKID_RESET] = &gxbb_reset.hw,
1691 [CLKID_NAND] = &gxbb_nand.hw,
1692 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1693 [CLKID_USB] = &gxbb_usb.hw,
1694 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1695 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1696 [CLKID_EFUSE] = &gxbb_efuse.hw,
1697 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1698 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1699 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1700 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1701 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1702 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1703 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1704 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1705 [CLKID_DVIN] = &gxbb_dvin.hw,
1706 [CLKID_UART2] = &gxbb_uart2.hw,
1707 [CLKID_SANA] = &gxbb_sana.hw,
1708 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1709 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1710 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1711 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1712 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1713 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1714 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1715 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1716 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1717 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1718 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1719 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1720 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1721 [CLKID_RNG1] = &gxbb_rng1.hw,
1722 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1723 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1724 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1725 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1726 [CLKID_EDP] = &gxbb_edp.hw,
1727 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1728 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1729 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1730 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1731 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
1732 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1733 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1734 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
1735 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1736 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1737 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1738 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1739 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1740 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1741 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1742 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1743 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1744 [CLKID_MALI] = &gxbb_mali.hw,
1745 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1746 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1747 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
1748 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1749 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1750 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
1751 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
1752 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
1753 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
1754 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
1755 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
1756 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
1757 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
1758 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
1759 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
1760 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
1761 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1762 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1763 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
1764 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
1765 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
1766 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
1767 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
1768 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
1769 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
1770 [CLKID_VPU] = &gxbb_vpu.hw,
1771 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
1772 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
1773 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
1774 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
1775 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
1776 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1777 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1778 [CLKID_VAPB] = &gxbb_vapb.hw,
1779 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
1780 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
1781 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
1782 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
1783 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
1784 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
1785 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
1786 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1787 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1788 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
1789 [NR_CLKS] = NULL,
1790 },
1791 .num = NR_CLKS,
1792};
1793
1794static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1795 .hws = {
1796 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1797 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
1798 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1799 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1800 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1801 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1802 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1803 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1804 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw,
1805 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1806 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1807 [CLKID_CLK81] = &gxbb_clk81.hw,
1808 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1809 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1810 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1811 [CLKID_DDR] = &gxbb_ddr.hw,
1812 [CLKID_DOS] = &gxbb_dos.hw,
1813 [CLKID_ISA] = &gxbb_isa.hw,
1814 [CLKID_PL301] = &gxbb_pl301.hw,
1815 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1816 [CLKID_SPICC] = &gxbb_spicc.hw,
1817 [CLKID_I2C] = &gxbb_i2c.hw,
1818 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1819 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1820 [CLKID_RNG0] = &gxbb_rng0.hw,
1821 [CLKID_UART0] = &gxbb_uart0.hw,
1822 [CLKID_SDHC] = &gxbb_sdhc.hw,
1823 [CLKID_STREAM] = &gxbb_stream.hw,
1824 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1825 [CLKID_SDIO] = &gxbb_sdio.hw,
1826 [CLKID_ABUF] = &gxbb_abuf.hw,
1827 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1828 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1829 [CLKID_SPI] = &gxbb_spi.hw,
1830 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1831 [CLKID_ETH] = &gxbb_eth.hw,
1832 [CLKID_DEMUX] = &gxbb_demux.hw,
1833 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1834 [CLKID_IEC958] = &gxbb_iec958.hw,
1835 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1836 [CLKID_AMCLK] = &gxbb_amclk.hw,
1837 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1838 [CLKID_MIXER] = &gxbb_mixer.hw,
1839 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1840 [CLKID_ADC] = &gxbb_adc.hw,
1841 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1842 [CLKID_AIU] = &gxbb_aiu.hw,
1843 [CLKID_UART1] = &gxbb_uart1.hw,
1844 [CLKID_G2D] = &gxbb_g2d.hw,
1845 [CLKID_USB0] = &gxbb_usb0.hw,
1846 [CLKID_USB1] = &gxbb_usb1.hw,
1847 [CLKID_RESET] = &gxbb_reset.hw,
1848 [CLKID_NAND] = &gxbb_nand.hw,
1849 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1850 [CLKID_USB] = &gxbb_usb.hw,
1851 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1852 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1853 [CLKID_EFUSE] = &gxbb_efuse.hw,
1854 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1855 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1856 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1857 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1858 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1859 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1860 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1861 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1862 [CLKID_DVIN] = &gxbb_dvin.hw,
1863 [CLKID_UART2] = &gxbb_uart2.hw,
1864 [CLKID_SANA] = &gxbb_sana.hw,
1865 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1866 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1867 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1868 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1869 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1870 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1871 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1872 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1873 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1874 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1875 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1876 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1877 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1878 [CLKID_RNG1] = &gxbb_rng1.hw,
1879 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1880 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1881 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1882 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1883 [CLKID_EDP] = &gxbb_edp.hw,
1884 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1885 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1886 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1887 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1888 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
1889 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1890 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1891 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
1892 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1893 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1894 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1895 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1896 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1897 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1898 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1899 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1900 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1901 [CLKID_MALI] = &gxbb_mali.hw,
1902 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1903 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1904 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
1905 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1906 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1907 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
1908 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
1909 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
1910 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
1911 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
1912 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
1913 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
1914 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
1915 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
1916 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
1917 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
1918 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1919 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1920 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
1921 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
1922 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
1923 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
1924 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
1925 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
1926 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
1927 [CLKID_VPU] = &gxbb_vpu.hw,
1928 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
1929 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
1930 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
1931 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
1932 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
1933 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1934 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1935 [CLKID_VAPB] = &gxbb_vapb.hw,
1936 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
1937 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
1938 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
1939 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
1940 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
1941 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
1942 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
1943 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
1944 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
1945 [NR_CLKS] = NULL,
1946 },
1947 .num = NR_CLKS,
1948};
1949
1950static struct clk_regmap *const gxbb_clk_regmaps[] = {
1951 &gxbb_gp0_pll,
1952 &gxbb_hdmi_pll,
1953};
1954
1955static struct clk_regmap *const gxl_clk_regmaps[] = {
1956 &gxl_gp0_pll,
1957 &gxl_hdmi_pll,
1958};
1959
1960static struct clk_regmap *const gx_clk_regmaps[] = {
1961 &gxbb_clk81,
1962 &gxbb_ddr,
1963 &gxbb_dos,
1964 &gxbb_isa,
1965 &gxbb_pl301,
1966 &gxbb_periphs,
1967 &gxbb_spicc,
1968 &gxbb_i2c,
1969 &gxbb_sar_adc,
1970 &gxbb_smart_card,
1971 &gxbb_rng0,
1972 &gxbb_uart0,
1973 &gxbb_sdhc,
1974 &gxbb_stream,
1975 &gxbb_async_fifo,
1976 &gxbb_sdio,
1977 &gxbb_abuf,
1978 &gxbb_hiu_iface,
1979 &gxbb_assist_misc,
1980 &gxbb_spi,
1981 &gxbb_i2s_spdif,
1982 &gxbb_eth,
1983 &gxbb_demux,
1984 &gxbb_aiu_glue,
1985 &gxbb_iec958,
1986 &gxbb_i2s_out,
1987 &gxbb_amclk,
1988 &gxbb_aififo2,
1989 &gxbb_mixer,
1990 &gxbb_mixer_iface,
1991 &gxbb_adc,
1992 &gxbb_blkmv,
1993 &gxbb_aiu,
1994 &gxbb_uart1,
1995 &gxbb_g2d,
1996 &gxbb_usb0,
1997 &gxbb_usb1,
1998 &gxbb_reset,
1999 &gxbb_nand,
2000 &gxbb_dos_parser,
2001 &gxbb_usb,
2002 &gxbb_vdin1,
2003 &gxbb_ahb_arb0,
2004 &gxbb_efuse,
2005 &gxbb_boot_rom,
2006 &gxbb_ahb_data_bus,
2007 &gxbb_ahb_ctrl_bus,
2008 &gxbb_hdmi_intr_sync,
2009 &gxbb_hdmi_pclk,
2010 &gxbb_usb1_ddr_bridge,
2011 &gxbb_usb0_ddr_bridge,
2012 &gxbb_mmc_pclk,
2013 &gxbb_dvin,
2014 &gxbb_uart2,
2015 &gxbb_sana,
2016 &gxbb_vpu_intr,
2017 &gxbb_sec_ahb_ahb3_bridge,
2018 &gxbb_clk81_a53,
2019 &gxbb_vclk2_venci0,
2020 &gxbb_vclk2_venci1,
2021 &gxbb_vclk2_vencp0,
2022 &gxbb_vclk2_vencp1,
2023 &gxbb_gclk_venci_int0,
2024 &gxbb_gclk_vencp_int,
2025 &gxbb_dac_clk,
2026 &gxbb_aoclk_gate,
2027 &gxbb_iec958_gate,
2028 &gxbb_enc480p,
2029 &gxbb_rng1,
2030 &gxbb_gclk_venci_int1,
2031 &gxbb_vclk2_venclmcc,
2032 &gxbb_vclk2_vencl,
2033 &gxbb_vclk_other,
2034 &gxbb_edp,
2035 &gxbb_ao_media_cpu,
2036 &gxbb_ao_ahb_sram,
2037 &gxbb_ao_ahb_bus,
2038 &gxbb_ao_iface,
2039 &gxbb_ao_i2c,
2040 &gxbb_emmc_a,
2041 &gxbb_emmc_b,
2042 &gxbb_emmc_c,
2043 &gxbb_sar_adc_clk,
2044 &gxbb_mali_0,
2045 &gxbb_mali_1,
2046 &gxbb_cts_amclk,
2047 &gxbb_cts_mclk_i958,
2048 &gxbb_32k_clk,
2049 &gxbb_sd_emmc_a_clk0,
2050 &gxbb_sd_emmc_b_clk0,
2051 &gxbb_sd_emmc_c_clk0,
2052 &gxbb_vpu_0,
2053 &gxbb_vpu_1,
2054 &gxbb_vapb_0,
2055 &gxbb_vapb_1,
2056 &gxbb_vapb,
2057 &gxbb_mpeg_clk_div,
2058 &gxbb_sar_adc_clk_div,
2059 &gxbb_mali_0_div,
2060 &gxbb_mali_1_div,
2061 &gxbb_cts_mclk_i958_div,
2062 &gxbb_32k_clk_div,
2063 &gxbb_sd_emmc_a_clk0_div,
2064 &gxbb_sd_emmc_b_clk0_div,
2065 &gxbb_sd_emmc_c_clk0_div,
2066 &gxbb_vpu_0_div,
2067 &gxbb_vpu_1_div,
2068 &gxbb_vapb_0_div,
2069 &gxbb_vapb_1_div,
2070 &gxbb_mpeg_clk_sel,
2071 &gxbb_sar_adc_clk_sel,
2072 &gxbb_mali_0_sel,
2073 &gxbb_mali_1_sel,
2074 &gxbb_mali,
2075 &gxbb_cts_amclk_sel,
2076 &gxbb_cts_mclk_i958_sel,
2077 &gxbb_cts_i958,
2078 &gxbb_32k_clk_sel,
2079 &gxbb_sd_emmc_a_clk0_sel,
2080 &gxbb_sd_emmc_b_clk0_sel,
2081 &gxbb_sd_emmc_c_clk0_sel,
2082 &gxbb_vpu_0_sel,
2083 &gxbb_vpu_1_sel,
2084 &gxbb_vpu,
2085 &gxbb_vapb_0_sel,
2086 &gxbb_vapb_1_sel,
2087 &gxbb_vapb_sel,
2088 &gxbb_mpll0,
2089 &gxbb_mpll1,
2090 &gxbb_mpll2,
2091 &gxbb_mpll0_div,
2092 &gxbb_mpll1_div,
2093 &gxbb_mpll2_div,
2094 &gxbb_cts_amclk_div,
2095 &gxbb_fixed_pll,
2096 &gxbb_sys_pll,
2097 &gxbb_mpll_prediv,
2098 &gxbb_fclk_div2,
2099 &gxbb_fclk_div3,
2100 &gxbb_fclk_div4,
2101 &gxbb_fclk_div5,
2102 &gxbb_fclk_div7,
2103};
2104
2105struct clkc_data {
2106 struct clk_regmap *const *regmap_clks;
2107 unsigned int regmap_clks_count;
2108 struct clk_hw_onecell_data *hw_onecell_data;
2109};
2110
2111static const struct clkc_data gxbb_clkc_data = {
2112 .regmap_clks = gxbb_clk_regmaps,
2113 .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps),
2114 .hw_onecell_data = &gxbb_hw_onecell_data,
2115};
2116
2117static const struct clkc_data gxl_clkc_data = {
2118 .regmap_clks = gxl_clk_regmaps,
2119 .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps),
2120 .hw_onecell_data = &gxl_hw_onecell_data,
2121};
2122
2123static const struct of_device_id clkc_match_table[] = {
2124 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
2125 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
2126 {},
2127};
2128
2129static const struct regmap_config clkc_regmap_config = {
2130 .reg_bits = 32,
2131 .val_bits = 32,
2132 .reg_stride = 4,
2133};
2134
2135static int gxbb_clkc_probe(struct platform_device *pdev)
2136{
2137 const struct clkc_data *clkc_data;
2138 struct resource *res;
2139 void __iomem *clk_base;
2140 struct regmap *map;
2141 int ret, i;
2142 struct device *dev = &pdev->dev;
2143
2144 clkc_data = of_device_get_match_data(dev);
2145 if (!clkc_data)
2146 return -EINVAL;
2147
2148 /* Get the hhi system controller node if available */
2149 map = syscon_node_to_regmap(of_get_parent(dev->of_node));
2150 if (IS_ERR(map)) {
2151 dev_err(dev,
2152 "failed to get HHI regmap - Trying obsolete regs\n");
2153
2154 /*
2155 * FIXME: HHI registers should be accessed through
2156 * the appropriate system controller. This is required because
2157 * there is more than just clocks in this register space
2158 *
2159 * This fallback method is only provided temporarily until
2160 * all the platform DTs are properly using the syscon node
2161 */
2162 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2163 if (!res)
2164 return -EINVAL;
2165
2166 clk_base = devm_ioremap(dev, res->start, resource_size(res));
2167 if (!clk_base) {
2168 dev_err(dev, "Unable to map clk base\n");
2169 return -ENXIO;
2170 }
2171
2172 map = devm_regmap_init_mmio(dev, clk_base,
2173 &clkc_regmap_config);
2174 if (IS_ERR(map))
2175 return PTR_ERR(map);
2176 }
2177
2178 /* Populate regmap for the common regmap backed clocks */
2179 for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)
2180 gx_clk_regmaps[i]->map = map;
2181
2182 /* Populate regmap for soc specific clocks */
2183 for (i = 0; i < clkc_data->regmap_clks_count; i++)
2184 clkc_data->regmap_clks[i]->map = map;
2185
2186 /* Register all clks */
2187 for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
2188 /* array might be sparse */
2189 if (!clkc_data->hw_onecell_data->hws[i])
2190 continue;
2191
2192 ret = devm_clk_hw_register(dev,
2193 clkc_data->hw_onecell_data->hws[i]);
2194 if (ret) {
2195 dev_err(dev, "Clock registration failed\n");
2196 return ret;
2197 }
2198 }
2199
2200 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
2201 clkc_data->hw_onecell_data);
2202}
2203
2204static struct platform_driver gxbb_driver = {
2205 .probe = gxbb_clkc_probe,
2206 .driver = {
2207 .name = "gxbb-clkc",
2208 .of_match_table = clkc_match_table,
2209 },
2210};
2211
2212builtin_platform_driver(gxbb_driver);